1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_GPU_H 10 #define HPM_GPU_H 11 12 typedef struct { 13 __RW uint32_t AQHICLOCKCONTROL; /* 0x0: clock control register */ 14 __R uint32_t AQHILDLE; /* 0x4: idle status register */ 15 __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ 16 __R uint32_t AQINTRACKNOWLEDGE; /* 0x10: interrupt acknoledge register */ 17 __RW uint32_t AQINTRENBL; /* 0x14: interrupt enable register */ 18 __R uint8_t RESERVED1[12]; /* 0x18 - 0x23: Reserved */ 19 __R uint32_t GCCHIPREV; /* 0x24: chip revison register */ 20 __R uint32_t GCCHIPDATE; /* 0x28: chip date register */ 21 __R uint8_t RESERVED2[108]; /* 0x2C - 0x97: Reserved */ 22 __R uint32_t GCREGHICHIPPATCHREV; /* 0x98: chip patch revision register */ 23 __R uint8_t RESERVED3[12]; /* 0x9C - 0xA7: Reserved */ 24 __R uint32_t GCPRODUCTID; /* 0xA8: product identification register */ 25 __R uint8_t RESERVED4[84]; /* 0xAC - 0xFF: Reserved */ 26 __RW uint32_t GCMODULEPOWERCONTROLS; /* 0x100: module power control register */ 27 __RW uint32_t GCMODULEPOWERMODULECONTROL; /* 0x104: module power module control register */ 28 __R uint32_t GCMODULEPOWERMODULESTATUS; /* 0x108: module power module status register */ 29 __R uint8_t RESERVED5[756]; /* 0x10C - 0x3FF: Reserved */ 30 __RW uint32_t AQMEMORYFEPAGETABLE; /* 0x400: fetch engine page table base address register */ 31 __R uint8_t RESERVED6[16]; /* 0x404 - 0x413: Reserved */ 32 __RW uint32_t AQMEMORYDEBUG; /* 0x414: memory debug register */ 33 __R uint8_t RESERVED7[20]; /* 0x418 - 0x42B: Reserved */ 34 __RW uint32_t AQREGISTERTIMINGCONTROL; /* 0x42C: timing control register */ 35 __R uint8_t RESERVED8[208]; /* 0x430 - 0x4FF: Reserved */ 36 __RW uint32_t GCREGFETCHADDRESS; /* 0x500: fetch command buffer base address register */ 37 __RW uint32_t GCREGFETCHCONTROL; /* 0x504: fetch control register */ 38 __R uint32_t GCREGCURRENTFETCHADDRESS; /* 0x508: current fetch command address register */ 39 } GPU_Type; 40 41 42 /* Bitfield definition for register: AQHICLOCKCONTROL */ 43 /* 44 * ISOLATE_GPU (RW) 45 * 46 * isolate GPU bit, used for power on/off 47 */ 48 #define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK (0x80000UL) 49 #define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT (19U) 50 #define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT) & GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK) 51 #define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK) >> GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT) 52 53 /* 54 * IDLE_VG (R) 55 * 56 * vg pipe is idle 57 */ 58 #define GPU_AQHICLOCKCONTROL_IDLE_VG_MASK (0x40000UL) 59 #define GPU_AQHICLOCKCONTROL_IDLE_VG_SHIFT (18U) 60 #define GPU_AQHICLOCKCONTROL_IDLE_VG_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE_VG_MASK) >> GPU_AQHICLOCKCONTROL_IDLE_VG_SHIFT) 61 62 /* 63 * IDLE2_D (R) 64 * 65 * 2D pipe is idle or not present 66 */ 67 #define GPU_AQHICLOCKCONTROL_IDLE2_D_MASK (0x20000UL) 68 #define GPU_AQHICLOCKCONTROL_IDLE2_D_SHIFT (17U) 69 #define GPU_AQHICLOCKCONTROL_IDLE2_D_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE2_D_MASK) >> GPU_AQHICLOCKCONTROL_IDLE2_D_SHIFT) 70 71 /* 72 * IDLE3_D (R) 73 * 74 * 3D pipe is idle or not present 75 */ 76 #define GPU_AQHICLOCKCONTROL_IDLE3_D_MASK (0x10000UL) 77 #define GPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT (16U) 78 #define GPU_AQHICLOCKCONTROL_IDLE3_D_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE3_D_MASK) >> GPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT) 79 80 /* 81 * DISABLE_RAM_POWER_OPTIMIZATION (RW) 82 * 83 * disables ram power optimization 84 */ 85 #define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK (0x2000U) 86 #define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT (13U) 87 #define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK) 88 #define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT) 89 90 /* 91 * SOFT_RESET (RW) 92 * 93 * soft reset the IP 94 */ 95 #define GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK (0x1000U) 96 #define GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT (12U) 97 #define GPU_AQHICLOCKCONTROL_SOFT_RESET_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT) & GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK) 98 #define GPU_AQHICLOCKCONTROL_SOFT_RESET_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK) >> GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT) 99 100 /* 101 * DISABLE_DEBUG_REGISTERS (RW) 102 * 103 * disable debug registers 104 */ 105 #define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK (0x800U) 106 #define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT (11U) 107 #define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK) 108 #define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT) 109 110 /* 111 * DISABLE_RAM_CLOCK_GATING (RW) 112 * 113 * disables clock gating for rams 114 */ 115 #define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK (0x400U) 116 #define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT (10U) 117 #define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK) 118 #define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT) 119 120 /* 121 * FSCALE_CMD_LOAD (RW) 122 * 123 * core clock frequency scale value enable 124 */ 125 #define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK (0x200U) 126 #define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT (9U) 127 #define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT) & GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK) 128 #define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK) >> GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT) 129 130 /* 131 * FSCALE_VAL (RW) 132 * 133 * core clock frequency scale value 134 */ 135 #define GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK (0x1FCU) 136 #define GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT (2U) 137 #define GPU_AQHICLOCKCONTROL_FSCALE_VAL_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT) & GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK) 138 #define GPU_AQHICLOCKCONTROL_FSCALE_VAL_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK) >> GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT) 139 140 /* 141 * CLK2D_DIS (RW) 142 * 143 * disable 2D/VG clock 144 */ 145 #define GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK (0x2U) 146 #define GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT (1U) 147 #define GPU_AQHICLOCKCONTROL_CLK2D_DIS_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT) & GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK) 148 #define GPU_AQHICLOCKCONTROL_CLK2D_DIS_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK) >> GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT) 149 150 /* Bitfield definition for register: AQHILDLE */ 151 /* 152 * AXI_LP (R) 153 * 154 * axi is in low power mode 155 */ 156 #define GPU_AQHILDLE_AXI_LP_MASK (0x80000000UL) 157 #define GPU_AQHILDLE_AXI_LP_SHIFT (31U) 158 #define GPU_AQHILDLE_AXI_LP_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_AXI_LP_MASK) >> GPU_AQHILDLE_AXI_LP_SHIFT) 159 160 /* 161 * IDLE_BLT (R) 162 * 163 * BLT is idle or not present 164 */ 165 #define GPU_AQHILDLE_IDLE_BLT_MASK (0x1000U) 166 #define GPU_AQHILDLE_IDLE_BLT_SHIFT (12U) 167 #define GPU_AQHILDLE_IDLE_BLT_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_BLT_MASK) >> GPU_AQHILDLE_IDLE_BLT_SHIFT) 168 169 /* 170 * IDLE_TS (R) 171 * 172 * Tessellation Engine is idle 173 */ 174 #define GPU_AQHILDLE_IDLE_TS_MASK (0x800U) 175 #define GPU_AQHILDLE_IDLE_TS_SHIFT (11U) 176 #define GPU_AQHILDLE_IDLE_TS_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_TS_MASK) >> GPU_AQHILDLE_IDLE_TS_SHIFT) 177 178 /* 179 * IDLE_FP (R) 180 * 181 * FP is idle or not present 182 */ 183 #define GPU_AQHILDLE_IDLE_FP_MASK (0x400U) 184 #define GPU_AQHILDLE_IDLE_FP_SHIFT (10U) 185 #define GPU_AQHILDLE_IDLE_FP_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_FP_MASK) >> GPU_AQHILDLE_IDLE_FP_SHIFT) 186 187 /* 188 * IDLE_IM (R) 189 * 190 * Image Engine is idle 191 */ 192 #define GPU_AQHILDLE_IDLE_IM_MASK (0x200U) 193 #define GPU_AQHILDLE_IDLE_IM_SHIFT (9U) 194 #define GPU_AQHILDLE_IDLE_IM_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_IM_MASK) >> GPU_AQHILDLE_IDLE_IM_SHIFT) 195 196 /* 197 * IDLE_VG (R) 198 * 199 * Vector Graphics Engine is idle 200 */ 201 #define GPU_AQHILDLE_IDLE_VG_MASK (0x100U) 202 #define GPU_AQHILDLE_IDLE_VG_SHIFT (8U) 203 #define GPU_AQHILDLE_IDLE_VG_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_VG_MASK) >> GPU_AQHILDLE_IDLE_VG_SHIFT) 204 205 /* 206 * IDLE_TX (R) 207 * 208 * TX is idle or not present 209 */ 210 #define GPU_AQHILDLE_IDLE_TX_MASK (0x80U) 211 #define GPU_AQHILDLE_IDLE_TX_SHIFT (7U) 212 #define GPU_AQHILDLE_IDLE_TX_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_TX_MASK) >> GPU_AQHILDLE_IDLE_TX_SHIFT) 213 214 /* 215 * IDLE_RA (R) 216 * 217 * RA is idle or not present 218 */ 219 #define GPU_AQHILDLE_IDLE_RA_MASK (0x40U) 220 #define GPU_AQHILDLE_IDLE_RA_SHIFT (6U) 221 #define GPU_AQHILDLE_IDLE_RA_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_RA_MASK) >> GPU_AQHILDLE_IDLE_RA_SHIFT) 222 223 /* 224 * IDLE_SE (R) 225 * 226 * SE is idle or not present 227 */ 228 #define GPU_AQHILDLE_IDLE_SE_MASK (0x20U) 229 #define GPU_AQHILDLE_IDLE_SE_SHIFT (5U) 230 #define GPU_AQHILDLE_IDLE_SE_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_SE_MASK) >> GPU_AQHILDLE_IDLE_SE_SHIFT) 231 232 /* 233 * IDLE_PA (R) 234 * 235 * PA is idle or not present 236 */ 237 #define GPU_AQHILDLE_IDLE_PA_MASK (0x10U) 238 #define GPU_AQHILDLE_IDLE_PA_SHIFT (4U) 239 #define GPU_AQHILDLE_IDLE_PA_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_PA_MASK) >> GPU_AQHILDLE_IDLE_PA_SHIFT) 240 241 /* 242 * IDLE_SH (R) 243 * 244 * SH is idle or not present 245 */ 246 #define GPU_AQHILDLE_IDLE_SH_MASK (0x8U) 247 #define GPU_AQHILDLE_IDLE_SH_SHIFT (3U) 248 #define GPU_AQHILDLE_IDLE_SH_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_SH_MASK) >> GPU_AQHILDLE_IDLE_SH_SHIFT) 249 250 /* 251 * IDLE_PE (R) 252 * 253 * Pixel engine is idle 254 */ 255 #define GPU_AQHILDLE_IDLE_PE_MASK (0x4U) 256 #define GPU_AQHILDLE_IDLE_PE_SHIFT (2U) 257 #define GPU_AQHILDLE_IDLE_PE_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_PE_MASK) >> GPU_AQHILDLE_IDLE_PE_SHIFT) 258 259 /* 260 * IDLE_DE (R) 261 * 262 * DE is dile or not present 263 */ 264 #define GPU_AQHILDLE_IDLE_DE_MASK (0x2U) 265 #define GPU_AQHILDLE_IDLE_DE_SHIFT (1U) 266 #define GPU_AQHILDLE_IDLE_DE_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_DE_MASK) >> GPU_AQHILDLE_IDLE_DE_SHIFT) 267 268 /* 269 * IDLE_FE (R) 270 * 271 * 0: fetch engine is busy 1:fetch engine is idle 272 */ 273 #define GPU_AQHILDLE_IDLE_FE_MASK (0x1U) 274 #define GPU_AQHILDLE_IDLE_FE_SHIFT (0U) 275 #define GPU_AQHILDLE_IDLE_FE_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_FE_MASK) >> GPU_AQHILDLE_IDLE_FE_SHIFT) 276 277 /* Bitfield definition for register: AQINTRACKNOWLEDGE */ 278 /* 279 * INTR_VEC (R) 280 * 281 * for each interrupt event, 0=clear,1=interrupt active 282 */ 283 #define GPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK (0xFFFFFFFFUL) 284 #define GPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT (0U) 285 #define GPU_AQINTRACKNOWLEDGE_INTR_VEC_GET(x) (((uint32_t)(x) & GPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK) >> GPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT) 286 287 /* Bitfield definition for register: AQINTRENBL */ 288 /* 289 * INTR_ENBL_VEC (RW) 290 * 291 * 0=disable interrupt; 1=enable interrupt 292 */ 293 #define GPU_AQINTRENBL_INTR_ENBL_VEC_MASK (0xFFFFFFFFUL) 294 #define GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT (0U) 295 #define GPU_AQINTRENBL_INTR_ENBL_VEC_SET(x) (((uint32_t)(x) << GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT) & GPU_AQINTRENBL_INTR_ENBL_VEC_MASK) 296 #define GPU_AQINTRENBL_INTR_ENBL_VEC_GET(x) (((uint32_t)(x) & GPU_AQINTRENBL_INTR_ENBL_VEC_MASK) >> GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT) 297 298 /* Bitfield definition for register: GCCHIPREV */ 299 /* 300 * REV (R) 301 * 302 * revision 303 */ 304 #define GPU_GCCHIPREV_REV_MASK (0xFFFFFFFFUL) 305 #define GPU_GCCHIPREV_REV_SHIFT (0U) 306 #define GPU_GCCHIPREV_REV_GET(x) (((uint32_t)(x) & GPU_GCCHIPREV_REV_MASK) >> GPU_GCCHIPREV_REV_SHIFT) 307 308 /* Bitfield definition for register: GCCHIPDATE */ 309 /* 310 * DATE (R) 311 * 312 * date 313 */ 314 #define GPU_GCCHIPDATE_DATE_MASK (0xFFFFFFFFUL) 315 #define GPU_GCCHIPDATE_DATE_SHIFT (0U) 316 #define GPU_GCCHIPDATE_DATE_GET(x) (((uint32_t)(x) & GPU_GCCHIPDATE_DATE_MASK) >> GPU_GCCHIPDATE_DATE_SHIFT) 317 318 /* Bitfield definition for register: GCREGHICHIPPATCHREV */ 319 /* 320 * PATCH_REV (R) 321 * 322 * patch revision 323 */ 324 #define GPU_GCREGHICHIPPATCHREV_PATCH_REV_MASK (0xFFU) 325 #define GPU_GCREGHICHIPPATCHREV_PATCH_REV_SHIFT (0U) 326 #define GPU_GCREGHICHIPPATCHREV_PATCH_REV_GET(x) (((uint32_t)(x) & GPU_GCREGHICHIPPATCHREV_PATCH_REV_MASK) >> GPU_GCREGHICHIPPATCHREV_PATCH_REV_SHIFT) 327 328 /* Bitfield definition for register: GCPRODUCTID */ 329 /* 330 * TYPE (R) 331 * 332 * product type is 3:VG 333 */ 334 #define GPU_GCPRODUCTID_TYPE_MASK (0xF000000UL) 335 #define GPU_GCPRODUCTID_TYPE_SHIFT (24U) 336 #define GPU_GCPRODUCTID_TYPE_GET(x) (((uint32_t)(x) & GPU_GCPRODUCTID_TYPE_MASK) >> GPU_GCPRODUCTID_TYPE_SHIFT) 337 338 /* 339 * NUM (R) 340 * 341 * product number is 265 342 */ 343 #define GPU_GCPRODUCTID_NUM_MASK (0xFFFFF0UL) 344 #define GPU_GCPRODUCTID_NUM_SHIFT (4U) 345 #define GPU_GCPRODUCTID_NUM_GET(x) (((uint32_t)(x) & GPU_GCPRODUCTID_NUM_MASK) >> GPU_GCPRODUCTID_NUM_SHIFT) 346 347 /* 348 * GRADE_LEVEL (R) 349 * 350 * 0:None_no extra letter on the product name for this core 1:nano 5:nano ultra 351 */ 352 #define GPU_GCPRODUCTID_GRADE_LEVEL_MASK (0xFU) 353 #define GPU_GCPRODUCTID_GRADE_LEVEL_SHIFT (0U) 354 #define GPU_GCPRODUCTID_GRADE_LEVEL_GET(x) (((uint32_t)(x) & GPU_GCPRODUCTID_GRADE_LEVEL_MASK) >> GPU_GCPRODUCTID_GRADE_LEVEL_SHIFT) 355 356 /* Bitfield definition for register: GCMODULEPOWERCONTROLS */ 357 /* 358 * TURN_OFF_COUNTER (RW) 359 * 360 * counter value for clock gating the module if the module is idle for this amout of clock cycles 361 */ 362 #define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK (0xFFFF0000UL) 363 #define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT (16U) 364 #define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT) & GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK) 365 #define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK) >> GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT) 366 367 /* 368 * TURN_ON_COUNTER (RW) 369 * 370 * number of clock cycle gating the module if the modules is idle for this amout of clockk cycles 371 */ 372 #define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK (0xF0U) 373 #define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT (4U) 374 #define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT) & GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK) 375 #define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK) >> GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT) 376 377 /* 378 * DISABLE_STARVE_MODULE_CLOCK_GATING (RW) 379 * 380 * disable module level clock gating for starve/idle condition 381 */ 382 #define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK (0x4U) 383 #define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT (2U) 384 #define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK) 385 #define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT) 386 387 /* 388 * DISABLE_STALL_MODULE_CLOCK_GATING (RW) 389 * 390 * disable module level clock gating for stall condition 391 */ 392 #define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK (0x2U) 393 #define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT (1U) 394 #define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK) 395 #define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT) 396 397 /* 398 * ENABLE_MODULE_CLOCK_GATING (RW) 399 * 400 * enable module level clock gating 401 */ 402 #define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK (0x1U) 403 #define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT (0U) 404 #define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK) 405 #define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT) 406 407 /* Bitfield definition for register: GCMODULEPOWERMODULECONTROL */ 408 /* 409 * DISABLE_MODULE_CLOCKGATING_FLEXA (RW) 410 * 411 * disables module level clock gating for flexa, not supported for all variants 412 */ 413 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK (0x1000U) 414 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT (12U) 415 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK) 416 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT) 417 418 /* 419 * DISABLE_MODULE_CLOCK_GATING_TS (RW) 420 * 421 * disables module level clock gating for TS 422 */ 423 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK (0x800U) 424 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT (11U) 425 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK) 426 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT) 427 428 /* 429 * DISABLE_MODULE_CLOCK_GATING_IM (RW) 430 * 431 * disables module level clock gating for IM 432 */ 433 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK (0x200U) 434 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT (9U) 435 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK) 436 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT) 437 438 /* 439 * DISABLE_MODULE_CLOCK_GATING_VG (RW) 440 * 441 * disables module lelvel clock gating for VG 442 */ 443 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK (0x100U) 444 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT (8U) 445 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK) 446 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT) 447 448 /* 449 * DISABLE_MODULE_CLOCK_GATING_PE (RW) 450 * 451 * disables module level clock gating for PE 452 */ 453 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK (0x4U) 454 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT (2U) 455 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK) 456 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT) 457 458 /* 459 * DISABLE_MODULE_CLOCK_GATING_FE (RW) 460 * 461 * disables module level clock gating for FE 462 */ 463 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK (0x1U) 464 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT (0U) 465 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK) 466 #define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT) 467 468 /* Bitfield definition for register: GCMODULEPOWERMODULESTATUS */ 469 /* 470 * MODULE_CLOCK_GATED_FLEXA (R) 471 * 472 * module level ckock gating is on for flexa 473 */ 474 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_MASK (0x1000U) 475 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_SHIFT (12U) 476 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_SHIFT) 477 478 /* 479 * MODULE_CLOCK_GATED_TS (R) 480 * 481 * module level ckock gating is on for ts 482 */ 483 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_MASK (0x800U) 484 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_SHIFT (11U) 485 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_SHIFT) 486 487 /* 488 * MODULE_CLOCK_GATED_IM (R) 489 * 490 * module level clock gating is on for IM 491 */ 492 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_MASK (0x200U) 493 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_SHIFT (9U) 494 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_SHIFT) 495 496 /* 497 * MODULE_CLOCK_GATED_VG (R) 498 * 499 * module level clock gating is on for VG 500 */ 501 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_MASK (0x100U) 502 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_SHIFT (8U) 503 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_SHIFT) 504 505 /* 506 * MODULE_CLOCK_GATED_PE (R) 507 * 508 * module level clock gating is on for PE 509 */ 510 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_MASK (0x4U) 511 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_SHIFT (2U) 512 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_SHIFT) 513 514 /* 515 * MODULE_CLOCK_GATED_FE (R) 516 * 517 * module level clock gating is on for FE 518 */ 519 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_MASK (0x1U) 520 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_SHIFT (0U) 521 #define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_SHIFT) 522 523 /* Bitfield definition for register: AQMEMORYFEPAGETABLE */ 524 /* 525 * BASE_ADDRESS (RW) 526 * 527 * base address for the FE virtual address lookup table 528 */ 529 #define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK (0xFFFFF000UL) 530 #define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT (12U) 531 #define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SET(x) (((uint32_t)(x) << GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT) & GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK) 532 #define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_GET(x) (((uint32_t)(x) & GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK) >> GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT) 533 534 /* Bitfield definition for register: AQMEMORYDEBUG */ 535 /* 536 * ZCOMP_LIMIT (RW) 537 * 538 * not relevant for vector graphics IP 539 */ 540 #define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK (0x3F000000UL) 541 #define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT (24U) 542 #define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SET(x) (((uint32_t)(x) << GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT) & GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK) 543 #define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_GET(x) (((uint32_t)(x) & GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK) >> GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT) 544 545 /* 546 * MAX_OUTSTANDING_READS (RW) 547 * 548 * limits the total number of outstanding read requests 549 */ 550 #define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK (0xFFU) 551 #define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT (0U) 552 #define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SET(x) (((uint32_t)(x) << GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT) & GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK) 553 #define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_GET(x) (((uint32_t)(x) & GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK) >> GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT) 554 555 /* Bitfield definition for register: AQREGISTERTIMINGCONTROL */ 556 /* 557 * POWER_DOWN (RW) 558 * 559 * powerdown memory 560 */ 561 #define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK (0x100000UL) 562 #define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT (20U) 563 #define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK) 564 #define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK) >> GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT) 565 566 /* 567 * FAST_WTC (RW) 568 * 569 * WTC for fast rams 570 */ 571 #define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK (0xC0000UL) 572 #define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT (18U) 573 #define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK) 574 #define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT) 575 576 /* 577 * FAST_RTC (RW) 578 * 579 * RTC for fast rams 580 */ 581 #define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK (0x30000UL) 582 #define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT (16U) 583 #define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK) 584 #define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT) 585 586 /* 587 * FOR_RF2P (RW) 588 * 589 * for 2 port ram 590 */ 591 #define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK (0xFF00U) 592 #define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT (8U) 593 #define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK) 594 #define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT) 595 596 /* 597 * FOR_RF1P (RW) 598 * 599 * for 1 port ram 600 */ 601 #define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK (0xFFU) 602 #define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT (0U) 603 #define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK) 604 #define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT) 605 606 /* Bitfield definition for register: GCREGFETCHADDRESS */ 607 /* 608 * ADDRESS (RW) 609 * 610 * address of command buffer 611 */ 612 #define GPU_GCREGFETCHADDRESS_ADDRESS_MASK (0xFFFFFFFCUL) 613 #define GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT (2U) 614 #define GPU_GCREGFETCHADDRESS_ADDRESS_SET(x) (((uint32_t)(x) << GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT) & GPU_GCREGFETCHADDRESS_ADDRESS_MASK) 615 #define GPU_GCREGFETCHADDRESS_ADDRESS_GET(x) (((uint32_t)(x) & GPU_GCREGFETCHADDRESS_ADDRESS_MASK) >> GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT) 616 617 /* 618 * TYPE (RW) 619 * 620 * 0=system 2=vritual 1=local 621 */ 622 #define GPU_GCREGFETCHADDRESS_TYPE_MASK (0x3U) 623 #define GPU_GCREGFETCHADDRESS_TYPE_SHIFT (0U) 624 #define GPU_GCREGFETCHADDRESS_TYPE_SET(x) (((uint32_t)(x) << GPU_GCREGFETCHADDRESS_TYPE_SHIFT) & GPU_GCREGFETCHADDRESS_TYPE_MASK) 625 #define GPU_GCREGFETCHADDRESS_TYPE_GET(x) (((uint32_t)(x) & GPU_GCREGFETCHADDRESS_TYPE_MASK) >> GPU_GCREGFETCHADDRESS_TYPE_SHIFT) 626 627 /* Bitfield definition for register: GCREGFETCHCONTROL */ 628 /* 629 * COUNT (RW) 630 * 631 * number of 64bit words to fetch 632 */ 633 #define GPU_GCREGFETCHCONTROL_COUNT_MASK (0x1FFFFFUL) 634 #define GPU_GCREGFETCHCONTROL_COUNT_SHIFT (0U) 635 #define GPU_GCREGFETCHCONTROL_COUNT_SET(x) (((uint32_t)(x) << GPU_GCREGFETCHCONTROL_COUNT_SHIFT) & GPU_GCREGFETCHCONTROL_COUNT_MASK) 636 #define GPU_GCREGFETCHCONTROL_COUNT_GET(x) (((uint32_t)(x) & GPU_GCREGFETCHCONTROL_COUNT_MASK) >> GPU_GCREGFETCHCONTROL_COUNT_SHIFT) 637 638 /* Bitfield definition for register: GCREGCURRENTFETCHADDRESS */ 639 /* 640 * ADDRESS (R) 641 * 642 * address 643 */ 644 #define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_MASK (0xFFFFFFFFUL) 645 #define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_SHIFT (0U) 646 #define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_GET(x) (((uint32_t)(x) & GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_MASK) >> GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_SHIFT) 647 648 649 650 651 #endif /* HPM_GPU_H */ 652