1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_hal_rcc_ex.c
4 * @author MCD Application Team
5 * @brief Extended RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities RCC extension peripheral:
8 * + Extended Peripheral Control functions
9 *
10 ******************************************************************************
11 * @attention
12 *
13 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
14 * All rights reserved.</center></h2>
15 *
16 * This software component is licensed by ST under BSD 3-Clause license,
17 * the "License"; You may not use this file except in compliance with the
18 * License. You may obtain a copy of the License at:
19 * opensource.org/licenses/BSD-3-Clause
20 *
21 ******************************************************************************
22 */
23
24 /* Includes ------------------------------------------------------------------*/
25 #include "stm32mp1xx_hal.h"
26
27 /** @addtogroup STM32MP1xx_HAL_Driver
28 * @{
29 */
30
31 /** @defgroup RCCEx RCCEx
32 * @brief RCC HAL module driver
33 * @{
34 */
35
36 #ifdef HAL_RCC_MODULE_ENABLED
37
38 /* Private typedef -----------------------------------------------------------*/
39 #define LSE_MASK (RCC_BDCR_LSEON | RCC_BDCR_LSEBYP | RCC_BDCR_DIGBYP)
40 /* Private defines -----------------------------------------------------------*/
41 /* Private macros ------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private function prototypes -----------------------------------------------*/
44 /** @defgroup RCCEx_Private_Function_Prototypes RCCEx Private Functions Prototypes
45 * @{
46 */
47
48 /**
49 * @}
50 */
51
52 /* Exported functions --------------------------------------------------------*/
53
54 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
55 * @{
56 */
57
58 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
59 * @brief Extended Peripheral Control functions
60 *
61 @verbatim
62 ===============================================================================
63 ##### Extended Peripheral Control functions #####
64 ===============================================================================
65 [..]
66 This subsection provides a set of functions allowing to control the RCC Clocks
67 frequencies.
68 [..]
69 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
70 select the RTC clock source; in this case the Backup domain will be reset in
71 order to modify the RTC Clock source, as consequence RTC registers (including
72 the backup registers) and RCC_BDCR register are set to their reset values.
73
74 @endverbatim
75 * @{
76 */
77 /**
78 * @brief Configures PLL2
79 * @param pll2: pointer to an RCC_PLLInitTypeDef structure
80 *
81 * @retval HAL status
82 */
83
RCCEx_PLL2_Config(RCC_PLLInitTypeDef * pll2)84 HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLLInitTypeDef *pll2)
85 {
86 uint32_t tickstart;
87
88 /* Check the parameters */
89 assert_param(IS_RCC_PLL(pll2->PLLState));
90 if ((pll2->PLLState) != RCC_PLL_NONE)
91 {
92 /* Check if the PLL is used as system clock or not (MPU, MCU, AXISS)*/
93 if (!__IS_PLL2_IN_USE()) /* If not used then */
94 {
95 if ((pll2->PLLState) == RCC_PLL_ON)
96 {
97 /* Check the parameters */
98 assert_param(IS_RCC_PLLMODE(pll2->PLLMODE));
99 assert_param(IS_RCC_PLL12SOURCE(pll2->PLLSource));
100 assert_param(IS_RCC_PLLM2_VALUE(pll2->PLLM));
101 if (pll2->PLLMODE == RCC_PLL_FRACTIONAL)
102 {
103 assert_param(IS_RCC_PLLN2_FRAC_VALUE(pll2->PLLN));
104 }
105 else
106 {
107 assert_param(IS_RCC_PLLN2_INT_VALUE(pll2->PLLN));
108 }
109 assert_param(IS_RCC_PLLP2_VALUE(pll2->PLLP));
110 assert_param(IS_RCC_PLLQ2_VALUE(pll2->PLLQ));
111 assert_param(IS_RCC_PLLR2_VALUE(pll2->PLLR));
112
113 /* Check that PLL2 OSC clock source is already set */
114 if ((__HAL_RCC_GET_PLL12_SOURCE() != RCC_PLL12SOURCE_HSI) &&
115 (__HAL_RCC_GET_PLL12_SOURCE() != RCC_PLL12SOURCE_HSE))
116 {
117 return HAL_ERROR;
118 }
119
120 /*Disable the post-dividers*/
121 __HAL_RCC_PLL2CLKOUT_DISABLE(RCC_PLL2_DIVP | RCC_PLL2_DIVQ | RCC_PLL2_DIVR);
122 /* Disable the main PLL. */
123 __HAL_RCC_PLL2_DISABLE();
124
125 /* Get Start Tick*/
126 tickstart = HAL_GetTick();
127
128 /* Wait till PLL is ready */
129 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
130 {
131 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
132 {
133 return HAL_TIMEOUT;
134 }
135 }
136
137 /*The PLL configuration below must be done before enabling the PLL:
138 -Selection of PLL clock entry (HSI or HSE)
139 -Frequency input range (PLLxRGE)
140 -Division factors (DIVMx, DIVNx, DIVPx, DIVQx & DIVRx)
141 Once the PLL is enabled, these parameters can not be changed.
142 If the User wants to change the PLL parameters he must disable the concerned PLL (PLLxON=0) and wait for the
143 PLLxRDY flag to be at 0.
144 The PLL configuration below can be done at any time:
145 -Enable/Disable of output clock dividers (DIVPxEN, DIVQxEN & DIVRxEN)
146 -Fractional Division Enable (PLLxFRACNEN)
147 -Fractional Division factor (FRACNx)*/
148
149 /* Do not change pll src if already in use */
150 if (__IS_PLL1_IN_USE())
151 {
152 if (pll2->PLLSource != __HAL_RCC_GET_PLL12_SOURCE())
153 {
154 return HAL_ERROR;
155 }
156 }
157 else
158 {
159 /* Configure PLL1 and PLL2 clock source */
160 __HAL_RCC_PLL12_SOURCE(pll2->PLLSource);
161 }
162
163 /* Configure the PLL2 multiplication and division factors. */
164 __HAL_RCC_PLL2_CONFIG(
165 pll2->PLLM,
166 pll2->PLLN,
167 pll2->PLLP,
168 pll2->PLLQ,
169 pll2->PLLR);
170
171
172 /* Configure the Fractional Divider */
173 __HAL_RCC_PLL2FRACV_DISABLE(); //Set FRACLE to ‘0’
174 /* In integer or clock spreading mode the application shall ensure that a 0 is loaded into the SDM */
175 if ((pll2->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) || (pll2->PLLMODE == RCC_PLL_INTEGER))
176 {
177 /* Do not use the fractional divider */
178 __HAL_RCC_PLL2FRACV_CONFIG(0); //Set FRACV to '0'
179 }
180 else
181 {
182 /* Configure PLL PLL2FRACV in fractional mode*/
183 __HAL_RCC_PLL2FRACV_CONFIG(pll2->PLLFRACV);
184 }
185 __HAL_RCC_PLL2FRACV_ENABLE(); //Set FRACLE to ‘1’
186
187
188 /* Configure the Spread Control */
189 if (pll2->PLLMODE == RCC_PLL_SPREAD_SPECTRUM)
190 {
191 assert_param(IS_RCC_INC_STEP(pll2->INC_STEP));
192 assert_param(IS_RCC_SSCG_MODE(pll2->SSCG_MODE));
193 assert_param(IS_RCC_RPDFN_DIS(pll2->RPDFN_DIS));
194 assert_param(IS_RCC_TPDFN_DIS(pll2->TPDFN_DIS));
195 assert_param(IS_RCC_MOD_PER(pll2->MOD_PER));
196
197 __HAL_RCC_PLL2CSGCONFIG(pll2->MOD_PER, pll2->TPDFN_DIS, pll2->RPDFN_DIS,
198 pll2->SSCG_MODE, pll2->INC_STEP);
199 __HAL_RCC_PLL2_SSMODE_ENABLE();
200 }
201 else
202 {
203 __HAL_RCC_PLL2_SSMODE_DISABLE();
204 }
205
206
207 /* Enable the PLL2. */
208 __HAL_RCC_PLL2_ENABLE();
209
210 /* Get Start Tick*/
211 tickstart = HAL_GetTick();
212
213 /* Wait till PLL is ready */
214 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
215 {
216 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
217 {
218 return HAL_TIMEOUT;
219 }
220 }
221 /*Enable the post-dividers*/
222 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP | RCC_PLL2_DIVQ | RCC_PLL2_DIVR);
223 }
224 else
225 {
226 /*Disable the post-dividers*/
227 __HAL_RCC_PLL2CLKOUT_DISABLE(RCC_PLL2_DIVP | RCC_PLL2_DIVQ | RCC_PLL2_DIVR);
228 /* Disable the PLL2. */
229 __HAL_RCC_PLL2_DISABLE();
230
231 /* Get Start Tick*/
232 tickstart = HAL_GetTick();
233
234 /* Wait till PLL is ready */
235 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
236 {
237 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
238 {
239 return HAL_TIMEOUT;
240 }
241 }
242 }
243 }
244 else
245 {
246 return HAL_ERROR;
247 }
248 }
249 return HAL_OK;
250
251 }
252
253
254
255 /**
256 * @brief Configures PLL3
257 * @param pll3: pointer to a RCC_PLLInitTypeDef structure
258 *
259 * @retval HAL status
260 */
RCCEx_PLL3_Config(RCC_PLLInitTypeDef * pll3)261 HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLLInitTypeDef *pll3)
262 {
263
264 uint32_t tickstart;
265
266 /* Check the parameters */
267 assert_param(IS_RCC_PLL(pll3->PLLState));
268 if ((pll3->PLLState) != RCC_PLL_NONE)
269 {
270 /* Check if the PLL is used as system clock or not (MPU, MCU, AXISS)*/
271 if (!__IS_PLL3_IN_USE()) /* If not used then*/
272 {
273 if ((pll3->PLLState) == RCC_PLL_ON)
274 {
275 /* Check the parameters */
276 assert_param(IS_RCC_PLLMODE(pll3->PLLMODE));
277 assert_param(IS_RCC_PLL3SOURCE(pll3->PLLSource));
278 assert_param(IS_RCC_PLLM1_VALUE(pll3->PLLM));
279 if (pll3->PLLMODE == RCC_PLL_FRACTIONAL)
280 {
281 assert_param(IS_RCC_PLLN3_FRAC_VALUE(pll3->PLLN));
282 }
283 else
284 {
285 assert_param(IS_RCC_PLLN3_INT_VALUE(pll3->PLLN));
286 }
287 assert_param(IS_RCC_PLLP3_VALUE(pll3->PLLP));
288 assert_param(IS_RCC_PLLQ3_VALUE(pll3->PLLQ));
289 assert_param(IS_RCC_PLLR3_VALUE(pll3->PLLR));
290
291 /*Disable the post-dividers*/
292 __HAL_RCC_PLL3CLKOUT_DISABLE(RCC_PLL3_DIVP | RCC_PLL3_DIVQ | RCC_PLL3_DIVR);
293 /* Disable the main PLL. */
294 __HAL_RCC_PLL3_DISABLE();
295
296 /* Get Start Tick*/
297 tickstart = HAL_GetTick();
298
299 /* Wait till PLL is ready */
300 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != RESET)
301 {
302 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
303 {
304 return HAL_TIMEOUT;
305 }
306 }
307
308
309 /*The PLL configuration below must be done before enabling the PLL:
310 -Selection of PLL clock entry (HSI or CSI or HSE)
311 -Frequency input range (PLLxRGE)
312 -Division factors (DIVMx, DIVNx, DIVPx, DIVQx & DIVRx)
313 Once the PLL is enabled, these parameters can not be changed.
314 If the User wants to change the PLL parameters he must disable the concerned PLL (PLLxON=0) and wait for the
315 PLLxRDY flag to be at 0.
316 The PLL configuration below can be done at any time:
317 -Enable/Disable of output clock dividers (DIVPxEN, DIVQxEN & DIVRxEN)
318 -Fractional Division Enable (PLLxFRACNEN)
319 -Fractional Division factor (FRACNx)*/
320
321 /* Configure PLL3 clock source */
322 __HAL_RCC_PLL3_SOURCE(pll3->PLLSource);
323
324 /* Wait till PLL SOURCE is ready */
325 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3SRCRDY) == RESET)
326 {
327 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
328 {
329 return HAL_TIMEOUT;
330 }
331 }
332
333 /* Select PLL3 input reference frequency range */
334 __HAL_RCC_PLL3_IFRANGE(pll3->PLLRGE) ;
335
336 /* Configure the PLL3 multiplication and division factors. */
337 __HAL_RCC_PLL3_CONFIG(
338 pll3->PLLM,
339 pll3->PLLN,
340 pll3->PLLP,
341 pll3->PLLQ,
342 pll3->PLLR);
343
344 /* Configure the Fractional Divider */
345 __HAL_RCC_PLL3FRACV_DISABLE(); //Set FRACLE to ‘0’
346 /* In integer or clock spreading mode the application shall ensure that a 0 is loaded into the SDM */
347 if ((pll3->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) || (pll3->PLLMODE == RCC_PLL_INTEGER))
348 {
349 /* Do not use the fractional divider */
350 __HAL_RCC_PLL3FRACV_CONFIG(0); //Set FRACV to '0'
351 }
352 else
353 {
354 /* Configure PLL PLL3FRACV in fractional mode*/
355 __HAL_RCC_PLL3FRACV_CONFIG(pll3->PLLFRACV);
356 }
357 __HAL_RCC_PLL3FRACV_ENABLE(); //Set FRACLE to ‘1’
358
359
360 /* Configure the Spread Control */
361 if (pll3->PLLMODE == RCC_PLL_SPREAD_SPECTRUM)
362 {
363 assert_param(IS_RCC_INC_STEP(pll3->INC_STEP));
364 assert_param(IS_RCC_SSCG_MODE(pll3->SSCG_MODE));
365 assert_param(IS_RCC_RPDFN_DIS(pll3->RPDFN_DIS));
366 assert_param(IS_RCC_TPDFN_DIS(pll3->TPDFN_DIS));
367 assert_param(IS_RCC_MOD_PER(pll3->MOD_PER));
368
369 __HAL_RCC_PLL3CSGCONFIG(pll3->MOD_PER, pll3->TPDFN_DIS, pll3->RPDFN_DIS,
370 pll3->SSCG_MODE, pll3->INC_STEP);
371 __HAL_RCC_PLL3_SSMODE_ENABLE();
372 }
373 else
374 {
375 __HAL_RCC_PLL3_SSMODE_DISABLE();
376 }
377
378
379 /* Enable the PLL3. */
380 __HAL_RCC_PLL3_ENABLE();
381
382 /* Get Start Tick*/
383 tickstart = HAL_GetTick();
384
385 /* Wait till PLL is ready */
386 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == RESET)
387 {
388 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
389 {
390 return HAL_TIMEOUT;
391 }
392 }
393 /* Enable the post-dividers */
394 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP | RCC_PLL3_DIVQ | RCC_PLL3_DIVR);
395 }
396 else
397 {
398 /*Disable the post-dividers*/
399 __HAL_RCC_PLL3CLKOUT_DISABLE(RCC_PLL3_DIVP | RCC_PLL3_DIVQ | RCC_PLL3_DIVR);
400 /* Disable the PLL3. */
401 __HAL_RCC_PLL3_DISABLE();
402
403 /* Get Start Tick*/
404 tickstart = HAL_GetTick();
405
406 /* Wait till PLL is ready */
407 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != RESET)
408 {
409 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
410 {
411 return HAL_TIMEOUT;
412 }
413 }
414 }
415 }
416 else
417 {
418 return HAL_ERROR;
419 }
420 }
421 return HAL_OK;
422 }
423
424
425 /**
426 * @brief Configures PLL4
427 * @param pll4: pointer to a RCC_PLLInitTypeDef structure
428 *
429 * @retval HAL status
430 */
RCCEx_PLL4_Config(RCC_PLLInitTypeDef * pll4)431 HAL_StatusTypeDef RCCEx_PLL4_Config(RCC_PLLInitTypeDef *pll4)
432 {
433
434 uint32_t tickstart;
435
436 /* Check the parameters */
437 assert_param(IS_RCC_PLL(pll4->PLLState));
438 if ((pll4->PLLState) != RCC_PLL_NONE)
439 {
440
441 if ((pll4->PLLState) == RCC_PLL_ON)
442 {
443 /* Check the parameters */
444 assert_param(IS_RCC_PLLMODE(pll4->PLLMODE));
445 assert_param(IS_RCC_PLL4SOURCE(pll4->PLLSource));
446 assert_param(IS_RCC_PLLM4_VALUE(pll4->PLLM));
447 if (pll4->PLLMODE == RCC_PLL_FRACTIONAL)
448 {
449 assert_param(IS_RCC_PLLN4_FRAC_VALUE(pll4->PLLN));
450 }
451 else
452 {
453 assert_param(IS_RCC_PLLN4_INT_VALUE(pll4->PLLN));
454 }
455 assert_param(IS_RCC_PLLP4_VALUE(pll4->PLLP));
456 assert_param(IS_RCC_PLLQ4_VALUE(pll4->PLLQ));
457 assert_param(IS_RCC_PLLR4_VALUE(pll4->PLLR));
458
459 /*Disable the post-dividers*/
460 __HAL_RCC_PLL4CLKOUT_DISABLE(RCC_PLL4_DIVP | RCC_PLL4_DIVQ | RCC_PLL4_DIVR);
461 /* Disable the main PLL. */
462 __HAL_RCC_PLL4_DISABLE();
463
464 /* Get Start Tick*/
465 tickstart = HAL_GetTick();
466
467 /* Wait till PLL is ready */
468 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) != RESET)
469 {
470 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
471 {
472 return HAL_TIMEOUT;
473 }
474 }
475
476
477 /*The PLL configuration below must be done before enabling the PLL:
478 -Selection of PLL clock entry (HSI or CSI or HSE)
479 -Frequency input range (PLLxRGE)
480 -Division factors (DIVMx, DIVNx, DIVPx, DIVQx & DIVRx)
481 Once the PLL is enabled, these parameters can not be changed.
482 If the User wants to change the PLL parameters he must disable the concerned PLL (PLLxON=0) and wait for the
483 PLLxRDY flag to be at 0.
484 The PLL configuration below can be done at any time:
485 -Enable/Disable of output clock dividers (DIVPxEN, DIVQxEN & DIVRxEN)
486 -Fractional Division Enable (PLLxFRACNEN)
487 -Fractional Division factor (FRACNx)*/
488
489 /* Configure PLL4 and PLL4 clock source */
490 __HAL_RCC_PLL4_SOURCE(pll4->PLLSource);
491
492 /* Wait till PLL SOURCE is ready */
493 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4SRCRDY) == RESET)
494 {
495 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
496 {
497 return HAL_TIMEOUT;
498 }
499 }
500
501 /* Select PLL4 input reference frequency range */
502 __HAL_RCC_PLL4_IFRANGE(pll4->PLLRGE) ;
503
504 /* Configure the PLL4 multiplication and division factors. */
505 __HAL_RCC_PLL4_CONFIG(
506 pll4->PLLM,
507 pll4->PLLN,
508 pll4->PLLP,
509 pll4->PLLQ,
510 pll4->PLLR);
511
512 /* Configure the Fractional Divider */
513 __HAL_RCC_PLL4FRACV_DISABLE(); //Set FRACLE to ‘0’
514 /* In integer or clock spreading mode the application shall ensure that a 0 is loaded into the SDM */
515 if ((pll4->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) || (pll4->PLLMODE == RCC_PLL_INTEGER))
516 {
517 /* Do not use the fractional divider */
518 __HAL_RCC_PLL4FRACV_CONFIG(0); //Set FRACV to '0'
519 }
520 else
521 {
522 /* Configure PLL PLL4FRACV in fractional mode*/
523 __HAL_RCC_PLL4FRACV_CONFIG(pll4->PLLFRACV);
524 }
525 __HAL_RCC_PLL4FRACV_ENABLE(); //Set FRACLE to ‘1’
526
527 /* Configure the Spread Control */
528 if (pll4->PLLMODE == RCC_PLL_SPREAD_SPECTRUM)
529 {
530 assert_param(IS_RCC_INC_STEP(pll4->INC_STEP));
531 assert_param(IS_RCC_SSCG_MODE(pll4->SSCG_MODE));
532 assert_param(IS_RCC_RPDFN_DIS(pll4->RPDFN_DIS));
533 assert_param(IS_RCC_TPDFN_DIS(pll4->TPDFN_DIS));
534 assert_param(IS_RCC_MOD_PER(pll4->MOD_PER));
535
536 __HAL_RCC_PLL4CSGCONFIG(pll4->MOD_PER, pll4->TPDFN_DIS, pll4->RPDFN_DIS,
537 pll4->SSCG_MODE, pll4->INC_STEP);
538 __HAL_RCC_PLL4_SSMODE_ENABLE();
539 }
540 else
541 {
542 __HAL_RCC_PLL4_SSMODE_DISABLE();
543 }
544
545 /* Enable the PLL4. */
546 __HAL_RCC_PLL4_ENABLE();
547
548 /* Get Start Tick*/
549 tickstart = HAL_GetTick();
550
551 /* Wait till PLL is ready */
552 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) == RESET)
553 {
554 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
555 {
556 return HAL_TIMEOUT;
557 }
558 }
559 /* Enable PLL4P Clock output. */
560 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP | RCC_PLL4_DIVQ | RCC_PLL4_DIVR);
561 }
562 else
563 {
564 /*Disable the post-dividers*/
565 __HAL_RCC_PLL4CLKOUT_DISABLE(RCC_PLL4_DIVP | RCC_PLL4_DIVQ | RCC_PLL4_DIVR);
566 /* Disable the PLL4. */
567 __HAL_RCC_PLL4_DISABLE();
568
569 /* Get Start Tick*/
570 tickstart = HAL_GetTick();
571
572 /* Wait till PLL is ready */
573 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) != RESET)
574 {
575 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
576 {
577 return HAL_TIMEOUT;
578 }
579 }
580 }
581 }
582 return HAL_OK;
583 }
584
585 /**
586 * @brief Initializes the RCC extended peripherals clocks according to the
587 * specified parameters in the RCC_PeriphCLKInitTypeDef.
588 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
589 * contains a field PeriphClockSelection which can be a combination of
590 * the following values:
591 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
592 * @arg @ref RCC_PERIPHCLK_UART24 USART2 and UART4 peripheral clock
593 * @arg @ref RCC_PERIPHCLK_UART35 USART3 and UART5 peripheral clock
594 * @arg @ref RCC_PERIPHCLK_I2C12 I2C1 and I2C2 peripheral clock
595 * @arg @ref RCC_PERIPHCLK_I2C35 I2C3 and I2C5 peripheral clock
596 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
597 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
598 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock
599 * @arg @ref RCC_PERIPHCLK_USBPHY USBPHY peripheral clock
600 * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
601 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
602 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
603 * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock
604 * @arg @ref RCC_PERIPHCLK_UART78 UART7 and UART8 peripheral clock
605 * @arg @ref RCC_PERIPHCLK_I2C46 I2C4 and I2C6 peripheral clock
606 * @arg @ref RCC_PERIPHCLK_LPTIM23 LPTIM2 and LPTIM3 peripheral clock
607 * @arg @ref RCC_PERIPHCLK_LPTIM45 LPTIM4 and LPTIM5 peripheral clock
608 * @arg @ref RCC_PERIPHCLK_SAI3 SAI3 peripheral clock
609 * @arg @ref RCC_PERIPHCLK_FMC FMC peripheral clock
610 * @arg @ref RCC_PERIPHCLK_QSPI QSPI peripheral clock
611 * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock
612 * @arg @ref RCC_PERIPHCLK_CKPER CKPER peripheral clock
613 * @arg @ref RCC_PERIPHCLK_SPDIFRX SPDIFRX peripheral clock
614 * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock
615 * @arg @ref RCC_PERIPHCLK_SPI1 SPI/I2S1 peripheral clock
616 * @arg @ref RCC_PERIPHCLK_SPI23 SPI/I2S2 and SPI/I2S3 peripheral clock
617 * @arg @ref RCC_PERIPHCLK_SPI45 SPI4 and SPI5 peripheral clock
618 * @arg @ref RCC_PERIPHCLK_SPI6 SPI6 peripheral clock
619 * @arg @ref RCC_PERIPHCLK_SAI4 SAI4 peripheral clock
620 * @arg @ref RCC_PERIPHCLK_SDMMC12 SDMMC1 and SDMMC2 peripheral clock
621 * @arg @ref RCC_PERIPHCLK_SDMMC3 SDMMC3 peripheral clock
622 * @arg @ref RCC_PERIPHCLK_ETH ETH peripheral clock
623 * @arg @ref RCC_PERIPHCLK_RNG1 RNG1 peripheral clock
624 * @arg @ref RCC_PERIPHCLK_RNG2 RNG2 peripheral clock
625 * @arg @ref RCC_PERIPHCLK_USBO USBO peripheral clock
626 * @arg @ref RCC_PERIPHCLK_STGEN STGEN peripheral clock
627 * @arg @ref RCC_PERIPHCLK_TIMG1 TIMG1 peripheral clock
628 * @arg @ref RCC_PERIPHCLK_TIMG2 TIMG2 peripheral clock
629 *
630 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
631 * select the RTC clock source; in this case the Backup domain will be
632 * reset in order to modify the RTC Clock source, as consequence RTC
633 * registers (including the backup registers) are set to their reset
634 * values.
635 *
636 * @retval HAL status
637 */
HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef * PeriphClkInit)638 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef
639 *PeriphClkInit)
640 {
641 uint32_t tmpreg = 0, RESERVED_BDCR_MASK = 0;
642 uint32_t tickstart;
643 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
644 HAL_StatusTypeDef status = HAL_OK; /* Final status */
645
646 /* Check the parameters */
647 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
648
649 /*---------------------------- CKPER configuration -------------------------*/
650 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) ==
651 RCC_PERIPHCLK_CKPER)
652 {
653 /* Check the parameters */
654 assert_param(IS_RCC_CKPERCLKSOURCE(PeriphClkInit->CkperClockSelection));
655
656 __HAL_RCC_CKPER_CONFIG(PeriphClkInit->CkperClockSelection);
657 }
658
659 /*------------------------------ I2C12 Configuration -----------------------*/
660 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C12) ==
661 RCC_PERIPHCLK_I2C12)
662 {
663 /* Check the parameters */
664 assert_param(IS_RCC_I2C12CLKSOURCE(PeriphClkInit->I2c12ClockSelection));
665
666 if ((PeriphClkInit->I2c12ClockSelection) == RCC_I2C12CLKSOURCE_PLL4)
667 {
668 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
669 if (status != HAL_OK)
670 {
671 return status;
672 }
673 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
674 }
675
676 __HAL_RCC_I2C12_CONFIG(PeriphClkInit->I2c12ClockSelection);
677 }
678
679 /*------------------------------ I2C35 Configuration -----------------------*/
680 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C35) ==
681 RCC_PERIPHCLK_I2C35)
682 {
683 /* Check the parameters */
684 assert_param(IS_RCC_I2C35CLKSOURCE(PeriphClkInit->I2c35ClockSelection));
685
686 if ((PeriphClkInit->I2c35ClockSelection) == RCC_I2C35CLKSOURCE_PLL4)
687 {
688 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
689 if (status != HAL_OK)
690 {
691 return status;
692 }
693 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
694 }
695
696 __HAL_RCC_I2C35_CONFIG(PeriphClkInit->I2c35ClockSelection);
697 }
698
699 /*------------------------------ I2C46 Configuration -----------------------*/
700 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C46) ==
701 RCC_PERIPHCLK_I2C46)
702 {
703 /* Check the parameters */
704 assert_param(IS_RCC_I2C46CLKSOURCE(PeriphClkInit->I2c46ClockSelection));
705
706 if ((PeriphClkInit->I2c46ClockSelection) == RCC_I2C46CLKSOURCE_PLL3)
707 {
708 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
709 if (status != HAL_OK)
710 {
711 return status;
712 }
713 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
714 }
715
716 __HAL_RCC_I2C46_CONFIG(PeriphClkInit->I2c46ClockSelection);
717 }
718
719 /*---------------------------- SAI1 configuration --------------------------*/
720 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) ==
721 RCC_PERIPHCLK_SAI1)
722 {
723 /* Check the parameters */
724 assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
725
726 switch (PeriphClkInit->Sai1ClockSelection)
727 {
728 case RCC_SAI1CLKSOURCE_PLL4: /* PLL4 is used as clock source for SAI1*/
729
730 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
731 if (status != HAL_OK)
732 {
733 return status;
734 }
735 /* Enable SAI Clock output generated on PLL4 */
736 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
737
738 break;
739
740 case RCC_SAI1CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SAI1*/
741
742 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
743 if (status != HAL_OK)
744 {
745 return status;
746 }
747 /* Enable SAI Clock output generated on PLL3 */
748
749 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
750
751 break;
752
753 case RCC_SAI1CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SAI1*/
754
755 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
756 if (status != HAL_OK)
757 {
758 return status;
759 }
760 /* Enable SAI Clock output generated on PLL3 */
761
762 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
763
764 break;
765 }
766
767 /* Set the source of SAI1 clock*/
768 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
769 }
770
771 /*---------------------------- SAI2 configuration --------------------------*/
772 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) ==
773 RCC_PERIPHCLK_SAI2)
774 {
775 /* Check the parameters */
776 assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
777
778 switch (PeriphClkInit->Sai2ClockSelection)
779 {
780 case RCC_SAI2CLKSOURCE_PLL4: /* PLL4 is used as clock source for SAI2*/
781
782 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
783 if (status != HAL_OK)
784 {
785 return status;
786 }
787 /* Enable SAI Clock output generated on PLL4 */
788 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
789
790 break;
791
792 case RCC_SAI2CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SAI2 */
793
794 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
795 if (status != HAL_OK)
796 {
797 return status;
798 }
799 /* Enable SAI Clock output generated on PLL3 */
800 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
801
802 break;
803
804 case RCC_SAI2CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SAI2 */
805
806 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
807 if (status != HAL_OK)
808 {
809 return status;
810 }
811 /* Enable SAI Clock output generated on PLL3 */
812 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
813
814 break;
815 }
816
817 /* Set the source of SAI2 clock*/
818 __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
819 }
820
821 /*---------------------------- SAI3 configuration --------------------------*/
822 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI3) ==
823 RCC_PERIPHCLK_SAI3)
824 {
825 /* Check the parameters */
826 assert_param(IS_RCC_SAI3CLKSOURCE(PeriphClkInit->Sai3ClockSelection));
827
828 switch (PeriphClkInit->Sai3ClockSelection)
829 {
830 case RCC_SAI3CLKSOURCE_PLL4: /* PLL4 is used as clock source for SAI3*/
831
832 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
833 if (status != HAL_OK)
834 {
835 return status;
836 }
837 /* Enable SAI Clock output generated on PLL4 */
838 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
839
840 break;
841
842 case RCC_SAI3CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SAI3 */
843
844 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
845 if (status != HAL_OK)
846 {
847 return status;
848 }
849 /* Enable SAI Clock output generated on PLL3 */
850 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
851
852 break;
853
854 case RCC_SAI3CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SAI3 */
855
856 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
857 if (status != HAL_OK)
858 {
859 return status;
860 }
861 /* Enable SAI Clock output generated on PLL3 */
862 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
863
864 break;
865 }
866
867 /* Set the source of SAI3 clock*/
868 __HAL_RCC_SAI3_CONFIG(PeriphClkInit->Sai3ClockSelection);
869 }
870
871 /*---------------------------- SAI4 configuration --------------------------*/
872 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4) ==
873 RCC_PERIPHCLK_SAI4)
874 {
875 /* Check the parameters */
876 assert_param(IS_RCC_SAI4CLKSOURCE(PeriphClkInit->Sai4ClockSelection));
877
878 switch (PeriphClkInit->Sai4ClockSelection)
879 {
880 case RCC_SAI4CLKSOURCE_PLL4: /* PLL4 is used as clock source for SAI4 */
881
882 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
883 if (status != HAL_OK)
884 {
885 return status;
886 }
887 /* Enable SAI Clock output generated on PLL4 . */
888 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
889
890 break;
891
892
893 case RCC_SAI4CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SAI4 */
894
895 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
896 if (status != HAL_OK)
897 {
898 return status;
899 }
900 /* Enable SAI Clock output generated on PLL3_Q */
901 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
902
903 break;
904
905 case RCC_SAI4CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SAI4 */
906
907 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
908 if (status != HAL_OK)
909 {
910 return status;
911 }
912 /* Enable SAI Clock output generated on PLL3_R */
913 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
914
915 break;
916 }
917
918 /* Set the source of SAI4 clock*/
919 __HAL_RCC_SAI4_CONFIG(PeriphClkInit->Sai4ClockSelection);
920 }
921
922 /*---------------------------- SPI1 configuration --------------------------*/
923 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) ==
924 RCC_PERIPHCLK_SPI1)
925 {
926 /* Check the parameters */
927 assert_param(IS_RCC_SPI1CLKSOURCE(PeriphClkInit->Spi1ClockSelection));
928
929 switch (PeriphClkInit->Spi1ClockSelection)
930 {
931 case RCC_SPI1CLKSOURCE_PLL4: /* PLL4 is used as clock source for SPI1 */
932
933 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
934 if (status != HAL_OK)
935 {
936 return status;
937 }
938 /* Enable SPI Clock output generated on PLL4 */
939 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
940
941 break;
942
943 case RCC_SPI1CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SPI1*/
944
945 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
946 if (status != HAL_OK)
947 {
948 return status;
949 }
950 /* Enable SPI Clock output generated on PLL3 */
951 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
952
953 break;
954
955 case RCC_SPI1CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SPI1 */
956
957 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
958 if (status != HAL_OK)
959 {
960 return status;
961 }
962 /* Enable SPI Clock output generated on PLL3 */
963 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
964
965 break;
966
967 }
968
969 /* Set the source of SPI1 clock*/
970 __HAL_RCC_SPI1_CONFIG(PeriphClkInit->Spi1ClockSelection);
971 }
972
973 /*---------------------------- SPI23 configuration -------------------------*/
974 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI23) ==
975 RCC_PERIPHCLK_SPI23)
976 {
977 /* Check the parameters */
978 assert_param(IS_RCC_SPI23CLKSOURCE(PeriphClkInit->Spi23ClockSelection));
979
980 switch (PeriphClkInit->Spi23ClockSelection)
981 {
982 case RCC_SPI23CLKSOURCE_PLL4: /* PLL4 is used as clock source for SPI23 */
983
984 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
985 if (status != HAL_OK)
986 {
987 return status;
988 }
989 /* Enable SPI Clock output generated on PLL4 . */
990 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
991
992 break;
993
994 case RCC_SPI23CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SPI23 */
995
996 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
997 if (status != HAL_OK)
998 {
999 return status;
1000 }
1001 /* Enable SPI Clock output generated on PLL3 . */
1002 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1003
1004 break;
1005
1006 case RCC_SPI23CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SPI23 */
1007
1008 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1009 if (status != HAL_OK)
1010 {
1011 return status;
1012 }
1013 /* Enable SPI Clock output generated on PLL3 . */
1014 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
1015
1016 break;
1017 }
1018
1019 /* Set the source of SPI2 clock*/
1020 __HAL_RCC_SPI23_CONFIG(PeriphClkInit->Spi23ClockSelection);
1021 }
1022
1023 /*---------------------------- SPI45 configuration -------------------------*/
1024 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) ==
1025 RCC_PERIPHCLK_SPI45)
1026 {
1027 /* Check the parameters */
1028 assert_param(IS_RCC_SPI45CLKSOURCE(PeriphClkInit->Spi45ClockSelection));
1029
1030 if (PeriphClkInit->Spi45ClockSelection == RCC_SPI45CLKSOURCE_PLL4)
1031 {
1032 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1033 if (status != HAL_OK)
1034 {
1035 return status;
1036 }
1037 /* Enable SPI Clock output generated on PLL4 . */
1038 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1039 }
1040
1041 /* Set the source of SPI45 clock*/
1042 __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
1043 }
1044
1045 /*---------------------------- SPI6 configuration --------------------------*/
1046 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) ==
1047 RCC_PERIPHCLK_SPI6)
1048 {
1049 /* Check the parameters */
1050 assert_param(IS_RCC_SPI6CLKSOURCE(PeriphClkInit->Spi6ClockSelection));
1051
1052 switch (PeriphClkInit->Spi6ClockSelection)
1053 {
1054 case RCC_SPI6CLKSOURCE_PLL4: /* PLL4 is used as clock source for SPI6 */
1055
1056 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1057 if (status != HAL_OK)
1058 {
1059 return status;
1060 }
1061 /* Enable SPI Clock output generated on PLL4 . */
1062 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1063
1064 break;
1065
1066 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6 */
1067
1068 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1069 if (status != HAL_OK)
1070 {
1071 return status;
1072 }
1073 /* Enable SPI Clock output generated on PLL3 . */
1074 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1075
1076 break;
1077 }
1078
1079 /* Set the source of SPI6 clock*/
1080 __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
1081 }
1082
1083 /*---------------------------- USART6 configuration ------------------------*/
1084 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) ==
1085 RCC_PERIPHCLK_USART6)
1086 {
1087 /* Check the parameters */
1088 assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
1089
1090 if (PeriphClkInit->Usart6ClockSelection == RCC_USART6CLKSOURCE_PLL4)
1091 {
1092 /* PLL4 is used as clock source for USART6 */
1093 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1094 if (status != HAL_OK)
1095 {
1096 return status;
1097 }
1098 /* Enable USART Clock output generated on PLL4 */
1099 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1100 }
1101
1102 /* Set the source of USART6 clock*/
1103 __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
1104 }
1105
1106 /*---------------------------- UART24 configuration ------------------------*/
1107 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART24) ==
1108 RCC_PERIPHCLK_UART24)
1109 {
1110 /* Check the parameters */
1111 assert_param(IS_RCC_UART24CLKSOURCE(PeriphClkInit->Uart24ClockSelection));
1112
1113 if (PeriphClkInit->Uart24ClockSelection == RCC_UART24CLKSOURCE_PLL4)
1114 {
1115 /* PLL4 is used as clock source for UART24 */
1116 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1117 if (status != HAL_OK)
1118 {
1119 return status;
1120 }
1121 /* Enable UART Clock output generated on PLL4 */
1122 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1123 }
1124
1125 /* Set the source of UART24 clock*/
1126 __HAL_RCC_UART24_CONFIG(PeriphClkInit->Uart24ClockSelection);
1127 }
1128
1129 /*---------------------------- UART35 configuration ------------------------*/
1130 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART35) ==
1131 RCC_PERIPHCLK_UART35)
1132 {
1133 /* Check the parameters */
1134 assert_param(IS_RCC_UART35CLKSOURCE(PeriphClkInit->Uart35ClockSelection));
1135
1136 if (PeriphClkInit->Uart35ClockSelection == RCC_UART35CLKSOURCE_PLL4)
1137 {
1138 /* PLL4 is used as clock source for UART35 */
1139 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1140 if (status != HAL_OK)
1141 {
1142 return status;
1143 }
1144 /* Enable UART Clock output generated on PLL4 */
1145 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1146 }
1147
1148 /* Set the source of UART35 clock*/
1149 __HAL_RCC_UART35_CONFIG(PeriphClkInit->Uart35ClockSelection);
1150 }
1151
1152 /*---------------------------- UAUART78 configuration ----------------------*/
1153 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART78) ==
1154 RCC_PERIPHCLK_UART78)
1155 {
1156 /* Check the parameters */
1157 assert_param(IS_RCC_UART78CLKSOURCE(PeriphClkInit->Uart78ClockSelection));
1158
1159 if (PeriphClkInit->Uart78ClockSelection == RCC_UART78CLKSOURCE_PLL4)
1160 {
1161 /* PLL4 is used as clock source for UART78 */
1162 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1163 if (status != HAL_OK)
1164 {
1165 return status;
1166 }
1167 /* Enable UART Clock output generated on PLL4 */
1168 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1169 }
1170
1171 /* Set the source of UART78 clock*/
1172 __HAL_RCC_UART78_CONFIG(PeriphClkInit->Uart78ClockSelection);
1173 }
1174
1175 /*---------------------------- USART1 configuration ------------------------*/
1176 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) ==
1177 RCC_PERIPHCLK_USART1)
1178 {
1179 /* Check the parameters */
1180 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
1181
1182 switch (PeriphClkInit->Usart1ClockSelection)
1183 {
1184 case RCC_USART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1 */
1185
1186 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1187 if (status != HAL_OK)
1188 {
1189 return status;
1190 }
1191 /* Enable UART Clock output generated on PLL3 */
1192 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1193
1194 break;
1195
1196 case RCC_USART1CLKSOURCE_PLL4: /* PLL4 is used as clock source for USART1 */
1197
1198 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1199 if (status != HAL_OK)
1200 {
1201 return status;
1202 }
1203 /* Enable USART Clock output generated on PLL4 . */
1204 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1205
1206 break;
1207 }
1208
1209 /* Set the source of USART1 clock*/
1210 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
1211 }
1212
1213 /*---------------------------- SDMMC12 configuration -----------------------*/
1214 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC12) ==
1215 RCC_PERIPHCLK_SDMMC12)
1216 {
1217 /* Check the parameters */
1218 assert_param(IS_RCC_SDMMC12CLKSOURCE(PeriphClkInit->Sdmmc12ClockSelection));
1219
1220 switch (PeriphClkInit->Sdmmc12ClockSelection)
1221 {
1222 case RCC_SDMMC12CLKSOURCE_PLL3: /* PLL3 is used as clock source for SDMMC12 */
1223
1224 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1225 if (status != HAL_OK)
1226 {
1227 return status;
1228 }
1229 /* Enable SDMMC12 Clock output generated on PLL3 . */
1230 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
1231
1232 break;
1233
1234 case RCC_SDMMC12CLKSOURCE_PLL4: /* PLL4 is used as clock source for SDMMC12 */
1235
1236 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1237 if (status != HAL_OK)
1238 {
1239 return status;
1240 }
1241 /* Enable SDMMC12 Clock output generated on PLL4 . */
1242 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1243
1244 break;
1245 }
1246
1247 /* Set the source of SDMMC12 clock*/
1248 __HAL_RCC_SDMMC12_CONFIG(PeriphClkInit->Sdmmc12ClockSelection);
1249 }
1250
1251 /*---------------------------- SDMMC3 configuration ------------------------*/
1252 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC3) ==
1253 RCC_PERIPHCLK_SDMMC3)
1254 {
1255 /* Check the parameters */
1256 assert_param(IS_RCC_SDMMC3CLKSOURCE(PeriphClkInit->Sdmmc3ClockSelection));
1257
1258 switch (PeriphClkInit->Sdmmc3ClockSelection)
1259 {
1260 case RCC_SDMMC3CLKSOURCE_PLL3: /* PLL3 is used as clock source for SDMMC3 */
1261
1262 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1263 if (status != HAL_OK)
1264 {
1265 return status;
1266 }
1267 /* Enable SDMMC3 Clock output generated on PLL3 . */
1268 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
1269
1270 break;
1271
1272 case RCC_SDMMC3CLKSOURCE_PLL4: /* PLL4 is used as clock source for SDMMC3 */
1273
1274 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1275 if (status != HAL_OK)
1276 {
1277 return status;
1278 }
1279 /* Enable SDMMC3 Clock output generated on PLL4 . */
1280 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1281
1282 break;
1283 }
1284
1285 /* Set the source of SDMMC3 clock*/
1286 __HAL_RCC_SDMMC3_CONFIG(PeriphClkInit->Sdmmc3ClockSelection);
1287 }
1288
1289 /*---------------------------- ETH configuration ---------------------------*/
1290 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ETH) ==
1291 RCC_PERIPHCLK_ETH)
1292 {
1293 /* Check the parameters */
1294 assert_param(IS_RCC_ETHCLKSOURCE(PeriphClkInit->EthClockSelection));
1295
1296 switch (PeriphClkInit->EthClockSelection)
1297 {
1298 case RCC_ETHCLKSOURCE_PLL4: /* PLL4 is used as clock source for ETH */
1299
1300 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1301 if (status != HAL_OK)
1302 {
1303 return status;
1304 }
1305 /* Enable ETH Clock output generated on PLL2 . */
1306 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1307
1308 break;
1309
1310 case RCC_ETHCLKSOURCE_PLL3: /* PLL3 is used as clock source for ETH */
1311
1312 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1313 if (status != HAL_OK)
1314 {
1315 return status;
1316 }
1317 /* Enable ETH Clock output generated on PLL3 . */
1318 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1319
1320 break;
1321 }
1322
1323 /* Set the source of ETH clock*/
1324 __HAL_RCC_ETH_CONFIG(PeriphClkInit->EthClockSelection);
1325 }
1326
1327 /*---------------------------- QSPI configuration --------------------------*/
1328 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) ==
1329 RCC_PERIPHCLK_QSPI)
1330 {
1331 /* Check the parameters */
1332 assert_param(IS_RCC_QSPICLKSOURCE(PeriphClkInit->QspiClockSelection));
1333
1334 switch (PeriphClkInit->QspiClockSelection)
1335 {
1336 case RCC_QSPICLKSOURCE_PLL3: /* PLL3 is used as clock source for QSPI */
1337
1338 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1339 if (status != HAL_OK)
1340 {
1341 return status;
1342 }
1343 /* Enable QSPI Clock output generated on PLL3 . */
1344 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
1345
1346 break;
1347
1348 case RCC_QSPICLKSOURCE_PLL4: /* PLL4 is used as clock source for QSPI */
1349
1350 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1351 if (status != HAL_OK)
1352 {
1353 return status;
1354 }
1355 /* Enable QSPI Clock output generated on PLL4 . */
1356 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1357
1358 break;
1359 }
1360
1361 /* Set the source of QSPI clock*/
1362 __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
1363 }
1364
1365 /*---------------------------- FMC configuration ---------------------------*/
1366 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) ==
1367 RCC_PERIPHCLK_FMC)
1368 {
1369 /* Check the parameters */
1370 assert_param(IS_RCC_FMCCLKSOURCE(PeriphClkInit->FmcClockSelection));
1371
1372 switch (PeriphClkInit->FmcClockSelection)
1373 {
1374 case RCC_FMCCLKSOURCE_PLL3: /* PLL3 is used as clock source for FMC */
1375
1376 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1377 if (status != HAL_OK)
1378 {
1379 return status;
1380 }
1381 /* Enable FMC Clock output generated on PLL3 . */
1382 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
1383
1384 break;
1385
1386 case RCC_FMCCLKSOURCE_PLL4: /* PLL4 is used as clock source for FMC */
1387
1388 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1389 if (status != HAL_OK)
1390 {
1391 return status;
1392 }
1393 /* Enable FMC Clock output generated on PLL4 . */
1394 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1395
1396 break;
1397 }
1398
1399 /* Set the source of FMC clock*/
1400 __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
1401 }
1402
1403 #if defined(FDCAN1)
1404 /*---------------------------- FDCAN configuration -------------------------*/
1405 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) ==
1406 RCC_PERIPHCLK_FDCAN)
1407 {
1408 /* Check the parameters */
1409 assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
1410
1411 switch (PeriphClkInit->FdcanClockSelection)
1412 {
1413 case RCC_FDCANCLKSOURCE_PLL3: /* PLL3 is used as clock source for FDCAN */
1414
1415 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1416 if (status != HAL_OK)
1417 {
1418 return status;
1419 }
1420 /* Enable FDCAN Clock output generated on PLL3 . */
1421 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1422
1423 break;
1424
1425 case RCC_FDCANCLKSOURCE_PLL4_Q: /* PLL4_Q is used as clock source for FDCAN */
1426
1427 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1428 if (status != HAL_OK)
1429 {
1430 return status;
1431 }
1432 /* Enable FDCAN Clock output generated on PLL4 */
1433 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1434
1435 break;
1436
1437 case RCC_FDCANCLKSOURCE_PLL4_R: /* PLL4_R is used as clock source for FDCAN */
1438
1439 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1440 if (status != HAL_OK)
1441 {
1442 return status;
1443 }
1444 /* Enable FDCAN Clock output generated on PLL4 */
1445 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
1446
1447 break;
1448 }
1449
1450 /* Set the source of FDCAN clock*/
1451 __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
1452 }
1453 #endif /*FDCAN1*/
1454
1455 /*---------------------------- SPDIFRX configuration -----------------------*/
1456 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) ==
1457 RCC_PERIPHCLK_SPDIFRX)
1458 {
1459 /* Check the parameters */
1460 assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifrxClockSelection));
1461
1462 switch (PeriphClkInit->SpdifrxClockSelection)
1463 {
1464 case RCC_SPDIFRXCLKSOURCE_PLL4: /* PLL4 is used as clock source for SPDIF */
1465
1466 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1467 if (status != HAL_OK)
1468 {
1469 return status;
1470 }
1471 /* Enable SPDIF Clock output generated on PLL4 . */
1472 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1473
1474 break;
1475
1476 case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIF */
1477
1478 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1479 if (status != HAL_OK)
1480 {
1481 return status;
1482 }
1483 /* Enable SPDIF Clock output generated on PLL3 . */
1484 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1485
1486 break;
1487 }
1488
1489 /* Set the source of SPDIF clock*/
1490 __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
1491 }
1492
1493 /*---------------------------- CEC configuration ---------------------------*/
1494 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) ==
1495 RCC_PERIPHCLK_CEC)
1496 {
1497 /* Check the parameters */
1498 assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
1499
1500 __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
1501 }
1502
1503 /*---------------------------- USBPHY configuration ------------------------*/
1504 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USBPHY) ==
1505 RCC_PERIPHCLK_USBPHY)
1506 {
1507 /* Check the parameters */
1508 assert_param(IS_RCC_USBPHYCLKSOURCE(PeriphClkInit->UsbphyClockSelection));
1509
1510 if (PeriphClkInit->UsbphyClockSelection == RCC_USBPHYCLKSOURCE_PLL4)
1511 {
1512 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1513 if (status != HAL_OK)
1514 {
1515 return status;
1516 }
1517 /* Enable USB PHY Clock output generated on PLL4 . */
1518 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
1519 }
1520
1521 __HAL_RCC_USBPHY_CONFIG(PeriphClkInit->UsbphyClockSelection);
1522 }
1523
1524 /*---------------------------- USBO configuration --------------------------*/
1525 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USBO) ==
1526 RCC_PERIPHCLK_USBO)
1527 {
1528 /* Check the parameters */
1529 assert_param(IS_RCC_USBOCLKSOURCE(PeriphClkInit->UsboClockSelection));
1530
1531 if (PeriphClkInit->UsboClockSelection == RCC_USBOCLKSOURCE_PLL4)
1532 {
1533 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1534 if (status != HAL_OK)
1535 {
1536 return status;
1537 }
1538 /* Enable USB OTG Clock output generated on PLL4 . */
1539 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
1540 }
1541
1542 __HAL_RCC_USBO_CONFIG(PeriphClkInit->UsboClockSelection);
1543 }
1544
1545 /*---------------------------- RNG1 configuration --------------------------*/
1546 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG1) ==
1547 RCC_PERIPHCLK_RNG1)
1548 {
1549 /* Check the parameters */
1550 assert_param(IS_RCC_RNG1CLKSOURCE(PeriphClkInit->Rng1ClockSelection));
1551
1552 if (PeriphClkInit->Rng1ClockSelection == RCC_RNG1CLKSOURCE_PLL4)
1553 {
1554 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1555 if (status != HAL_OK)
1556 {
1557 return status;
1558 }
1559 /* Enable RNG1 Clock output generated on PLL4 . */
1560 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
1561 }
1562
1563 /* Set the source of RNG1 clock*/
1564 __HAL_RCC_RNG1_CONFIG(PeriphClkInit->Rng1ClockSelection);
1565 }
1566
1567 /*---------------------------- RNG2 configuration --------------------------*/
1568 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG2) ==
1569 RCC_PERIPHCLK_RNG2)
1570 {
1571 /* Check the parameters */
1572 assert_param(IS_RCC_RNG2CLKSOURCE(PeriphClkInit->Rng2ClockSelection));
1573
1574 if (PeriphClkInit->Rng2ClockSelection == RCC_RNG2CLKSOURCE_PLL4)
1575 {
1576 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1577 if (status != HAL_OK)
1578 {
1579 return status;
1580 }
1581 /* Enable RNG2 Clock output generated on PLL4 . */
1582 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
1583 }
1584
1585 /* Set the source of RNG2 clock*/
1586 __HAL_RCC_RNG2_CONFIG(PeriphClkInit->Rng2ClockSelection);
1587 }
1588
1589 /*---------------------------- STGEN configuration -------------------------*/
1590 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_STGEN) ==
1591 RCC_PERIPHCLK_STGEN)
1592 {
1593 /* Check the parameters */
1594 assert_param(IS_RCC_STGENCLKSOURCE(PeriphClkInit->StgenClockSelection));
1595
1596 __HAL_RCC_STGEN_CONFIG(PeriphClkInit->StgenClockSelection);
1597 }
1598
1599 #if defined(DSI)
1600 /*---------------------------- DSI configuration ---------------------------*/
1601 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) ==
1602 RCC_PERIPHCLK_DSI)
1603 {
1604 /* Check the parameters */
1605 assert_param(IS_RCC_DSICLKSOURCE(PeriphClkInit->DsiClockSelection));
1606
1607 if (PeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLL4)
1608 {
1609 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1610 if (status != HAL_OK)
1611 {
1612 return status;
1613 }
1614 /* Enable DSI Clock output generated on PLL4 . */
1615 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1616 }
1617
1618 __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
1619 }
1620 #endif /*DSI*/
1621
1622 /*---------------------------- ADC configuration ---------------------------*/
1623 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) ==
1624 RCC_PERIPHCLK_ADC)
1625 {
1626 /* Check the parameters */
1627 assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
1628
1629 switch (PeriphClkInit->AdcClockSelection)
1630 {
1631 case RCC_ADCCLKSOURCE_PLL4: /* PLL4 is used as clock source for ADC */
1632
1633 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1634 if (status != HAL_OK)
1635 {
1636 return status;
1637 }
1638 /* Enable ADC Clock output generated on PLL4 */
1639 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
1640 break;
1641
1642 case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC */
1643
1644 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1645 if (status != HAL_OK)
1646 {
1647 return status;
1648 }
1649 /* Enable ADC Clock output generated on PLL3 */
1650 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1651
1652 break;
1653 }
1654
1655 /* Set the source of ADC clock*/
1656 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
1657 }
1658
1659 /*---------------------------- LPTIM45 configuration -----------------------*/
1660 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM45) ==
1661 RCC_PERIPHCLK_LPTIM45)
1662 {
1663 /* Check the parameters */
1664 assert_param(IS_RCC_LPTIM45CLKSOURCE(PeriphClkInit->Lptim45ClockSelection));
1665
1666 switch (PeriphClkInit->Lptim45ClockSelection)
1667 {
1668 case RCC_LPTIM45CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM45 */
1669
1670 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1671 if (status != HAL_OK)
1672 {
1673 return status;
1674 }
1675 /* Enable clock output generated on PLL3 . */
1676 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1677
1678 break;
1679
1680 case RCC_LPTIM45CLKSOURCE_PLL4: /* PLL4 is used as clock source for LPTIM45 */
1681
1682 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1683 if (status != HAL_OK)
1684 {
1685 return status;
1686 }
1687 /* Enable clock output generated on PLL4 . */
1688 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1689
1690 break;
1691 }
1692
1693 /* Set the source of LPTIM45 clock*/
1694 __HAL_RCC_LPTIM45_CONFIG(PeriphClkInit->Lptim45ClockSelection);
1695 }
1696
1697 /*---------------------------- LPTIM23 configuration -----------------------*/
1698 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM23) ==
1699 RCC_PERIPHCLK_LPTIM23)
1700 {
1701 /* Check the parameters */
1702 assert_param(IS_RCC_LPTIM23CLKSOURCE(PeriphClkInit->Lptim23ClockSelection));
1703
1704 if (PeriphClkInit->Lptim23ClockSelection == RCC_LPTIM23CLKSOURCE_PLL4)
1705 {
1706 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1707 if (status != HAL_OK)
1708 {
1709 return status;
1710 }
1711 /* Enable clock output generated on PLL4 . */
1712 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1713 }
1714
1715 /* Set the source of LPTIM23 clock*/
1716 __HAL_RCC_LPTIM23_CONFIG(PeriphClkInit->Lptim23ClockSelection);
1717 }
1718
1719 /*---------------------------- LPTIM1 configuration ------------------------*/
1720 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) ==
1721 RCC_PERIPHCLK_LPTIM1)
1722 {
1723 /* Check the parameters */
1724 assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
1725
1726 switch (PeriphClkInit->Lptim1ClockSelection)
1727 {
1728 case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1 */
1729
1730 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1731 if (status != HAL_OK)
1732 {
1733 return status;
1734 }
1735 /* Enable clock output generated on PLL3 . */
1736 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1737
1738 break;
1739
1740 case RCC_LPTIM1CLKSOURCE_PLL4: /* PLL4 is used as clock source for LPTIM1 */
1741
1742 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1743 if (status != HAL_OK)
1744 {
1745 return status;
1746 }
1747 /* Enable clock output generated on PLL4 . */
1748 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1749
1750 break;
1751 }
1752
1753 /* Set the source of LPTIM1 clock*/
1754 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
1755 }
1756
1757 /*---------------------------- RTC configuration ---------------------------*/
1758 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) ==
1759 RCC_PERIPHCLK_RTC)
1760 {
1761 /* check for RTC Parameters used to output RTCCLK */
1762 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
1763
1764 /* Enable write access to Backup domain */
1765 SET_BIT(PWR->CR1, PWR_CR1_DBP);
1766
1767 /* Wait for Backup domain Write protection disable */
1768 tickstart = HAL_GetTick();
1769
1770 while ((PWR->CR1 & PWR_CR1_DBP) == RESET)
1771 {
1772 if ((HAL_GetTick() - tickstart) > DBP_TIMEOUT_VALUE)
1773 {
1774 ret = HAL_TIMEOUT;
1775 }
1776 }
1777
1778 if (ret == HAL_OK)
1779 {
1780 /* Reset the Backup domain only if the RTC Clock source selection is modified */
1781 if ((RCC->BDCR & RCC_BDCR_RTCSRC) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSRC))
1782 {
1783 /* Store the content of BDCR register before the reset of Backup Domain */
1784 tmpreg = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSRC));
1785 /* RTC Clock selection can be changed only if the Backup Domain is reset */
1786 __HAL_RCC_BACKUPRESET_FORCE();
1787 __HAL_RCC_BACKUPRESET_RELEASE();
1788
1789 /* Set the LSEDrive value */
1790 __HAL_RCC_LSEDRIVE_CONFIG(tmpreg & RCC_BDCR_LSEDRV);
1791
1792 /* RCC_BDCR_LSEON can be enabled for RTC or another IP, re-enable it */
1793 RCC_OscInitTypeDef RCC_OscInitStructure;
1794 /* Configure LSE Oscillator*/
1795 RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_LSE;
1796 RCC_OscInitStructure.LSEState = (tmpreg & LSE_MASK);
1797
1798 RCC_OscInitStructure.PLL.PLLState = RCC_PLL_NONE;
1799 RCC_OscInitStructure.PLL2.PLLState = RCC_PLL_NONE;
1800 RCC_OscInitStructure.PLL3.PLLState = RCC_PLL_NONE;
1801 RCC_OscInitStructure.PLL4.PLLState = RCC_PLL_NONE;
1802 ret = HAL_RCC_OscConfig(&RCC_OscInitStructure);
1803 if (ret != HAL_OK)
1804 {
1805 return ret;
1806 }
1807
1808 /* Write the RTCSRC */
1809 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
1810
1811 /* Fill up Reserved register mask for BDCR
1812 * All already filled up or what shouldn't be modified must be put on the mask */
1813 RESERVED_BDCR_MASK = ~(RCC_BDCR_VSWRST | RCC_BDCR_RTCCKEN | RCC_BDCR_RTCSRC |
1814 RCC_BDCR_LSECSSD | RCC_BDCR_LSEDRV | RCC_BDCR_DIGBYP |
1815 RCC_BDCR_LSERDY | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON);
1816
1817 /* Restore the BDCR context: RESERVED registers plus RCC_BDCR_LSECSSON */
1818 WRITE_REG(RCC->BDCR, (READ_REG(RCC->BDCR) | (tmpreg & RESERVED_BDCR_MASK)));
1819
1820 }/* End RTCSRC changed */
1821
1822 /*Enable RTC clock */
1823 __HAL_RCC_RTC_ENABLE();
1824 }
1825 else
1826 {
1827 // Enable write access to Backup domain failed
1828 /* return the error */
1829 return ret;
1830 }
1831 }
1832
1833 /*---------------------------- TIMG1 configuration -------------------------*/
1834 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIMG1) ==
1835 RCC_PERIPHCLK_TIMG1)
1836 {
1837 /* Check the parameters */
1838 assert_param(IS_RCC_TIMG1PRES(PeriphClkInit->TIMG1PresSelection));
1839
1840 /* Set TIMG1 division factor */
1841 __HAL_RCC_TIMG1PRES(PeriphClkInit->TIMG1PresSelection);
1842
1843 /* Get Start Tick*/
1844 tickstart = HAL_GetTick();
1845
1846 /* Wait till TIMG1 is ready */
1847 while (__HAL_RCC_GET_FLAG(RCC_FLAG_TIMG1PRERDY) == RESET)
1848 {
1849 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1850 {
1851 return HAL_TIMEOUT;
1852 }
1853 }
1854 }
1855
1856 /*---------------------------- TIMG2 configuration -------------------------*/
1857 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIMG2) ==
1858 RCC_PERIPHCLK_TIMG2)
1859 {
1860 /* Check the parameters */
1861 assert_param(IS_RCC_TIMG2PRES(PeriphClkInit->TIMG2PresSelection));
1862
1863 /* Set TIMG1 division factor */
1864 __HAL_RCC_TIMG2PRES(PeriphClkInit->TIMG2PresSelection);
1865
1866 /* Get Start Tick*/
1867 tickstart = HAL_GetTick();
1868
1869 /* Wait till TIMG1 is ready */
1870 while (__HAL_RCC_GET_FLAG(RCC_FLAG_TIMG2PRERDY) == RESET)
1871 {
1872 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1873 {
1874 return HAL_TIMEOUT;
1875 }
1876 }
1877 }
1878
1879 return HAL_OK;
1880 }
1881
1882
1883
1884 /**
1885 * @brief Get the RCC_ClkInitStruct according to the internal RCC
1886 * configuration registers.
1887 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
1888 * returns the configuration information for the Extended Peripherals
1889 * clocks : CKPER, I2C12, I2C35, I2C46, I2C5, SAI1, SAI2, SAI3, SAI4,
1890 * SPI1, SPI2, SPI3, SPI45, SPI6, USART1, UART24, USART3, UART24, UART35,
1891 * USART6, UART78, SDMMC12, SDMMC3, ETH, QSPI,FMC, FDCAN,
1892 * SPDIFRX, CEC, USBPHY, USBO, RNG1, RNG2, STGEN, DSI, ADC, RTC,
1893 * LPTIM1, LPTIM23, LPTIM45
1894 * @retval None
1895 */
HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef * PeriphClkInit)1896 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
1897 {
1898 /* Set all possible values for the extended clock type parameter------------*/
1899 PeriphClkInit->PeriphClockSelection =
1900 RCC_PERIPHCLK_CKPER | RCC_PERIPHCLK_I2C12 | RCC_PERIPHCLK_I2C35 |
1901 RCC_PERIPHCLK_I2C46 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |
1902 RCC_PERIPHCLK_SAI3 | RCC_PERIPHCLK_SAI4 | RCC_PERIPHCLK_SPI1 |
1903 RCC_PERIPHCLK_SPI23 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 |
1904 RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_UART24 | RCC_PERIPHCLK_UART35 |
1905 RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART78 | RCC_PERIPHCLK_SDMMC12 |
1906 RCC_PERIPHCLK_SDMMC3 | RCC_PERIPHCLK_ETH | RCC_PERIPHCLK_QSPI |
1907 RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_SPDIFRX |
1908 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_USBPHY | RCC_PERIPHCLK_USBO |
1909 RCC_PERIPHCLK_RNG1 | RCC_PERIPHCLK_RNG2 | RCC_PERIPHCLK_STGEN |
1910 RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC |
1911 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM23 | RCC_PERIPHCLK_LPTIM45;
1912
1913 /* Get the CKPER clock source ----------------------------------------------*/
1914 PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CKPER_SOURCE();
1915
1916 /* Get the I2C12 clock source ----------------------------------------------*/
1917 PeriphClkInit->I2c12ClockSelection = __HAL_RCC_GET_I2C12_SOURCE();
1918 /* Get the I2C35 clock source ----------------------------------------------*/
1919 PeriphClkInit->I2c35ClockSelection = __HAL_RCC_GET_I2C35_SOURCE();
1920 /* Get the I2C46 clock source -----------------------------------------------*/
1921 PeriphClkInit->I2c46ClockSelection = __HAL_RCC_GET_I2C46_SOURCE();
1922
1923 /* Get the SAI1 clock source -----------------------------------------------*/
1924 PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
1925 /* Get the SAI2 clock source -----------------------------------------------*/
1926 PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
1927 /* Get the SAI3 clock source -----------------------------------------------*/
1928 PeriphClkInit->Sai3ClockSelection = __HAL_RCC_GET_SAI3_SOURCE();
1929 /* Get the SAI4 clock source -----------------------------------------------*/
1930 PeriphClkInit->Sai4ClockSelection = __HAL_RCC_GET_SAI4_SOURCE();
1931
1932 /* Get the SPI1 clock source -----------------------------------------------*/
1933 PeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE();
1934 /* Get the SPI23 clock source ----------------------------------------------*/
1935 PeriphClkInit->Spi23ClockSelection = __HAL_RCC_GET_SPI23_SOURCE();
1936 /* Get the SPI45 clock source ----------------------------------------------*/
1937 PeriphClkInit->Spi45ClockSelection = __HAL_RCC_GET_SPI45_SOURCE();
1938 /* Get the SPI6 clock source -----------------------------------------------*/
1939 PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE();
1940
1941 /* Get the USART1 configuration --------------------------------------------*/
1942 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
1943 /* Get the UART24 clock source ----------------------------------------------*/
1944 PeriphClkInit->Uart24ClockSelection = __HAL_RCC_GET_UART24_SOURCE();
1945 /* Get the UART35 clock source ---------------------------------------------*/
1946 PeriphClkInit->Uart35ClockSelection = __HAL_RCC_GET_UART35_SOURCE();
1947 /* Get the USART6 clock source ---------------------------------------------*/
1948 PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
1949 /* Get the UART78 clock source ---------------------------------------------*/
1950 PeriphClkInit->Uart78ClockSelection = __HAL_RCC_GET_UART78_SOURCE();
1951
1952 /* Get the SDMMC12 clock source --------------------------------------------*/
1953 PeriphClkInit->Sdmmc12ClockSelection = __HAL_RCC_GET_SDMMC12_SOURCE();
1954 /* Get the SDMMC3 clock source ---------------------------------------------*/
1955 PeriphClkInit->Sdmmc3ClockSelection = __HAL_RCC_GET_SDMMC3_SOURCE();
1956 /* Get the SDMMC3 clock source ---------------------------------------------*/
1957 PeriphClkInit->EthClockSelection = __HAL_RCC_GET_ETH_SOURCE();
1958
1959 /* Get the QSPI clock source -----------------------------------------------*/
1960 PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE();
1961 /* Get the FMC clock source ------------------------------------------------*/
1962 PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE();
1963 #if defined(FDCAN1)
1964 /* Get the FDCAN clock source ----------------------------------------------*/
1965 PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();
1966 #endif /*FDCAN1*/
1967 /* Get the SPDIFRX clock source --------------------------------------------*/
1968 PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
1969 /* Get the CEC clock source ------------------------------------------------*/
1970 PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
1971 /* Get the USBPHY clock source ---------------------------------------------*/
1972 PeriphClkInit-> UsbphyClockSelection = __HAL_RCC_GET_USBPHY_SOURCE();
1973 /* Get the USBO clock source -----------------------------------------------*/
1974 PeriphClkInit-> UsboClockSelection = __HAL_RCC_GET_USBO_SOURCE();
1975 /* Get the RNG1 clock source -----------------------------------------------*/
1976 PeriphClkInit->Rng1ClockSelection = __HAL_RCC_GET_RNG1_SOURCE();
1977 /* Get the RNG2 clock source -----------------------------------------------*/
1978 PeriphClkInit->Rng2ClockSelection = __HAL_RCC_GET_RNG2_SOURCE();
1979 /* Get the STGEN clock source ----------------------------------------------*/
1980 PeriphClkInit->StgenClockSelection = __HAL_RCC_GET_STGEN_SOURCE();
1981 #if defined(DSI)
1982 /* Get the DSI clock source ------------------------------------------------*/
1983 PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();
1984 #endif /*DSI*/
1985 /* Get the ADC clock source ------------------------------------------------*/
1986 PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
1987 /* Get the RTC clock source ------------------------------------------------*/
1988 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
1989
1990 /* Get the LPTIM1 clock source ---------------------------------------------*/
1991 PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
1992 /* Get the LPTIM23 clock source ---------------------------------------------*/
1993 PeriphClkInit->Lptim23ClockSelection = __HAL_RCC_GET_LPTIM23_SOURCE();
1994 /* Get the LPTIM45 clock source ---------------------------------------------*/
1995 PeriphClkInit->Lptim45ClockSelection = __HAL_RCC_GET_LPTIM45_SOURCE();
1996
1997 /* Get the TIM1 Prescaler configuration ------------------------------------*/
1998 PeriphClkInit->TIMG1PresSelection = __HAL_RCC_GET_TIMG1PRES();
1999 /* Get the TIM2 Prescaler configuration ------------------------------------*/
2000 PeriphClkInit->TIMG2PresSelection = __HAL_RCC_GET_TIMG2PRES();
2001 }
2002
2003 /**
2004 * @brief Enables the LSE Clock Security System.
2005 * @note After reset BDCR register is write-protected and the DBP bit in the
2006 * PWR control register 1 (PWR_CR1) has to be set before it can be written.
2007 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
2008 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
2009 * clock with HAL_RCCEx_PeriphCLKConfig().
2010 * @retval None
2011 */
HAL_RCCEx_EnableLSECSS(void)2012 void HAL_RCCEx_EnableLSECSS(void)
2013 {
2014 /* Set LSECSSON bit */
2015 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2016 }
2017
2018 /**
2019 * @brief Disables the LSE Clock Security System.
2020 * @note LSE Clock Security System can only be disabled after a LSE failure detection.
2021 * @note After reset BDCR register is write-protected and the DBP bit in the
2022 * PWR control register 1 (PWR_CR1) has to be set before it can be written.
2023 * @retval None
2024 */
HAL_RCCEx_DisableLSECSS(void)2025 void HAL_RCCEx_DisableLSECSS(void)
2026 {
2027 /* Unset LSECSSON bit */
2028 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2029 }
2030
2031
2032 /**
2033 * @brief Returns the peripheral clock frequency
2034 * @note Returns 0 if peripheral clock is unknown
2035 * @param PeriphClk: Peripheral clock identifier
2036 * This parameter can be a value of :
2037 * @ref RCCEx_Periph_Clock_Selection
2038 * @ref RCCEx_Periph_One_Clock
2039 * @retval Frequency in Hz
2040 */
HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)2041 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
2042 {
2043 uint32_t frequency = 0, clksource = 0;
2044
2045 PLL2_ClocksTypeDef pll2_clocks;
2046 PLL3_ClocksTypeDef pll3_clocks;
2047 PLL4_ClocksTypeDef pll4_clocks;
2048
2049 /* Check the parameters */
2050 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk) || IS_RCC_PERIPHONECLOCK(PeriphClk));
2051
2052 switch (PeriphClk)
2053 {
2054
2055 case RCC_PERIPHCLK_DAC:
2056 {
2057 frequency = LSI_VALUE;
2058 }
2059 break; /*RCC_PERIPHCLK_DAC*/
2060
2061
2062 case RCC_PERIPHCLK_WWDG:
2063 {
2064 frequency = HAL_RCC_GetPCLK1Freq();
2065 }
2066 break; /* RCC_PERIPHCLK_WWDG */
2067
2068
2069 case RCC_PERIPHCLK_CEC:
2070 {
2071 clksource = __HAL_RCC_GET_CEC_SOURCE();
2072
2073 switch (clksource)
2074 {
2075 case RCC_CECCLKSOURCE_LSE:
2076 frequency = LSE_VALUE;
2077 break;
2078
2079 case RCC_CECCLKSOURCE_LSI:
2080 frequency = LSI_VALUE;
2081 break;
2082
2083 case RCC_CECCLKSOURCE_CSI122:
2084 frequency = (CSI_VALUE / 122);
2085 break;
2086
2087 default:
2088 frequency = 0;
2089 break;
2090 }
2091 }
2092 break; /* RCC_PERIPHCLK_CEC */
2093
2094
2095 case RCC_PERIPHCLK_I2C12:
2096 {
2097 clksource = __HAL_RCC_GET_I2C12_SOURCE();
2098
2099 switch (clksource)
2100 {
2101 case RCC_I2C12CLKSOURCE_BCLK:
2102 frequency = HAL_RCC_GetPCLK1Freq();
2103 break;
2104
2105 case RCC_I2C12CLKSOURCE_PLL4:
2106 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2107 frequency = pll4_clocks.PLL4_R_Frequency;
2108 break;
2109
2110 case RCC_I2C12CLKSOURCE_HSI:
2111 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2112 break;
2113
2114 case RCC_I2C12CLKSOURCE_CSI:
2115 frequency = CSI_VALUE;
2116 break;
2117 }
2118 }
2119 break; /* RCC_PERIPHCLK_I2C12 */
2120
2121
2122 case RCC_PERIPHCLK_I2C35:
2123 {
2124 clksource = __HAL_RCC_GET_I2C35_SOURCE();
2125
2126 switch (clksource)
2127 {
2128 case RCC_I2C35CLKSOURCE_BCLK:
2129 frequency = HAL_RCC_GetPCLK1Freq();
2130 break;
2131
2132 case RCC_I2C35CLKSOURCE_PLL4:
2133 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2134 frequency = pll4_clocks.PLL4_R_Frequency;
2135 break;
2136
2137 case RCC_I2C35CLKSOURCE_HSI:
2138 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2139 break;
2140
2141 case RCC_I2C35CLKSOURCE_CSI:
2142 frequency = CSI_VALUE;
2143 break;
2144 }
2145 }
2146 break; /* RCC_PERIPHCLK_I2C35 */
2147
2148
2149 case RCC_PERIPHCLK_LPTIM1:
2150 {
2151 clksource = __HAL_RCC_GET_LPTIM1_SOURCE();
2152
2153 switch (clksource)
2154 {
2155 case RCC_LPTIM1CLKSOURCE_BCLK:
2156 frequency = HAL_RCC_GetPCLK1Freq();
2157 break;
2158
2159 case RCC_LPTIM1CLKSOURCE_PLL4:
2160 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2161 frequency = pll4_clocks.PLL4_P_Frequency;
2162 break;
2163
2164 case RCC_LPTIM1CLKSOURCE_PLL3:
2165 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2166 frequency = pll3_clocks.PLL3_Q_Frequency;
2167 break;
2168
2169 case RCC_LPTIM1CLKSOURCE_LSE:
2170 frequency = LSE_VALUE;
2171 break;
2172
2173 case RCC_LPTIM1CLKSOURCE_LSI:
2174 frequency = LSI_VALUE;
2175 break;
2176
2177 case RCC_LPTIM1CLKSOURCE_PER:
2178 frequency = RCC_GetCKPERFreq();
2179 break;
2180
2181 default:
2182 frequency = 0;
2183 break;
2184 }
2185 }
2186 break; /* RCC_PERIPHCLK_LPTIM1 */
2187
2188
2189 case RCC_PERIPHCLK_SPDIFRX:
2190 {
2191 clksource = __HAL_RCC_GET_SPDIFRX_SOURCE();
2192
2193 switch (clksource)
2194 {
2195 case RCC_SPDIFRXCLKSOURCE_PLL4:
2196 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2197 frequency = pll4_clocks.PLL4_P_Frequency;
2198 break;
2199
2200 case RCC_SPDIFRXCLKSOURCE_PLL3:
2201 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2202 frequency = pll3_clocks.PLL3_Q_Frequency;
2203 break;
2204
2205 case RCC_SPDIFRXCLKSOURCE_HSI:
2206 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2207 break;
2208
2209 default:
2210 frequency = 0;
2211 break;
2212 }
2213 }
2214 break; /* RCC_PERIPHCLK_SPDIFRX */
2215
2216 case RCC_PERIPHCLK_SPI23:
2217 {
2218 clksource = __HAL_RCC_GET_SPI23_SOURCE();
2219
2220 switch (clksource)
2221 {
2222 case RCC_SPI23CLKSOURCE_PLL4:
2223 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2224 frequency = pll4_clocks.PLL4_P_Frequency;
2225 break;
2226
2227 case RCC_SPI23CLKSOURCE_PLL3_Q:
2228 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2229 frequency = pll3_clocks.PLL3_Q_Frequency;
2230 break;
2231
2232 case RCC_SPI23CLKSOURCE_PLL3_R:
2233 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2234 frequency = pll3_clocks.PLL3_R_Frequency;
2235 break;
2236
2237 case RCC_SPI23CLKSOURCE_I2SCKIN:
2238 frequency = EXTERNAL_CLOCK_VALUE;
2239 break;
2240
2241 case RCC_SPI23CLKSOURCE_PER:
2242 frequency = RCC_GetCKPERFreq();
2243 break;
2244
2245 default:
2246 frequency = 0;
2247 break;
2248 }
2249 }
2250 break; /* RCC_PERIPHCLK_SPI23 */
2251
2252
2253 case RCC_PERIPHCLK_UART24:
2254 {
2255 clksource = __HAL_RCC_GET_UART24_SOURCE();
2256
2257 switch (clksource)
2258 {
2259 case RCC_UART24CLKSOURCE_BCLK:
2260 frequency = HAL_RCC_GetPCLK1Freq();
2261 break;
2262
2263 case RCC_UART24CLKSOURCE_PLL4:
2264 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2265 frequency = pll4_clocks.PLL4_Q_Frequency;
2266 break;
2267
2268 case RCC_UART24CLKSOURCE_HSI:
2269 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2270 break;
2271
2272 case RCC_UART24CLKSOURCE_CSI:
2273 frequency = CSI_VALUE;
2274 break;
2275
2276 case RCC_UART24CLKSOURCE_HSE:
2277 frequency = HSE_VALUE;
2278 break;
2279
2280 default:
2281 frequency = 0;
2282 break;
2283 }
2284 }
2285 break; /* RCC_PERIPHCLK_UART24 */
2286
2287
2288 case RCC_PERIPHCLK_UART35:
2289 {
2290 clksource = __HAL_RCC_GET_UART35_SOURCE();
2291
2292 switch (clksource)
2293 {
2294 case RCC_UART35CLKSOURCE_BCLK:
2295 frequency = HAL_RCC_GetPCLK1Freq();
2296 break;
2297
2298 case RCC_UART35CLKSOURCE_PLL4:
2299 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2300 frequency = pll4_clocks.PLL4_Q_Frequency;
2301 break;
2302
2303 case RCC_UART35CLKSOURCE_HSI:
2304 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2305 break;
2306
2307 case RCC_UART35CLKSOURCE_CSI:
2308 frequency = CSI_VALUE;
2309 break;
2310
2311 case RCC_UART35CLKSOURCE_HSE:
2312 frequency = HSE_VALUE;
2313 break;
2314
2315 default:
2316 frequency = 0;
2317 break;
2318 }
2319 }
2320 break; /* RCC_PERIPHCLK_USART35 */
2321
2322
2323 case RCC_PERIPHCLK_UART78:
2324 {
2325 clksource = __HAL_RCC_GET_UART78_SOURCE();
2326
2327 switch (clksource)
2328 {
2329 case RCC_UART78CLKSOURCE_BCLK:
2330 frequency = HAL_RCC_GetPCLK1Freq();
2331 break;
2332
2333 case RCC_UART78CLKSOURCE_PLL4:
2334 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2335 frequency = pll4_clocks.PLL4_Q_Frequency;
2336 break;
2337
2338 case RCC_UART78CLKSOURCE_HSI:
2339 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2340 break;
2341
2342 case RCC_UART78CLKSOURCE_CSI:
2343 frequency = CSI_VALUE;
2344 break;
2345
2346 case RCC_UART78CLKSOURCE_HSE:
2347 frequency = HSE_VALUE;
2348 break;
2349
2350 default:
2351 frequency = 0;
2352 break;
2353 }
2354 }
2355 break; /*RCC_PERIPHCLK_UART78 */
2356
2357
2358 case RCC_PERIPHCLK_DFSDM1:
2359 {
2360 frequency = HAL_RCC_GetMLHCLKFreq();
2361 }
2362 break;//RCC_PERIPHCLK_DFSDM1
2363
2364 #if defined(FDCAN1)
2365 case RCC_PERIPHCLK_FDCAN:
2366 {
2367 clksource = __HAL_RCC_GET_FDCAN_SOURCE();
2368
2369 switch (clksource)
2370 {
2371 case RCC_FDCANCLKSOURCE_HSE:
2372 frequency = HSE_VALUE;
2373 break;
2374
2375 case RCC_FDCANCLKSOURCE_PLL3:
2376 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2377 frequency = pll3_clocks.PLL3_Q_Frequency;
2378 break;
2379
2380 case RCC_FDCANCLKSOURCE_PLL4_Q:
2381 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2382 frequency = pll4_clocks.PLL4_Q_Frequency;
2383 break;
2384
2385 case RCC_FDCANCLKSOURCE_PLL4_R:
2386 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2387 frequency = pll4_clocks.PLL4_R_Frequency;
2388 break;
2389
2390 default:
2391 frequency = 0;
2392 break;
2393 }
2394 }
2395 break;//RCC_PERIPHCLK_FDCAN
2396 #endif /*FDCAN1*/
2397
2398 case RCC_PERIPHCLK_SAI1:
2399 {
2400 clksource = __HAL_RCC_GET_SAI1_SOURCE();
2401
2402 switch (clksource)
2403 {
2404 case RCC_SAI1CLKSOURCE_PLL4:
2405 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2406 frequency = pll4_clocks.PLL4_Q_Frequency;
2407 break;
2408
2409 case RCC_SAI1CLKSOURCE_PLL3_Q:
2410 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2411 frequency = pll3_clocks.PLL3_Q_Frequency;
2412 break;
2413
2414 case RCC_SAI1CLKSOURCE_PLL3_R:
2415 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2416 frequency = pll3_clocks.PLL3_R_Frequency;
2417 break;
2418
2419 case RCC_SAI1CLKSOURCE_I2SCKIN:
2420 frequency = EXTERNAL_CLOCK_VALUE;
2421 break;
2422
2423 case RCC_SAI1CLKSOURCE_PER:
2424 frequency = RCC_GetCKPERFreq();
2425 break;
2426
2427 default:
2428 frequency = 0;
2429 break;
2430 }
2431 }
2432 break;//RCC_PERIPHCLK_SAI1
2433
2434
2435 case RCC_PERIPHCLK_SAI2:
2436 {
2437 clksource = __HAL_RCC_GET_SAI2_SOURCE();
2438
2439 switch (clksource)
2440 {
2441 case RCC_SAI2CLKSOURCE_PLL4:
2442 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2443 frequency = pll4_clocks.PLL4_Q_Frequency;
2444 break;
2445
2446 case RCC_SAI2CLKSOURCE_PLL3_Q:
2447 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2448 frequency = pll3_clocks.PLL3_Q_Frequency;
2449 break;
2450
2451 case RCC_SAI2CLKSOURCE_PLL3_R:
2452 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2453 frequency = pll3_clocks.PLL3_R_Frequency;
2454 break;
2455
2456 case RCC_SAI2CLKSOURCE_I2SCKIN:
2457 frequency = EXTERNAL_CLOCK_VALUE;
2458 break;
2459
2460 case RCC_SAI2CLKSOURCE_PER:
2461 frequency = RCC_GetCKPERFreq();
2462 break;
2463
2464 case RCC_SAI2CLKSOURCE_SPDIF:
2465 frequency = 0; //SAI2 manage this SPDIF_CKSYMB_VALUE
2466 break;
2467
2468 default:
2469 frequency = 0;
2470 break;
2471 }
2472 }
2473 break;//RCC_PERIPHCLK_SAI2
2474
2475
2476 case RCC_PERIPHCLK_SAI3:
2477 {
2478 clksource = __HAL_RCC_GET_SAI3_SOURCE();
2479
2480 switch (clksource)
2481 {
2482 case RCC_SAI3CLKSOURCE_PLL4:
2483 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2484 frequency = pll4_clocks.PLL4_Q_Frequency;
2485 break;
2486
2487 case RCC_SAI3CLKSOURCE_PLL3_Q:
2488 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2489 frequency = pll3_clocks.PLL3_Q_Frequency;
2490 break;
2491
2492 case RCC_SAI3CLKSOURCE_PLL3_R:
2493 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2494 frequency = pll3_clocks.PLL3_R_Frequency;
2495 break;
2496
2497 case RCC_SAI3CLKSOURCE_I2SCKIN:
2498 frequency = EXTERNAL_CLOCK_VALUE;
2499 break;
2500
2501 case RCC_SAI2CLKSOURCE_PER:
2502 frequency = RCC_GetCKPERFreq();
2503 break;
2504
2505 default:
2506 frequency = 0;
2507 break;
2508 }
2509 }
2510 break;//RCC_PERIPHCLK_SAI3
2511
2512
2513 case RCC_PERIPHCLK_SPI1:
2514 {
2515 clksource = __HAL_RCC_GET_SPI1_SOURCE();
2516
2517 switch (clksource)
2518 {
2519 case RCC_SPI1CLKSOURCE_PLL4:
2520 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2521 frequency = pll4_clocks.PLL4_Q_Frequency;
2522 break;
2523
2524 case RCC_SPI1CLKSOURCE_PLL3_Q:
2525 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2526 frequency = pll3_clocks.PLL3_Q_Frequency;
2527 break;
2528
2529 case RCC_SPI1CLKSOURCE_PLL3_R:
2530 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2531 frequency = pll3_clocks.PLL3_R_Frequency;
2532 break;
2533
2534 case RCC_SPI1CLKSOURCE_I2SCKIN:
2535 frequency = EXTERNAL_CLOCK_VALUE;
2536 break;
2537
2538 case RCC_SPI1CLKSOURCE_PER:
2539 frequency = RCC_GetCKPERFreq();
2540 break;
2541
2542 default:
2543 frequency = 0;
2544 break;
2545 }
2546 }
2547 break;//RCC_PERIPHCLK_SPI1
2548
2549
2550 case RCC_PERIPHCLK_SPI45:
2551 {
2552 clksource = __HAL_RCC_GET_SPI45_SOURCE();
2553
2554 switch (clksource)
2555 {
2556 case RCC_SPI45CLKSOURCE_BCLK:
2557 frequency = HAL_RCC_GetPCLK2Freq();
2558 break;
2559
2560 case RCC_SPI45CLKSOURCE_PLL4:
2561 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2562 frequency = pll4_clocks.PLL4_Q_Frequency;
2563 break;
2564
2565 case RCC_SPI45CLKSOURCE_HSI:
2566 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2567 break;
2568
2569 case RCC_SPI45CLKSOURCE_CSI:
2570 frequency = CSI_VALUE;
2571 break;
2572
2573 case RCC_SPI45CLKSOURCE_HSE:
2574 frequency = HSE_VALUE;
2575 break;
2576
2577 default:
2578 frequency = 0;
2579 break;
2580 }
2581 }
2582 break; /* RCC_PERIPHCLK_SPI45 */
2583
2584
2585 case RCC_PERIPHCLK_USART6:
2586 {
2587 clksource = __HAL_RCC_GET_USART6_SOURCE();
2588
2589 switch (clksource)
2590 {
2591 case RCC_USART6CLKSOURCE_BCLK:
2592 frequency = HAL_RCC_GetPCLK2Freq();
2593 break;
2594
2595 case RCC_USART6CLKSOURCE_PLL4:
2596 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2597 frequency = pll4_clocks.PLL4_Q_Frequency;
2598 break;
2599
2600 case RCC_USART6CLKSOURCE_HSI:
2601 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2602 break;
2603
2604 case RCC_USART6CLKSOURCE_CSI:
2605 frequency = CSI_VALUE;
2606 break;
2607
2608 case RCC_USART6CLKSOURCE_HSE:
2609 frequency = HSE_VALUE;
2610 break;
2611
2612 default:
2613 frequency = 0;
2614 break;
2615 }
2616 }
2617 break;//RCC_PERIPHCLK_USART6
2618
2619 case RCC_PERIPHCLK_LPTIM23:
2620 {
2621 clksource = __HAL_RCC_GET_LPTIM23_SOURCE();
2622
2623 switch (clksource)
2624 {
2625 case RCC_LPTIM23CLKSOURCE_BCLK:
2626 frequency = HAL_RCC_GetPCLK3Freq();
2627 break;
2628
2629 case RCC_LPTIM23CLKSOURCE_PLL4:
2630 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2631 frequency = pll4_clocks.PLL4_Q_Frequency;
2632 break;
2633
2634 case RCC_LPTIM23CLKSOURCE_PER:
2635 frequency = RCC_GetCKPERFreq();
2636 break;
2637
2638 case RCC_LPTIM23CLKSOURCE_LSE:
2639 frequency = LSE_VALUE;
2640 break;
2641
2642 case RCC_LPTIM23CLKSOURCE_LSI:
2643 frequency = LSI_VALUE;
2644 break;
2645
2646 default:
2647 frequency = 0;
2648 break;
2649 }
2650 }
2651 break; /* RCC_PERIPHCLK_LPTIM23 */
2652
2653 case RCC_PERIPHCLK_LPTIM45:
2654 {
2655 clksource = __HAL_RCC_GET_LPTIM45_SOURCE();
2656
2657 switch (clksource)
2658 {
2659 case RCC_LPTIM45CLKSOURCE_BCLK:
2660 frequency = HAL_RCC_GetPCLK3Freq();
2661 break;
2662
2663 case RCC_LPTIM45CLKSOURCE_PLL4:
2664 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2665 frequency = pll4_clocks.PLL4_P_Frequency;
2666 break;
2667
2668 case RCC_LPTIM45CLKSOURCE_PLL3:
2669 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2670 frequency = pll3_clocks.PLL3_Q_Frequency;
2671 break;
2672
2673 case RCC_LPTIM45CLKSOURCE_LSE:
2674 frequency = LSE_VALUE;
2675 break;
2676
2677 case RCC_LPTIM45CLKSOURCE_LSI:
2678 frequency = LSI_VALUE;
2679 break;
2680
2681 case RCC_LPTIM45CLKSOURCE_PER:
2682 frequency = RCC_GetCKPERFreq();
2683 break;
2684
2685 default:
2686 frequency = 0;
2687 break;
2688 }
2689 }
2690 break; /* RCC_PERIPHCLK_LPTIM45 */
2691
2692
2693 case RCC_PERIPHCLK_SAI4:
2694 {
2695 clksource = __HAL_RCC_GET_SAI4_SOURCE();
2696
2697 switch (clksource)
2698 {
2699 case RCC_SAI4CLKSOURCE_PLL4:
2700 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2701 frequency = pll4_clocks.PLL4_Q_Frequency;
2702 break;
2703
2704 case RCC_SAI4CLKSOURCE_PLL3_Q:
2705 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2706 frequency = pll3_clocks.PLL3_Q_Frequency;
2707 break;
2708
2709 case RCC_SAI4CLKSOURCE_PLL3_R:
2710 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2711 frequency = pll3_clocks.PLL3_R_Frequency;
2712 break;
2713
2714 case RCC_SAI4CLKSOURCE_I2SCKIN:
2715 frequency = EXTERNAL_CLOCK_VALUE;
2716 break;
2717
2718 case RCC_SAI4CLKSOURCE_PER:
2719 frequency = RCC_GetCKPERFreq();
2720 break;
2721
2722 default:
2723 frequency = 0;
2724 break;
2725 }
2726 }
2727 break;//RCC_PERIPHCLK_SAI4
2728
2729
2730 case RCC_PERIPHCLK_TEMP:
2731 {
2732 frequency = LSE_VALUE;
2733 }
2734 break;//RCC_PERIPHCLK_TEMP
2735
2736
2737 #if defined(DSI)
2738 case RCC_PERIPHCLK_DSI:
2739 {
2740 clksource = __HAL_RCC_GET_DSI_SOURCE();
2741
2742 switch (clksource)
2743 {
2744 case RCC_DSICLKSOURCE_PHY:
2745 /* It has no sense to ask for DSIPHY freq. because it is generated
2746 * by DSI itself, so send back 0 as kernel frequency
2747 */
2748 frequency = 0;
2749 break;
2750
2751 case RCC_DSICLKSOURCE_PLL4:
2752 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2753 frequency = pll4_clocks.PLL4_P_Frequency;
2754 break;
2755 }
2756 }
2757 break;//RCC_PERIPHCLK_DSI
2758 #endif /*DSI*/
2759
2760 case RCC_PERIPHCLK_LTDC:
2761 {
2762 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2763 frequency = pll4_clocks.PLL4_Q_Frequency;
2764 }
2765 break;//RCC_PERIPHCLK_LTDC
2766
2767
2768 case RCC_PERIPHCLK_USBPHY:
2769 {
2770 clksource = __HAL_RCC_GET_USBPHY_SOURCE();
2771
2772 switch (clksource)
2773 {
2774 case RCC_USBPHYCLKSOURCE_HSE:
2775 frequency = HSE_VALUE;
2776 break;
2777
2778 case RCC_USBPHYCLKSOURCE_PLL4:
2779 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2780 frequency = pll4_clocks.PLL4_R_Frequency;
2781 break;
2782
2783 case RCC_USBPHYCLKSOURCE_HSE2:
2784 frequency = (HSE_VALUE / 2);
2785 break;
2786
2787 default:
2788 frequency = 0;
2789 break;
2790 }
2791 }
2792 break;//RCC_PERIPHCLK_USBPHY
2793
2794
2795 case RCC_PERIPHCLK_IWDG2:
2796 {
2797 frequency = LSI_VALUE;
2798 }
2799 break;//RCC_PERIPHCLK_IWDG2
2800
2801
2802 case RCC_PERIPHCLK_DDRPHYC:
2803 {
2804 HAL_RCC_GetPLL2ClockFreq(&pll2_clocks);
2805 frequency = pll2_clocks.PLL2_R_Frequency;
2806 }
2807 break;//RCC_PERIPHCLK_DDRPHYC
2808
2809
2810 case RCC_PERIPHCLK_RTC:
2811 {
2812 clksource = __HAL_RCC_GET_RTC_SOURCE();
2813
2814 switch (clksource)
2815 {
2816 case RCC_RTCCLKSOURCE_OFF:
2817 frequency = 0;
2818 break;
2819
2820 case RCC_RTCCLKSOURCE_LSE:
2821 frequency = LSE_VALUE;
2822 break;
2823
2824 case RCC_RTCCLKSOURCE_LSI:
2825 frequency = LSI_VALUE;
2826 break;
2827
2828 case RCC_RTCCLKSOURCE_HSE_DIV:
2829 frequency = (HSE_VALUE / __HAL_RCC_GET_RTC_HSEDIV());
2830 break;
2831 }
2832 }
2833 break;//RCC_PERIPHCLK_RTC
2834
2835
2836 case RCC_PERIPHCLK_IWDG1:
2837 {
2838 frequency = LSI_VALUE;
2839 }
2840 break;//RCC_PERIPHCLK_IWDG1
2841
2842
2843 case RCC_PERIPHCLK_I2C46:
2844 {
2845 clksource = __HAL_RCC_GET_I2C46_SOURCE();
2846
2847 switch (clksource)
2848 {
2849 case RCC_I2C46CLKSOURCE_BCLK:
2850 frequency = HAL_RCC_GetPCLK5Freq();
2851 break;
2852
2853 case RCC_I2C46CLKSOURCE_PLL3:
2854 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2855 frequency = pll3_clocks.PLL3_Q_Frequency;
2856 break;
2857
2858 case RCC_I2C46CLKSOURCE_HSI:
2859 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2860 break;
2861
2862 case RCC_I2C46CLKSOURCE_CSI:
2863 frequency = CSI_VALUE;
2864 break;
2865
2866 default:
2867 frequency = 0;
2868 break;
2869 }
2870 }
2871 break; /* RCC_PERIPHCLK_I2C46 */
2872
2873
2874 case RCC_PERIPHCLK_SPI6:
2875 {
2876 clksource = __HAL_RCC_GET_SPI6_SOURCE();
2877
2878 switch (clksource)
2879 {
2880 case RCC_SPI6CLKSOURCE_BCLK:
2881 frequency = HAL_RCC_GetPCLK5Freq();
2882 break;
2883
2884 case RCC_SPI6CLKSOURCE_PLL4:
2885 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2886 frequency = pll4_clocks.PLL4_Q_Frequency;
2887 break;
2888
2889 case RCC_SPI6CLKSOURCE_HSI:
2890 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2891 break;
2892
2893 case RCC_SPI6CLKSOURCE_CSI:
2894 frequency = CSI_VALUE;
2895 break;
2896
2897 case RCC_SPI6CLKSOURCE_HSE:
2898 frequency = HSE_VALUE;
2899 break;
2900
2901 case RCC_SPI6CLKSOURCE_PLL3:
2902 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2903 frequency = pll3_clocks.PLL3_Q_Frequency;
2904 break;
2905
2906 default:
2907 frequency = 0;
2908 break;
2909 }
2910 }
2911 break;//RCC_PERIPHCLK_SPI6
2912
2913 case RCC_PERIPHCLK_USART1:
2914 {
2915 clksource = __HAL_RCC_GET_USART1_SOURCE();
2916
2917 switch (clksource)
2918 {
2919 case RCC_USART1CLKSOURCE_BCLK:
2920 frequency = HAL_RCC_GetPCLK5Freq();
2921 break;
2922
2923 case RCC_USART1CLKSOURCE_PLL3:
2924 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2925 frequency = pll3_clocks.PLL3_Q_Frequency;
2926 break;
2927
2928 case RCC_USART1CLKSOURCE_HSI:
2929 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2930 break;
2931
2932 case RCC_USART1CLKSOURCE_CSI:
2933 frequency = CSI_VALUE;
2934 break;
2935
2936 case RCC_USART1CLKSOURCE_PLL4:
2937 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2938 frequency = pll4_clocks.PLL4_Q_Frequency;
2939 break;
2940
2941 case RCC_USART1CLKSOURCE_HSE:
2942 frequency = HSE_VALUE;
2943 break;
2944
2945 default:
2946 frequency = 0;
2947 break;
2948 }
2949 }
2950 break;//RCC_PERIPHCLK_USART1
2951
2952
2953 case RCC_PERIPHCLK_STGEN:
2954 {
2955 clksource = __HAL_RCC_GET_STGEN_SOURCE();
2956
2957 switch (clksource)
2958 {
2959 case RCC_STGENCLKSOURCE_HSI:
2960 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2961 break;
2962
2963 case RCC_STGENCLKSOURCE_HSE:
2964 frequency = HSE_VALUE;
2965 break;
2966
2967 default:
2968 frequency = 0;
2969 break;
2970 }
2971 }
2972 break;//RCC_PERIPHCLK_STGEN
2973
2974
2975 case RCC_PERIPHCLK_QSPI:
2976 {
2977 clksource = __HAL_RCC_GET_QSPI_SOURCE();
2978
2979 switch (clksource)
2980 {
2981 case RCC_QSPICLKSOURCE_BCLK:
2982 frequency = HAL_RCC_GetACLKFreq();
2983 break;
2984
2985 case RCC_QSPICLKSOURCE_PLL3:
2986 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2987 frequency = pll3_clocks.PLL3_R_Frequency;
2988 break;
2989
2990 case RCC_QSPICLKSOURCE_PLL4:
2991 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2992 frequency = pll4_clocks.PLL4_P_Frequency;
2993 break;
2994
2995 case RCC_QSPICLKSOURCE_PER:
2996 frequency = RCC_GetCKPERFreq();
2997 break;
2998
2999 default:
3000 frequency = 0;
3001 break;
3002 }
3003 }
3004 break;//RCC_PERIPHCLK_QSPI
3005
3006
3007 case RCC_PERIPHCLK_ETH:
3008 {
3009 clksource = __HAL_RCC_GET_ETH_SOURCE();
3010
3011 switch (clksource)
3012 {
3013 case RCC_ETHCLKSOURCE_PLL4:
3014 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
3015 frequency = pll4_clocks.PLL4_P_Frequency;
3016 break;
3017
3018 case RCC_ETHCLKSOURCE_PLL3:
3019 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
3020 frequency = pll3_clocks.PLL3_Q_Frequency;
3021 break;
3022
3023 default:
3024 frequency = 0;
3025 break;
3026 }
3027 }
3028 break;//RCC_PERIPHCLK_ETH
3029
3030
3031 case RCC_PERIPHCLK_FMC:
3032 {
3033 clksource = __HAL_RCC_GET_FMC_SOURCE();
3034
3035 switch (clksource)
3036 {
3037 case RCC_FMCCLKSOURCE_BCLK:
3038 frequency = HAL_RCC_GetACLKFreq();
3039 break;
3040
3041 case RCC_FMCCLKSOURCE_PLL3:
3042 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
3043 frequency = pll3_clocks.PLL3_R_Frequency;
3044 break;
3045
3046 case RCC_FMCCLKSOURCE_PLL4:
3047 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
3048 frequency = pll4_clocks.PLL4_P_Frequency;
3049 break;
3050
3051 case RCC_FMCCLKSOURCE_PER:
3052 frequency = RCC_GetCKPERFreq();
3053 break;
3054
3055 }
3056 }
3057 break;//RCC_PERIPHCLK_FMC
3058
3059
3060 case RCC_PERIPHCLK_GPU:
3061 {
3062 HAL_RCC_GetPLL2ClockFreq(&pll2_clocks);
3063 frequency = pll2_clocks.PLL2_Q_Frequency;
3064 }
3065 break;//RCC_PERIPHCLK_GPU
3066
3067
3068 case RCC_PERIPHCLK_USBO:
3069 {
3070 clksource = __HAL_RCC_GET_USBO_SOURCE();
3071
3072 switch (clksource)
3073 {
3074 case RCC_USBOCLKSOURCE_PLL4:
3075 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
3076 frequency = pll4_clocks.PLL4_R_Frequency;
3077 break;
3078
3079 case RCC_USBOCLKSOURCE_PHY:
3080 frequency = USB_PHY_VALUE;
3081 break;
3082 }
3083 }
3084 break;//RCC_PERIPHCLK_USBO
3085
3086
3087 case RCC_PERIPHCLK_SDMMC3:
3088 {
3089 clksource = __HAL_RCC_GET_SDMMC3_SOURCE();
3090
3091 switch (clksource)
3092 {
3093 case RCC_SDMMC3CLKSOURCE_BCLK:
3094 frequency = HAL_RCC_GetHCLK2Freq();
3095 break;
3096
3097 case RCC_SDMMC3CLKSOURCE_PLL3:
3098 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
3099 frequency = pll3_clocks.PLL3_R_Frequency;
3100 break;
3101
3102 case RCC_SDMMC3CLKSOURCE_PLL4:
3103 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
3104 frequency = pll4_clocks.PLL4_P_Frequency;
3105 break;
3106
3107 case RCC_SDMMC3CLKSOURCE_HSI:
3108 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
3109
3110 default:
3111 frequency = 0;
3112 break;
3113 }
3114 }
3115 break;//RCC_PERIPHCLK_SDMMC3
3116
3117
3118 case RCC_PERIPHCLK_ADC:
3119 {
3120 clksource = __HAL_RCC_GET_ADC_SOURCE();
3121
3122 switch (clksource)
3123 {
3124 case RCC_ADCCLKSOURCE_PLL4:
3125 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
3126 frequency = pll4_clocks.PLL4_R_Frequency;
3127 break;
3128
3129 case RCC_ADCCLKSOURCE_PER:
3130 frequency = RCC_GetCKPERFreq();
3131 break;
3132
3133 case RCC_ADCCLKSOURCE_PLL3:
3134 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
3135 frequency = pll3_clocks.PLL3_Q_Frequency;
3136
3137 default:
3138 frequency = 0;
3139 break;
3140 }
3141 }
3142 break; /* RCC_PERIPHCLK_ADC */
3143
3144
3145 case RCC_PERIPHCLK_RNG2:
3146 {
3147 clksource = __HAL_RCC_GET_RNG2_SOURCE();
3148
3149 switch (clksource)
3150 {
3151 case RCC_RNG2CLKSOURCE_CSI:
3152 frequency = CSI_VALUE;
3153 break;
3154
3155 case RCC_RNG2CLKSOURCE_PLL4:
3156 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
3157 frequency = pll4_clocks.PLL4_R_Frequency;
3158 break;
3159
3160 case RCC_RNG2CLKSOURCE_LSE:
3161 frequency = LSE_VALUE;
3162 break;
3163
3164 case RCC_RNG2CLKSOURCE_LSI:
3165 frequency = LSI_VALUE;
3166 break;
3167 }
3168 }
3169 break;//RCC_PERIPHCLK_RNG2
3170
3171
3172 case RCC_PERIPHCLK_RNG1:
3173 {
3174 clksource = __HAL_RCC_GET_RNG1_SOURCE();
3175
3176 switch (clksource)
3177 {
3178 case RCC_RNG1CLKSOURCE_CSI:
3179 frequency = CSI_VALUE;
3180 break;
3181
3182 case RCC_RNG1CLKSOURCE_PLL4:
3183 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
3184 frequency = pll4_clocks.PLL4_R_Frequency;
3185 break;
3186
3187 case RCC_RNG1CLKSOURCE_LSE:
3188 frequency = LSE_VALUE;
3189 break;
3190
3191 case RCC_RNG1CLKSOURCE_LSI:
3192 frequency = LSI_VALUE;
3193 break;
3194 }
3195 }
3196 break;//RCC_PERIPHCLK_RNG1
3197
3198 case RCC_PERIPHCLK_SDMMC12:
3199 {
3200 clksource = __HAL_RCC_GET_SDMMC12_SOURCE();
3201
3202 switch (clksource)
3203 {
3204 case RCC_SDMMC12CLKSOURCE_BCLK:
3205 frequency = HAL_RCC_GetHCLK6Freq();
3206 break;
3207
3208 case RCC_SDMMC12CLKSOURCE_PLL3:
3209 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
3210 frequency = pll3_clocks.PLL3_R_Frequency;
3211 break;
3212
3213 case RCC_SDMMC12CLKSOURCE_PLL4:
3214 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
3215 frequency = pll4_clocks.PLL4_P_Frequency;
3216 break;
3217
3218 case RCC_SDMMC12CLKSOURCE_HSI:
3219 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
3220 break;
3221
3222 default:
3223 frequency = 0;
3224 break;
3225 }
3226 }
3227 break; /* RCC_PERIPHCLK_SDMMC12 */
3228
3229 case RCC_PERIPHCLK_TIMG1:
3230 {
3231 frequency = HAL_RCC_GetMCUFreq();
3232 if (__HAL_RCC_GET_TIMG1PRES() == RCC_TIMG1PRES_ACTIVATED)
3233 {
3234 switch (__HAL_RCC_GET_APB1_DIV())
3235 {
3236 case RCC_APB1_DIV1:
3237 case RCC_APB1_DIV2:
3238 case RCC_APB1_DIV4:
3239 break;
3240 case RCC_APB1_DIV8:
3241 frequency /= 2;
3242 break;
3243 case RCC_APB1_DIV16:
3244 frequency /= 4;
3245 break;
3246 }
3247 }
3248 else
3249 {
3250 switch (__HAL_RCC_GET_APB1_DIV())
3251 {
3252 case RCC_APB1_DIV1:
3253 case RCC_APB1_DIV2:
3254 break;
3255 case RCC_APB1_DIV4:
3256 frequency /= 2;
3257 break;
3258 case RCC_APB1_DIV8:
3259 frequency /= 4;
3260 break;
3261 case RCC_APB1_DIV16:
3262 frequency /= 8;
3263 break;
3264 }
3265 }
3266 }
3267 break;
3268
3269
3270 case RCC_PERIPHCLK_TIMG2:
3271 {
3272 frequency = HAL_RCC_GetMCUFreq();
3273 if (__HAL_RCC_GET_TIMG2PRES() == RCC_TIMG2PRES_ACTIVATED)
3274 {
3275 switch (__HAL_RCC_GET_APB2_DIV())
3276 {
3277 case RCC_APB2_DIV1:
3278 case RCC_APB2_DIV2:
3279 case RCC_APB2_DIV4:
3280 break;
3281 case RCC_APB2_DIV8:
3282 frequency /= 2;
3283 break;
3284 case RCC_APB2_DIV16:
3285 frequency /= 4;
3286 break;
3287 }
3288 }
3289 else
3290 {
3291 switch (__HAL_RCC_GET_APB2_DIV())
3292 {
3293 case RCC_APB2_DIV1:
3294 case RCC_APB2_DIV2:
3295 break;
3296 case RCC_APB2_DIV4:
3297 frequency /= 2;
3298 break;
3299 case RCC_APB2_DIV8:
3300 frequency /= 4;
3301 break;
3302 case RCC_APB2_DIV16:
3303 frequency /= 8;
3304 break;
3305 }
3306 }
3307 }
3308 break;
3309
3310 }
3311
3312 return (frequency);
3313 }
3314
3315 #ifdef CORE_CA7
3316 /**
3317 * @brief Control the enable boot function when the system exits from STANDBY
3318 * @param RCC_BootCx: Boot Core to be enabled (set to 1)
3319 * This parameter can be one (or both) of the following values:
3320 * @arg RCC_BOOT_C1: CA7 core selection
3321 * @arg RCC_BOOT_C2: CM4 core selection
3322 *
3323 * @note Next combinations are possible:
3324 * RCC_BOOT_C1 RCC_BOOT_C2 Expected result
3325 * 0 0 MPU boots, MCU does not boot
3326 * 0 1 Only MCU boots
3327 * 1 0 Only MPU boots
3328 * 1 1 MPU and MCU boot
3329 *
3330 * @note This function is reset when a system reset occurs, but not when the
3331 * circuit exits from STANDBY (rst_app reset)
3332 * @note This function can only be called by the CA7
3333 * @retval None
3334 */
HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)3335 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)
3336 {
3337 assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));
3338 SET_BIT(RCC->MP_BOOTCR, RCC_BootCx);
3339 }
3340
3341 /**
3342 * @brief Control the disable boot function when the system exits from STANDBY
3343 * @param RCC_BootCx: Boot Core to be disabled (set to 0)
3344 * This parameter can be one (or both) of the following values:
3345 * @arg RCC_BOOT_C1: CA7 core selection
3346 * @arg RCC_BOOT_C2: CM4 core selection
3347 *
3348 * @note Next combinations are possible:
3349 * RCC_BOOT_C1 RCC_BOOT_C2 Expected result
3350 * 0 0 MPU boots, MCU does not boot
3351 * 0 1 Only MCU boots
3352 * 1 0 Only MPU boots
3353 * 1 1 MPU and MCU boot
3354 *
3355 * @note This function is reset when a system reset occurs, but not when the
3356 * circuit exits from STANDBY (rst_app reset)
3357 * @note This function can only be called by the CA7
3358 * @retval None
3359 */
HAL_RCCEx_DisableBootCore(uint32_t RCC_BootCx)3360 void HAL_RCCEx_DisableBootCore(uint32_t RCC_BootCx)
3361 {
3362 assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));
3363 CLEAR_BIT(RCC->MP_BOOTCR, RCC_BootCx);
3364 }
3365
3366
3367 /**
3368 * @brief The MCU will be set in HOLD_BOOT when the next MCU core reset occurs
3369 * @retval None
3370 */
HAL_RCCEx_HoldBootMCU(void)3371 void HAL_RCCEx_HoldBootMCU(void)
3372 {
3373 CLEAR_BIT(RCC->MP_GCR, RCC_MP_GCR_BOOT_MCU);
3374 }
3375
3376 /**
3377 * @brief The MCU will not be in HOLD_BOOT mode when the next MCU core reset occurs.
3378 * @note If the MCU was in HOLD_BOOT it will cause the MCU to boot.
3379 * @retval None
3380 */
HAL_RCCEx_BootMCU(void)3381 void HAL_RCCEx_BootMCU(void)
3382 {
3383 SET_BIT(RCC->MP_GCR, RCC_MP_GCR_BOOT_MCU);
3384 }
3385
3386 #endif /*CORE_CA7*/
3387
3388 /**
3389 * @}
3390 */
3391
3392 /**
3393 * @}
3394 */
3395
3396 #endif /* HAL_RCC_MODULE_ENABLED */
3397 /**
3398 * @}
3399 */
3400
3401 /**
3402 * @}
3403 */
3404
3405 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3406
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