1 /* 2 * include/linux/amlogic/media/registers/regs/hevc_regs.h 3 * 4 * Copyright (C) 2017 Amlogic, Inc. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 */ 17 18 #ifndef HEVC_REGS_HEADERS__ 19 #define HEVC_REGS_HEADERS__ 20 /*add from M8M2*/ 21 #define HEVC_ASSIST_AFIFO_CTRL 0x3001 22 #define HEVC_ASSIST_AFIFO_CTRL1 0x3002 23 #define HEVC_ASSIST_GCLK_EN 0x3003 24 #define HEVC_ASSIST_SW_RESET 0x3004 25 #define HEVC_ASSIST_AMR1_INT0 0x3025 26 #define HEVC_ASSIST_AMR1_INT1 0x3026 27 #define HEVC_ASSIST_AMR1_INT2 0x3027 28 #define HEVC_ASSIST_AMR1_INT3 0x3028 29 #define HEVC_ASSIST_AMR1_INT4 0x3029 30 #define HEVC_ASSIST_AMR1_INT5 0x302a 31 #define HEVC_ASSIST_AMR1_INT6 0x302b 32 #define HEVC_ASSIST_AMR1_INT7 0x302c 33 #define HEVC_ASSIST_AMR1_INT8 0x302d 34 #define HEVC_ASSIST_AMR1_INT9 0x302e 35 #define HEVC_ASSIST_AMR1_INTA 0x302f 36 #define HEVC_ASSIST_AMR1_INTB 0x3030 37 #define HEVC_ASSIST_AMR1_INTC 0x3031 38 #define HEVC_ASSIST_AMR1_INTD 0x3032 39 #define HEVC_ASSIST_AMR1_INTE 0x3033 40 #define HEVC_ASSIST_AMR1_INTF 0x3034 41 #define HEVC_ASSIST_AMR2_INT0 0x3035 42 #define HEVC_ASSIST_AMR2_INT1 0x3036 43 #define HEVC_ASSIST_AMR2_INT2 0x3037 44 #define HEVC_ASSIST_AMR2_INT3 0x3038 45 #define HEVC_ASSIST_AMR2_INT4 0x3039 46 #define HEVC_ASSIST_AMR2_INT5 0x303a 47 #define HEVC_ASSIST_AMR2_INT6 0x303b 48 #define HEVC_ASSIST_AMR2_INT7 0x303c 49 #define HEVC_ASSIST_AMR2_INT8 0x303d 50 #define HEVC_ASSIST_AMR2_INT9 0x303e 51 #define HEVC_ASSIST_AMR2_INTA 0x303f 52 #define HEVC_ASSIST_AMR2_INTB 0x3040 53 #define HEVC_ASSIST_AMR2_INTC 0x3041 54 #define HEVC_ASSIST_AMR2_INTD 0x3042 55 #define HEVC_ASSIST_AMR2_INTE 0x3043 56 #define HEVC_ASSIST_AMR2_INTF 0x3044 57 #define HEVC_ASSIST_MBX_SSEL 0x3045 58 #define HEVC_ASSIST_TIMER0_LO 0x3060 59 #define HEVC_ASSIST_TIMER0_HI 0x3061 60 #define HEVC_ASSIST_TIMER1_LO 0x3062 61 #define HEVC_ASSIST_TIMER1_HI 0x3063 62 #define HEVC_ASSIST_DMA_INT 0x3064 63 #define HEVC_ASSIST_DMA_INT_MSK 0x3065 64 #define HEVC_ASSIST_DMA_INT2 0x3066 65 #define HEVC_ASSIST_DMA_INT_MSK2 0x3067 66 #define HEVC_ASSIST_MBOX0_IRQ_REG 0x3070 67 #define HEVC_ASSIST_MBOX0_CLR_REG 0x3071 68 #define HEVC_ASSIST_MBOX0_MASK 0x3072 69 #define HEVC_ASSIST_MBOX0_FIQ_SEL 0x3073 70 #define HEVC_ASSIST_MBOX1_IRQ_REG 0x3074 71 #define HEVC_ASSIST_MBOX1_CLR_REG 0x3075 72 #define HEVC_ASSIST_MBOX1_MASK 0x3076 73 #define HEVC_ASSIST_MBOX1_FIQ_SEL 0x3077 74 #define HEVC_ASSIST_MBOX2_IRQ_REG 0x3078 75 #define HEVC_ASSIST_MBOX2_CLR_REG 0x3079 76 #define HEVC_ASSIST_MBOX2_MASK 0x307a 77 #define HEVC_ASSIST_MBOX2_FIQ_SEL 0x307b 78 #define HEVC_ASSIST_AXI_CTRL 0x307c 79 #define HEVC_ASSIST_AXI_STATUS 0x307d 80 #define HEVC_ASSIST_SCRATCH_0 0x30c0 81 #define HEVC_ASSIST_SCRATCH_1 0x30c1 82 #define HEVC_ASSIST_SCRATCH_2 0x30c2 83 #define HEVC_ASSIST_SCRATCH_3 0x30c3 84 #define HEVC_ASSIST_SCRATCH_4 0x30c4 85 #define HEVC_ASSIST_SCRATCH_5 0x30c5 86 #define HEVC_ASSIST_SCRATCH_6 0x30c6 87 #define HEVC_ASSIST_SCRATCH_7 0x30c7 88 #define HEVC_ASSIST_SCRATCH_8 0x30c8 89 #define HEVC_ASSIST_SCRATCH_9 0x30c9 90 #define HEVC_ASSIST_SCRATCH_A 0x30ca 91 #define HEVC_ASSIST_SCRATCH_B 0x30cb 92 #define HEVC_ASSIST_SCRATCH_C 0x30cc 93 #define HEVC_ASSIST_SCRATCH_D 0x30cd 94 #define HEVC_ASSIST_SCRATCH_E 0x30ce 95 #define HEVC_ASSIST_SCRATCH_F 0x30cf 96 #define HEVC_ASSIST_SCRATCH_G 0x30d0 97 #define HEVC_ASSIST_SCRATCH_H 0x30d1 98 #define HEVC_ASSIST_SCRATCH_I 0x30d2 99 #define HEVC_ASSIST_SCRATCH_J 0x30d3 100 #define HEVC_ASSIST_SCRATCH_K 0x30d4 101 #define HEVC_ASSIST_SCRATCH_L 0x30d5 102 #define HEVC_ASSIST_SCRATCH_M 0x30d6 103 #define HEVC_ASSIST_SCRATCH_N 0x30d7 104 #define HEVC_PARSER_VERSION 0x3100 105 #define HEVC_STREAM_CONTROL 0x3101 106 #define HEVC_STREAM_START_ADDR 0x3102 107 #define HEVC_STREAM_END_ADDR 0x3103 108 #define HEVC_STREAM_WR_PTR 0x3104 109 #define HEVC_STREAM_RD_PTR 0x3105 110 #define HEVC_STREAM_LEVEL 0x3106 111 #define HEVC_STREAM_FIFO_CTL 0x3107 112 #define HEVC_SHIFT_CONTROL 0x3108 113 #define HEVC_SHIFT_STARTCODE 0x3109 114 #define HEVC_SHIFT_EMULATECODE 0x310a 115 #define HEVC_SHIFT_STATUS 0x310b 116 #define HEVC_SHIFTED_DATA 0x310c 117 #define HEVC_SHIFT_BYTE_COUNT 0x310d 118 #define HEVC_SHIFT_COMMAND 0x310e 119 #define HEVC_ELEMENT_RESULT 0x310f 120 #define HEVC_CABAC_CONTROL 0x3110 121 #define HEVC_PARSER_SLICE_INFO 0x3111 122 #define HEVC_PARSER_CMD_WRITE 0x3112 123 #define HEVC_PARSER_CORE_CONTROL 0x3113 124 #define HEVC_PARSER_CMD_FETCH 0x3114 125 #define HEVC_PARSER_CMD_STATUS 0x3115 126 #define HEVC_PARSER_LCU_INFO 0x3116 127 #define HEVC_PARSER_HEADER_INFO 0x3117 128 #define HEVC_PARSER_RESULT_0 0x3118 129 #define HEVC_PARSER_RESULT_1 0x3119 130 #define HEVC_PARSER_RESULT_2 0x311a 131 #define HEVC_PARSER_RESULT_3 0x311b 132 #define HEVC_CABAC_TOP_INFO 0x311c 133 #define HEVC_CABAC_TOP_INFO_2 0x311d 134 #define HEVC_CABAC_LEFT_INFO 0x311e 135 #define HEVC_CABAC_LEFT_INFO_2 0x311f 136 #define HEVC_PARSER_INT_CONTROL 0x3120 137 #define HEVC_PARSER_INT_STATUS 0x3121 138 #define HEVC_PARSER_IF_CONTROL 0x3122 139 #define HEVC_PARSER_PICTURE_SIZE 0x3123 140 #define HEVC_PARSER_LCU_START 0x3124 141 #define HEVC_PARSER_HEADER_INFO2 0x3125 142 #define HEVC_PARSER_QUANT_READ 0x3126 143 #define HEVC_PARSER_RESERVED_27 0x3127 144 #define HEVC_PARSER_CMD_SKIP_0 0x3128 145 #define HEVC_PARSER_CMD_SKIP_1 0x3129 146 #define HEVC_PARSER_CMD_SKIP_2 0x312a 147 #define HEVC_PARSER_MANUAL_CMD 0x312b 148 #define HEVC_PARSER_MEM_RD_ADDR 0x312c 149 #define HEVC_PARSER_MEM_WR_ADDR 0x312d 150 #define HEVC_PARSER_MEM_RW_DATA 0x312e 151 #define HEVC_SAO_IF_STATUS 0x3130 152 #define HEVC_SAO_IF_DATA_Y 0x3131 153 #define HEVC_SAO_IF_DATA_U 0x3132 154 #define HEVC_SAO_IF_DATA_V 0x3133 155 #define HEVC_STREAM_SWAP_ADDR 0x3134 156 #define HEVC_STREAM_SWAP_CTRL 0x3135 157 #define HEVC_IQIT_IF_WAIT_CNT 0x3136 158 #define HEVC_MPRED_IF_WAIT_CNT 0x3137 159 #define HEVC_SAO_IF_WAIT_CNT 0x3138 160 #define HEVC_PARSER_DEBUG_IDX 0x313e 161 #define HEVC_PARSER_DEBUG_DAT 0x313f 162 #define HEVC_MPRED_VERSION 0x3200 163 #define HEVC_MPRED_CTRL0 0x3201 164 #define HEVC_MPRED_CTRL1 0x3202 165 #define HEVC_MPRED_INT_EN 0x3203 166 #define HEVC_MPRED_INT_STATUS 0x3204 167 #define HEVC_MPRED_PIC_SIZE 0x3205 168 #define HEVC_MPRED_PIC_SIZE_LCU 0x3206 169 #define HEVC_MPRED_TILE_START 0x3207 170 #define HEVC_MPRED_TILE_SIZE_LCU 0x3208 171 #define HEVC_MPRED_REF_NUM 0x3209 172 #define HEVC_MPRED_LT_REF 0x320a 173 #define HEVC_MPRED_LT_COLREF 0x320b 174 #define HEVC_MPRED_REF_EN_L0 0x320c 175 #define HEVC_MPRED_REF_EN_L1 0x320d 176 #define HEVC_MPRED_COLREF_EN_L0 0x320e 177 #define HEVC_MPRED_COLREF_EN_L1 0x320f 178 #define HEVC_MPRED_AXI_WCTRL 0x3210 179 #define HEVC_MPRED_AXI_RCTRL 0x3211 180 #define HEVC_MPRED_ABV_START_ADDR 0x3212 181 #define HEVC_MPRED_MV_WR_START_ADDR 0x3213 182 #define HEVC_MPRED_MV_RD_START_ADDR 0x3214 183 #define HEVC_MPRED_MV_WPTR 0x3215 184 #define HEVC_MPRED_MV_RPTR 0x3216 185 #define HEVC_MPRED_MV_WR_ROW_JUMP 0x3217 186 #define HEVC_MPRED_MV_RD_ROW_JUMP 0x3218 187 #define HEVC_MPRED_CURR_LCU 0x3219 188 #define HEVC_MPRED_ABV_WPTR 0x321a 189 #define HEVC_MPRED_ABV_RPTR 0x321b 190 #define HEVC_MPRED_CTRL2 0x321c 191 #define HEVC_MPRED_CTRL3 0x321d 192 #define HEVC_MPRED_MV_WLCUY 0x321e 193 #define HEVC_MPRED_MV_RLCUY 0x321f 194 #define HEVC_MPRED_L0_REF00_POC 0x3220 195 #define HEVC_MPRED_L0_REF01_POC 0x3221 196 #define HEVC_MPRED_L0_REF02_POC 0x3222 197 #define HEVC_MPRED_L0_REF03_POC 0x3223 198 #define HEVC_MPRED_L0_REF04_POC 0x3224 199 #define HEVC_MPRED_L0_REF05_POC 0x3225 200 #define HEVC_MPRED_L0_REF06_POC 0x3226 201 #define HEVC_MPRED_L0_REF07_POC 0x3227 202 #define HEVC_MPRED_L0_REF08_POC 0x3228 203 #define HEVC_MPRED_L0_REF09_POC 0x3229 204 #define HEVC_MPRED_L0_REF10_POC 0x322a 205 #define HEVC_MPRED_L0_REF11_POC 0x322b 206 #define HEVC_MPRED_L0_REF12_POC 0x322c 207 #define HEVC_MPRED_L0_REF13_POC 0x322d 208 #define HEVC_MPRED_L0_REF14_POC 0x322e 209 #define HEVC_MPRED_L0_REF15_POC 0x322f 210 #define HEVC_MPRED_L1_REF00_POC 0x3230 211 #define HEVC_MPRED_L1_REF01_POC 0x3231 212 #define HEVC_MPRED_L1_REF02_POC 0x3232 213 #define HEVC_MPRED_L1_REF03_POC 0x3233 214 #define HEVC_MPRED_L1_REF04_POC 0x3234 215 #define HEVC_MPRED_L1_REF05_POC 0x3235 216 #define HEVC_MPRED_L1_REF06_POC 0x3236 217 #define HEVC_MPRED_L1_REF07_POC 0x3237 218 #define HEVC_MPRED_L1_REF08_POC 0x3238 219 #define HEVC_MPRED_L1_REF09_POC 0x3239 220 #define HEVC_MPRED_L1_REF10_POC 0x323a 221 #define HEVC_MPRED_L1_REF11_POC 0x323b 222 #define HEVC_MPRED_L1_REF12_POC 0x323c 223 #define HEVC_MPRED_L1_REF13_POC 0x323d 224 #define HEVC_MPRED_L1_REF14_POC 0x323e 225 #define HEVC_MPRED_L1_REF15_POC 0x323f 226 #define HEVC_MPRED_PIC_SIZE_EXT 0x3240 227 #define HEVC_MPRED_DBG_MODE0 0x3241 228 #define HEVC_MPRED_DBG_MODE1 0x3242 229 #define HEVC_MPRED_DBG2_MODE 0x3243 230 #define HEVC_MPRED_IMP_CMD0 0x3244 231 #define HEVC_MPRED_IMP_CMD1 0x3245 232 #define HEVC_MPRED_IMP_CMD2 0x3246 233 #define HEVC_MPRED_IMP_CMD3 0x3247 234 #define HEVC_MPRED_DBG2_DATA_0 0x3248 235 #define HEVC_MPRED_DBG2_DATA_1 0x3249 236 #define HEVC_MPRED_DBG2_DATA_2 0x324a 237 #define HEVC_MPRED_DBG2_DATA_3 0x324b 238 #define HEVC_MPRED_DBG_DATA_0 0x3250 239 #define HEVC_MPRED_DBG_DATA_1 0x3251 240 #define HEVC_MPRED_DBG_DATA_2 0x3252 241 #define HEVC_MPRED_DBG_DATA_3 0x3253 242 #define HEVC_MPRED_DBG_DATA_4 0x3254 243 #define HEVC_MPRED_DBG_DATA_5 0x3255 244 #define HEVC_MPRED_DBG_DATA_6 0x3256 245 #define HEVC_MPRED_DBG_DATA_7 0x3257 246 #define HEVC_MPRED_CUR_POC 0x3260 247 #define HEVC_MPRED_COL_POC 0x3261 248 #define HEVC_MPRED_MV_RD_END_ADDR 0x3262 249 #define HEVCD_IPP_TOP_CNTL 0x3400 250 #define HEVCD_IPP_TOP_STATUS 0x3401 251 #define HEVCD_IPP_TOP_FRMCONFIG 0x3402 252 #define HEVCD_IPP_TOP_TILECONFIG1 0x3403 253 #define HEVCD_IPP_TOP_TILECONFIG2 0x3404 254 #define HEVCD_IPP_TOP_TILECONFIG3 0x3405 255 #define HEVCD_IPP_TOP_LCUCONFIG 0x3406 256 #define HEVCD_IPP_TOP_FRMCTL 0x3407 257 #define HEVCD_IPP_CONFIG 0x3408 258 #define HEVCD_IPP_LINEBUFF_BASE 0x3409 259 #define HEVCD_IPP_INTR_MASK 0x340a 260 #define HEVCD_IPP_AXIIF_CONFIG 0x340b 261 #define HEVCD_IPP_BITDEPTH_CONFIG 0x340c 262 #define HEVCD_IPP_SWMPREDIF_CONFIG 0x3410 263 #define HEVCD_IPP_SWMPREDIF_STATUS 0x3411 264 #define HEVCD_IPP_SWMPREDIF_CTBINFO 0x3412 265 #define HEVCD_IPP_SWMPREDIF_PUINFO0 0x3413 266 #define HEVCD_IPP_SWMPREDIF_PUINFO1 0x3414 267 #define HEVCD_IPP_SWMPREDIF_PUINFO2 0x3415 268 #define HEVCD_IPP_SWMPREDIF_PUINFO3 0x3416 269 #define HEVCD_IPP_DYNCLKGATE_CONFIG 0x3420 270 #define HEVCD_IPP_DYNCLKGATE_STATUS 0x3421 271 #define HEVCD_IPP_DBG_SEL 0x3430 272 #define HEVCD_IPP_DBG_DATA 0x3431 273 #define HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR 0x3460 274 #define HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR 0x3461 275 #define HEVCD_MPP_ANC2AXI_TBL_WDATA_ADDR 0x3462 276 #define HEVCD_MPP_ANC2AXI_TBL_RDATA_ADDR 0x3463 277 #define HEVCD_MPP_WEIGHTPRED_CNTL_ADDR 0x347b 278 #define HEVCD_MPP_L0_WEIGHT_FLAG_ADDR 0x347c 279 #define HEVCD_MPP_L1_WEIGHT_FLAG_ADDR 0x347d 280 #define HEVCD_MPP_YLOG2WGHTDENOM_ADDR 0x347e 281 #define HEVCD_MPP_DELTACLOG2WGHTDENOM_ADDR 0x347f 282 #define HEVCD_MPP_WEIGHT_ADDR 0x3480 283 #define HEVCD_MPP_WEIGHT_DATA 0x3481 284 #define HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR 0x34c0 285 #define HEVCD_MPP_ANC_CANVAS_DATA_ADDR 0x34c1 286 #define HEVCD_MPP_DECOMP_CTL1 0x34c2 287 #define HEVCD_MPP_DECOMP_CTL2 0x34c3 288 #define HEVCD_MPP_DECOMP_PERFMON_CTL 0x34c5 289 #define HEVCD_MPP_DECOMP_PERFMON_DATA 0x34c6 290 #define HEVCD_MCRCC_CTL1 0x34f0 291 #define HEVCD_MCRCC_CTL2 0x34f1 292 #define HEVCD_MCRCC_CTL3 0x34f2 293 #define HEVCD_MCRCC_PERFMON_CTL 0x34f3 294 #define HEVCD_MCRCC_PERFMON_DATA 0x34f4 295 #define HEVC_DBLK_CFG0 0x3500 296 #define HEVC_DBLK_CFG1 0x3501 297 #define HEVC_DBLK_CFG2 0x3502 298 #define HEVC_DBLK_CFG3 0x3503 299 #define HEVC_DBLK_CFG4 0x3504 300 #define HEVC_DBLK_CFG5 0x3505 301 #define HEVC_DBLK_CFG6 0x3506 302 #define HEVC_DBLK_CFG7 0x3507 303 #define HEVC_DBLK_CFG8 0x3508 304 #define HEVC_DBLK_CFG9 0x3509 305 #define HEVC_DBLK_CFGA 0x350a 306 #define HEVC_DBLK_CFGE 0x350e 307 #define HEVC_DBLK_STS0 0x350b /* changes the val to 0x350f on g12a */ 308 #define HEVC_DBLK_STS1 0x350c /* changes the val to 0x3510 on g12a */ 309 #define HEVC_SAO_VERSION 0x3600 310 #define HEVC_SAO_CTRL0 0x3601 311 #define HEVC_SAO_CTRL1 0x3602 312 #define HEVC_SAO_INT_EN 0x3603 313 #define HEVC_SAO_INT_STATUS 0x3604 314 #define HEVC_SAO_PIC_SIZE 0x3605 315 #define HEVC_SAO_PIC_SIZE_LCU 0x3606 316 #define HEVC_SAO_TILE_START 0x3607 317 #define HEVC_SAO_TILE_SIZE_LCU 0x3608 318 #define HEVC_SAO_AXI_WCTRL 0x3609 319 #define HEVC_SAO_AXI_RCTRL 0x360a 320 #define HEVC_SAO_Y_START_ADDR 0x360b 321 #define HEVC_SAO_Y_LENGTH 0x360c 322 #define HEVC_SAO_C_START_ADDR 0x360d 323 #define HEVC_SAO_C_LENGTH 0x360e 324 #define HEVC_SAO_Y_WPTR 0x360f 325 #define HEVC_SAO_C_WPTR 0x3610 326 #define HEVC_SAO_ABV_START_ADDR 0x3611 327 #define HEVC_SAO_VB_WR_START_ADDR 0x3612 328 #define HEVC_SAO_VB_RD_START_ADDR 0x3613 329 #define HEVC_SAO_ABV_WPTR 0x3614 330 #define HEVC_SAO_ABV_RPTR 0x3615 331 #define HEVC_SAO_VB_WPTR 0x3616 332 #define HEVC_SAO_VB_RPTR 0x3617 333 #define HEVC_SAO_DBG_MODE0 0x361e 334 #define HEVC_SAO_DBG_MODE1 0x361f 335 #define HEVC_SAO_CTRL2 0x3620 336 #define HEVC_SAO_CTRL3 0x3621 337 #define HEVC_SAO_CTRL4 0x3622 338 #define HEVC_SAO_CTRL5 0x3623 339 #define HEVC_SAO_CTRL6 0x3624 340 #define HEVC_SAO_CTRL7 0x3625 341 #define HEVC_SAO_DBG_DATA_0 0x3630 342 #define HEVC_SAO_DBG_DATA_1 0x3631 343 #define HEVC_SAO_DBG_DATA_2 0x3632 344 #define HEVC_SAO_DBG_DATA_3 0x3633 345 #define HEVC_SAO_DBG_DATA_4 0x3634 346 #define HEVC_SAO_DBG_DATA_5 0x3635 347 #define HEVC_SAO_DBG_DATA_6 0x3636 348 #define HEVC_SAO_DBG_DATA_7 0x3637 349 #define HEVC_SAO_MMU_STATUS 0x3639 350 #define HEVC_SAO_MMU_DMA_CTRL 0x363e 351 #define HEVC_SAO_MMU_DMA_STATUS 0x363f 352 #define HEVC_CM_CORE_STATUS 0x3640 353 #define HEVC_SAO_MMU_RESET_CTRL 0x3641 354 #define HEVC_IQIT_CLK_RST_CTRL 0x3700 355 #define HEVC_IQIT_DEQUANT_CTRL 0x3701 356 #define HEVC_IQIT_SCALELUT_WR_ADDR 0x3702 357 #define HEVC_IQIT_SCALELUT_RD_ADDR 0x3703 358 #define HEVC_IQIT_SCALELUT_DATA 0x3704 359 #define HEVC_IQIT_SCALELUT_IDX_4 0x3705 360 #define HEVC_IQIT_SCALELUT_IDX_8 0x3706 361 #define HEVC_IQIT_SCALELUT_IDX_16_32 0x3707 362 #define HEVC_IQIT_STAT_GEN0 0x3708 363 #define HEVC_QP_WRITE 0x3709 364 #define HEVC_IQIT_STAT_GEN1 0x370a 365 #define HEVC_IQIT_BITDEPTH 0x370b 366 #define HEVC_IQIT_STAT_GEN2 0x370c 367 #define HEVC_IQIT_AVS2_WQP_0123 0x370d 368 #define HEVC_IQIT_AVS2_WQP_45 0x370e 369 #define HEVC_IQIT_AVS2_QP_DELTA 0x370f 370 #define HEVC_PIC_QUALITY_CTRL 0x3710 371 #define HEVC_PIC_QUALITY_DATA 0x3711 372 373 /**/ 374 375 /*add from M8M2*/ 376 #define HEVC_MC_CTRL_REG 0x3900 377 #define HEVC_MC_MB_INFO 0x3901 378 #define HEVC_MC_PIC_INFO 0x3902 379 #define HEVC_MC_HALF_PEL_ONE 0x3903 380 #define HEVC_MC_HALF_PEL_TWO 0x3904 381 #define HEVC_POWER_CTL_MC 0x3905 382 #define HEVC_MC_CMD 0x3906 383 #define HEVC_MC_CTRL0 0x3907 384 #define HEVC_MC_PIC_W_H 0x3908 385 #define HEVC_MC_STATUS0 0x3909 386 #define HEVC_MC_STATUS1 0x390a 387 #define HEVC_MC_CTRL1 0x390b 388 #define HEVC_MC_MIX_RATIO0 0x390c 389 #define HEVC_MC_MIX_RATIO1 0x390d 390 #define HEVC_MC_DP_MB_XY 0x390e 391 #define HEVC_MC_OM_MB_XY 0x390f 392 #define HEVC_PSCALE_RST 0x3910 393 #define HEVC_PSCALE_CTRL 0x3911 394 #define HEVC_PSCALE_PICI_W 0x3912 395 #define HEVC_PSCALE_PICI_H 0x3913 396 #define HEVC_PSCALE_PICO_W 0x3914 397 #define HEVC_PSCALE_PICO_H 0x3915 398 #define HEVC_PSCALE_PICO_START_X 0x3916 399 #define HEVC_PSCALE_PICO_START_Y 0x3917 400 #define HEVC_PSCALE_DUMMY 0x3918 401 #define HEVC_PSCALE_FILT0_COEF0 0x3919 402 #define HEVC_PSCALE_FILT0_COEF1 0x391a 403 #define HEVC_PSCALE_CMD_CTRL 0x391b 404 #define HEVC_PSCALE_CMD_BLK_X 0x391c 405 #define HEVC_PSCALE_CMD_BLK_Y 0x391d 406 #define HEVC_PSCALE_STATUS 0x391e 407 #define HEVC_PSCALE_BMEM_ADDR 0x391f 408 #define HEVC_PSCALE_BMEM_DAT 0x3920 409 #define HEVC_PSCALE_DRAM_BUF_CTRL 0x3921 410 #define HEVC_PSCALE_MCMD_CTRL 0x3922 411 #define HEVC_PSCALE_MCMD_XSIZE 0x3923 412 #define HEVC_PSCALE_MCMD_YSIZE 0x3924 413 #define HEVC_PSCALE_RBUF_START_BLKX 0x3925 414 #define HEVC_PSCALE_RBUF_START_BLKY 0x3926 415 #define HEVC_PSCALE_PICO_SHIFT_XY 0x3928 416 #define HEVC_PSCALE_CTRL1 0x3929 417 #define HEVC_PSCALE_SRCKEY_CTRL0 0x392a 418 #define HEVC_PSCALE_SRCKEY_CTRL1 0x392b 419 #define HEVC_PSCALE_CANVAS_RD_ADDR 0x392c 420 #define HEVC_PSCALE_CANVAS_WR_ADDR 0x392d 421 #define HEVC_PSCALE_CTRL2 0x392e 422 #define HEVC_HDEC_MC_OMEM_AUTO 0x3930 423 #define HEVC_HDEC_MC_MBRIGHT_IDX 0x3931 424 #define HEVC_HDEC_MC_MBRIGHT_RD 0x3932 425 #define HEVC_MC_MPORT_CTRL 0x3940 426 #define HEVC_MC_MPORT_DAT 0x3941 427 #define HEVC_MC_WT_PRED_CTRL 0x3942 428 #define HEVC_MC_MBBOT_ST_EVEN_ADDR 0x3944 429 #define HEVC_MC_MBBOT_ST_ODD_ADDR 0x3945 430 #define HEVC_MC_DPDN_MB_XY 0x3946 431 #define HEVC_MC_OMDN_MB_XY 0x3947 432 #define HEVC_MC_HCMDBUF_H 0x3948 433 #define HEVC_MC_HCMDBUF_L 0x3949 434 #define HEVC_MC_HCMD_H 0x394a 435 #define HEVC_MC_HCMD_L 0x394b 436 #define HEVC_MC_IDCT_DAT 0x394c 437 #define HEVC_MC_CTRL_GCLK_CTRL 0x394d 438 #define HEVC_MC_OTHER_GCLK_CTRL 0x394e 439 #define HEVC_MC_CTRL2 0x394f 440 #define HEVC_MDEC_PIC_DC_CTRL 0x398e 441 #define HEVC_MDEC_PIC_DC_STATUS 0x398f 442 #define HEVC_ANC0_CANVAS_ADDR 0x3990 443 #define HEVC_ANC1_CANVAS_ADDR 0x3991 444 #define HEVC_ANC2_CANVAS_ADDR 0x3992 445 #define HEVC_ANC3_CANVAS_ADDR 0x3993 446 #define HEVC_ANC4_CANVAS_ADDR 0x3994 447 #define HEVC_ANC5_CANVAS_ADDR 0x3995 448 #define HEVC_ANC6_CANVAS_ADDR 0x3996 449 #define HEVC_ANC7_CANVAS_ADDR 0x3997 450 #define HEVC_ANC8_CANVAS_ADDR 0x3998 451 #define HEVC_ANC9_CANVAS_ADDR 0x3999 452 #define HEVC_ANC10_CANVAS_ADDR 0x399a 453 #define HEVC_ANC11_CANVAS_ADDR 0x399b 454 #define HEVC_ANC12_CANVAS_ADDR 0x399c 455 #define HEVC_ANC13_CANVAS_ADDR 0x399d 456 #define HEVC_ANC14_CANVAS_ADDR 0x399e 457 #define HEVC_ANC15_CANVAS_ADDR 0x399f 458 #define HEVC_ANC16_CANVAS_ADDR 0x39a0 459 #define HEVC_ANC17_CANVAS_ADDR 0x39a1 460 #define HEVC_ANC18_CANVAS_ADDR 0x39a2 461 #define HEVC_ANC19_CANVAS_ADDR 0x39a3 462 #define HEVC_ANC20_CANVAS_ADDR 0x39a4 463 #define HEVC_ANC21_CANVAS_ADDR 0x39a5 464 #define HEVC_ANC22_CANVAS_ADDR 0x39a6 465 #define HEVC_ANC23_CANVAS_ADDR 0x39a7 466 #define HEVC_ANC24_CANVAS_ADDR 0x39a8 467 #define HEVC_ANC25_CANVAS_ADDR 0x39a9 468 #define HEVC_ANC26_CANVAS_ADDR 0x39aa 469 #define HEVC_ANC27_CANVAS_ADDR 0x39ab 470 #define HEVC_ANC28_CANVAS_ADDR 0x39ac 471 #define HEVC_ANC29_CANVAS_ADDR 0x39ad 472 #define HEVC_ANC30_CANVAS_ADDR 0x39ae 473 #define HEVC_ANC31_CANVAS_ADDR 0x39af 474 #define HEVC_DBKR_CANVAS_ADDR 0x39b0 475 #define HEVC_DBKW_CANVAS_ADDR 0x39b1 476 #define HEVC_REC_CANVAS_ADDR 0x39b2 477 #define HEVC_CURR_CANVAS_CTRL 0x39b3 478 #define HEVC_MDEC_PIC_DC_THRESH 0x39b8 479 #define HEVC_MDEC_PICR_BUF_STATUS 0x39b9 480 #define HEVC_MDEC_PICW_BUF_STATUS 0x39ba 481 #define HEVC_MCW_DBLK_WRRSP_CNT 0x39bb 482 #define HEVC_MC_MBBOT_WRRSP_CNT 0x39bc 483 #define HEVC_MDEC_PICW_BUF2_STATUS 0x39bd 484 #define HEVC_WRRSP_FIFO_PICW_DBK 0x39be 485 #define HEVC_WRRSP_FIFO_PICW_MC 0x39bf 486 #define HEVC_AV_SCRATCH_0 0x39c0 487 #define HEVC_AV_SCRATCH_1 0x39c1 488 #define HEVC_AV_SCRATCH_2 0x39c2 489 #define HEVC_AV_SCRATCH_3 0x39c3 490 #define HEVC_AV_SCRATCH_4 0x39c4 491 #define HEVC_AV_SCRATCH_5 0x39c5 492 #define HEVC_AV_SCRATCH_6 0x39c6 493 #define HEVC_AV_SCRATCH_7 0x39c7 494 #define HEVC_AV_SCRATCH_8 0x39c8 495 #define HEVC_AV_SCRATCH_9 0x39c9 496 #define HEVC_AV_SCRATCH_A 0x39ca 497 #define HEVC_AV_SCRATCH_B 0x39cb 498 #define HEVC_AV_SCRATCH_C 0x39cc 499 #define HEVC_AV_SCRATCH_D 0x39cd 500 #define HEVC_AV_SCRATCH_E 0x39ce 501 #define HEVC_AV_SCRATCH_F 0x39cf 502 #define HEVC_AV_SCRATCH_G 0x39d0 503 #define HEVC_AV_SCRATCH_H 0x39d1 504 #define HEVC_AV_SCRATCH_I 0x39d2 505 #define HEVC_AV_SCRATCH_J 0x39d3 506 #define HEVC_AV_SCRATCH_K 0x39d4 507 #define HEVC_AV_SCRATCH_L 0x39d5 508 #define HEVC_AV_SCRATCH_M 0x39d6 509 #define HEVC_AV_SCRATCH_N 0x39d7 510 #define HEVC_WRRSP_CO_MB 0x39d8 511 #define HEVC_WRRSP_DCAC 0x39d9 512 #define HEVC_WRRSP_VLD 0x39da 513 #define HEVC_MDEC_DOUBLEW_CFG0 0x39db 514 #define HEVC_MDEC_DOUBLEW_CFG1 0x39dc 515 #define HEVC_MDEC_DOUBLEW_CFG2 0x39dd 516 #define HEVC_MDEC_DOUBLEW_CFG3 0x39de 517 #define HEVC_MDEC_DOUBLEW_CFG4 0x39df 518 #define HEVC_MDEC_DOUBLEW_CFG5 0x39e0 519 #define HEVC_MDEC_DOUBLEW_CFG6 0x39e1 520 #define HEVC_MDEC_DOUBLEW_CFG7 0x39e2 521 #define HEVC_MDEC_DOUBLEW_STATUS 0x39e3 522 #define HEVC_DBLK_RST 0x3950 523 #define HEVC_DBLK_CTRL 0x3951 524 #define HEVC_DBLK_MB_WID_HEIGHT 0x3952 525 #define HEVC_DBLK_STATUS 0x3953 526 #define HEVC_DBLK_CMD_CTRL 0x3954 527 #define HEVC_DBLK_MB_XY 0x3955 528 #define HEVC_DBLK_QP 0x3956 529 #define HEVC_DBLK_Y_BHFILT 0x3957 530 #define HEVC_DBLK_Y_BHFILT_HIGH 0x3958 531 #define HEVC_DBLK_Y_BVFILT 0x3959 532 #define HEVC_DBLK_CB_BFILT 0x395a 533 #define HEVC_DBLK_CR_BFILT 0x395b 534 #define HEVC_DBLK_Y_HFILT 0x395c 535 #define HEVC_DBLK_Y_HFILT_HIGH 0x395d 536 #define HEVC_DBLK_Y_VFILT 0x395e 537 #define HEVC_DBLK_CB_FILT 0x395f 538 #define HEVC_DBLK_CR_FILT 0x3960 539 #define HEVC_DBLK_BETAX_QP_SEL 0x3961 540 #define HEVC_DBLK_CLIP_CTRL0 0x3962 541 #define HEVC_DBLK_CLIP_CTRL1 0x3963 542 #define HEVC_DBLK_CLIP_CTRL2 0x3964 543 #define HEVC_DBLK_CLIP_CTRL3 0x3965 544 #define HEVC_DBLK_CLIP_CTRL4 0x3966 545 #define HEVC_DBLK_CLIP_CTRL5 0x3967 546 #define HEVC_DBLK_CLIP_CTRL6 0x3968 547 #define HEVC_DBLK_CLIP_CTRL7 0x3969 548 #define HEVC_DBLK_CLIP_CTRL8 0x396a 549 #define HEVC_DBLK_STATUS1 0x396b 550 #define HEVC_DBLK_GCLK_FREE 0x396c 551 #define HEVC_DBLK_GCLK_OFF 0x396d 552 #define HEVC_DBLK_AVSFLAGS 0x396e 553 #define HEVC_DBLK_CBPY 0x3970 554 #define HEVC_DBLK_CBPY_ADJ 0x3971 555 #define HEVC_DBLK_CBPC 0x3972 556 #define HEVC_DBLK_CBPC_ADJ 0x3973 557 #define HEVC_DBLK_VHMVD 0x3974 558 #define HEVC_DBLK_STRONG 0x3975 559 #define HEVC_DBLK_RV8_QUANT 0x3976 560 #define HEVC_DBLK_CBUS_HCMD2 0x3977 561 #define HEVC_DBLK_CBUS_HCMD1 0x3978 562 #define HEVC_DBLK_CBUS_HCMD0 0x3979 563 #define HEVC_DBLK_VLD_HCMD2 0x397a 564 #define HEVC_DBLK_VLD_HCMD1 0x397b 565 #define HEVC_DBLK_VLD_HCMD0 0x397c 566 #define HEVC_DBLK_OST_YBASE 0x397d 567 #define HEVC_DBLK_OST_CBCRDIFF 0x397e 568 #define HEVC_DBLK_CTRL1 0x397f 569 #define HEVC_MCRCC_CTL1 0x3980 570 #define HEVC_MCRCC_CTL2 0x3981 571 #define HEVC_MCRCC_CTL3 0x3982 572 #define HEVC_GCLK_EN 0x3983 573 #define HEVC_MDEC_SW_RESET 0x3984 574 575 /*add from M8M2*/ 576 #define HEVC_VLD_STATUS_CTRL 0x3c00 577 #define HEVC_MPEG1_2_REG 0x3c01 578 #define HEVC_F_CODE_REG 0x3c02 579 #define HEVC_PIC_HEAD_INFO 0x3c03 580 #define HEVC_SLICE_VER_POS_PIC_TYPE 0x3c04 581 #define HEVC_QP_VALUE_REG 0x3c05 582 #define HEVC_MBA_INC 0x3c06 583 #define HEVC_MB_MOTION_MODE 0x3c07 584 #define HEVC_POWER_CTL_VLD 0x3c08 585 #define HEVC_MB_WIDTH 0x3c09 586 #define HEVC_SLICE_QP 0x3c0a 587 #define HEVC_PRE_START_CODE 0x3c0b 588 #define HEVC_SLICE_START_BYTE_01 0x3c0c 589 #define HEVC_SLICE_START_BYTE_23 0x3c0d 590 #define HEVC_RESYNC_MARKER_LENGTH 0x3c0e 591 #define HEVC_DECODER_BUFFER_INFO 0x3c0f 592 #define HEVC_FST_FOR_MV_X 0x3c10 593 #define HEVC_FST_FOR_MV_Y 0x3c11 594 #define HEVC_SCD_FOR_MV_X 0x3c12 595 #define HEVC_SCD_FOR_MV_Y 0x3c13 596 #define HEVC_FST_BAK_MV_X 0x3c14 597 #define HEVC_FST_BAK_MV_Y 0x3c15 598 #define HEVC_SCD_BAK_MV_X 0x3c16 599 #define HEVC_SCD_BAK_MV_Y 0x3c17 600 #define HEVC_VLD_DECODE_CONTROL 0x3c18 601 #define HEVC_VLD_REVERVED_19 0x3c19 602 #define HEVC_VIFF_BIT_CNT 0x3c1a 603 #define HEVC_BYTE_ALIGN_PEAK_HI 0x3c1b 604 #define HEVC_BYTE_ALIGN_PEAK_LO 0x3c1c 605 #define HEVC_NEXT_ALIGN_PEAK 0x3c1d 606 #define HEVC_VC1_CONTROL_REG 0x3c1e 607 #define HEVC_PMV1_X 0x3c20 608 #define HEVC_PMV1_Y 0x3c21 609 #define HEVC_PMV2_X 0x3c22 610 #define HEVC_PMV2_Y 0x3c23 611 #define HEVC_PMV3_X 0x3c24 612 #define HEVC_PMV3_Y 0x3c25 613 #define HEVC_PMV4_X 0x3c26 614 #define HEVC_PMV4_Y 0x3c27 615 #define HEVC_M4_TABLE_SELECT 0x3c28 616 #define HEVC_M4_CONTROL_REG 0x3c29 617 #define HEVC_BLOCK_NUM 0x3c2a 618 #define HEVC_PATTERN_CODE 0x3c2b 619 #define HEVC_MB_INFO 0x3c2c 620 #define HEVC_VLD_DC_PRED 0x3c2d 621 #define HEVC_VLD_ERROR_MASK 0x3c2e 622 #define HEVC_VLD_DC_PRED_C 0x3c2f 623 #define HEVC_LAST_SLICE_MV_ADDR 0x3c30 624 #define HEVC_LAST_MVX 0x3c31 625 #define HEVC_LAST_MVY 0x3c32 626 #define HEVC_VLD_C38 0x3c38 627 #define HEVC_VLD_C39 0x3c39 628 #define HEVC_VLD_STATUS 0x3c3a 629 #define HEVC_VLD_SHIFT_STATUS 0x3c3b 630 #define HEVC_VOFF_STATUS 0x3c3c 631 #define HEVC_VLD_C3D 0x3c3d 632 #define HEVC_VLD_DBG_INDEX 0x3c3e 633 #define HEVC_VLD_DBG_DATA 0x3c3f 634 #define HEVC_VLD_MEM_VIFIFO_START_PTR 0x3c40 635 #define HEVC_VLD_MEM_VIFIFO_CURR_PTR 0x3c41 636 #define HEVC_VLD_MEM_VIFIFO_END_PTR 0x3c42 637 #define HEVC_VLD_MEM_VIFIFO_BYTES_AVAIL 0x3c43 638 #define HEVC_VLD_MEM_VIFIFO_CONTROL 0x3c44 639 #define HEVC_VLD_MEM_VIFIFO_WP 0x3c45 640 #define HEVC_VLD_MEM_VIFIFO_RP 0x3c46 641 #define HEVC_VLD_MEM_VIFIFO_LEVEL 0x3c47 642 #define HEVC_VLD_MEM_VIFIFO_BUF_CNTL 0x3c48 643 #define HEVC_VLD_TIME_STAMP_CNTL 0x3c49 644 #define HEVC_VLD_TIME_STAMP_SYNC_0 0x3c4a 645 #define HEVC_VLD_TIME_STAMP_SYNC_1 0x3c4b 646 #define HEVC_VLD_TIME_STAMP_0 0x3c4c 647 #define HEVC_VLD_TIME_STAMP_1 0x3c4d 648 #define HEVC_VLD_TIME_STAMP_2 0x3c4e 649 #define HEVC_VLD_TIME_STAMP_3 0x3c4f 650 #define HEVC_VLD_TIME_STAMP_LENGTH 0x3c50 651 #define HEVC_VLD_MEM_VIFIFO_WRAP_COUNT 0x3c51 652 #define HEVC_VLD_MEM_VIFIFO_MEM_CTL 0x3c52 653 #define HEVC_VLD_MEM_VBUF_RD_PTR 0x3c53 654 #define HEVC_VLD_MEM_VBUF2_RD_PTR 0x3c54 655 #define HEVC_VLD_MEM_SWAP_ADDR 0x3c55 656 #define HEVC_VLD_MEM_SWAP_CTL 0x3c56 657 /**/ 658 659 /*add from M8M2*/ 660 #define HEVC_VCOP_CTRL_REG 0x3e00 661 #define HEVC_QP_CTRL_REG 0x3e01 662 #define HEVC_INTRA_QUANT_MATRIX 0x3e02 663 #define HEVC_NON_I_QUANT_MATRIX 0x3e03 664 #define HEVC_DC_SCALER 0x3e04 665 #define HEVC_DC_AC_CTRL 0x3e05 666 #define HEVC_DC_AC_SCALE_MUL 0x3e06 667 #define HEVC_DC_AC_SCALE_DIV 0x3e07 668 #define HEVC_POWER_CTL_IQIDCT 0x3e08 669 #define HEVC_RV_AI_Y_X 0x3e09 670 #define HEVC_RV_AI_U_X 0x3e0a 671 #define HEVC_RV_AI_V_X 0x3e0b 672 #define HEVC_RV_AI_MB_COUNT 0x3e0c 673 #define HEVC_NEXT_INTRA_DMA_ADDRESS 0x3e0d 674 #define HEVC_IQIDCT_CONTROL 0x3e0e 675 #define HEVC_IQIDCT_DEBUG_INFO_0 0x3e0f 676 #define HEVC_DEBLK_CMD 0x3e10 677 #define HEVC_IQIDCT_DEBUG_IDCT 0x3e11 678 #define HEVC_DCAC_DMA_CTRL 0x3e12 679 #define HEVC_DCAC_DMA_ADDRESS 0x3e13 680 #define HEVC_DCAC_CPU_ADDRESS 0x3e14 681 #define HEVC_DCAC_CPU_DATA 0x3e15 682 #define HEVC_DCAC_MB_COUNT 0x3e16 683 #define HEVC_IQ_QUANT 0x3e17 684 #define HEVC_VC1_BITPLANE_CTL 0x3e18 685 686 687 /*add from M8M2*/ 688 #define HEVC_MSP 0x3300 689 #define HEVC_MPSR 0x3301 690 #define HEVC_MINT_VEC_BASE 0x3302 691 #define HEVC_MCPU_INTR_GRP 0x3303 692 #define HEVC_MCPU_INTR_MSK 0x3304 693 #define HEVC_MCPU_INTR_REQ 0x3305 694 #define HEVC_MPC_P 0x3306 695 #define HEVC_MPC_D 0x3307 696 #define HEVC_MPC_E 0x3308 697 #define HEVC_MPC_W 0x3309 698 #define HEVC_MINDEX0_REG 0x330a 699 #define HEVC_MINDEX1_REG 0x330b 700 #define HEVC_MINDEX2_REG 0x330c 701 #define HEVC_MINDEX3_REG 0x330d 702 #define HEVC_MINDEX4_REG 0x330e 703 #define HEVC_MINDEX5_REG 0x330f 704 #define HEVC_MINDEX6_REG 0x3310 705 #define HEVC_MINDEX7_REG 0x3311 706 #define HEVC_MMIN_REG 0x3312 707 #define HEVC_MMAX_REG 0x3313 708 #define HEVC_MBREAK0_REG 0x3314 709 #define HEVC_MBREAK1_REG 0x3315 710 #define HEVC_MBREAK2_REG 0x3316 711 #define HEVC_MBREAK3_REG 0x3317 712 #define HEVC_MBREAK_TYPE 0x3318 713 #define HEVC_MBREAK_CTRL 0x3319 714 #define HEVC_MBREAK_STAUTS 0x331a 715 #define HEVC_MDB_ADDR_REG 0x331b 716 #define HEVC_MDB_DATA_REG 0x331c 717 #define HEVC_MDB_CTRL 0x331d 718 #define HEVC_MSFTINT0 0x331e 719 #define HEVC_MSFTINT1 0x331f 720 #define HEVC_CSP 0x3320 721 #define HEVC_CPSR 0x3321 722 #define HEVC_CINT_VEC_BASE 0x3322 723 #define HEVC_CCPU_INTR_GRP 0x3323 724 #define HEVC_CCPU_INTR_MSK 0x3324 725 #define HEVC_CCPU_INTR_REQ 0x3325 726 #define HEVC_CPC_P 0x3326 727 #define HEVC_CPC_D 0x3327 728 #define HEVC_CPC_E 0x3328 729 #define HEVC_CPC_W 0x3329 730 #define HEVC_CINDEX0_REG 0x332a 731 #define HEVC_CINDEX1_REG 0x332b 732 #define HEVC_CINDEX2_REG 0x332c 733 #define HEVC_CINDEX3_REG 0x332d 734 #define HEVC_CINDEX4_REG 0x332e 735 #define HEVC_CINDEX5_REG 0x332f 736 #define HEVC_CINDEX6_REG 0x3330 737 #define HEVC_CINDEX7_REG 0x3331 738 #define HEVC_CMIN_REG 0x3332 739 #define HEVC_CMAX_REG 0x3333 740 #define HEVC_CBREAK0_REG 0x3334 741 #define HEVC_CBREAK1_REG 0x3335 742 #define HEVC_CBREAK2_REG 0x3336 743 #define HEVC_CBREAK3_REG 0x3337 744 #define HEVC_CBREAK_TYPE 0x3338 745 #define HEVC_CBREAK_CTRL 0x3339 746 #define HEVC_CBREAK_STAUTS 0x333a 747 #define HEVC_CDB_ADDR_REG 0x333b 748 #define HEVC_CDB_DATA_REG 0x333c 749 #define HEVC_CDB_CTRL 0x333d 750 #define HEVC_CSFTINT0 0x333e 751 #define HEVC_CSFTINT1 0x333f 752 #define HEVC_IMEM_DMA_CTRL 0x3340 753 #define HEVC_IMEM_DMA_ADR 0x3341 754 #define HEVC_IMEM_DMA_COUNT 0x3342 755 #define HEVC_WRRSP_IMEM 0x3343 756 #define HEVC_LMEM_DMA_CTRL 0x3350 757 #define HEVC_LMEM_DMA_ADR 0x3351 758 #define HEVC_LMEM_DMA_COUNT 0x3352 759 #define HEVC_WRRSP_LMEM 0x3353 760 #define HEVC_MAC_CTRL1 0x3360 761 #define HEVC_ACC0REG1 0x3361 762 #define HEVC_ACC1REG1 0x3362 763 #define HEVC_MAC_CTRL2 0x3370 764 #define HEVC_ACC0REG2 0x3371 765 #define HEVC_ACC1REG2 0x3372 766 #define HEVC_CPU_TRACE 0x3380 767 /**/ 768 769 #endif 770 771