1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_JPEG_H 10 #define HPM_JPEG_H 11 12 typedef struct { 13 __RW uint32_t INDMA_MISC; /* 0x0: In DMA Misc Control Register */ 14 __RW uint32_t INDMABASE; /* 0x4: In DMA Buf Address */ 15 __R uint8_t RESERVED0[4]; /* 0x8 - 0xB: Reserved */ 16 __RW uint32_t INDMA_CTRL0; /* 0xC: In DMA Buf Control 0 Register */ 17 __RW uint32_t INDMA_CTRL1; /* 0x10: In DMA Buf Control 1 Register */ 18 __RW uint32_t INXT_CMD; /* 0x14: In DMA Next Command Register */ 19 __R uint8_t RESERVED1[8]; /* 0x18 - 0x1F: Reserved */ 20 __RW uint32_t OUTDMA_MISC; /* 0x20: Out DMA Misc Control Register */ 21 __RW uint32_t OUTDMABASE; /* 0x24: Out DMA Buf Address */ 22 __R uint8_t RESERVED2[4]; /* 0x28 - 0x2B: Reserved */ 23 __RW uint32_t OUTDMA_CTRL0; /* 0x2C: Out DMA Buf Control 0 Register */ 24 __RW uint32_t OUTDMA_CTRL1; /* 0x30: Out DMA Buf Control 1 Register */ 25 __RW uint32_t ONXT_CMD; /* 0x34: Out DMA Next Command Register */ 26 __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */ 27 __RW uint32_t CFG; /* 0x40: Configuration Register */ 28 __RW uint32_t STAT; /* 0x44: Status Register */ 29 __RW uint32_t WIDTH; /* 0x48: Image width register */ 30 __RW uint32_t HEIGHT; /* 0x4C: Image height register */ 31 __RW uint32_t BUFADDR; /* 0x50: Buf Access Addr */ 32 __RW uint32_t BUFDATA; /* 0x54: Buf Access Data */ 33 __R uint32_t OUTDMACNT; /* 0x58: Out DMA Bytes Counter */ 34 __RW uint32_t CSC_COEF0; /* 0x5C: YUV2RGB coefficients Register 0 */ 35 __RW uint32_t CSC_COEF1; /* 0x60: YUV2RGB coefficients Register 1 */ 36 __RW uint32_t CSC_COEF2; /* 0x64: YUV2RGB coefficients Register 2 */ 37 __RW uint32_t RGB2YUV_COEF0; /* 0x68: RGB2YUV coefficients Register 0 */ 38 __RW uint32_t RGB2YUV_COEF1; /* 0x6C: RGB2YUV coefficients Register 1 */ 39 __RW uint32_t RGB2YUV_COEF2; /* 0x70: RGB2YUV coefficients Register 2 */ 40 __RW uint32_t RGB2YUV_COEF3; /* 0x74: RGB2YUV coefficients Register 3 */ 41 __RW uint32_t RGB2YUV_COEF4; /* 0x78: RGB2YUV coefficients Register 4 */ 42 __R uint8_t RESERVED4[8]; /* 0x7C - 0x83: Reserved */ 43 __RW uint32_t IMGREG1; /* 0x84: Image Control Register 1 */ 44 __RW uint32_t IMGREG2; /* 0x88: Image Control Register 2 */ 45 __RW uint32_t IMGREG3; /* 0x8C: Image Control Register 3 */ 46 __RW uint32_t IMGREG[4]; /* 0x90 - 0x9C: Image Control Register 40 */ 47 } JPEG_Type; 48 49 50 /* Bitfield definition for register: INDMA_MISC */ 51 /* 52 * ARQOS (RW) 53 * 54 * QoS for AXI read channel 55 */ 56 #define JPEG_INDMA_MISC_ARQOS_MASK (0x780000UL) 57 #define JPEG_INDMA_MISC_ARQOS_SHIFT (19U) 58 #define JPEG_INDMA_MISC_ARQOS_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_ARQOS_SHIFT) & JPEG_INDMA_MISC_ARQOS_MASK) 59 #define JPEG_INDMA_MISC_ARQOS_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_ARQOS_MASK) >> JPEG_INDMA_MISC_ARQOS_SHIFT) 60 61 /* 62 * MAX_OT (RW) 63 * 64 * max_ot when input are RGB pixels. 65 * For 16 bits per pixel, it can be set as 4. 66 * For 32 bits per pixel, it will be set as 2. 67 */ 68 #define JPEG_INDMA_MISC_MAX_OT_MASK (0x78000UL) 69 #define JPEG_INDMA_MISC_MAX_OT_SHIFT (15U) 70 #define JPEG_INDMA_MISC_MAX_OT_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_MAX_OT_SHIFT) & JPEG_INDMA_MISC_MAX_OT_MASK) 71 #define JPEG_INDMA_MISC_MAX_OT_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_MAX_OT_MASK) >> JPEG_INDMA_MISC_MAX_OT_SHIFT) 72 73 /* 74 * INB13_SWAP (RW) 75 * 76 * Swap bit[31:24] and bit [15:8] before pack dir operation. Only work for pixel data. 77 */ 78 #define JPEG_INDMA_MISC_INB13_SWAP_MASK (0x4000U) 79 #define JPEG_INDMA_MISC_INB13_SWAP_SHIFT (14U) 80 #define JPEG_INDMA_MISC_INB13_SWAP_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_INB13_SWAP_SHIFT) & JPEG_INDMA_MISC_INB13_SWAP_MASK) 81 #define JPEG_INDMA_MISC_INB13_SWAP_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_INB13_SWAP_MASK) >> JPEG_INDMA_MISC_INB13_SWAP_SHIFT) 82 83 /* 84 * PACK_DIR (RW) 85 * 86 * Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. Only work for pixel data. 87 * 2'b00: no change {A3, A2, A1, A0} 88 * 2'b01: {A2, A3, A0, A1} 89 * 2'b10: {A1, A0, A3, A2} 90 * 2'b11: {A0, A1, A2, A3} 91 */ 92 #define JPEG_INDMA_MISC_PACK_DIR_MASK (0x3000U) 93 #define JPEG_INDMA_MISC_PACK_DIR_SHIFT (12U) 94 #define JPEG_INDMA_MISC_PACK_DIR_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_PACK_DIR_SHIFT) & JPEG_INDMA_MISC_PACK_DIR_MASK) 95 #define JPEG_INDMA_MISC_PACK_DIR_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_PACK_DIR_MASK) >> JPEG_INDMA_MISC_PACK_DIR_SHIFT) 96 97 /* 98 * INDMA_RENEW (RW) 99 * 100 * Renew In DMA. Default is to continue the write address counter when a new DMA request comes. Asserted to reset the write address counter. 101 */ 102 #define JPEG_INDMA_MISC_INDMA_RENEW_MASK (0x800U) 103 #define JPEG_INDMA_MISC_INDMA_RENEW_SHIFT (11U) 104 #define JPEG_INDMA_MISC_INDMA_RENEW_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_INDMA_RENEW_SHIFT) & JPEG_INDMA_MISC_INDMA_RENEW_MASK) 105 #define JPEG_INDMA_MISC_INDMA_RENEW_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_INDMA_RENEW_MASK) >> JPEG_INDMA_MISC_INDMA_RENEW_SHIFT) 106 107 /* 108 * NXT_IRQ_EN (RW) 109 * 110 * In DMA Next Interrupt Enable 111 */ 112 #define JPEG_INDMA_MISC_NXT_IRQ_EN_MASK (0x400U) 113 #define JPEG_INDMA_MISC_NXT_IRQ_EN_SHIFT (10U) 114 #define JPEG_INDMA_MISC_NXT_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_NXT_IRQ_EN_SHIFT) & JPEG_INDMA_MISC_NXT_IRQ_EN_MASK) 115 #define JPEG_INDMA_MISC_NXT_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_NXT_IRQ_EN_MASK) >> JPEG_INDMA_MISC_NXT_IRQ_EN_SHIFT) 116 117 /* 118 * IN_DMA_DONE_IRQ_EN (RW) 119 * 120 * In DMA Done enable 121 */ 122 #define JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_MASK (0x200U) 123 #define JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_SHIFT (9U) 124 #define JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_SHIFT) & JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_MASK) 125 #define JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_MASK) >> JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_SHIFT) 126 127 /* 128 * AXI_ERR_IRQ_EN (RW) 129 * 130 * In DMA axi bus error inetrrupt enable 131 */ 132 #define JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_MASK (0x100U) 133 #define JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_SHIFT (8U) 134 #define JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_SHIFT) & JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_MASK) 135 #define JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_MASK) >> JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_SHIFT) 136 137 /* 138 * IRQ_EN (RW) 139 * 140 * interrupt enable for all interrupt sources of In DMA module 141 */ 142 #define JPEG_INDMA_MISC_IRQ_EN_MASK (0x80U) 143 #define JPEG_INDMA_MISC_IRQ_EN_SHIFT (7U) 144 #define JPEG_INDMA_MISC_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_IRQ_EN_SHIFT) & JPEG_INDMA_MISC_IRQ_EN_MASK) 145 #define JPEG_INDMA_MISC_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_IRQ_EN_MASK) >> JPEG_INDMA_MISC_IRQ_EN_SHIFT) 146 147 /* 148 * IN_DMA_ID (RW) 149 * 150 * 0: Pixel (In) 151 * 1: ECS (In) 152 * 2: Qmem 153 * 3: HuffEnc 154 * 4: HuffMin 155 * 5: HuffBase 156 * 6: HuffSymb 157 */ 158 #define JPEG_INDMA_MISC_IN_DMA_ID_MASK (0x70U) 159 #define JPEG_INDMA_MISC_IN_DMA_ID_SHIFT (4U) 160 #define JPEG_INDMA_MISC_IN_DMA_ID_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_IN_DMA_ID_SHIFT) & JPEG_INDMA_MISC_IN_DMA_ID_MASK) 161 #define JPEG_INDMA_MISC_IN_DMA_ID_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_IN_DMA_ID_MASK) >> JPEG_INDMA_MISC_IN_DMA_ID_SHIFT) 162 163 /* 164 * IN_DMA_REQ (RW) 165 * 166 * Asserted to request DMA. Automatically clear after DMA is done. 167 */ 168 #define JPEG_INDMA_MISC_IN_DMA_REQ_MASK (0x8U) 169 #define JPEG_INDMA_MISC_IN_DMA_REQ_SHIFT (3U) 170 #define JPEG_INDMA_MISC_IN_DMA_REQ_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_IN_DMA_REQ_SHIFT) & JPEG_INDMA_MISC_IN_DMA_REQ_MASK) 171 #define JPEG_INDMA_MISC_IN_DMA_REQ_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_IN_DMA_REQ_MASK) >> JPEG_INDMA_MISC_IN_DMA_REQ_SHIFT) 172 173 /* 174 * INDMA2D (RW) 175 * 176 * Asserted if In_DMA_ID=Pixel. 177 */ 178 #define JPEG_INDMA_MISC_INDMA2D_MASK (0x4U) 179 #define JPEG_INDMA_MISC_INDMA2D_SHIFT (2U) 180 #define JPEG_INDMA_MISC_INDMA2D_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_INDMA2D_SHIFT) & JPEG_INDMA_MISC_INDMA2D_MASK) 181 #define JPEG_INDMA_MISC_INDMA2D_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_INDMA2D_MASK) >> JPEG_INDMA_MISC_INDMA2D_SHIFT) 182 183 /* Bitfield definition for register: INDMABASE */ 184 /* 185 * ADDR (RW) 186 * 187 * Y plane (or Encoded Bit Plane) 188 */ 189 #define JPEG_INDMABASE_ADDR_MASK (0xFFFFFFFFUL) 190 #define JPEG_INDMABASE_ADDR_SHIFT (0U) 191 #define JPEG_INDMABASE_ADDR_SET(x) (((uint32_t)(x) << JPEG_INDMABASE_ADDR_SHIFT) & JPEG_INDMABASE_ADDR_MASK) 192 #define JPEG_INDMABASE_ADDR_GET(x) (((uint32_t)(x) & JPEG_INDMABASE_ADDR_MASK) >> JPEG_INDMABASE_ADDR_SHIFT) 193 194 /* Bitfield definition for register: INDMA_CTRL0 */ 195 /* 196 * TTLEN (RW) 197 * 198 * Total length (Low 16 bits) in Bytes -1 for transfer when In_DMA_ID!=Pixel. 199 */ 200 #define JPEG_INDMA_CTRL0_TTLEN_MASK (0xFFFF0000UL) 201 #define JPEG_INDMA_CTRL0_TTLEN_SHIFT (16U) 202 #define JPEG_INDMA_CTRL0_TTLEN_SET(x) (((uint32_t)(x) << JPEG_INDMA_CTRL0_TTLEN_SHIFT) & JPEG_INDMA_CTRL0_TTLEN_MASK) 203 #define JPEG_INDMA_CTRL0_TTLEN_GET(x) (((uint32_t)(x) & JPEG_INDMA_CTRL0_TTLEN_MASK) >> JPEG_INDMA_CTRL0_TTLEN_SHIFT) 204 205 /* 206 * PITCH (RW) 207 * 208 * Pitch between the starting point of Rows. Only active when In_DMA_ID=Pixel.. 209 */ 210 #define JPEG_INDMA_CTRL0_PITCH_MASK (0xFFFFU) 211 #define JPEG_INDMA_CTRL0_PITCH_SHIFT (0U) 212 #define JPEG_INDMA_CTRL0_PITCH_SET(x) (((uint32_t)(x) << JPEG_INDMA_CTRL0_PITCH_SHIFT) & JPEG_INDMA_CTRL0_PITCH_MASK) 213 #define JPEG_INDMA_CTRL0_PITCH_GET(x) (((uint32_t)(x) & JPEG_INDMA_CTRL0_PITCH_MASK) >> JPEG_INDMA_CTRL0_PITCH_SHIFT) 214 215 /* Bitfield definition for register: INDMA_CTRL1 */ 216 /* 217 * ROWLEN (RW) 218 * 219 * Total length (High 16 bits) in Bytes -1 for transfer. See reference in InDMA_Ctrl0[TTLEN] 220 */ 221 #define JPEG_INDMA_CTRL1_ROWLEN_MASK (0xFFFFU) 222 #define JPEG_INDMA_CTRL1_ROWLEN_SHIFT (0U) 223 #define JPEG_INDMA_CTRL1_ROWLEN_SET(x) (((uint32_t)(x) << JPEG_INDMA_CTRL1_ROWLEN_SHIFT) & JPEG_INDMA_CTRL1_ROWLEN_MASK) 224 #define JPEG_INDMA_CTRL1_ROWLEN_GET(x) (((uint32_t)(x) & JPEG_INDMA_CTRL1_ROWLEN_MASK) >> JPEG_INDMA_CTRL1_ROWLEN_SHIFT) 225 226 /* Bitfield definition for register: INXT_CMD */ 227 /* 228 * ADDR (RW) 229 * 230 * The address pointing to the next command 231 */ 232 #define JPEG_INXT_CMD_ADDR_MASK (0xFFFFFFFCUL) 233 #define JPEG_INXT_CMD_ADDR_SHIFT (2U) 234 #define JPEG_INXT_CMD_ADDR_SET(x) (((uint32_t)(x) << JPEG_INXT_CMD_ADDR_SHIFT) & JPEG_INXT_CMD_ADDR_MASK) 235 #define JPEG_INXT_CMD_ADDR_GET(x) (((uint32_t)(x) & JPEG_INXT_CMD_ADDR_MASK) >> JPEG_INXT_CMD_ADDR_SHIFT) 236 237 /* 238 * OP_VALID (RW) 239 * 240 * asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the InDMA transfer if CFG[JPEG_EN] is 1. 241 */ 242 #define JPEG_INXT_CMD_OP_VALID_MASK (0x2U) 243 #define JPEG_INXT_CMD_OP_VALID_SHIFT (1U) 244 #define JPEG_INXT_CMD_OP_VALID_SET(x) (((uint32_t)(x) << JPEG_INXT_CMD_OP_VALID_SHIFT) & JPEG_INXT_CMD_OP_VALID_MASK) 245 #define JPEG_INXT_CMD_OP_VALID_GET(x) (((uint32_t)(x) & JPEG_INXT_CMD_OP_VALID_MASK) >> JPEG_INXT_CMD_OP_VALID_SHIFT) 246 247 /* 248 * EN (RW) 249 * 250 * NXTCMD phase Enable Bit 251 */ 252 #define JPEG_INXT_CMD_EN_MASK (0x1U) 253 #define JPEG_INXT_CMD_EN_SHIFT (0U) 254 #define JPEG_INXT_CMD_EN_SET(x) (((uint32_t)(x) << JPEG_INXT_CMD_EN_SHIFT) & JPEG_INXT_CMD_EN_MASK) 255 #define JPEG_INXT_CMD_EN_GET(x) (((uint32_t)(x) & JPEG_INXT_CMD_EN_MASK) >> JPEG_INXT_CMD_EN_SHIFT) 256 257 /* Bitfield definition for register: OUTDMA_MISC */ 258 /* 259 * AWQOS (RW) 260 * 261 */ 262 #define JPEG_OUTDMA_MISC_AWQOS_MASK (0x3C000UL) 263 #define JPEG_OUTDMA_MISC_AWQOS_SHIFT (14U) 264 #define JPEG_OUTDMA_MISC_AWQOS_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_AWQOS_SHIFT) & JPEG_OUTDMA_MISC_AWQOS_MASK) 265 #define JPEG_OUTDMA_MISC_AWQOS_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_AWQOS_MASK) >> JPEG_OUTDMA_MISC_AWQOS_SHIFT) 266 267 /* 268 * PACK_DIR (RW) 269 * 270 * Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. All outdma data are impacted. 271 * 2'b00: no change {A3, A2, A1, A0} (This is used for ecs stream) 272 * 2'b01: {A2, A3, A0, A1} 273 * 2'b10: {A1, A0, A3, A2} 274 * 2'b11: {A0, A1, A2, A3} 275 */ 276 #define JPEG_OUTDMA_MISC_PACK_DIR_MASK (0x3000U) 277 #define JPEG_OUTDMA_MISC_PACK_DIR_SHIFT (12U) 278 #define JPEG_OUTDMA_MISC_PACK_DIR_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_PACK_DIR_SHIFT) & JPEG_OUTDMA_MISC_PACK_DIR_MASK) 279 #define JPEG_OUTDMA_MISC_PACK_DIR_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_PACK_DIR_MASK) >> JPEG_OUTDMA_MISC_PACK_DIR_SHIFT) 280 281 /* 282 * EN_OUTCNT (RW) 283 * 284 * Enable output counter (unit as bytes) 285 */ 286 #define JPEG_OUTDMA_MISC_EN_OUTCNT_MASK (0x800U) 287 #define JPEG_OUTDMA_MISC_EN_OUTCNT_SHIFT (11U) 288 #define JPEG_OUTDMA_MISC_EN_OUTCNT_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_EN_OUTCNT_SHIFT) & JPEG_OUTDMA_MISC_EN_OUTCNT_MASK) 289 #define JPEG_OUTDMA_MISC_EN_OUTCNT_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_EN_OUTCNT_MASK) >> JPEG_OUTDMA_MISC_EN_OUTCNT_SHIFT) 290 291 /* 292 * INI_OUTCNT (RW) 293 * 294 * Asserted to ini output counter 295 */ 296 #define JPEG_OUTDMA_MISC_INI_OUTCNT_MASK (0x400U) 297 #define JPEG_OUTDMA_MISC_INI_OUTCNT_SHIFT (10U) 298 #define JPEG_OUTDMA_MISC_INI_OUTCNT_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_INI_OUTCNT_SHIFT) & JPEG_OUTDMA_MISC_INI_OUTCNT_MASK) 299 #define JPEG_OUTDMA_MISC_INI_OUTCNT_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_INI_OUTCNT_MASK) >> JPEG_OUTDMA_MISC_INI_OUTCNT_SHIFT) 300 301 /* 302 * ADD_ODMA_ENDINGS (RW) 303 * 304 * Add 0xFFD9 to the ending of the odma stream when all original image pixels are processed by the encoder module. 305 */ 306 #define JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_MASK (0x200U) 307 #define JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_SHIFT (9U) 308 #define JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_SHIFT) & JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_MASK) 309 #define JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_MASK) >> JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_SHIFT) 310 311 /* 312 * NXT_IRQ_EN (RW) 313 * 314 * Out DMA Next Interrupt Enable 315 */ 316 #define JPEG_OUTDMA_MISC_NXT_IRQ_EN_MASK (0x100U) 317 #define JPEG_OUTDMA_MISC_NXT_IRQ_EN_SHIFT (8U) 318 #define JPEG_OUTDMA_MISC_NXT_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_NXT_IRQ_EN_SHIFT) & JPEG_OUTDMA_MISC_NXT_IRQ_EN_MASK) 319 #define JPEG_OUTDMA_MISC_NXT_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_NXT_IRQ_EN_MASK) >> JPEG_OUTDMA_MISC_NXT_IRQ_EN_SHIFT) 320 321 /* 322 * OUT_DMA_DONE_IRQ_EN (RW) 323 * 324 * Out DMA Done interrupt Enable 325 */ 326 #define JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_MASK (0x80U) 327 #define JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_SHIFT (7U) 328 #define JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_SHIFT) & JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_MASK) 329 #define JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_MASK) >> JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_SHIFT) 330 331 /* 332 * AXI_ERR_IRQ_EN (RW) 333 * 334 * Out DMA axi bus error inetrrupt enable 335 */ 336 #define JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_MASK (0x40U) 337 #define JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_SHIFT (6U) 338 #define JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_SHIFT) & JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_MASK) 339 #define JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_MASK) >> JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_SHIFT) 340 341 /* 342 * IRQ_EN (RW) 343 * 344 * interrupt enable for all interrupt sources of Out DMA module 345 */ 346 #define JPEG_OUTDMA_MISC_IRQ_EN_MASK (0x20U) 347 #define JPEG_OUTDMA_MISC_IRQ_EN_SHIFT (5U) 348 #define JPEG_OUTDMA_MISC_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_IRQ_EN_SHIFT) & JPEG_OUTDMA_MISC_IRQ_EN_MASK) 349 #define JPEG_OUTDMA_MISC_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_IRQ_EN_MASK) >> JPEG_OUTDMA_MISC_IRQ_EN_SHIFT) 350 351 /* 352 * OUT_DMA_ID (RW) 353 * 354 * 0: Pixel (Out) 355 * 1: ECS (Out) 356 */ 357 #define JPEG_OUTDMA_MISC_OUT_DMA_ID_MASK (0x10U) 358 #define JPEG_OUTDMA_MISC_OUT_DMA_ID_SHIFT (4U) 359 #define JPEG_OUTDMA_MISC_OUT_DMA_ID_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_OUT_DMA_ID_SHIFT) & JPEG_OUTDMA_MISC_OUT_DMA_ID_MASK) 360 #define JPEG_OUTDMA_MISC_OUT_DMA_ID_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_OUT_DMA_ID_MASK) >> JPEG_OUTDMA_MISC_OUT_DMA_ID_SHIFT) 361 362 /* 363 * OUT_DMA_REQ (RW) 364 * 365 * Asserted to enable Out DMA request 366 */ 367 #define JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK (0x8U) 368 #define JPEG_OUTDMA_MISC_OUT_DMA_REQ_SHIFT (3U) 369 #define JPEG_OUTDMA_MISC_OUT_DMA_REQ_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_OUT_DMA_REQ_SHIFT) & JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK) 370 #define JPEG_OUTDMA_MISC_OUT_DMA_REQ_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK) >> JPEG_OUTDMA_MISC_OUT_DMA_REQ_SHIFT) 371 372 /* 373 * OUTDMA2D (RW) 374 * 375 * Asserted if Out_DMA_ID==Pixel 376 */ 377 #define JPEG_OUTDMA_MISC_OUTDMA2D_MASK (0x4U) 378 #define JPEG_OUTDMA_MISC_OUTDMA2D_SHIFT (2U) 379 #define JPEG_OUTDMA_MISC_OUTDMA2D_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_OUTDMA2D_SHIFT) & JPEG_OUTDMA_MISC_OUTDMA2D_MASK) 380 #define JPEG_OUTDMA_MISC_OUTDMA2D_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_OUTDMA2D_MASK) >> JPEG_OUTDMA_MISC_OUTDMA2D_SHIFT) 381 382 /* Bitfield definition for register: OUTDMABASE */ 383 /* 384 * ADDR (RW) 385 * 386 * Y plane (or Encoded Bit Plane) 387 */ 388 #define JPEG_OUTDMABASE_ADDR_MASK (0xFFFFFFFFUL) 389 #define JPEG_OUTDMABASE_ADDR_SHIFT (0U) 390 #define JPEG_OUTDMABASE_ADDR_SET(x) (((uint32_t)(x) << JPEG_OUTDMABASE_ADDR_SHIFT) & JPEG_OUTDMABASE_ADDR_MASK) 391 #define JPEG_OUTDMABASE_ADDR_GET(x) (((uint32_t)(x) & JPEG_OUTDMABASE_ADDR_MASK) >> JPEG_OUTDMABASE_ADDR_SHIFT) 392 393 /* Bitfield definition for register: OUTDMA_CTRL0 */ 394 /* 395 * TTLEN (RW) 396 * 397 * Total length (Low 16 bits) in Bytes -1 for transfer when Out_DMA_ID!=Pixel. If Out_DMA_ID=ECS, it can be any value greater than the length of the ECS, for example, the number of encoded bytes. 398 */ 399 #define JPEG_OUTDMA_CTRL0_TTLEN_MASK (0xFFFF0000UL) 400 #define JPEG_OUTDMA_CTRL0_TTLEN_SHIFT (16U) 401 #define JPEG_OUTDMA_CTRL0_TTLEN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_CTRL0_TTLEN_SHIFT) & JPEG_OUTDMA_CTRL0_TTLEN_MASK) 402 #define JPEG_OUTDMA_CTRL0_TTLEN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_CTRL0_TTLEN_MASK) >> JPEG_OUTDMA_CTRL0_TTLEN_SHIFT) 403 404 /* 405 * PITCH (RW) 406 * 407 * Pitch between the starting point of Rows when Out_DMA_ID==Pixel 408 */ 409 #define JPEG_OUTDMA_CTRL0_PITCH_MASK (0xFFFFU) 410 #define JPEG_OUTDMA_CTRL0_PITCH_SHIFT (0U) 411 #define JPEG_OUTDMA_CTRL0_PITCH_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_CTRL0_PITCH_SHIFT) & JPEG_OUTDMA_CTRL0_PITCH_MASK) 412 #define JPEG_OUTDMA_CTRL0_PITCH_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_CTRL0_PITCH_MASK) >> JPEG_OUTDMA_CTRL0_PITCH_SHIFT) 413 414 /* Bitfield definition for register: OUTDMA_CTRL1 */ 415 /* 416 * ROWLEN (RW) 417 * 418 * Total length (High 16 bits) in Bytes -1 for transfer. See reference in OutDMA_Ctrl0[TTLEN] 419 */ 420 #define JPEG_OUTDMA_CTRL1_ROWLEN_MASK (0xFFFFU) 421 #define JPEG_OUTDMA_CTRL1_ROWLEN_SHIFT (0U) 422 #define JPEG_OUTDMA_CTRL1_ROWLEN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_CTRL1_ROWLEN_SHIFT) & JPEG_OUTDMA_CTRL1_ROWLEN_MASK) 423 #define JPEG_OUTDMA_CTRL1_ROWLEN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_CTRL1_ROWLEN_MASK) >> JPEG_OUTDMA_CTRL1_ROWLEN_SHIFT) 424 425 /* Bitfield definition for register: ONXT_CMD */ 426 /* 427 * ADDR (RW) 428 * 429 * The address pointing to the next command 430 */ 431 #define JPEG_ONXT_CMD_ADDR_MASK (0xFFFFFFFCUL) 432 #define JPEG_ONXT_CMD_ADDR_SHIFT (2U) 433 #define JPEG_ONXT_CMD_ADDR_SET(x) (((uint32_t)(x) << JPEG_ONXT_CMD_ADDR_SHIFT) & JPEG_ONXT_CMD_ADDR_MASK) 434 #define JPEG_ONXT_CMD_ADDR_GET(x) (((uint32_t)(x) & JPEG_ONXT_CMD_ADDR_MASK) >> JPEG_ONXT_CMD_ADDR_SHIFT) 435 436 /* 437 * OP_VALID (RW) 438 * 439 * asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the OutDMA and NXTCMD phase transfer if CFG[JPEG_EN] is 1. 440 */ 441 #define JPEG_ONXT_CMD_OP_VALID_MASK (0x2U) 442 #define JPEG_ONXT_CMD_OP_VALID_SHIFT (1U) 443 #define JPEG_ONXT_CMD_OP_VALID_SET(x) (((uint32_t)(x) << JPEG_ONXT_CMD_OP_VALID_SHIFT) & JPEG_ONXT_CMD_OP_VALID_MASK) 444 #define JPEG_ONXT_CMD_OP_VALID_GET(x) (((uint32_t)(x) & JPEG_ONXT_CMD_OP_VALID_MASK) >> JPEG_ONXT_CMD_OP_VALID_SHIFT) 445 446 /* 447 * EN (RW) 448 * 449 * NXTCMD phase Enable Bit 450 */ 451 #define JPEG_ONXT_CMD_EN_MASK (0x1U) 452 #define JPEG_ONXT_CMD_EN_SHIFT (0U) 453 #define JPEG_ONXT_CMD_EN_SET(x) (((uint32_t)(x) << JPEG_ONXT_CMD_EN_SHIFT) & JPEG_ONXT_CMD_EN_MASK) 454 #define JPEG_ONXT_CMD_EN_GET(x) (((uint32_t)(x) & JPEG_ONXT_CMD_EN_MASK) >> JPEG_ONXT_CMD_EN_SHIFT) 455 456 /* Bitfield definition for register: CFG */ 457 /* 458 * JD_UVSWAP (RW) 459 * 460 * Normally the default CbCr sequence is that Cb macro block coming before Cr macro blk. If Cr macro block is first, set this bit to 1'b1. This bit only impact the color space conversion from/to RGB. 461 */ 462 #define JPEG_CFG_JD_UVSWAP_MASK (0x400000UL) 463 #define JPEG_CFG_JD_UVSWAP_SHIFT (22U) 464 #define JPEG_CFG_JD_UVSWAP_SET(x) (((uint32_t)(x) << JPEG_CFG_JD_UVSWAP_SHIFT) & JPEG_CFG_JD_UVSWAP_MASK) 465 #define JPEG_CFG_JD_UVSWAP_GET(x) (((uint32_t)(x) & JPEG_CFG_JD_UVSWAP_MASK) >> JPEG_CFG_JD_UVSWAP_SHIFT) 466 467 /* 468 * CFG_IPATH_SEL (RW) 469 * 470 * 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V 471 * 2'b01:ARGB8888, byte sequence as B,G,R,A 472 * 2'b10:RGB565, byte sequence as B,R 473 * 2'b11: YUV422H, byte sequence as Y0,U0,Y1,V0 474 */ 475 #define JPEG_CFG_CFG_IPATH_SEL_MASK (0x300000UL) 476 #define JPEG_CFG_CFG_IPATH_SEL_SHIFT (20U) 477 #define JPEG_CFG_CFG_IPATH_SEL_SET(x) (((uint32_t)(x) << JPEG_CFG_CFG_IPATH_SEL_SHIFT) & JPEG_CFG_CFG_IPATH_SEL_MASK) 478 #define JPEG_CFG_CFG_IPATH_SEL_GET(x) (((uint32_t)(x) & JPEG_CFG_CFG_IPATH_SEL_MASK) >> JPEG_CFG_CFG_IPATH_SEL_SHIFT) 479 480 /* 481 * CODEC_OVER_IRQ_EN (RW) 482 * 483 * The jpg endec process done interrupt enable 484 */ 485 #define JPEG_CFG_CODEC_OVER_IRQ_EN_MASK (0x80000UL) 486 #define JPEG_CFG_CODEC_OVER_IRQ_EN_SHIFT (19U) 487 #define JPEG_CFG_CODEC_OVER_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_CFG_CODEC_OVER_IRQ_EN_SHIFT) & JPEG_CFG_CODEC_OVER_IRQ_EN_MASK) 488 #define JPEG_CFG_CODEC_OVER_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_CFG_CODEC_OVER_IRQ_EN_MASK) >> JPEG_CFG_CODEC_OVER_IRQ_EN_SHIFT) 489 490 /* 491 * CODEC_RESTART_ERR_IRQ_EN (RW) 492 * 493 * The jpg endec restart error interrupt enable 494 */ 495 #define JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK (0x40000UL) 496 #define JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_SHIFT (18U) 497 #define JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_SHIFT) & JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK) 498 #define JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK) >> JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_SHIFT) 499 500 /* 501 * MEM_DEBUG_CLK_SEL (RW) 502 * 503 * asserted to use APB clock, so that the memory contents could be read out through APB interface 504 */ 505 #define JPEG_CFG_MEM_DEBUG_CLK_SEL_MASK (0x20000UL) 506 #define JPEG_CFG_MEM_DEBUG_CLK_SEL_SHIFT (17U) 507 #define JPEG_CFG_MEM_DEBUG_CLK_SEL_SET(x) (((uint32_t)(x) << JPEG_CFG_MEM_DEBUG_CLK_SEL_SHIFT) & JPEG_CFG_MEM_DEBUG_CLK_SEL_MASK) 508 #define JPEG_CFG_MEM_DEBUG_CLK_SEL_GET(x) (((uint32_t)(x) & JPEG_CFG_MEM_DEBUG_CLK_SEL_MASK) >> JPEG_CFG_MEM_DEBUG_CLK_SEL_SHIFT) 509 510 /* 511 * CLKGATE (RW) 512 * 513 * Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. 514 */ 515 #define JPEG_CFG_CLKGATE_MASK (0x200U) 516 #define JPEG_CFG_CLKGATE_SHIFT (9U) 517 #define JPEG_CFG_CLKGATE_SET(x) (((uint32_t)(x) << JPEG_CFG_CLKGATE_SHIFT) & JPEG_CFG_CLKGATE_MASK) 518 #define JPEG_CFG_CLKGATE_GET(x) (((uint32_t)(x) & JPEG_CFG_CLKGATE_MASK) >> JPEG_CFG_CLKGATE_SHIFT) 519 520 /* 521 * CFG_OPATH_SEL (RW) 522 * 523 * 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V 524 * 2'b01:ARGB8888, byte sequence as B,G,R,A 525 * 2'b10:RGB565, byte sequence as R,B 526 * 2'b11: YUV422H1P, byte sequence as Y0,U0,Y1,V0 527 */ 528 #define JPEG_CFG_CFG_OPATH_SEL_MASK (0x180U) 529 #define JPEG_CFG_CFG_OPATH_SEL_SHIFT (7U) 530 #define JPEG_CFG_CFG_OPATH_SEL_SET(x) (((uint32_t)(x) << JPEG_CFG_CFG_OPATH_SEL_SHIFT) & JPEG_CFG_CFG_OPATH_SEL_MASK) 531 #define JPEG_CFG_CFG_OPATH_SEL_GET(x) (((uint32_t)(x) & JPEG_CFG_CFG_OPATH_SEL_MASK) >> JPEG_CFG_CFG_OPATH_SEL_SHIFT) 532 533 /* 534 * JDATA_FORMAT (RW) 535 * 536 * 3'b000: for 420, hy=2, vy=2, hc=1, vc=1 // 6 sub-blocks per MCU 537 * 3'b001: for 422h, hy=2, vy=1, hc=1, vc=1 // 4 sub-blocks per MCU 538 * 3'b010: for 422v, hy=1, vy=2, hc=1, vc=1 // 4 sub-blocks per MCU 539 * 3'b011: for 444, hy=1, vy=1, hc=1, vc=1 // 3 sub-blocks per MCU 540 * 3'b100: for 400, hy=2, vy=2, hc=0, vc=0 // 4 sub-blocks per MCU 541 * Others: Undefined 542 */ 543 #define JPEG_CFG_JDATA_FORMAT_MASK (0x70U) 544 #define JPEG_CFG_JDATA_FORMAT_SHIFT (4U) 545 #define JPEG_CFG_JDATA_FORMAT_SET(x) (((uint32_t)(x) << JPEG_CFG_JDATA_FORMAT_SHIFT) & JPEG_CFG_JDATA_FORMAT_MASK) 546 #define JPEG_CFG_JDATA_FORMAT_GET(x) (((uint32_t)(x) & JPEG_CFG_JDATA_FORMAT_MASK) >> JPEG_CFG_JDATA_FORMAT_SHIFT) 547 548 /* 549 * JPEG_SFTRST (RW) 550 * 551 * Software Reset 552 */ 553 #define JPEG_CFG_JPEG_SFTRST_MASK (0x8U) 554 #define JPEG_CFG_JPEG_SFTRST_SHIFT (3U) 555 #define JPEG_CFG_JPEG_SFTRST_SET(x) (((uint32_t)(x) << JPEG_CFG_JPEG_SFTRST_SHIFT) & JPEG_CFG_JPEG_SFTRST_MASK) 556 #define JPEG_CFG_JPEG_SFTRST_GET(x) (((uint32_t)(x) & JPEG_CFG_JPEG_SFTRST_MASK) >> JPEG_CFG_JPEG_SFTRST_SHIFT) 557 558 /* 559 * START (RW) 560 * 561 * Asserted if to start a new encoder/decoder conversion. 562 * It will at first stop the inner JPEG module, then reset it, and then re-run it. 563 * It is a different mode from DMA phase mode. 564 * It cannot be configured in the DMA chain descriptor. It should be configured by the core processor. 565 * Auto clear. 566 */ 567 #define JPEG_CFG_START_MASK (0x4U) 568 #define JPEG_CFG_START_SHIFT (2U) 569 #define JPEG_CFG_START_SET(x) (((uint32_t)(x) << JPEG_CFG_START_SHIFT) & JPEG_CFG_START_MASK) 570 #define JPEG_CFG_START_GET(x) (((uint32_t)(x) & JPEG_CFG_START_MASK) >> JPEG_CFG_START_SHIFT) 571 572 /* 573 * MODE (RW) 574 * 575 * 1: decoder, 0:encoder 576 */ 577 #define JPEG_CFG_MODE_MASK (0x2U) 578 #define JPEG_CFG_MODE_SHIFT (1U) 579 #define JPEG_CFG_MODE_SET(x) (((uint32_t)(x) << JPEG_CFG_MODE_SHIFT) & JPEG_CFG_MODE_MASK) 580 #define JPEG_CFG_MODE_GET(x) (((uint32_t)(x) & JPEG_CFG_MODE_MASK) >> JPEG_CFG_MODE_SHIFT) 581 582 /* 583 * JPEG_EN (RW) 584 * 585 * 1b - Enabled 586 */ 587 #define JPEG_CFG_JPEG_EN_MASK (0x1U) 588 #define JPEG_CFG_JPEG_EN_SHIFT (0U) 589 #define JPEG_CFG_JPEG_EN_SET(x) (((uint32_t)(x) << JPEG_CFG_JPEG_EN_SHIFT) & JPEG_CFG_JPEG_EN_MASK) 590 #define JPEG_CFG_JPEG_EN_GET(x) (((uint32_t)(x) & JPEG_CFG_JPEG_EN_MASK) >> JPEG_CFG_JPEG_EN_SHIFT) 591 592 /* Bitfield definition for register: STAT */ 593 /* 594 * BUSY (RO) 595 * 596 * When 1 means that the module is busy doing conversion and data transfer. 597 */ 598 #define JPEG_STAT_BUSY_MASK (0x80000000UL) 599 #define JPEG_STAT_BUSY_SHIFT (31U) 600 #define JPEG_STAT_BUSY_GET(x) (((uint32_t)(x) & JPEG_STAT_BUSY_MASK) >> JPEG_STAT_BUSY_SHIFT) 601 602 /* 603 * AXI_ERR_ID (RO) 604 * 605 * the axi err id 606 */ 607 #define JPEG_STAT_AXI_ERR_ID_MASK (0x3C00U) 608 #define JPEG_STAT_AXI_ERR_ID_SHIFT (10U) 609 #define JPEG_STAT_AXI_ERR_ID_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_ERR_ID_MASK) >> JPEG_STAT_AXI_ERR_ID_SHIFT) 610 611 /* 612 * AXI_READ_ERR (RO) 613 * 614 * in-dma axi bus error 615 */ 616 #define JPEG_STAT_AXI_READ_ERR_MASK (0x200U) 617 #define JPEG_STAT_AXI_READ_ERR_SHIFT (9U) 618 #define JPEG_STAT_AXI_READ_ERR_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_READ_ERR_MASK) >> JPEG_STAT_AXI_READ_ERR_SHIFT) 619 620 /* 621 * AXI_WRITE_ERR (RO) 622 * 623 * out-dma axi bus error 624 */ 625 #define JPEG_STAT_AXI_WRITE_ERR_MASK (0x100U) 626 #define JPEG_STAT_AXI_WRITE_ERR_SHIFT (8U) 627 #define JPEG_STAT_AXI_WRITE_ERR_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_WRITE_ERR_MASK) >> JPEG_STAT_AXI_WRITE_ERR_SHIFT) 628 629 /* 630 * AXI_ERR (W1C) 631 * 632 * axi bus error 633 */ 634 #define JPEG_STAT_AXI_ERR_MASK (0x80U) 635 #define JPEG_STAT_AXI_ERR_SHIFT (7U) 636 #define JPEG_STAT_AXI_ERR_SET(x) (((uint32_t)(x) << JPEG_STAT_AXI_ERR_SHIFT) & JPEG_STAT_AXI_ERR_MASK) 637 #define JPEG_STAT_AXI_ERR_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_ERR_MASK) >> JPEG_STAT_AXI_ERR_SHIFT) 638 639 /* 640 * ONXT_IRQ (W1C) 641 * 642 * OutDMA next interrupt 643 */ 644 #define JPEG_STAT_ONXT_IRQ_MASK (0x40U) 645 #define JPEG_STAT_ONXT_IRQ_SHIFT (6U) 646 #define JPEG_STAT_ONXT_IRQ_SET(x) (((uint32_t)(x) << JPEG_STAT_ONXT_IRQ_SHIFT) & JPEG_STAT_ONXT_IRQ_MASK) 647 #define JPEG_STAT_ONXT_IRQ_GET(x) (((uint32_t)(x) & JPEG_STAT_ONXT_IRQ_MASK) >> JPEG_STAT_ONXT_IRQ_SHIFT) 648 649 /* 650 * INXT_IRQ (W1C) 651 * 652 * InDMA next interrupt 653 */ 654 #define JPEG_STAT_INXT_IRQ_MASK (0x20U) 655 #define JPEG_STAT_INXT_IRQ_SHIFT (5U) 656 #define JPEG_STAT_INXT_IRQ_SET(x) (((uint32_t)(x) << JPEG_STAT_INXT_IRQ_SHIFT) & JPEG_STAT_INXT_IRQ_MASK) 657 #define JPEG_STAT_INXT_IRQ_GET(x) (((uint32_t)(x) & JPEG_STAT_INXT_IRQ_MASK) >> JPEG_STAT_INXT_IRQ_SHIFT) 658 659 /* 660 * OUT_DMA_TRANSFER_DONE (W1C) 661 * 662 * OutDMA process done 663 */ 664 #define JPEG_STAT_OUT_DMA_TRANSFER_DONE_MASK (0x10U) 665 #define JPEG_STAT_OUT_DMA_TRANSFER_DONE_SHIFT (4U) 666 #define JPEG_STAT_OUT_DMA_TRANSFER_DONE_SET(x) (((uint32_t)(x) << JPEG_STAT_OUT_DMA_TRANSFER_DONE_SHIFT) & JPEG_STAT_OUT_DMA_TRANSFER_DONE_MASK) 667 #define JPEG_STAT_OUT_DMA_TRANSFER_DONE_GET(x) (((uint32_t)(x) & JPEG_STAT_OUT_DMA_TRANSFER_DONE_MASK) >> JPEG_STAT_OUT_DMA_TRANSFER_DONE_SHIFT) 668 669 /* 670 * IN_DMA_TRANSFER_DONE (W1C) 671 * 672 * InDMA process done 673 */ 674 #define JPEG_STAT_IN_DMA_TRANSFER_DONE_MASK (0x8U) 675 #define JPEG_STAT_IN_DMA_TRANSFER_DONE_SHIFT (3U) 676 #define JPEG_STAT_IN_DMA_TRANSFER_DONE_SET(x) (((uint32_t)(x) << JPEG_STAT_IN_DMA_TRANSFER_DONE_SHIFT) & JPEG_STAT_IN_DMA_TRANSFER_DONE_MASK) 677 #define JPEG_STAT_IN_DMA_TRANSFER_DONE_GET(x) (((uint32_t)(x) & JPEG_STAT_IN_DMA_TRANSFER_DONE_MASK) >> JPEG_STAT_IN_DMA_TRANSFER_DONE_SHIFT) 678 679 /* 680 * CODEC_OVER (W1C) 681 * 682 * Coding or decoding process is over. DMA is not included. 683 * The module is completely not busy only when in_dma_transfer_done and out_dma_transfer_done, and codec_over are all asserted. 684 */ 685 #define JPEG_STAT_CODEC_OVER_MASK (0x4U) 686 #define JPEG_STAT_CODEC_OVER_SHIFT (2U) 687 #define JPEG_STAT_CODEC_OVER_SET(x) (((uint32_t)(x) << JPEG_STAT_CODEC_OVER_SHIFT) & JPEG_STAT_CODEC_OVER_MASK) 688 #define JPEG_STAT_CODEC_OVER_GET(x) (((uint32_t)(x) & JPEG_STAT_CODEC_OVER_MASK) >> JPEG_STAT_CODEC_OVER_SHIFT) 689 690 /* 691 * RESTART_MARKER_ERROR (W1C) 692 * 693 * codec restart marker error interrupt 694 */ 695 #define JPEG_STAT_RESTART_MARKER_ERROR_MASK (0x2U) 696 #define JPEG_STAT_RESTART_MARKER_ERROR_SHIFT (1U) 697 #define JPEG_STAT_RESTART_MARKER_ERROR_SET(x) (((uint32_t)(x) << JPEG_STAT_RESTART_MARKER_ERROR_SHIFT) & JPEG_STAT_RESTART_MARKER_ERROR_MASK) 698 #define JPEG_STAT_RESTART_MARKER_ERROR_GET(x) (((uint32_t)(x) & JPEG_STAT_RESTART_MARKER_ERROR_MASK) >> JPEG_STAT_RESTART_MARKER_ERROR_SHIFT) 699 700 /* Bitfield definition for register: WIDTH */ 701 /* 702 * IMG (RW) 703 * 704 * Image Width (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) 705 */ 706 #define JPEG_WIDTH_IMG_MASK (0xFFFFU) 707 #define JPEG_WIDTH_IMG_SHIFT (0U) 708 #define JPEG_WIDTH_IMG_SET(x) (((uint32_t)(x) << JPEG_WIDTH_IMG_SHIFT) & JPEG_WIDTH_IMG_MASK) 709 #define JPEG_WIDTH_IMG_GET(x) (((uint32_t)(x) & JPEG_WIDTH_IMG_MASK) >> JPEG_WIDTH_IMG_SHIFT) 710 711 /* Bitfield definition for register: HEIGHT */ 712 /* 713 * IMG (RW) 714 * 715 * Image Height (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) 716 */ 717 #define JPEG_HEIGHT_IMG_MASK (0xFFFFU) 718 #define JPEG_HEIGHT_IMG_SHIFT (0U) 719 #define JPEG_HEIGHT_IMG_SET(x) (((uint32_t)(x) << JPEG_HEIGHT_IMG_SHIFT) & JPEG_HEIGHT_IMG_MASK) 720 #define JPEG_HEIGHT_IMG_GET(x) (((uint32_t)(x) & JPEG_HEIGHT_IMG_MASK) >> JPEG_HEIGHT_IMG_SHIFT) 721 722 /* Bitfield definition for register: BUFADDR */ 723 /* 724 * ADDR (RW) 725 * 726 * ADDR[31:28] denotes the buffer type: 727 * 0x2: Qmem 728 * 0x3: HuffEnc 729 * 0x4: HuffMin 730 * 0x5: HuffBase 731 * 0x6: HuffSymb 732 * ADDR[27:0] is the address inside the buffer 733 */ 734 #define JPEG_BUFADDR_ADDR_MASK (0xFFFFFFFFUL) 735 #define JPEG_BUFADDR_ADDR_SHIFT (0U) 736 #define JPEG_BUFADDR_ADDR_SET(x) (((uint32_t)(x) << JPEG_BUFADDR_ADDR_SHIFT) & JPEG_BUFADDR_ADDR_MASK) 737 #define JPEG_BUFADDR_ADDR_GET(x) (((uint32_t)(x) & JPEG_BUFADDR_ADDR_MASK) >> JPEG_BUFADDR_ADDR_SHIFT) 738 739 /* Bitfield definition for register: BUFDATA */ 740 /* 741 * DATA (RW) 742 * 743 * The data write-to/read-from buffer. 744 * The n-th address read will be actually the data written for n-1 th address, and the actual stored location is n-1 th address. 745 */ 746 #define JPEG_BUFDATA_DATA_MASK (0xFFFFFFFFUL) 747 #define JPEG_BUFDATA_DATA_SHIFT (0U) 748 #define JPEG_BUFDATA_DATA_SET(x) (((uint32_t)(x) << JPEG_BUFDATA_DATA_SHIFT) & JPEG_BUFDATA_DATA_MASK) 749 #define JPEG_BUFDATA_DATA_GET(x) (((uint32_t)(x) & JPEG_BUFDATA_DATA_MASK) >> JPEG_BUFDATA_DATA_SHIFT) 750 751 /* Bitfield definition for register: OUTDMACNT */ 752 /* 753 * VAL (RO) 754 * 755 * The out DMA counter 756 */ 757 #define JPEG_OUTDMACNT_VAL_MASK (0xFFFFFFFFUL) 758 #define JPEG_OUTDMACNT_VAL_SHIFT (0U) 759 #define JPEG_OUTDMACNT_VAL_GET(x) (((uint32_t)(x) & JPEG_OUTDMACNT_VAL_MASK) >> JPEG_OUTDMACNT_VAL_SHIFT) 760 761 /* Bitfield definition for register: CSC_COEF0 */ 762 /* 763 * YCBCR_MODE (RW) 764 * 765 * This bit changes the behavior when performing U/V converting. 766 * 0b - Converting YUV to RGB data 767 * 1b - Converting YCbCr to RGB data 768 */ 769 #define JPEG_CSC_COEF0_YCBCR_MODE_MASK (0x80000000UL) 770 #define JPEG_CSC_COEF0_YCBCR_MODE_SHIFT (31U) 771 #define JPEG_CSC_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_YCBCR_MODE_SHIFT) & JPEG_CSC_COEF0_YCBCR_MODE_MASK) 772 #define JPEG_CSC_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_YCBCR_MODE_MASK) >> JPEG_CSC_COEF0_YCBCR_MODE_SHIFT) 773 774 /* 775 * ENABLE (RW) 776 * 777 * Enable the CSC unit. 778 * 0b - The CSC is bypassed 779 * 1b - The CSC is enabled 780 */ 781 #define JPEG_CSC_COEF0_ENABLE_MASK (0x40000000UL) 782 #define JPEG_CSC_COEF0_ENABLE_SHIFT (30U) 783 #define JPEG_CSC_COEF0_ENABLE_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_ENABLE_SHIFT) & JPEG_CSC_COEF0_ENABLE_MASK) 784 #define JPEG_CSC_COEF0_ENABLE_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_ENABLE_MASK) >> JPEG_CSC_COEF0_ENABLE_SHIFT) 785 786 /* 787 * C0 (RW) 788 * 789 * Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) 790 */ 791 #define JPEG_CSC_COEF0_C0_MASK (0x1FFC0000UL) 792 #define JPEG_CSC_COEF0_C0_SHIFT (18U) 793 #define JPEG_CSC_COEF0_C0_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_C0_SHIFT) & JPEG_CSC_COEF0_C0_MASK) 794 #define JPEG_CSC_COEF0_C0_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_C0_MASK) >> JPEG_CSC_COEF0_C0_SHIFT) 795 796 /* 797 * UV_OFFSET (RW) 798 * 799 * Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. 800 * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). 801 */ 802 #define JPEG_CSC_COEF0_UV_OFFSET_MASK (0x3FE00UL) 803 #define JPEG_CSC_COEF0_UV_OFFSET_SHIFT (9U) 804 #define JPEG_CSC_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_UV_OFFSET_SHIFT) & JPEG_CSC_COEF0_UV_OFFSET_MASK) 805 #define JPEG_CSC_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_UV_OFFSET_MASK) >> JPEG_CSC_COEF0_UV_OFFSET_SHIFT) 806 807 /* 808 * Y_OFFSET (RW) 809 * 810 * Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is 811 * typically -16 (0x1F0). 812 */ 813 #define JPEG_CSC_COEF0_Y_OFFSET_MASK (0x1FFU) 814 #define JPEG_CSC_COEF0_Y_OFFSET_SHIFT (0U) 815 #define JPEG_CSC_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_Y_OFFSET_SHIFT) & JPEG_CSC_COEF0_Y_OFFSET_MASK) 816 #define JPEG_CSC_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_Y_OFFSET_MASK) >> JPEG_CSC_COEF0_Y_OFFSET_SHIFT) 817 818 /* Bitfield definition for register: CSC_COEF1 */ 819 /* 820 * C1 (RW) 821 * 822 * Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). 823 */ 824 #define JPEG_CSC_COEF1_C1_MASK (0x7FF0000UL) 825 #define JPEG_CSC_COEF1_C1_SHIFT (16U) 826 #define JPEG_CSC_COEF1_C1_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF1_C1_SHIFT) & JPEG_CSC_COEF1_C1_MASK) 827 #define JPEG_CSC_COEF1_C1_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF1_C1_MASK) >> JPEG_CSC_COEF1_C1_SHIFT) 828 829 /* 830 * C4 (RW) 831 * 832 * Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). 833 */ 834 #define JPEG_CSC_COEF1_C4_MASK (0x7FFU) 835 #define JPEG_CSC_COEF1_C4_SHIFT (0U) 836 #define JPEG_CSC_COEF1_C4_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF1_C4_SHIFT) & JPEG_CSC_COEF1_C4_MASK) 837 #define JPEG_CSC_COEF1_C4_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF1_C4_MASK) >> JPEG_CSC_COEF1_C4_SHIFT) 838 839 /* Bitfield definition for register: CSC_COEF2 */ 840 /* 841 * C2 (RW) 842 * 843 * Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). 844 */ 845 #define JPEG_CSC_COEF2_C2_MASK (0x7FF0000UL) 846 #define JPEG_CSC_COEF2_C2_SHIFT (16U) 847 #define JPEG_CSC_COEF2_C2_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF2_C2_SHIFT) & JPEG_CSC_COEF2_C2_MASK) 848 #define JPEG_CSC_COEF2_C2_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF2_C2_MASK) >> JPEG_CSC_COEF2_C2_SHIFT) 849 850 /* 851 * C3 (RW) 852 * 853 * Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). 854 */ 855 #define JPEG_CSC_COEF2_C3_MASK (0x7FFU) 856 #define JPEG_CSC_COEF2_C3_SHIFT (0U) 857 #define JPEG_CSC_COEF2_C3_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF2_C3_SHIFT) & JPEG_CSC_COEF2_C3_MASK) 858 #define JPEG_CSC_COEF2_C3_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF2_C3_MASK) >> JPEG_CSC_COEF2_C3_SHIFT) 859 860 /* Bitfield definition for register: RGB2YUV_COEF0 */ 861 /* 862 * YCBCR_MODE (RW) 863 * 864 * Asserted to use YCrCb mode. Must be assigned as 1. 865 */ 866 #define JPEG_RGB2YUV_COEF0_YCBCR_MODE_MASK (0x80000000UL) 867 #define JPEG_RGB2YUV_COEF0_YCBCR_MODE_SHIFT (31U) 868 #define JPEG_RGB2YUV_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_YCBCR_MODE_SHIFT) & JPEG_RGB2YUV_COEF0_YCBCR_MODE_MASK) 869 #define JPEG_RGB2YUV_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_YCBCR_MODE_MASK) >> JPEG_RGB2YUV_COEF0_YCBCR_MODE_SHIFT) 870 871 /* 872 * ENABLE (RW) 873 * 874 * Asserted to enable this RGB2YCbCr CSC stage 875 */ 876 #define JPEG_RGB2YUV_COEF0_ENABLE_MASK (0x40000000UL) 877 #define JPEG_RGB2YUV_COEF0_ENABLE_SHIFT (30U) 878 #define JPEG_RGB2YUV_COEF0_ENABLE_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_ENABLE_SHIFT) & JPEG_RGB2YUV_COEF0_ENABLE_MASK) 879 #define JPEG_RGB2YUV_COEF0_ENABLE_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_ENABLE_MASK) >> JPEG_RGB2YUV_COEF0_ENABLE_SHIFT) 880 881 /* 882 * C0 (RW) 883 * 884 * CSC parameters C0 885 */ 886 #define JPEG_RGB2YUV_COEF0_C0_MASK (0x1FFC0000UL) 887 #define JPEG_RGB2YUV_COEF0_C0_SHIFT (18U) 888 #define JPEG_RGB2YUV_COEF0_C0_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_C0_SHIFT) & JPEG_RGB2YUV_COEF0_C0_MASK) 889 #define JPEG_RGB2YUV_COEF0_C0_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_C0_MASK) >> JPEG_RGB2YUV_COEF0_C0_SHIFT) 890 891 /* 892 * UV_OFFSET (RW) 893 * 894 * CSC parameters UV_OFFSET 895 */ 896 #define JPEG_RGB2YUV_COEF0_UV_OFFSET_MASK (0x3FE00UL) 897 #define JPEG_RGB2YUV_COEF0_UV_OFFSET_SHIFT (9U) 898 #define JPEG_RGB2YUV_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_UV_OFFSET_SHIFT) & JPEG_RGB2YUV_COEF0_UV_OFFSET_MASK) 899 #define JPEG_RGB2YUV_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_UV_OFFSET_MASK) >> JPEG_RGB2YUV_COEF0_UV_OFFSET_SHIFT) 900 901 /* 902 * Y_OFFSET (RW) 903 * 904 * CSC parameters Y_OFFSET 905 */ 906 #define JPEG_RGB2YUV_COEF0_Y_OFFSET_MASK (0x1FFU) 907 #define JPEG_RGB2YUV_COEF0_Y_OFFSET_SHIFT (0U) 908 #define JPEG_RGB2YUV_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_Y_OFFSET_SHIFT) & JPEG_RGB2YUV_COEF0_Y_OFFSET_MASK) 909 #define JPEG_RGB2YUV_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_Y_OFFSET_MASK) >> JPEG_RGB2YUV_COEF0_Y_OFFSET_SHIFT) 910 911 /* Bitfield definition for register: RGB2YUV_COEF1 */ 912 /* 913 * C1 (RW) 914 * 915 * CSC parameters C1 916 */ 917 #define JPEG_RGB2YUV_COEF1_C1_MASK (0x7FF0000UL) 918 #define JPEG_RGB2YUV_COEF1_C1_SHIFT (16U) 919 #define JPEG_RGB2YUV_COEF1_C1_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF1_C1_SHIFT) & JPEG_RGB2YUV_COEF1_C1_MASK) 920 #define JPEG_RGB2YUV_COEF1_C1_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF1_C1_MASK) >> JPEG_RGB2YUV_COEF1_C1_SHIFT) 921 922 /* 923 * C4 (RW) 924 * 925 * CSC parameters C4 926 */ 927 #define JPEG_RGB2YUV_COEF1_C4_MASK (0x7FFU) 928 #define JPEG_RGB2YUV_COEF1_C4_SHIFT (0U) 929 #define JPEG_RGB2YUV_COEF1_C4_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF1_C4_SHIFT) & JPEG_RGB2YUV_COEF1_C4_MASK) 930 #define JPEG_RGB2YUV_COEF1_C4_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF1_C4_MASK) >> JPEG_RGB2YUV_COEF1_C4_SHIFT) 931 932 /* Bitfield definition for register: RGB2YUV_COEF2 */ 933 /* 934 * C2 (RW) 935 * 936 * CSC parameters C2 937 */ 938 #define JPEG_RGB2YUV_COEF2_C2_MASK (0x7FF0000UL) 939 #define JPEG_RGB2YUV_COEF2_C2_SHIFT (16U) 940 #define JPEG_RGB2YUV_COEF2_C2_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF2_C2_SHIFT) & JPEG_RGB2YUV_COEF2_C2_MASK) 941 #define JPEG_RGB2YUV_COEF2_C2_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF2_C2_MASK) >> JPEG_RGB2YUV_COEF2_C2_SHIFT) 942 943 /* 944 * C3 (RW) 945 * 946 * CSC parameters C3 947 */ 948 #define JPEG_RGB2YUV_COEF2_C3_MASK (0x7FFU) 949 #define JPEG_RGB2YUV_COEF2_C3_SHIFT (0U) 950 #define JPEG_RGB2YUV_COEF2_C3_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF2_C3_SHIFT) & JPEG_RGB2YUV_COEF2_C3_MASK) 951 #define JPEG_RGB2YUV_COEF2_C3_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF2_C3_MASK) >> JPEG_RGB2YUV_COEF2_C3_SHIFT) 952 953 /* Bitfield definition for register: RGB2YUV_COEF3 */ 954 /* 955 * C6 (RW) 956 * 957 * CSC parameters C6 958 */ 959 #define JPEG_RGB2YUV_COEF3_C6_MASK (0x7FF0000UL) 960 #define JPEG_RGB2YUV_COEF3_C6_SHIFT (16U) 961 #define JPEG_RGB2YUV_COEF3_C6_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF3_C6_SHIFT) & JPEG_RGB2YUV_COEF3_C6_MASK) 962 #define JPEG_RGB2YUV_COEF3_C6_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF3_C6_MASK) >> JPEG_RGB2YUV_COEF3_C6_SHIFT) 963 964 /* 965 * C5 (RW) 966 * 967 * CSC parameters C5 968 */ 969 #define JPEG_RGB2YUV_COEF3_C5_MASK (0x7FFU) 970 #define JPEG_RGB2YUV_COEF3_C5_SHIFT (0U) 971 #define JPEG_RGB2YUV_COEF3_C5_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF3_C5_SHIFT) & JPEG_RGB2YUV_COEF3_C5_MASK) 972 #define JPEG_RGB2YUV_COEF3_C5_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF3_C5_MASK) >> JPEG_RGB2YUV_COEF3_C5_SHIFT) 973 974 /* Bitfield definition for register: RGB2YUV_COEF4 */ 975 /* 976 * C8 (RW) 977 * 978 * CSC parameters C8 979 */ 980 #define JPEG_RGB2YUV_COEF4_C8_MASK (0x7FF0000UL) 981 #define JPEG_RGB2YUV_COEF4_C8_SHIFT (16U) 982 #define JPEG_RGB2YUV_COEF4_C8_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF4_C8_SHIFT) & JPEG_RGB2YUV_COEF4_C8_MASK) 983 #define JPEG_RGB2YUV_COEF4_C8_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF4_C8_MASK) >> JPEG_RGB2YUV_COEF4_C8_SHIFT) 984 985 /* 986 * C7 (RW) 987 * 988 * CSC parameters C7 989 */ 990 #define JPEG_RGB2YUV_COEF4_C7_MASK (0x7FFU) 991 #define JPEG_RGB2YUV_COEF4_C7_SHIFT (0U) 992 #define JPEG_RGB2YUV_COEF4_C7_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF4_C7_SHIFT) & JPEG_RGB2YUV_COEF4_C7_MASK) 993 #define JPEG_RGB2YUV_COEF4_C7_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF4_C7_MASK) >> JPEG_RGB2YUV_COEF4_C7_SHIFT) 994 995 /* Bitfield definition for register: IMGREG1 */ 996 /* 997 * RE (RW) 998 * 999 * Encoder Use only. 1000 * Asseted to enable the Restart Marker processing. A Restart Marker is inserted in the outputted ECS (Entropy Coded Segment) every NRST+1 MCUs 1001 */ 1002 #define JPEG_IMGREG1_RE_MASK (0x4U) 1003 #define JPEG_IMGREG1_RE_SHIFT (2U) 1004 #define JPEG_IMGREG1_RE_SET(x) (((uint32_t)(x) << JPEG_IMGREG1_RE_SHIFT) & JPEG_IMGREG1_RE_MASK) 1005 #define JPEG_IMGREG1_RE_GET(x) (((uint32_t)(x) & JPEG_IMGREG1_RE_MASK) >> JPEG_IMGREG1_RE_SHIFT) 1006 1007 /* 1008 * NCOL (RW) 1009 * 1010 * Ncol is the number of color components in the image data to process minus 1. For example, for a grayscale image Ncol=0, for an RGB image, Ncol=2 1011 */ 1012 #define JPEG_IMGREG1_NCOL_MASK (0x3U) 1013 #define JPEG_IMGREG1_NCOL_SHIFT (0U) 1014 #define JPEG_IMGREG1_NCOL_SET(x) (((uint32_t)(x) << JPEG_IMGREG1_NCOL_SHIFT) & JPEG_IMGREG1_NCOL_MASK) 1015 #define JPEG_IMGREG1_NCOL_GET(x) (((uint32_t)(x) & JPEG_IMGREG1_NCOL_MASK) >> JPEG_IMGREG1_NCOL_SHIFT) 1016 1017 /* Bitfield definition for register: IMGREG2 */ 1018 /* 1019 * NMCU (RW) 1020 * 1021 * Encoder Use only. 1022 * The number of NMCU to be generated in encoder mode 1023 */ 1024 #define JPEG_IMGREG2_NMCU_MASK (0x3FFFFFFUL) 1025 #define JPEG_IMGREG2_NMCU_SHIFT (0U) 1026 #define JPEG_IMGREG2_NMCU_SET(x) (((uint32_t)(x) << JPEG_IMGREG2_NMCU_SHIFT) & JPEG_IMGREG2_NMCU_MASK) 1027 #define JPEG_IMGREG2_NMCU_GET(x) (((uint32_t)(x) & JPEG_IMGREG2_NMCU_MASK) >> JPEG_IMGREG2_NMCU_SHIFT) 1028 1029 /* Bitfield definition for register: IMGREG3 */ 1030 /* 1031 * NRST (RW) 1032 * 1033 * Encoder use only. 1034 * It is the number of MCUs between two Restart Markers (if enabled) minus 1. The content of this register is ignored if the Re bit inregister 1 is not set. 1035 */ 1036 #define JPEG_IMGREG3_NRST_MASK (0xFFFFU) 1037 #define JPEG_IMGREG3_NRST_SHIFT (0U) 1038 #define JPEG_IMGREG3_NRST_SET(x) (((uint32_t)(x) << JPEG_IMGREG3_NRST_SHIFT) & JPEG_IMGREG3_NRST_MASK) 1039 #define JPEG_IMGREG3_NRST_GET(x) (((uint32_t)(x) & JPEG_IMGREG3_NRST_MASK) >> JPEG_IMGREG3_NRST_SHIFT) 1040 1041 /* Bitfield definition for register array: IMGREG */ 1042 /* 1043 * NBLOCK (RW) 1044 * 1045 * Encoder use only. 1046 * The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. 1047 */ 1048 #define JPEG_IMGREG_NBLOCK_MASK (0xF0U) 1049 #define JPEG_IMGREG_NBLOCK_SHIFT (4U) 1050 #define JPEG_IMGREG_NBLOCK_SET(x) (((uint32_t)(x) << JPEG_IMGREG_NBLOCK_SHIFT) & JPEG_IMGREG_NBLOCK_MASK) 1051 #define JPEG_IMGREG_NBLOCK_GET(x) (((uint32_t)(x) & JPEG_IMGREG_NBLOCK_MASK) >> JPEG_IMGREG_NBLOCK_SHIFT) 1052 1053 /* 1054 * QT (RW) 1055 * 1056 * Encoder use only. 1057 * The selection of the quantization table. 1058 */ 1059 #define JPEG_IMGREG_QT_MASK (0xCU) 1060 #define JPEG_IMGREG_QT_SHIFT (2U) 1061 #define JPEG_IMGREG_QT_SET(x) (((uint32_t)(x) << JPEG_IMGREG_QT_SHIFT) & JPEG_IMGREG_QT_MASK) 1062 #define JPEG_IMGREG_QT_GET(x) (((uint32_t)(x) & JPEG_IMGREG_QT_MASK) >> JPEG_IMGREG_QT_SHIFT) 1063 1064 /* 1065 * HA (RW) 1066 * 1067 * Encoder use only. 1068 * The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. 1069 */ 1070 #define JPEG_IMGREG_HA_MASK (0x2U) 1071 #define JPEG_IMGREG_HA_SHIFT (1U) 1072 #define JPEG_IMGREG_HA_SET(x) (((uint32_t)(x) << JPEG_IMGREG_HA_SHIFT) & JPEG_IMGREG_HA_MASK) 1073 #define JPEG_IMGREG_HA_GET(x) (((uint32_t)(x) & JPEG_IMGREG_HA_MASK) >> JPEG_IMGREG_HA_SHIFT) 1074 1075 /* 1076 * HD (RW) 1077 * 1078 * Encoder use only. 1079 * The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. 1080 */ 1081 #define JPEG_IMGREG_HD_MASK (0x1U) 1082 #define JPEG_IMGREG_HD_SHIFT (0U) 1083 #define JPEG_IMGREG_HD_SET(x) (((uint32_t)(x) << JPEG_IMGREG_HD_SHIFT) & JPEG_IMGREG_HD_MASK) 1084 #define JPEG_IMGREG_HD_GET(x) (((uint32_t)(x) & JPEG_IMGREG_HD_MASK) >> JPEG_IMGREG_HD_SHIFT) 1085 1086 1087 1088 /* IMGREG register group index macro definition */ 1089 #define JPEG_IMGREG_REG40 (0UL) 1090 #define JPEG_IMGREG_REG41 (1UL) 1091 #define JPEG_IMGREG_REG42 (2UL) 1092 #define JPEG_IMGREG_REG43 (3UL) 1093 1094 1095 #endif /* HPM_JPEG_H */ 1096