1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_FEMC_H 10 #define HPM_FEMC_H 11 12 typedef struct { 13 __RW uint32_t CTRL; /* 0x0: Control Register */ 14 __RW uint32_t IOCTRL; /* 0x4: IO Mux Control Register */ 15 __RW uint32_t BMW0; /* 0x8: Bus (AXI) Weight Control Register 0 */ 16 __RW uint32_t BMW1; /* 0xC: Bus (AXI) Weight Control Register 1 */ 17 __RW uint32_t BR[7]; /* 0x10 - 0x28: Base Register 0 (for SDRAM CS0 device) */ 18 __R uint8_t RESERVED0[12]; /* 0x2C - 0x37: Reserved */ 19 __RW uint32_t INTEN; /* 0x38: Interrupt Enable Register */ 20 __W uint32_t INTR; /* 0x3C: Interrupt Status Register */ 21 __RW uint32_t SDRCTRL0; /* 0x40: SDRAM Control Register 0 */ 22 __RW uint32_t SDRCTRL1; /* 0x44: SDRAM Control Register 1 */ 23 __RW uint32_t SDRCTRL2; /* 0x48: SDRAM Control Register 2 */ 24 __RW uint32_t SDRCTRL3; /* 0x4C: SDRAM Control Register 3 */ 25 __R uint8_t RESERVED1[32]; /* 0x50 - 0x6F: Reserved */ 26 __RW uint32_t SRCTRL0; /* 0x70: SRAM control register 0 */ 27 __RW uint32_t SRCTRL1; /* 0x74: SRAM control register 1 */ 28 __R uint8_t RESERVED2[24]; /* 0x78 - 0x8F: Reserved */ 29 __RW uint32_t SADDR; /* 0x90: IP Command Control Register 0 */ 30 __RW uint32_t DATSZ; /* 0x94: IP Command Control Register 1 */ 31 __RW uint32_t BYTEMSK; /* 0x98: IP Command Control Register 2 */ 32 __RW uint32_t IPCMD; /* 0x9C: IP Command Register */ 33 __RW uint32_t IPTX; /* 0xA0: TX DATA Register */ 34 __R uint8_t RESERVED3[12]; /* 0xA4 - 0xAF: Reserved */ 35 __RW uint32_t IPRX; /* 0xB0: RX DATA Register */ 36 __R uint8_t RESERVED4[12]; /* 0xB4 - 0xBF: Reserved */ 37 __R uint32_t STAT0; /* 0xC0: Status Register 0 */ 38 __R uint8_t RESERVED5[140]; /* 0xC4 - 0x14F: Reserved */ 39 __RW uint32_t DLYCFG; /* 0x150: Delay Line Config Register */ 40 } FEMC_Type; 41 42 43 /* Bitfield definition for register: CTRL */ 44 /* 45 * BTO (RW) 46 * 47 * Bus timeout cycles 48 * AXI Bus timeout cycle is as following (255*(2^BTO)): 49 * 00000b - 255*1 50 * 00001-11110b - 255*2 - 255*2^30 51 * 11111b - 255*2^31 52 */ 53 #define FEMC_CTRL_BTO_MASK (0x1F000000UL) 54 #define FEMC_CTRL_BTO_SHIFT (24U) 55 #define FEMC_CTRL_BTO_SET(x) (((uint32_t)(x) << FEMC_CTRL_BTO_SHIFT) & FEMC_CTRL_BTO_MASK) 56 #define FEMC_CTRL_BTO_GET(x) (((uint32_t)(x) & FEMC_CTRL_BTO_MASK) >> FEMC_CTRL_BTO_SHIFT) 57 58 /* 59 * CTO (RW) 60 * 61 * Command Execution timeout cycles 62 * When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is 63 * generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is 64 * CTO*1024 cycle. 65 */ 66 #define FEMC_CTRL_CTO_MASK (0xFF0000UL) 67 #define FEMC_CTRL_CTO_SHIFT (16U) 68 #define FEMC_CTRL_CTO_SET(x) (((uint32_t)(x) << FEMC_CTRL_CTO_SHIFT) & FEMC_CTRL_CTO_MASK) 69 #define FEMC_CTRL_CTO_GET(x) (((uint32_t)(x) & FEMC_CTRL_CTO_MASK) >> FEMC_CTRL_CTO_SHIFT) 70 71 /* 72 * DQS (RW) 73 * 74 * DQS (read strobe) mode 75 * 0b - Dummy read strobe loopbacked internally 76 * 1b - Dummy read strobe loopbacked from DQS pad 77 */ 78 #define FEMC_CTRL_DQS_MASK (0x4U) 79 #define FEMC_CTRL_DQS_SHIFT (2U) 80 #define FEMC_CTRL_DQS_SET(x) (((uint32_t)(x) << FEMC_CTRL_DQS_SHIFT) & FEMC_CTRL_DQS_MASK) 81 #define FEMC_CTRL_DQS_GET(x) (((uint32_t)(x) & FEMC_CTRL_DQS_MASK) >> FEMC_CTRL_DQS_SHIFT) 82 83 /* 84 * DIS (RW) 85 * 86 * Module Disable 87 * 0b - Module enabled 88 * 1b - Module disabled 89 */ 90 #define FEMC_CTRL_DIS_MASK (0x2U) 91 #define FEMC_CTRL_DIS_SHIFT (1U) 92 #define FEMC_CTRL_DIS_SET(x) (((uint32_t)(x) << FEMC_CTRL_DIS_SHIFT) & FEMC_CTRL_DIS_MASK) 93 #define FEMC_CTRL_DIS_GET(x) (((uint32_t)(x) & FEMC_CTRL_DIS_MASK) >> FEMC_CTRL_DIS_SHIFT) 94 95 /* 96 * RST (RW) 97 * 98 * Software Reset 99 * Reset all internal logic in SEMC except configuration register 100 */ 101 #define FEMC_CTRL_RST_MASK (0x1U) 102 #define FEMC_CTRL_RST_SHIFT (0U) 103 #define FEMC_CTRL_RST_SET(x) (((uint32_t)(x) << FEMC_CTRL_RST_SHIFT) & FEMC_CTRL_RST_MASK) 104 #define FEMC_CTRL_RST_GET(x) (((uint32_t)(x) & FEMC_CTRL_RST_MASK) >> FEMC_CTRL_RST_SHIFT) 105 106 /* Bitfield definition for register: IOCTRL */ 107 /* 108 * IO_CSX (RW) 109 * 110 * IO_CSX output selection 111 * 0001b - SDRAM CS1 112 * 0110b - SRAM CE# 113 */ 114 #define FEMC_IOCTRL_IO_CSX_MASK (0xF0U) 115 #define FEMC_IOCTRL_IO_CSX_SHIFT (4U) 116 #define FEMC_IOCTRL_IO_CSX_SET(x) (((uint32_t)(x) << FEMC_IOCTRL_IO_CSX_SHIFT) & FEMC_IOCTRL_IO_CSX_MASK) 117 #define FEMC_IOCTRL_IO_CSX_GET(x) (((uint32_t)(x) & FEMC_IOCTRL_IO_CSX_MASK) >> FEMC_IOCTRL_IO_CSX_SHIFT) 118 119 /* Bitfield definition for register: BMW0 */ 120 /* 121 * RWS (RW) 122 * 123 * Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is 124 * same as current executing command with read/write operation switch. 125 */ 126 #define FEMC_BMW0_RWS_MASK (0xFF0000UL) 127 #define FEMC_BMW0_RWS_SHIFT (16U) 128 #define FEMC_BMW0_RWS_SET(x) (((uint32_t)(x) << FEMC_BMW0_RWS_SHIFT) & FEMC_BMW0_RWS_MASK) 129 #define FEMC_BMW0_RWS_GET(x) (((uint32_t)(x) & FEMC_BMW0_RWS_MASK) >> FEMC_BMW0_RWS_SHIFT) 130 131 /* 132 * SH (RW) 133 * 134 * Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is 135 * same as current executing command without read/write operation switch. 136 */ 137 #define FEMC_BMW0_SH_MASK (0xFF00U) 138 #define FEMC_BMW0_SH_SHIFT (8U) 139 #define FEMC_BMW0_SH_SET(x) (((uint32_t)(x) << FEMC_BMW0_SH_SHIFT) & FEMC_BMW0_SH_MASK) 140 #define FEMC_BMW0_SH_GET(x) (((uint32_t)(x) & FEMC_BMW0_SH_MASK) >> FEMC_BMW0_SH_SHIFT) 141 142 /* 143 * AGE (RW) 144 * 145 * Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is 146 * multiplied by WAGE to get weight score. 147 */ 148 #define FEMC_BMW0_AGE_MASK (0xF0U) 149 #define FEMC_BMW0_AGE_SHIFT (4U) 150 #define FEMC_BMW0_AGE_SET(x) (((uint32_t)(x) << FEMC_BMW0_AGE_SHIFT) & FEMC_BMW0_AGE_MASK) 151 #define FEMC_BMW0_AGE_GET(x) (((uint32_t)(x) & FEMC_BMW0_AGE_MASK) >> FEMC_BMW0_AGE_SHIFT) 152 153 /* 154 * QOS (RW) 155 * 156 * Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator 157 * for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS 158 * is multiplied by WQOS to get weight score. 159 */ 160 #define FEMC_BMW0_QOS_MASK (0xFU) 161 #define FEMC_BMW0_QOS_SHIFT (0U) 162 #define FEMC_BMW0_QOS_SET(x) (((uint32_t)(x) << FEMC_BMW0_QOS_SHIFT) & FEMC_BMW0_QOS_MASK) 163 #define FEMC_BMW0_QOS_GET(x) (((uint32_t)(x) & FEMC_BMW0_QOS_MASK) >> FEMC_BMW0_QOS_SHIFT) 164 165 /* Bitfield definition for register: BMW1 */ 166 /* 167 * BR (RW) 168 * 169 * Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current 170 * executing command. 171 */ 172 #define FEMC_BMW1_BR_MASK (0xFF000000UL) 173 #define FEMC_BMW1_BR_SHIFT (24U) 174 #define FEMC_BMW1_BR_SET(x) (((uint32_t)(x) << FEMC_BMW1_BR_SHIFT) & FEMC_BMW1_BR_MASK) 175 #define FEMC_BMW1_BR_GET(x) (((uint32_t)(x) & FEMC_BMW1_BR_MASK) >> FEMC_BMW1_BR_SHIFT) 176 177 /* 178 * RWS (RW) 179 * 180 * Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is 181 * same as current executing command with read/write operation switch. 182 */ 183 #define FEMC_BMW1_RWS_MASK (0xFF0000UL) 184 #define FEMC_BMW1_RWS_SHIFT (16U) 185 #define FEMC_BMW1_RWS_SET(x) (((uint32_t)(x) << FEMC_BMW1_RWS_SHIFT) & FEMC_BMW1_RWS_MASK) 186 #define FEMC_BMW1_RWS_GET(x) (((uint32_t)(x) & FEMC_BMW1_RWS_MASK) >> FEMC_BMW1_RWS_SHIFT) 187 188 /* 189 * PH (RW) 190 * 191 * Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is 192 * same as current executing command without read/write operation switch. 193 */ 194 #define FEMC_BMW1_PH_MASK (0xFF00U) 195 #define FEMC_BMW1_PH_SHIFT (8U) 196 #define FEMC_BMW1_PH_SET(x) (((uint32_t)(x) << FEMC_BMW1_PH_SHIFT) & FEMC_BMW1_PH_MASK) 197 #define FEMC_BMW1_PH_GET(x) (((uint32_t)(x) & FEMC_BMW1_PH_MASK) >> FEMC_BMW1_PH_SHIFT) 198 199 /* 200 * AGE (RW) 201 * 202 * Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is 203 * multiplied by WAGE to get weight score. 204 */ 205 #define FEMC_BMW1_AGE_MASK (0xF0U) 206 #define FEMC_BMW1_AGE_SHIFT (4U) 207 #define FEMC_BMW1_AGE_SET(x) (((uint32_t)(x) << FEMC_BMW1_AGE_SHIFT) & FEMC_BMW1_AGE_MASK) 208 #define FEMC_BMW1_AGE_GET(x) (((uint32_t)(x) & FEMC_BMW1_AGE_MASK) >> FEMC_BMW1_AGE_SHIFT) 209 210 /* 211 * QOS (RW) 212 * 213 * Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator 214 * for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS 215 * is multiplied by WQOS to get weight score. 216 */ 217 #define FEMC_BMW1_QOS_MASK (0xFU) 218 #define FEMC_BMW1_QOS_SHIFT (0U) 219 #define FEMC_BMW1_QOS_SET(x) (((uint32_t)(x) << FEMC_BMW1_QOS_SHIFT) & FEMC_BMW1_QOS_MASK) 220 #define FEMC_BMW1_QOS_GET(x) (((uint32_t)(x) & FEMC_BMW1_QOS_MASK) >> FEMC_BMW1_QOS_SHIFT) 221 222 /* Bitfield definition for register array: BR */ 223 /* 224 * BASE (RW) 225 * 226 * Base Address 227 * This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low 228 * position 12 bits are all zero. 229 */ 230 #define FEMC_BR_BASE_MASK (0xFFFFF000UL) 231 #define FEMC_BR_BASE_SHIFT (12U) 232 #define FEMC_BR_BASE_SET(x) (((uint32_t)(x) << FEMC_BR_BASE_SHIFT) & FEMC_BR_BASE_MASK) 233 #define FEMC_BR_BASE_GET(x) (((uint32_t)(x) & FEMC_BR_BASE_MASK) >> FEMC_BR_BASE_SHIFT) 234 235 /* 236 * SIZE (RW) 237 * 238 * Memory size 239 * 00000b - 4KB 240 * 00001b - 8KB 241 * 00010b - 16KB 242 * 00011b - 32KB 243 * 00100b - 64KB 244 * 00101b - 128KB 245 * 00110b - 256KB 246 * 00111b - 512KB 247 * 01000b - 1MB 248 * 01001b - 2MB 249 * 01010b - 4MB 250 * 01011b - 8MB 251 * 01100b - 16MB 252 * 01101b - 32MB 253 * 01110b - 64MB 254 * 01111b - 128MB 255 * 10000b - 256MB 256 * 10001b - 512MB 257 * 10010b - 1GB 258 * 10011b - 2GB 259 * 10100-11111b - 4GB 260 */ 261 #define FEMC_BR_SIZE_MASK (0x3EU) 262 #define FEMC_BR_SIZE_SHIFT (1U) 263 #define FEMC_BR_SIZE_SET(x) (((uint32_t)(x) << FEMC_BR_SIZE_SHIFT) & FEMC_BR_SIZE_MASK) 264 #define FEMC_BR_SIZE_GET(x) (((uint32_t)(x) & FEMC_BR_SIZE_MASK) >> FEMC_BR_SIZE_SHIFT) 265 266 /* 267 * VLD (RW) 268 * 269 * Valid 270 */ 271 #define FEMC_BR_VLD_MASK (0x1U) 272 #define FEMC_BR_VLD_SHIFT (0U) 273 #define FEMC_BR_VLD_SET(x) (((uint32_t)(x) << FEMC_BR_VLD_SHIFT) & FEMC_BR_VLD_MASK) 274 #define FEMC_BR_VLD_GET(x) (((uint32_t)(x) & FEMC_BR_VLD_MASK) >> FEMC_BR_VLD_SHIFT) 275 276 /* Bitfield definition for register: INTEN */ 277 /* 278 * AXIBUSERR (RW) 279 * 280 * AXI BUS error interrupt enable 281 * 0b - Interrupt is disabled 282 * 1b - Interrupt is enabled 283 */ 284 #define FEMC_INTEN_AXIBUSERR_MASK (0x8U) 285 #define FEMC_INTEN_AXIBUSERR_SHIFT (3U) 286 #define FEMC_INTEN_AXIBUSERR_SET(x) (((uint32_t)(x) << FEMC_INTEN_AXIBUSERR_SHIFT) & FEMC_INTEN_AXIBUSERR_MASK) 287 #define FEMC_INTEN_AXIBUSERR_GET(x) (((uint32_t)(x) & FEMC_INTEN_AXIBUSERR_MASK) >> FEMC_INTEN_AXIBUSERR_SHIFT) 288 289 /* 290 * AXICMDERR (RW) 291 * 292 * AXI command error interrupt enable 293 * 0b - Interrupt is disabled 294 * 1b - Interrupt is enabled 295 */ 296 #define FEMC_INTEN_AXICMDERR_MASK (0x4U) 297 #define FEMC_INTEN_AXICMDERR_SHIFT (2U) 298 #define FEMC_INTEN_AXICMDERR_SET(x) (((uint32_t)(x) << FEMC_INTEN_AXICMDERR_SHIFT) & FEMC_INTEN_AXICMDERR_MASK) 299 #define FEMC_INTEN_AXICMDERR_GET(x) (((uint32_t)(x) & FEMC_INTEN_AXICMDERR_MASK) >> FEMC_INTEN_AXICMDERR_SHIFT) 300 301 /* 302 * IPCMDERR (RW) 303 * 304 * IP command error interrupt enable 305 * 0b - Interrupt is disabled 306 * 1b - Interrupt is enabled 307 */ 308 #define FEMC_INTEN_IPCMDERR_MASK (0x2U) 309 #define FEMC_INTEN_IPCMDERR_SHIFT (1U) 310 #define FEMC_INTEN_IPCMDERR_SET(x) (((uint32_t)(x) << FEMC_INTEN_IPCMDERR_SHIFT) & FEMC_INTEN_IPCMDERR_MASK) 311 #define FEMC_INTEN_IPCMDERR_GET(x) (((uint32_t)(x) & FEMC_INTEN_IPCMDERR_MASK) >> FEMC_INTEN_IPCMDERR_SHIFT) 312 313 /* 314 * IPCMDDONE (RW) 315 * 316 * IP command done interrupt enable 317 * 0b - Interrupt is disabled 318 * 1b - Interrupt is enabled 319 */ 320 #define FEMC_INTEN_IPCMDDONE_MASK (0x1U) 321 #define FEMC_INTEN_IPCMDDONE_SHIFT (0U) 322 #define FEMC_INTEN_IPCMDDONE_SET(x) (((uint32_t)(x) << FEMC_INTEN_IPCMDDONE_SHIFT) & FEMC_INTEN_IPCMDDONE_MASK) 323 #define FEMC_INTEN_IPCMDDONE_GET(x) (((uint32_t)(x) & FEMC_INTEN_IPCMDDONE_MASK) >> FEMC_INTEN_IPCMDDONE_SHIFT) 324 325 /* Bitfield definition for register: INTR */ 326 /* 327 * AXIBUSERR (W1C) 328 * 329 * AXI bus error interrupt 330 * AXI Bus error interrupt is generated in following cases: 331 * • AXI address is invalid 332 * • AXI 8-bit or 16-bit WRAP write/read 333 */ 334 #define FEMC_INTR_AXIBUSERR_MASK (0x8U) 335 #define FEMC_INTR_AXIBUSERR_SHIFT (3U) 336 #define FEMC_INTR_AXIBUSERR_SET(x) (((uint32_t)(x) << FEMC_INTR_AXIBUSERR_SHIFT) & FEMC_INTR_AXIBUSERR_MASK) 337 #define FEMC_INTR_AXIBUSERR_GET(x) (((uint32_t)(x) & FEMC_INTR_AXIBUSERR_MASK) >> FEMC_INTR_AXIBUSERR_SHIFT) 338 339 /* 340 * AXICMDERR (W1C) 341 * 342 * AXI command error interrupt 343 * AXI command error interrupt is generated when AXI command execution timeout. 344 */ 345 #define FEMC_INTR_AXICMDERR_MASK (0x4U) 346 #define FEMC_INTR_AXICMDERR_SHIFT (2U) 347 #define FEMC_INTR_AXICMDERR_SET(x) (((uint32_t)(x) << FEMC_INTR_AXICMDERR_SHIFT) & FEMC_INTR_AXICMDERR_MASK) 348 #define FEMC_INTR_AXICMDERR_GET(x) (((uint32_t)(x) & FEMC_INTR_AXICMDERR_MASK) >> FEMC_INTR_AXICMDERR_SHIFT) 349 350 /* 351 * IPCMDERR (W1C) 352 * 353 * IP command error done interrupt 354 * IP command error interrupt is generated in following case: 355 * • IP Command Address target invalid device space 356 * • IP Command Code unsupported 357 * • IP Command triggered when previous command 358 */ 359 #define FEMC_INTR_IPCMDERR_MASK (0x2U) 360 #define FEMC_INTR_IPCMDERR_SHIFT (1U) 361 #define FEMC_INTR_IPCMDERR_SET(x) (((uint32_t)(x) << FEMC_INTR_IPCMDERR_SHIFT) & FEMC_INTR_IPCMDERR_MASK) 362 #define FEMC_INTR_IPCMDERR_GET(x) (((uint32_t)(x) & FEMC_INTR_IPCMDERR_MASK) >> FEMC_INTR_IPCMDERR_SHIFT) 363 364 /* 365 * IPCMDDONE (W1C) 366 * 367 * IP command normal done interrupt 368 */ 369 #define FEMC_INTR_IPCMDDONE_MASK (0x1U) 370 #define FEMC_INTR_IPCMDDONE_SHIFT (0U) 371 #define FEMC_INTR_IPCMDDONE_SET(x) (((uint32_t)(x) << FEMC_INTR_IPCMDDONE_SHIFT) & FEMC_INTR_IPCMDDONE_MASK) 372 #define FEMC_INTR_IPCMDDONE_GET(x) (((uint32_t)(x) & FEMC_INTR_IPCMDDONE_MASK) >> FEMC_INTR_IPCMDDONE_SHIFT) 373 374 /* Bitfield definition for register: SDRCTRL0 */ 375 /* 376 * BANK2 (RW) 377 * 378 * 2 Bank selection bit 379 * 0b - SDRAM device has 4 banks. 380 * 1b - SDRAM device has 2 banks. 381 */ 382 #define FEMC_SDRCTRL0_BANK2_MASK (0x4000U) 383 #define FEMC_SDRCTRL0_BANK2_SHIFT (14U) 384 #define FEMC_SDRCTRL0_BANK2_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_BANK2_SHIFT) & FEMC_SDRCTRL0_BANK2_MASK) 385 #define FEMC_SDRCTRL0_BANK2_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_BANK2_MASK) >> FEMC_SDRCTRL0_BANK2_SHIFT) 386 387 /* 388 * CAS (RW) 389 * 390 * CAS Latency 391 * 00b - 1 392 * 01b - 1 393 * 10b - 2 394 * 11b - 3 395 */ 396 #define FEMC_SDRCTRL0_CAS_MASK (0xC00U) 397 #define FEMC_SDRCTRL0_CAS_SHIFT (10U) 398 #define FEMC_SDRCTRL0_CAS_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_CAS_SHIFT) & FEMC_SDRCTRL0_CAS_MASK) 399 #define FEMC_SDRCTRL0_CAS_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_CAS_MASK) >> FEMC_SDRCTRL0_CAS_SHIFT) 400 401 /* 402 * COL (RW) 403 * 404 * Column address bit number 405 * 00b - 12 bit 406 * 01b - 11 bit 407 * 10b - 10 bit 408 * 11b - 9 bit 409 */ 410 #define FEMC_SDRCTRL0_COL_MASK (0x300U) 411 #define FEMC_SDRCTRL0_COL_SHIFT (8U) 412 #define FEMC_SDRCTRL0_COL_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_COL_SHIFT) & FEMC_SDRCTRL0_COL_MASK) 413 #define FEMC_SDRCTRL0_COL_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_COL_MASK) >> FEMC_SDRCTRL0_COL_SHIFT) 414 415 /* 416 * COL8 (RW) 417 * 418 * Column 8 selection bit 419 * 0b - Column address bit number is decided by COL field. 420 * 1b - Column address bit number is 8. COL field is ignored. 421 */ 422 #define FEMC_SDRCTRL0_COL8_MASK (0x80U) 423 #define FEMC_SDRCTRL0_COL8_SHIFT (7U) 424 #define FEMC_SDRCTRL0_COL8_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_COL8_SHIFT) & FEMC_SDRCTRL0_COL8_MASK) 425 #define FEMC_SDRCTRL0_COL8_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_COL8_MASK) >> FEMC_SDRCTRL0_COL8_SHIFT) 426 427 /* 428 * BURSTLEN (RW) 429 * 430 * Burst Length 431 * 000b - 1 432 * 001b - 2 433 * 010b - 4 434 * 011b - 8 435 * 100b - 8 436 * 101b - 8 437 * 110b - 8 438 * 111b - 8 439 */ 440 #define FEMC_SDRCTRL0_BURSTLEN_MASK (0x70U) 441 #define FEMC_SDRCTRL0_BURSTLEN_SHIFT (4U) 442 #define FEMC_SDRCTRL0_BURSTLEN_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_BURSTLEN_SHIFT) & FEMC_SDRCTRL0_BURSTLEN_MASK) 443 #define FEMC_SDRCTRL0_BURSTLEN_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_BURSTLEN_MASK) >> FEMC_SDRCTRL0_BURSTLEN_SHIFT) 444 445 /* 446 * HIGHBAND (RW) 447 * 448 * high band select 449 * 0: use data[15:0] for 16bit SDRAM; 450 * 1: use data[31:16] for 16bit SDRAM; 451 * only used when Port Size is 16bit(PORTSZ=01b) 452 */ 453 #define FEMC_SDRCTRL0_HIGHBAND_MASK (0x8U) 454 #define FEMC_SDRCTRL0_HIGHBAND_SHIFT (3U) 455 #define FEMC_SDRCTRL0_HIGHBAND_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_HIGHBAND_SHIFT) & FEMC_SDRCTRL0_HIGHBAND_MASK) 456 #define FEMC_SDRCTRL0_HIGHBAND_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_HIGHBAND_MASK) >> FEMC_SDRCTRL0_HIGHBAND_SHIFT) 457 458 /* 459 * PORTSZ (RW) 460 * 461 * Port Size 462 * 00b - 8bit 463 * 01b - 16bit 464 * 10b - 32bit 465 */ 466 #define FEMC_SDRCTRL0_PORTSZ_MASK (0x3U) 467 #define FEMC_SDRCTRL0_PORTSZ_SHIFT (0U) 468 #define FEMC_SDRCTRL0_PORTSZ_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_PORTSZ_SHIFT) & FEMC_SDRCTRL0_PORTSZ_MASK) 469 #define FEMC_SDRCTRL0_PORTSZ_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_PORTSZ_MASK) >> FEMC_SDRCTRL0_PORTSZ_SHIFT) 470 471 /* Bitfield definition for register: SDRCTRL1 */ 472 /* 473 * ACT2PRE (RW) 474 * 475 * ACT to Precharge minimum time 476 * It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. 477 */ 478 #define FEMC_SDRCTRL1_ACT2PRE_MASK (0xF00000UL) 479 #define FEMC_SDRCTRL1_ACT2PRE_SHIFT (20U) 480 #define FEMC_SDRCTRL1_ACT2PRE_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_ACT2PRE_SHIFT) & FEMC_SDRCTRL1_ACT2PRE_MASK) 481 #define FEMC_SDRCTRL1_ACT2PRE_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_ACT2PRE_MASK) >> FEMC_SDRCTRL1_ACT2PRE_SHIFT) 482 483 /* 484 * CKEOFF (RW) 485 * 486 * CKE OFF minimum time 487 * It is promised clock suspend last at leat CKEOFF+1 clock cycles. 488 */ 489 #define FEMC_SDRCTRL1_CKEOFF_MASK (0xF0000UL) 490 #define FEMC_SDRCTRL1_CKEOFF_SHIFT (16U) 491 #define FEMC_SDRCTRL1_CKEOFF_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_CKEOFF_SHIFT) & FEMC_SDRCTRL1_CKEOFF_MASK) 492 #define FEMC_SDRCTRL1_CKEOFF_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_CKEOFF_MASK) >> FEMC_SDRCTRL1_CKEOFF_SHIFT) 493 494 /* 495 * WRC (RW) 496 * 497 * Write recovery time 498 * It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. 499 */ 500 #define FEMC_SDRCTRL1_WRC_MASK (0xE000U) 501 #define FEMC_SDRCTRL1_WRC_SHIFT (13U) 502 #define FEMC_SDRCTRL1_WRC_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_WRC_SHIFT) & FEMC_SDRCTRL1_WRC_MASK) 503 #define FEMC_SDRCTRL1_WRC_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_WRC_MASK) >> FEMC_SDRCTRL1_WRC_SHIFT) 504 505 /* 506 * RFRC (RW) 507 * 508 * Refresh recovery time 509 * It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. 510 */ 511 #define FEMC_SDRCTRL1_RFRC_MASK (0x1F00U) 512 #define FEMC_SDRCTRL1_RFRC_SHIFT (8U) 513 #define FEMC_SDRCTRL1_RFRC_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_RFRC_SHIFT) & FEMC_SDRCTRL1_RFRC_MASK) 514 #define FEMC_SDRCTRL1_RFRC_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_RFRC_MASK) >> FEMC_SDRCTRL1_RFRC_SHIFT) 515 516 /* 517 * ACT2RW (RW) 518 * 519 * ACT to Read/Write wait time 520 * It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. 521 */ 522 #define FEMC_SDRCTRL1_ACT2RW_MASK (0xF0U) 523 #define FEMC_SDRCTRL1_ACT2RW_SHIFT (4U) 524 #define FEMC_SDRCTRL1_ACT2RW_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_ACT2RW_SHIFT) & FEMC_SDRCTRL1_ACT2RW_MASK) 525 #define FEMC_SDRCTRL1_ACT2RW_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_ACT2RW_MASK) >> FEMC_SDRCTRL1_ACT2RW_SHIFT) 526 527 /* 528 * PRE2ACT (RW) 529 * 530 * PRECHARGE to ACT/Refresh wait time 531 * It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. 532 */ 533 #define FEMC_SDRCTRL1_PRE2ACT_MASK (0xFU) 534 #define FEMC_SDRCTRL1_PRE2ACT_SHIFT (0U) 535 #define FEMC_SDRCTRL1_PRE2ACT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_PRE2ACT_SHIFT) & FEMC_SDRCTRL1_PRE2ACT_MASK) 536 #define FEMC_SDRCTRL1_PRE2ACT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_PRE2ACT_MASK) >> FEMC_SDRCTRL1_PRE2ACT_SHIFT) 537 538 /* Bitfield definition for register: SDRCTRL2 */ 539 /* 540 * ITO (RW) 541 * 542 * SDRAM Idle timeout 543 * It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is 544 * considered idle when there is no AXI Bus transfer and no SDRAM command pending. 545 * 00000000b - IDLE timeout period is 256*Prescale period. 546 * 00000001-11111111b - IDLE timeout period is ITO*Prescale period. 547 */ 548 #define FEMC_SDRCTRL2_ITO_MASK (0xFF000000UL) 549 #define FEMC_SDRCTRL2_ITO_SHIFT (24U) 550 #define FEMC_SDRCTRL2_ITO_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_ITO_SHIFT) & FEMC_SDRCTRL2_ITO_MASK) 551 #define FEMC_SDRCTRL2_ITO_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_ITO_MASK) >> FEMC_SDRCTRL2_ITO_SHIFT) 552 553 /* 554 * ACT2ACT (RW) 555 * 556 * ACT to ACT wait time 557 * It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This 558 * could help to meet tRRD timing requirement by SDRAM device. 559 */ 560 #define FEMC_SDRCTRL2_ACT2ACT_MASK (0xFF0000UL) 561 #define FEMC_SDRCTRL2_ACT2ACT_SHIFT (16U) 562 #define FEMC_SDRCTRL2_ACT2ACT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_ACT2ACT_SHIFT) & FEMC_SDRCTRL2_ACT2ACT_MASK) 563 #define FEMC_SDRCTRL2_ACT2ACT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_ACT2ACT_MASK) >> FEMC_SDRCTRL2_ACT2ACT_SHIFT) 564 565 /* 566 * REF2REF (RW) 567 * 568 * Refresh to Refresh wait time 569 * It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. 570 * This could help to meet tRFC timing requirement by SDRAM device. 571 */ 572 #define FEMC_SDRCTRL2_REF2REF_MASK (0xFF00U) 573 #define FEMC_SDRCTRL2_REF2REF_SHIFT (8U) 574 #define FEMC_SDRCTRL2_REF2REF_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_REF2REF_SHIFT) & FEMC_SDRCTRL2_REF2REF_MASK) 575 #define FEMC_SDRCTRL2_REF2REF_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_REF2REF_MASK) >> FEMC_SDRCTRL2_REF2REF_SHIFT) 576 577 /* 578 * SRRC (RW) 579 * 580 * Self Refresh Recovery time 581 * It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. 582 */ 583 #define FEMC_SDRCTRL2_SRRC_MASK (0xFFU) 584 #define FEMC_SDRCTRL2_SRRC_SHIFT (0U) 585 #define FEMC_SDRCTRL2_SRRC_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_SRRC_SHIFT) & FEMC_SDRCTRL2_SRRC_MASK) 586 #define FEMC_SDRCTRL2_SRRC_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_SRRC_MASK) >> FEMC_SDRCTRL2_SRRC_SHIFT) 587 588 /* Bitfield definition for register: SDRCTRL3 */ 589 /* 590 * UT (RW) 591 * 592 * Refresh urgent threshold 593 * Internal refresh request is generated on every Refresh period. Before internal request timer count up to 594 * urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh 595 * request is handled in lower priority than any pending AXI command or IP command to SDRAM device. 596 * When internal request timer count up to this urgent threshold, refresh request is considered as urgent 597 * refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP 598 * command to SDRAM device. 599 * NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as 600 * urgent refresh request. 601 * Refresh urgent threshold is as follwoing: 602 * 00000000b - 256*Prescaler period 603 * 00000001-11111111b - UT*Prescaler period 604 */ 605 #define FEMC_SDRCTRL3_UT_MASK (0xFF000000UL) 606 #define FEMC_SDRCTRL3_UT_SHIFT (24U) 607 #define FEMC_SDRCTRL3_UT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_UT_SHIFT) & FEMC_SDRCTRL3_UT_MASK) 608 #define FEMC_SDRCTRL3_UT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_UT_MASK) >> FEMC_SDRCTRL3_UT_SHIFT) 609 610 /* 611 * RT (RW) 612 * 613 * Refresh timer period 614 * Refresh timer period is as following: 615 * 00000000b - 256*Prescaler period 616 * 00000001-11111111b - RT*Prescaler period 617 */ 618 #define FEMC_SDRCTRL3_RT_MASK (0xFF0000UL) 619 #define FEMC_SDRCTRL3_RT_SHIFT (16U) 620 #define FEMC_SDRCTRL3_RT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_RT_SHIFT) & FEMC_SDRCTRL3_RT_MASK) 621 #define FEMC_SDRCTRL3_RT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_RT_MASK) >> FEMC_SDRCTRL3_RT_SHIFT) 622 623 /* 624 * PRESCALE (RW) 625 * 626 * Prescaler timer period 627 * Prescaler timer period is as following: 628 * 00000000b - 256*16 clock cycles 629 * 00000001-11111111b - PRESCALE*16 clock cycles 630 */ 631 #define FEMC_SDRCTRL3_PRESCALE_MASK (0xFF00U) 632 #define FEMC_SDRCTRL3_PRESCALE_SHIFT (8U) 633 #define FEMC_SDRCTRL3_PRESCALE_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_PRESCALE_SHIFT) & FEMC_SDRCTRL3_PRESCALE_MASK) 634 #define FEMC_SDRCTRL3_PRESCALE_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_PRESCALE_MASK) >> FEMC_SDRCTRL3_PRESCALE_SHIFT) 635 636 /* 637 * REBL (RW) 638 * 639 * Refresh burst length 640 * It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The 641 * number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. 642 * 000b - 1 643 * 001b - 2 644 * 010b - 3 645 * 011b - 4 646 * 100b - 5 647 * 101b - 6 648 * 110b - 7 649 * 111b - 8 650 */ 651 #define FEMC_SDRCTRL3_REBL_MASK (0xEU) 652 #define FEMC_SDRCTRL3_REBL_SHIFT (1U) 653 #define FEMC_SDRCTRL3_REBL_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_REBL_SHIFT) & FEMC_SDRCTRL3_REBL_MASK) 654 #define FEMC_SDRCTRL3_REBL_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_REBL_MASK) >> FEMC_SDRCTRL3_REBL_SHIFT) 655 656 /* 657 * REN (RW) 658 * 659 * Refresh enable 660 */ 661 #define FEMC_SDRCTRL3_REN_MASK (0x1U) 662 #define FEMC_SDRCTRL3_REN_SHIFT (0U) 663 #define FEMC_SDRCTRL3_REN_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_REN_SHIFT) & FEMC_SDRCTRL3_REN_MASK) 664 #define FEMC_SDRCTRL3_REN_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_REN_MASK) >> FEMC_SDRCTRL3_REN_SHIFT) 665 666 /* Bitfield definition for register: SRCTRL0 */ 667 /* 668 * ADVH (RW) 669 * 670 * ADV hold state 671 * 0b - ADV is high during address hold state 672 * 1b - ADV is low during address hold state 673 */ 674 #define FEMC_SRCTRL0_ADVH_MASK (0x800U) 675 #define FEMC_SRCTRL0_ADVH_SHIFT (11U) 676 #define FEMC_SRCTRL0_ADVH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_ADVH_SHIFT) & FEMC_SRCTRL0_ADVH_MASK) 677 #define FEMC_SRCTRL0_ADVH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_ADVH_MASK) >> FEMC_SRCTRL0_ADVH_SHIFT) 678 679 /* 680 * ADVP (RW) 681 * 682 * ADV polarity 683 * 0b - ADV is active low 684 * 1b - ADV is active high 685 */ 686 #define FEMC_SRCTRL0_ADVP_MASK (0x400U) 687 #define FEMC_SRCTRL0_ADVP_SHIFT (10U) 688 #define FEMC_SRCTRL0_ADVP_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_ADVP_SHIFT) & FEMC_SRCTRL0_ADVP_MASK) 689 #define FEMC_SRCTRL0_ADVP_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_ADVP_MASK) >> FEMC_SRCTRL0_ADVP_SHIFT) 690 691 /* 692 * ADM (RW) 693 * 694 * address data mode 695 * 00b - address and data MUX mode 696 * 11b - address and data non-MUX mode 697 */ 698 #define FEMC_SRCTRL0_ADM_MASK (0x300U) 699 #define FEMC_SRCTRL0_ADM_SHIFT (8U) 700 #define FEMC_SRCTRL0_ADM_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_ADM_SHIFT) & FEMC_SRCTRL0_ADM_MASK) 701 #define FEMC_SRCTRL0_ADM_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_ADM_MASK) >> FEMC_SRCTRL0_ADM_SHIFT) 702 703 /* 704 * PORTSZ (RW) 705 * 706 * port size 707 * 0b - 8bit 708 * 1b - 16bit 709 */ 710 #define FEMC_SRCTRL0_PORTSZ_MASK (0x1U) 711 #define FEMC_SRCTRL0_PORTSZ_SHIFT (0U) 712 #define FEMC_SRCTRL0_PORTSZ_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_PORTSZ_SHIFT) & FEMC_SRCTRL0_PORTSZ_MASK) 713 #define FEMC_SRCTRL0_PORTSZ_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_PORTSZ_MASK) >> FEMC_SRCTRL0_PORTSZ_SHIFT) 714 715 /* Bitfield definition for register: SRCTRL1 */ 716 /* 717 * OEH (RW) 718 * 719 * OE high time, is OEH+1 clock cycles 720 */ 721 #define FEMC_SRCTRL1_OEH_MASK (0xF0000000UL) 722 #define FEMC_SRCTRL1_OEH_SHIFT (28U) 723 #define FEMC_SRCTRL1_OEH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_OEH_SHIFT) & FEMC_SRCTRL1_OEH_MASK) 724 #define FEMC_SRCTRL1_OEH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_OEH_MASK) >> FEMC_SRCTRL1_OEH_SHIFT) 725 726 /* 727 * OEL (RW) 728 * 729 * OE low time, is OEL+1 clock cycles 730 */ 731 #define FEMC_SRCTRL1_OEL_MASK (0xF000000UL) 732 #define FEMC_SRCTRL1_OEL_SHIFT (24U) 733 #define FEMC_SRCTRL1_OEL_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_OEL_SHIFT) & FEMC_SRCTRL1_OEL_MASK) 734 #define FEMC_SRCTRL1_OEL_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_OEL_MASK) >> FEMC_SRCTRL1_OEL_SHIFT) 735 736 /* 737 * WEH (RW) 738 * 739 * WE high time, is WEH+1 clock cycles 740 */ 741 #define FEMC_SRCTRL1_WEH_MASK (0xF00000UL) 742 #define FEMC_SRCTRL1_WEH_SHIFT (20U) 743 #define FEMC_SRCTRL1_WEH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_WEH_SHIFT) & FEMC_SRCTRL1_WEH_MASK) 744 #define FEMC_SRCTRL1_WEH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_WEH_MASK) >> FEMC_SRCTRL1_WEH_SHIFT) 745 746 /* 747 * WEL (RW) 748 * 749 * WE low time, is WEL+1 clock cycles 750 */ 751 #define FEMC_SRCTRL1_WEL_MASK (0xF0000UL) 752 #define FEMC_SRCTRL1_WEL_SHIFT (16U) 753 #define FEMC_SRCTRL1_WEL_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_WEL_SHIFT) & FEMC_SRCTRL1_WEL_MASK) 754 #define FEMC_SRCTRL1_WEL_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_WEL_MASK) >> FEMC_SRCTRL1_WEL_SHIFT) 755 756 /* 757 * AH (RW) 758 * 759 * Address hold time, is AH+1 clock cycles 760 */ 761 #define FEMC_SRCTRL1_AH_MASK (0xF000U) 762 #define FEMC_SRCTRL1_AH_SHIFT (12U) 763 #define FEMC_SRCTRL1_AH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_AH_SHIFT) & FEMC_SRCTRL1_AH_MASK) 764 #define FEMC_SRCTRL1_AH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_AH_MASK) >> FEMC_SRCTRL1_AH_SHIFT) 765 766 /* 767 * AS (RW) 768 * 769 * Address setup time, is AS+1 clock cycles 770 */ 771 #define FEMC_SRCTRL1_AS_MASK (0xF00U) 772 #define FEMC_SRCTRL1_AS_SHIFT (8U) 773 #define FEMC_SRCTRL1_AS_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_AS_SHIFT) & FEMC_SRCTRL1_AS_MASK) 774 #define FEMC_SRCTRL1_AS_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_AS_MASK) >> FEMC_SRCTRL1_AS_SHIFT) 775 776 /* 777 * CEH (RW) 778 * 779 * Chip enable hold time, is CEH+1 clock cycles 780 */ 781 #define FEMC_SRCTRL1_CEH_MASK (0xF0U) 782 #define FEMC_SRCTRL1_CEH_SHIFT (4U) 783 #define FEMC_SRCTRL1_CEH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_CEH_SHIFT) & FEMC_SRCTRL1_CEH_MASK) 784 #define FEMC_SRCTRL1_CEH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_CEH_MASK) >> FEMC_SRCTRL1_CEH_SHIFT) 785 786 /* 787 * CES (RW) 788 * 789 * Chip enable setup time, is CES+1 clock cycles 790 */ 791 #define FEMC_SRCTRL1_CES_MASK (0xFU) 792 #define FEMC_SRCTRL1_CES_SHIFT (0U) 793 #define FEMC_SRCTRL1_CES_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_CES_SHIFT) & FEMC_SRCTRL1_CES_MASK) 794 #define FEMC_SRCTRL1_CES_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_CES_MASK) >> FEMC_SRCTRL1_CES_SHIFT) 795 796 /* Bitfield definition for register: SADDR */ 797 /* 798 * SA (RW) 799 * 800 * Slave address 801 */ 802 #define FEMC_SADDR_SA_MASK (0xFFFFFFFFUL) 803 #define FEMC_SADDR_SA_SHIFT (0U) 804 #define FEMC_SADDR_SA_SET(x) (((uint32_t)(x) << FEMC_SADDR_SA_SHIFT) & FEMC_SADDR_SA_MASK) 805 #define FEMC_SADDR_SA_GET(x) (((uint32_t)(x) & FEMC_SADDR_SA_MASK) >> FEMC_SADDR_SA_SHIFT) 806 807 /* Bitfield definition for register: DATSZ */ 808 /* 809 * DATSZ (RW) 810 * 811 * Data Size in Byte 812 * When IP command is not a write/read operation, DATSZ field would be ignored. 813 * 000b - 4 814 * 001b - 1 815 * 010b - 2 816 * 011b - 3 817 * 100b - 4 818 * 101b - 4 819 * 110b - 4 820 * 111b - 4 821 */ 822 #define FEMC_DATSZ_DATSZ_MASK (0x7U) 823 #define FEMC_DATSZ_DATSZ_SHIFT (0U) 824 #define FEMC_DATSZ_DATSZ_SET(x) (((uint32_t)(x) << FEMC_DATSZ_DATSZ_SHIFT) & FEMC_DATSZ_DATSZ_MASK) 825 #define FEMC_DATSZ_DATSZ_GET(x) (((uint32_t)(x) & FEMC_DATSZ_DATSZ_MASK) >> FEMC_DATSZ_DATSZ_SHIFT) 826 827 /* Bitfield definition for register: BYTEMSK */ 828 /* 829 * BM3 (RW) 830 * 831 * Byte Mask for Byte 3 (IPTXD bit 31:24) 832 * 0b - Byte Unmasked 833 * 1b - Byte Masked 834 */ 835 #define FEMC_BYTEMSK_BM3_MASK (0x8U) 836 #define FEMC_BYTEMSK_BM3_SHIFT (3U) 837 #define FEMC_BYTEMSK_BM3_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM3_SHIFT) & FEMC_BYTEMSK_BM3_MASK) 838 #define FEMC_BYTEMSK_BM3_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM3_MASK) >> FEMC_BYTEMSK_BM3_SHIFT) 839 840 /* 841 * BM2 (RW) 842 * 843 * Byte Mask for Byte 2 (IPTXD bit 23:16) 844 * 0b - Byte Unmasked 845 * 1b - Byte Masked 846 */ 847 #define FEMC_BYTEMSK_BM2_MASK (0x4U) 848 #define FEMC_BYTEMSK_BM2_SHIFT (2U) 849 #define FEMC_BYTEMSK_BM2_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM2_SHIFT) & FEMC_BYTEMSK_BM2_MASK) 850 #define FEMC_BYTEMSK_BM2_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM2_MASK) >> FEMC_BYTEMSK_BM2_SHIFT) 851 852 /* 853 * BM1 (RW) 854 * 855 * Byte Mask for Byte 1 (IPTXD bit 15:8) 856 * 0b - Byte Unmasked 857 * 1b - Byte Masked 858 */ 859 #define FEMC_BYTEMSK_BM1_MASK (0x2U) 860 #define FEMC_BYTEMSK_BM1_SHIFT (1U) 861 #define FEMC_BYTEMSK_BM1_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM1_SHIFT) & FEMC_BYTEMSK_BM1_MASK) 862 #define FEMC_BYTEMSK_BM1_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM1_MASK) >> FEMC_BYTEMSK_BM1_SHIFT) 863 864 /* 865 * BM0 (RW) 866 * 867 * Byte Mask for Byte 0 (IPTXD bit 7:0) 868 * 0b - Byte Unmasked 869 * 1b - Byte Masked 870 */ 871 #define FEMC_BYTEMSK_BM0_MASK (0x1U) 872 #define FEMC_BYTEMSK_BM0_SHIFT (0U) 873 #define FEMC_BYTEMSK_BM0_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM0_SHIFT) & FEMC_BYTEMSK_BM0_MASK) 874 #define FEMC_BYTEMSK_BM0_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM0_MASK) >> FEMC_BYTEMSK_BM0_SHIFT) 875 876 /* Bitfield definition for register: IPCMD */ 877 /* 878 * KEY (WO) 879 * 880 * This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory 881 * device is selected by BRx settings and IPCR0 registers. 882 */ 883 #define FEMC_IPCMD_KEY_MASK (0xFFFF0000UL) 884 #define FEMC_IPCMD_KEY_SHIFT (16U) 885 #define FEMC_IPCMD_KEY_SET(x) (((uint32_t)(x) << FEMC_IPCMD_KEY_SHIFT) & FEMC_IPCMD_KEY_MASK) 886 #define FEMC_IPCMD_KEY_GET(x) (((uint32_t)(x) & FEMC_IPCMD_KEY_MASK) >> FEMC_IPCMD_KEY_SHIFT) 887 888 /* 889 * CMD (RW) 890 * 891 * SDRAM Commands: 892 * • 0x8: READ 893 * • 0x9: WRITE 894 * • 0xA: MODESET 895 * • 0xB: ACTIVE 896 * • 0xC: AUTO REFRESH 897 * • 0xD: SELF REFRESH 898 * • 0xE: PRECHARGE 899 * • 0xF: PRECHARGE ALL 900 * • Others: RSVD 901 * NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. 902 */ 903 #define FEMC_IPCMD_CMD_MASK (0xFFFFU) 904 #define FEMC_IPCMD_CMD_SHIFT (0U) 905 #define FEMC_IPCMD_CMD_SET(x) (((uint32_t)(x) << FEMC_IPCMD_CMD_SHIFT) & FEMC_IPCMD_CMD_MASK) 906 #define FEMC_IPCMD_CMD_GET(x) (((uint32_t)(x) & FEMC_IPCMD_CMD_MASK) >> FEMC_IPCMD_CMD_SHIFT) 907 908 /* Bitfield definition for register: IPTX */ 909 /* 910 * DAT (RW) 911 * 912 * Data 913 */ 914 #define FEMC_IPTX_DAT_MASK (0xFFFFFFFFUL) 915 #define FEMC_IPTX_DAT_SHIFT (0U) 916 #define FEMC_IPTX_DAT_SET(x) (((uint32_t)(x) << FEMC_IPTX_DAT_SHIFT) & FEMC_IPTX_DAT_MASK) 917 #define FEMC_IPTX_DAT_GET(x) (((uint32_t)(x) & FEMC_IPTX_DAT_MASK) >> FEMC_IPTX_DAT_SHIFT) 918 919 /* Bitfield definition for register: IPRX */ 920 /* 921 * DAT (RW) 922 * 923 * Data 924 */ 925 #define FEMC_IPRX_DAT_MASK (0xFFFFFFFFUL) 926 #define FEMC_IPRX_DAT_SHIFT (0U) 927 #define FEMC_IPRX_DAT_SET(x) (((uint32_t)(x) << FEMC_IPRX_DAT_SHIFT) & FEMC_IPRX_DAT_MASK) 928 #define FEMC_IPRX_DAT_GET(x) (((uint32_t)(x) & FEMC_IPRX_DAT_MASK) >> FEMC_IPRX_DAT_SHIFT) 929 930 /* Bitfield definition for register: STAT0 */ 931 /* 932 * IDLE (RO) 933 * 934 * Indicating whether it is in IDLE state. 935 * When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no 936 * pending device access. 937 */ 938 #define FEMC_STAT0_IDLE_MASK (0x1U) 939 #define FEMC_STAT0_IDLE_SHIFT (0U) 940 #define FEMC_STAT0_IDLE_GET(x) (((uint32_t)(x) & FEMC_STAT0_IDLE_MASK) >> FEMC_STAT0_IDLE_SHIFT) 941 942 /* Bitfield definition for register: DLYCFG */ 943 /* 944 * OE (RW) 945 * 946 * delay clock output enable, should be set after setting DLYEN and DLYSEL 947 */ 948 #define FEMC_DLYCFG_OE_MASK (0x2000U) 949 #define FEMC_DLYCFG_OE_SHIFT (13U) 950 #define FEMC_DLYCFG_OE_SET(x) (((uint32_t)(x) << FEMC_DLYCFG_OE_SHIFT) & FEMC_DLYCFG_OE_MASK) 951 #define FEMC_DLYCFG_OE_GET(x) (((uint32_t)(x) & FEMC_DLYCFG_OE_MASK) >> FEMC_DLYCFG_OE_SHIFT) 952 953 /* 954 * DLYSEL (RW) 955 * 956 * delay line select, 0 for 1 cell, 31 for all 32 cells 957 */ 958 #define FEMC_DLYCFG_DLYSEL_MASK (0x3EU) 959 #define FEMC_DLYCFG_DLYSEL_SHIFT (1U) 960 #define FEMC_DLYCFG_DLYSEL_SET(x) (((uint32_t)(x) << FEMC_DLYCFG_DLYSEL_SHIFT) & FEMC_DLYCFG_DLYSEL_MASK) 961 #define FEMC_DLYCFG_DLYSEL_GET(x) (((uint32_t)(x) & FEMC_DLYCFG_DLYSEL_MASK) >> FEMC_DLYCFG_DLYSEL_SHIFT) 962 963 /* 964 * DLYEN (RW) 965 * 966 * delay line enable 967 */ 968 #define FEMC_DLYCFG_DLYEN_MASK (0x1U) 969 #define FEMC_DLYCFG_DLYEN_SHIFT (0U) 970 #define FEMC_DLYCFG_DLYEN_SET(x) (((uint32_t)(x) << FEMC_DLYCFG_DLYEN_SHIFT) & FEMC_DLYCFG_DLYEN_MASK) 971 #define FEMC_DLYCFG_DLYEN_GET(x) (((uint32_t)(x) & FEMC_DLYCFG_DLYEN_MASK) >> FEMC_DLYCFG_DLYEN_SHIFT) 972 973 974 975 /* BR register group index macro definition */ 976 #define FEMC_BR_BASE0 (0UL) 977 #define FEMC_BR_BASE1 (1UL) 978 #define FEMC_BR_BASE6 (6UL) 979 980 981 #endif /* HPM_FEMC_H */ 982