1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_adc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32MP1xx_HAL_ADC_EX_H 22 #define STM32MP1xx_HAL_ADC_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32mp1xx_hal_def.h" 30 31 /** @addtogroup STM32MP1xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup ADCEx 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief ADC Injected Conversion Oversampling structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Ratio; /*!< Configures the oversampling ratio. 50 This parameter can be a value between 1 and 1024 */ 51 52 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 53 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 54 } ADC_InjOversamplingTypeDef; 55 56 /** 57 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected 58 * @note Parameters of this structure are shared within 2 scopes: 59 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset 60 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 61 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. 62 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 63 * ADC state can be either: 64 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') 65 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. 66 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. 67 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 68 * on ADC groups regular and injected. 69 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 70 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 71 */ 72 typedef struct 73 { 74 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. 75 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 76 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 77 78 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. 79 This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. 80 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 81 the new channel setting (or parameter number of conversions adjusted) */ 82 83 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 84 Unit: ADC clock cycles. 85 Conversion time is the addition of sampling time and processing time 86 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 87 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 88 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 89 It overwrites the last setting. 90 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 91 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 92 Refer to device datasheet for timings values. */ 93 94 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 95 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 96 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 97 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. 98 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 99 It overwrites the last setting. 100 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 101 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 102 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 103 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 104 of another parameter update on the fly) */ 105 106 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 107 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. 108 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 109 110 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. 111 Offset value must be a positive number. 112 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 113 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 114 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 115 without continuous mode or external trigger that could launch a conversion). */ 116 117 uint32_t InjectedOffsetRightShift; /*!< Specifies whether the 1 bit Right-shift feature is used or not. 118 This parameter is applied only for 16-bit or 8-bit resolution. 119 This parameter can be set to ENABLE or DISABLE. */ 120 121 FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not. 122 This parameter is applied only for 16-bit or 8-bit resolution. 123 This parameter can be set to ENABLE or DISABLE. */ 124 uint32_t InjectedLeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling. 125 This parameter can be a value of @ref ADCEx_Left_Bit_Shift */ 126 127 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. 128 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 129 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 130 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 131 configure a channel on injected group can impact the configuration of other channels previously set. */ 132 133 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence 134 (main sequence subdivided in successive parts). 135 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 136 Discontinuous mode can be enabled only if continuous mode is disabled. 137 This parameter can be set to ENABLE or DISABLE. 138 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 139 Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). 140 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 141 configure a channel on injected group can impact the configuration of other channels previously set. */ 142 143 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one 144 This parameter can be set to ENABLE or DISABLE. 145 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 146 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) 147 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 148 To maintain JAUTO always enabled, DMA must be configured in circular mode. 149 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 150 configure a channel on injected group can impact the configuration of other channels previously set. */ 151 152 FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. 153 This parameter can be set to ENABLE or DISABLE. 154 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a 155 new injected context is set when queue is full, error is triggered by interruption and through function 156 'HAL_ADCEx_InjectedQueueOverflowCallback'. 157 Caution: This feature request that the sequence is fully configured before injected conversion start. 158 Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. 159 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 160 configure a channel on injected group can impact the configuration of other channels previously set. 161 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ 162 163 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 164 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 165 This parameter can be a value of @ref ADC_injected_external_trigger_source. 166 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 167 configure a channel on injected group can impact the configuration of other channels previously set. */ 168 169 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 170 This parameter can be a value of @ref ADC_injected_external_trigger_edge. 171 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. 172 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 173 configure a channel on injected group can impact the configuration of other channels previously set. */ 174 175 FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 176 This parameter can be set to ENABLE or DISABLE. 177 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 178 179 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 180 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. 181 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 182 } ADC_InjectionConfTypeDef; 183 184 #if defined(ADC_MULTIMODE_SUPPORT) 185 /** 186 * @brief Structure definition of ADC multimode 187 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). 188 * Both Master and Slave ADCs must be disabled. 189 */ 190 typedef struct 191 { 192 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. 193 This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ 194 195 uint32_t DualModeData; /*!< Configures the Dual ADC Mode Data Format: 196 This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */ 197 198 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 199 This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. 200 Delay range depends on selected resolution: 201 from 1 to 9 clock cycles for 16 bits, 202 from 1 to 9 clock cycles for 14 bits 203 from 1 to 8 clock cycles for 12 bits 204 from 1 to 6 clock cycles for 10 bits 205 from 1 to 6 clock cycles for 8 bits */ 206 } ADC_MultiModeTypeDef; 207 #endif /* ADC_MULTIMODE_SUPPORT */ 208 209 /** 210 * @} 211 */ 212 213 /* Exported constants --------------------------------------------------------*/ 214 215 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 216 * @{ 217 */ 218 219 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source 220 * @{ 221 */ 222 /* ADC group regular trigger sources for all ADC instances */ 223 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ 224 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */ 225 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 226 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */ 227 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 228 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 229 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */ 230 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 231 #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 232 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */ 233 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */ 234 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */ 235 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 236 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */ 237 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 238 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */ 239 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */ 240 #define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */ 241 #define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */ 242 #define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. Trigger edge set to rising edge (default setting). */ 243 /** 244 * @} 245 */ 246 247 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) 248 * @{ 249 */ 250 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ 251 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ 252 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ 253 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ 254 /** 255 * @} 256 */ 257 258 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 259 * @{ 260 */ 261 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ 262 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ 263 /** 264 * @} 265 */ 266 267 /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number 268 * @{ 269 */ 270 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ 271 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 272 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 273 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 274 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 275 /** 276 * @} 277 */ 278 279 /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 280 * @{ 281 */ 282 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ 283 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ 284 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ 285 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ 286 /** 287 * @} 288 */ 289 290 #if defined(ADC_MULTIMODE_SUPPORT) 291 /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode 292 * @{ 293 */ 294 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ 295 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ 296 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ 297 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ 298 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 299 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 300 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 301 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 302 303 /** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting 304 * @{ 305 */ 306 #define ADC_DUALMODEDATAFORMAT_DISABLED (0x00000000UL) /*!< Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used */ 307 #define ADC_DUALMODEDATAFORMAT_32_10_BITS (ADC_CCR_DAMDF_1) /*!< Data formatting mode for 32 down to 10-bit resolution */ 308 #define ADC_DUALMODEDATAFORMAT_8_BITS ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1)) /*!< Data formatting mode for 8-bit resolution */ 309 /** 310 * @} 311 */ 312 313 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 314 * @{ 315 */ 316 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ 317 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ 318 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ 319 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ 320 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ 321 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 322 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 323 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES_5) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 324 /** 325 * @} 326 */ 327 328 /** 329 * @} 330 */ 331 #endif /* ADC_MULTIMODE_SUPPORT */ 332 333 /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups 334 * @{ 335 */ 336 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ 337 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ 338 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ 339 /** 340 * @} 341 */ 342 343 /** @defgroup ADC_CFGR_fields ADCx CFGR fields 344 * @{ 345 */ 346 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 347 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 348 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 349 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 350 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | |\ 351 ADC_CFGR_RES | ADC_CFGR_DMNGT ) 352 /** 353 * @} 354 */ 355 356 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields 357 * @{ 358 */ 359 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 360 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 361 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 362 ADC_SMPR1_SMP0) 363 /** 364 * @} 365 */ 366 367 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 368 * @{ 369 */ 370 /* ADC_CFGR fields of parameters that can be updated when no conversion 371 (neither regular nor injected) is on-going */ 372 #define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY)) 373 /** 374 * @} 375 */ 376 377 378 /** 379 * @} 380 */ 381 382 /* Exported macros -----------------------------------------------------------*/ 383 384 #if defined(ADC_MULTIMODE_SUPPORT) 385 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros 386 * @{ 387 */ 388 389 /** @brief Force ADC instance in multimode mode independent (multimode disable). 390 * @note This macro must be used only in case of transition from multimode 391 * to mode independent and in case of unknown previous state, 392 * to ensure ADC configuration is in mode independent. 393 * @note Standard way of multimode configuration change is done from 394 * HAL ADC handle of ADC master using function 395 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". 396 * Usage of this macro is not the Standard way of multimode 397 * configuration and can lead to have HAL ADC handles status 398 * misaligned. Usage of this macro must be limited to cases 399 * mentioned above. 400 * @param __HANDLE__ ADC handle. 401 * @retval None 402 */ 403 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ 404 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) 405 406 /** 407 * @} 408 */ 409 #endif /* ADC_MULTIMODE_SUPPORT */ 410 411 /* Private macros ------------------------------------------------------------*/ 412 413 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 414 * @{ 415 */ 416 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 417 /* code of final user. */ 418 419 /** 420 * @brief Test if conversion trigger of injected group is software start 421 * or external trigger. 422 * @param __HANDLE__ ADC handle. 423 * @retval SET (software start) or RESET (external trigger). 424 */ 425 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 426 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) 427 428 /** 429 * @brief Check whether or not ADC is independent. 430 * @param __HANDLE__ ADC handle. 431 * @note When multimode feature is not available, the macro always returns SET. 432 * @retval SET (ADC is independent) or RESET (ADC is not). 433 */ 434 #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) 435 436 /** 437 * @brief Set the selected injected Channel rank. 438 * @param __CHANNELNB__ Channel number. 439 * @param __RANKNB__ Rank number. 440 * @retval None 441 */ 442 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\ 443 & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) 444 445 /** 446 * @brief Configure ADC injected context queue 447 * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. 448 * @retval None 449 */ 450 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) 451 452 /** 453 * @brief Configure ADC discontinuous conversion mode for injected group 454 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. 455 * @retval None 456 */ 457 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) 458 459 /** 460 * @brief Configure ADC discontinuous conversion mode for regular group 461 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. 462 * @retval None 463 */ 464 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) 465 466 /** 467 * @brief Configure the number of discontinuous conversions for regular group. 468 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. 469 * @retval None 470 */ 471 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) 472 473 /** 474 * @brief Configure the ADC auto delay mode. 475 * @param __AUTOWAIT__ Auto delay bit enable or disable. 476 * @retval None 477 */ 478 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) 479 480 /** 481 * @brief Configure ADC continuous conversion mode. 482 * @param __CONTINUOUS_MODE__ Continuous mode. 483 * @retval None 484 */ 485 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) 486 487 /** 488 * @brief Enable the ADC DMA continuous request. 489 * @param __DMACONTREQ_MODE__: DMA continuous request mode. 490 * @retval None 491 */ 492 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__)) 493 494 /** 495 * @brief Configure the channel number into offset OFRx register. 496 * @param __CHANNEL__ ADC Channel. 497 * @retval None 498 */ 499 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos) 500 501 /** 502 * @brief Configure the channel number into differential mode selection register. 503 * @param __CHANNEL__ ADC Channel. 504 * @retval None 505 */ 506 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__)) 507 508 /** 509 * @brief Configure calibration factor in differential mode to be set into calibration register. 510 * @param __CALIBRATION_FACTOR__ Calibration factor value. 511 * @retval None 512 */ 513 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__)\ 514 & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos) 515 516 /** 517 * @brief Calibration factor in differential mode to be retrieved from calibration register. 518 * @param __CALIBRATION_FACTOR__ Calibration factor value. 519 * @retval None 520 */ 521 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos) 522 523 /** 524 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. 525 * @param __THRESHOLD__ Threshold value. 526 * @retval None 527 */ 528 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL) 529 530 #if defined(ADC_MULTIMODE_SUPPORT) 531 /** 532 * @brief Configure the ADC DMA continuous request for ADC multimode. 533 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 534 * @retval None 535 */ 536 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) 537 #endif /* ADC_MULTIMODE_SUPPORT */ 538 539 /** 540 * @brief Shift the offset in function of the selected ADC resolution. 541 * @note Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0 542 * If resolution 16 bits, no shift. 543 * If resolution 14 bits, shift of 2 ranks on the left. 544 * If resolution 12 bits, shift of 4 ranks on the left. 545 * If resolution 10 bits, shift of 6 ranks on the left. 546 * If resolution 8 bits, shift of 8 ranks on the left. 547 * therefore, shift = (16 - resolution) = 16 - (16 - (((RES[2:0]) >> 2)*2)) 548 * @param __HANDLE__: ADC handle 549 * @param __OFFSET__: Value to be shifted 550 * @retval None 551 */ 552 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 553 ( ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 554 ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 555 : \ 556 ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 557 ) 558 559 /** 560 * @brief Shift the AWD1 threshold in function of the selected ADC resolution. 561 * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. 562 * If resolution 16 bits, no shift. 563 * If resolution 14 bits, shift of 2 ranks on the left. 564 * If resolution 12 bits, shift of 4 ranks on the left. 565 * If resolution 10 bits, shift of 6 ranks on the left. 566 * If resolution 8 bits, shift of 8 ranks on the left. 567 * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2)) 568 * @param __HANDLE__: ADC handle 569 * @param __THRESHOLD__: Value to be shifted 570 * @retval None 571 */ 572 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 573 ( ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 574 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 575 : \ 576 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 577 ) 578 579 /** 580 * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution. 581 * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. 582 * If resolution 16 bits, no shift. 583 * If resolution 14 bits, shift of 2 ranks on the left. 584 * If resolution 12 bits, shift of 4 ranks on the left. 585 * If resolution 10 bits, shift of 6 ranks on the left. 586 * If resolution 8 bits, shift of 8 ranks on the left. 587 * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2)) 588 * @param __HANDLE__: ADC handle 589 * @param __THRESHOLD__: Value to be shifted 590 * @retval None 591 */ 592 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 593 ( ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 594 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 595 : \ 596 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 597 ) 598 /** 599 * @brief Clear Common Control Register. 600 * @param __HANDLE__ ADC handle. 601 * @retval None 602 */ 603 /** 604 * @brief Report common register to ADC1 and ADC2 605 * @param __HANDLE__: ADC handle 606 * @retval Common control register 607 */ 608 #define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON) 609 610 /** 611 * @brief Report Master Instance 612 * @param __HANDLE__: ADC handle 613 * @note return same instance if ADC of input handle is independent ADC 614 * @retval Master Instance 615 */ 616 #define ADC_MASTER_REGISTER(__HANDLE__) \ 617 ( ( (((__HANDLE__)->Instance) == ADC1) \ 618 )? \ 619 ((__HANDLE__)->Instance) \ 620 : \ 621 (ADC1) \ 622 ) 623 624 /** 625 * @brief Check whether or not dual regular conversions are enabled 626 * @param __HANDLE__: ADC handle 627 * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) 628 */ 629 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \ 630 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ 631 )? \ 632 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \ 633 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \ 634 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \ 635 : \ 636 RESET \ 637 ) 638 639 /** 640 * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master 641 * @param __HANDLE__: ADC handle 642 * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode) 643 */ 644 #define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ 645 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \ 646 )? \ 647 SET \ 648 : \ 649 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ 650 ) 651 652 /** 653 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled 654 * @param __HANDLE__: ADC handle 655 * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled) 656 */ 657 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ 658 ( ( ((__HANDLE__)->Instance == ADC1) \ 659 )? \ 660 SET \ 661 : \ 662 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 663 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \ 664 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) 665 666 /** 667 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled 668 * @param __HANDLE__: ADC handle 669 * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled) 670 */ 671 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \ 672 ( ( ((__HANDLE__)->Instance == ADC1) \ 673 )? \ 674 SET \ 675 : \ 676 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 677 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \ 678 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) )) 679 680 681 682 #if defined(ADC_MULTIMODE_SUPPORT) 683 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ 684 ADC_CCR_PRESC | \ 685 ADC_CCR_VBATEN | \ 686 ADC_CCR_VSENSEEN | \ 687 ADC_CCR_VREFEN | \ 688 ADC_CCR_DAMDF | \ 689 ADC_CCR_DELAY | \ 690 ADC_CCR_DUAL ) 691 #endif /* ADC_MULTIMODE_SUPPORT */ 692 693 /** 694 * @brief Set handle instance of the ADC slave associated to the ADC master. 695 * @param __HANDLE_MASTER__ ADC master handle. 696 * @param __HANDLE_SLAVE__ ADC slave handle. 697 * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. 698 * @retval None 699 */ 700 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 701 ( ((__HANDLE_MASTER__)->Instance == ADC1) ? \ 702 ((__HANDLE_SLAVE__)->Instance = ADC2) \ 703 : \ 704 ((__HANDLE_SLAVE__)->Instance = NULL) \ 705 ) 706 707 708 /** 709 * @brief Verify the ADC instance connected to the temperature sensor. 710 * @param __HANDLE__ ADC handle. 711 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 712 */ 713 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 714 715 /** 716 * @brief Verify the ADC instance connected to the battery voltage VBAT. 717 * @param __HANDLE__ ADC handle. 718 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 719 */ 720 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 721 722 /** 723 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 724 * @param __HANDLE__ ADC handle. 725 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 726 */ 727 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 728 729 /** 730 * @brief Verify the ADC instance connected to the internal voltage reference VDDCORE. 731 * @param __HANDLE__ ADC handle. 732 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 733 */ 734 /* The internal voltage reference VDDCORE measurement path (channel 0) is available on ADC2 */ 735 #define ADC_VDDCORE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 736 737 /** 738 * @brief Verify the length of scheduled injected conversions group. 739 * @param __LENGTH__ number of programmed conversions. 740 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) 741 */ 742 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) 743 744 /** 745 * @brief Calibration factor size verification (7 bits maximum). 746 * @param __CALIBRATION_FACTOR__ Calibration factor value. 747 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 748 */ 749 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) 750 751 752 /** 753 * @brief Verify the ADC channel setting. 754 * @param __CHANNEL__ programmed ADC channel. 755 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 756 */ 757 #define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \ 758 ((__CHANNEL__) == ADC_CHANNEL_1) || \ 759 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 760 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 761 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 762 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 763 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 764 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 765 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 766 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 767 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 768 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 769 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 770 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 771 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 772 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 773 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 774 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 775 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 776 ((__CHANNEL__) == ADC_CHANNEL_19) || \ 777 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 778 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 779 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \ 780 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)|| \ 781 ((__CHANNEL__) == ADC_CHANNEL_VCORE) || \ 782 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) ) 783 784 /** 785 * @brief Verify the ADC channel setting in differential mode for ADC1. 786 * @param __CHANNEL__: programmed ADC channel. 787 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 788 */ 789 #define IS_ADC1_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 790 ((__CHANNEL__) == ADC_CHANNEL_2) ||\ 791 ((__CHANNEL__) == ADC_CHANNEL_3) ||\ 792 ((__CHANNEL__) == ADC_CHANNEL_4) ||\ 793 ((__CHANNEL__) == ADC_CHANNEL_5) ||\ 794 ((__CHANNEL__) == ADC_CHANNEL_10) ||\ 795 ((__CHANNEL__) == ADC_CHANNEL_11) ||\ 796 ((__CHANNEL__) == ADC_CHANNEL_12) ||\ 797 ((__CHANNEL__) == ADC_CHANNEL_16) ||\ 798 ((__CHANNEL__) == ADC_CHANNEL_18) ) 799 800 /** 801 * @brief Verify the ADC channel setting in differential mode for ADC2. 802 * @param __CHANNEL__: programmed ADC channel. 803 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 804 */ 805 #define IS_ADC2_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 806 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 807 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 808 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 809 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 810 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 811 ((__CHANNEL__) == ADC_CHANNEL_18) ) 812 813 /** 814 * @brief Verify the ADC single-ended input or differential mode setting. 815 * @param __SING_DIFF__ programmed channel setting. 816 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 817 */ 818 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 819 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 820 821 /** 822 * @brief Verify the ADC offset management setting. 823 * @param __OFFSET_NUMBER__ ADC offset management. 824 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 825 */ 826 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 827 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 828 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 829 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 830 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 831 832 /** 833 * @brief Verify the ADC injected channel setting. 834 * @param __CHANNEL__ programmed ADC injected channel. 835 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 836 */ 837 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 838 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 839 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 840 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 841 842 /** 843 * @brief Verify the ADC injected conversions external trigger. 844 * @param __INJTRIG__ programmed ADC injected conversions external trigger. 845 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) 846 */ 847 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 848 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 849 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 850 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 851 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 852 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 853 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 854 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 855 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 856 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 857 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 858 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 859 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 860 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 861 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 862 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 863 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \ 864 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \ 865 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \ 866 \ 867 ((__INJTRIG__) == ADC_SOFTWARE_START) ) 868 869 /** 870 * @brief Verify the ADC edge trigger setting for injected group. 871 * @param __EDGE__ programmed ADC edge trigger setting. 872 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 873 */ 874 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 875 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 876 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 877 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 878 879 #if defined(ADC_MULTIMODE_SUPPORT) 880 /** 881 * @brief Verify the ADC multimode setting. 882 * @param __MODE__ programmed ADC multimode setting. 883 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 884 */ 885 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ 886 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 887 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 888 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 889 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ 890 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ 891 ((__MODE__) == ADC_DUALMODE_INTERL) || \ 892 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) 893 894 /** 895 * @brief Verify the ADC dual data mode setting. 896 * @param MODE: programmed ADC dual mode setting. 897 * @retval SET (MODE is valid) or RESET (MODE is invalid) 898 */ 899 #define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED) || \ 900 ((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \ 901 ((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS) ) 902 903 /** 904 * @brief Verify the ADC multimode delay setting. 905 * @param __DELAY__ programmed ADC multimode delay setting. 906 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) 907 */ 908 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 909 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 910 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 911 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 912 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 913 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 914 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 915 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) ) 916 #endif /* ADC_MULTIMODE_SUPPORT */ 917 918 /** 919 * @brief Verify the ADC analog watchdog setting. 920 * @param __WATCHDOG__ programmed ADC analog watchdog setting. 921 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 922 */ 923 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 924 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 925 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 926 927 /** 928 * @brief Verify the ADC analog watchdog mode setting. 929 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. 930 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 931 */ 932 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 933 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 934 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 935 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 936 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 937 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 938 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 939 940 /** 941 * @brief Verify the ADC conversion (regular or injected or both). 942 * @param __CONVERSION__ ADC conversion group. 943 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 944 */ 945 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 946 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 947 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 948 949 /** 950 * @brief Verify the ADC event type. 951 * @param __EVENT__ ADC event. 952 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 953 */ 954 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 955 ((__EVENT__) == ADC_AWD_EVENT) || \ 956 ((__EVENT__) == ADC_AWD2_EVENT) || \ 957 ((__EVENT__) == ADC_AWD3_EVENT) || \ 958 ((__EVENT__) == ADC_OVR_EVENT) || \ 959 ((__EVENT__) == ADC_JQOVF_EVENT) ) 960 961 /** 962 * @brief Verify the ADC oversampling ratio. 963 * @param RATIO: programmed ADC oversampling ratio. 964 * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid) 965 */ 966 #define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) >= 1UL) && ((RATIO) <= 1024UL)) 967 968 /** 969 * @brief Verify the ADC oversampling shift. 970 * @param __SHIFT__ programmed ADC oversampling shift. 971 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 972 */ 973 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 974 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 975 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 976 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 977 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 978 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 979 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 980 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 981 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) 982 983 /** 984 * @brief Verify the ADC oversampling triggered mode. 985 * @param __MODE__ programmed ADC oversampling triggered mode. 986 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 987 */ 988 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 989 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 990 991 /** 992 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 993 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. 994 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 995 */ 996 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 997 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 998 999 /** 1000 * @brief Verify the DFSDM mode configuration. 1001 * @param __HANDLE__ ADC handle. 1002 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For 1003 * this reason, the input parameter is the ADC handle and not the configuration parameter 1004 * directly. 1005 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) 1006 */ 1007 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) 1008 1009 /** 1010 * @brief Return the DFSDM configuration mode. 1011 * @param __HANDLE__ ADC handle. 1012 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). 1013 * For this reason, the input parameter is the ADC handle and not the configuration parameter 1014 * directly. 1015 * @retval DFSDM configuration mode 1016 */ 1017 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) 1018 1019 /** 1020 * @} 1021 */ 1022 1023 1024 /* Exported functions --------------------------------------------------------*/ 1025 /** @addtogroup ADCEx_Exported_Functions 1026 * @{ 1027 */ 1028 1029 /** @addtogroup ADCEx_Exported_Functions_Group1 1030 * @{ 1031 */ 1032 /* IO operation functions *****************************************************/ 1033 1034 /* ADC calibration */ 1035 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff); 1036 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1037 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer); 1038 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); 1039 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer); 1040 1041 /* Blocking mode: Polling */ 1042 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); 1043 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); 1044 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1045 1046 /* Non-blocking mode: Interruption */ 1047 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); 1048 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); 1049 1050 #if defined(ADC_MULTIMODE_SUPPORT) 1051 /* ADC multimode */ 1052 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1053 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1054 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); 1055 #endif /* ADC_MULTIMODE_SUPPORT */ 1056 1057 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1058 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); 1059 1060 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 1061 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); 1062 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); 1063 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); 1064 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); 1065 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); 1066 1067 /* ADC group regular conversions stop */ 1068 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); 1069 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); 1070 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); 1071 #if defined(ADC_MULTIMODE_SUPPORT) 1072 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1073 #endif /* ADC_MULTIMODE_SUPPORT */ 1074 1075 /** 1076 * @} 1077 */ 1078 1079 /** @addtogroup ADCEx_Exported_Functions_Group2 1080 * @{ 1081 */ 1082 /* Peripheral Control functions ***********************************************/ 1083 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, 1084 ADC_InjectionConfTypeDef *sConfigInjected); 1085 #if defined(ADC_MULTIMODE_SUPPORT) 1086 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); 1087 #endif /* ADC_MULTIMODE_SUPPORT */ 1088 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); 1089 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); 1090 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); 1091 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); 1092 1093 /** 1094 * @} 1095 */ 1096 1097 /** 1098 * @} 1099 */ 1100 1101 /** 1102 * @} 1103 */ 1104 1105 /** 1106 * @} 1107 */ 1108 1109 #ifdef __cplusplus 1110 } 1111 #endif 1112 1113 #endif /* STM32MP1xx_HAL_ADC_EX_H */ 1114 1115 1116 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1117