1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 /*++
16 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
17
18 Module Name:
19 HalPwrSeqCmd.c
20
21 Abstract:
22 Implement HW Power sequence configuration CMD handling routine for Realtek devices.
23
24 Major Change History:
25 When Who What
26 ---------- --------------- -------------------------------
27 2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
28 2011-07-07 Roger Create.
29
30 --*/
31 #include <HalPwrSeqCmd.h>
32
33
34 /*
35 * Description:
36 * This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
37 *
38 * Assumption:
39 * We should follow specific format which was released from HW SD.
40 *
41 * 2011.07.07, added by Roger.
42 * */
HalPwrSeqCmdParsing(PADAPTER padapter,u8 CutVersion,u8 FabVersion,u8 InterfaceType,WLAN_PWR_CFG PwrSeqCmd[])43 u8 HalPwrSeqCmdParsing(
44 PADAPTER padapter,
45 u8 CutVersion,
46 u8 FabVersion,
47 u8 InterfaceType,
48 WLAN_PWR_CFG PwrSeqCmd[])
49 {
50 WLAN_PWR_CFG PwrCfgCmd = {0};
51 u8 bPollingBit = _FALSE;
52 u8 bHWICSupport = _FALSE;
53 u32 AryIdx = 0;
54 u8 value = 0;
55 u32 offset = 0;
56 u8 flag = 0;
57 u32 pollingCount = 0; /* polling autoload done. */
58 u32 maxPollingCnt = 5000;
59
60 do {
61 PwrCfgCmd = PwrSeqCmd[AryIdx];
62
63
64 /* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
65 if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
66 (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
67 (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {
68 switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
69 case PWR_CMD_READ:
70 break;
71
72 case PWR_CMD_WRITE:
73 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
74
75 #ifdef CONFIG_SDIO_HCI
76 /* */
77 /* <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */
78 /* 2011.07.07. */
79 /* */
80 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
81 /* Read Back SDIO Local value */
82 value = SdioLocalCmd52Read1Byte(padapter, offset);
83
84 value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
85 value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
86
87 /* Write Back SDIO Local value */
88 SdioLocalCmd52Write1Byte(padapter, offset, value);
89 } else
90 #endif
91 {
92 #ifdef CONFIG_GSPI_HCI
93 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
94 offset = SPI_LOCAL_OFFSET | offset;
95 #endif
96 /* Read the value from system register */
97 value = rtw_read8(padapter, offset);
98
99 value = value & (~(GET_PWR_CFG_MASK(PwrCfgCmd)));
100 value = value | (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
101
102 /* Write the value back to sytem register */
103 rtw_write8(padapter, offset, value);
104 }
105 break;
106
107 case PWR_CMD_POLLING:
108
109 bPollingBit = _FALSE;
110 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
111
112 rtw_hal_get_hwreg(padapter, HW_VAR_PWR_CMD, &bHWICSupport);
113 if (bHWICSupport && offset == 0x06) {
114 flag = 0;
115 maxPollingCnt = 100000;
116 } else
117 maxPollingCnt = 5000;
118
119 #ifdef CONFIG_GSPI_HCI
120 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
121 offset = SPI_LOCAL_OFFSET | offset;
122 #endif
123 do {
124 #ifdef CONFIG_SDIO_HCI
125 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
126 value = SdioLocalCmd52Read1Byte(padapter, offset);
127 else
128 #endif
129 value = rtw_read8(padapter, offset);
130
131 value = value & GET_PWR_CFG_MASK(PwrCfgCmd);
132 if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
133 bPollingBit = _TRUE;
134 else
135 rtw_udelay_os(10);
136
137 if (pollingCount++ > maxPollingCnt) {
138 RTW_ERR("HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
139
140 /* For PCIE + USB package poll power bit timeout issue only modify 8821AE and 8723BE */
141 if (bHWICSupport && offset == 0x06 && flag == 0) {
142
143 RTW_ERR("[WARNING] PCIE polling(0x%X) timeout(%d), Toggle 0x04[3] and try again.\n", offset, maxPollingCnt);
144 if (IS_HARDWARE_TYPE_8723DE(padapter))
145 PlatformEFIOWrite1Byte(padapter, 0x40, (PlatformEFIORead1Byte(padapter, 0x40)) & (~BIT3));
146
147 PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) | BIT3);
148 PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) & ~BIT3);
149
150 if (IS_HARDWARE_TYPE_8723DE(padapter))
151 PlatformEFIOWrite1Byte(padapter, 0x40, PlatformEFIORead1Byte(padapter, 0x40)|BIT3);
152
153 /* Retry Polling Process one more time */
154 pollingCount = 0;
155 flag = 1;
156 } else {
157 return _FALSE;
158 }
159 }
160 } while (!bPollingBit);
161
162 break;
163
164 case PWR_CMD_DELAY:
165 if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
166 rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
167 else
168 rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd) * 1000);
169 break;
170
171 case PWR_CMD_END:
172 /* When this command is parsed, end the process */
173 return _TRUE;
174 break;
175
176 default:
177 break;
178 }
179 }
180
181 AryIdx++;/* Add Array Index */
182 } while (1);
183
184 return _TRUE;
185 }
186