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1 /*
2  * Copyright (c) 2021-2023 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SDP_H
10 #define HPM_SDP_H
11 
12 typedef struct {
13     __RW uint32_t SDPCR;                       /* 0x0: SDP control register */
14     __RW uint32_t MODCTRL;                     /* 0x4: Mod control register. */
15     __RW uint32_t PKTCNT;                      /* 0x8: packet counter registers. */
16     __RW uint32_t STA;                         /* 0xC: Status Registers */
17     __RW uint32_t KEYADDR;                     /* 0x10: Key Address */
18     __RW uint32_t KEYDAT;                      /* 0x14: Key Data */
19     __RW uint32_t CIPHIV[4];                   /* 0x18 - 0x24: Cipher Initializtion Vector 0 */
20     __RW uint32_t HASWRD[8];                   /* 0x28 - 0x44: Hash Data Word 0 */
21     __RW uint32_t CMDPTR;                      /* 0x48: Command Pointer */
22     __RW uint32_t NPKTPTR;                     /* 0x4C: Next Packet Address Pointer */
23     __RW uint32_t PKTCTL;                      /* 0x50: Packet Control Registers */
24     __RW uint32_t PKTSRC;                      /* 0x54: Packet Memory Source Address */
25     __RW uint32_t PKTDST;                      /* 0x58: Packet Memory Destination Address */
26     __RW uint32_t PKTBUF;                      /* 0x5C: Packet buffer size. */
27 } SDP_Type;
28 
29 
30 /* Bitfield definition for register: SDPCR */
31 /*
32  * SFTRST (RW)
33  *
34  * soft reset.
35  * Write 1 then 0, to reset the SDP block.
36  */
37 #define SDP_SDPCR_SFTRST_MASK (0x80000000UL)
38 #define SDP_SDPCR_SFTRST_SHIFT (31U)
39 #define SDP_SDPCR_SFTRST_SET(x) (((uint32_t)(x) << SDP_SDPCR_SFTRST_SHIFT) & SDP_SDPCR_SFTRST_MASK)
40 #define SDP_SDPCR_SFTRST_GET(x) (((uint32_t)(x) & SDP_SDPCR_SFTRST_MASK) >> SDP_SDPCR_SFTRST_SHIFT)
41 
42 /*
43  * CLKGAT (RW)
44  *
45  * Clock Gate for the SDP main logic.
46  * Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block.
47  */
48 #define SDP_SDPCR_CLKGAT_MASK (0x40000000UL)
49 #define SDP_SDPCR_CLKGAT_SHIFT (30U)
50 #define SDP_SDPCR_CLKGAT_SET(x) (((uint32_t)(x) << SDP_SDPCR_CLKGAT_SHIFT) & SDP_SDPCR_CLKGAT_MASK)
51 #define SDP_SDPCR_CLKGAT_GET(x) (((uint32_t)(x) & SDP_SDPCR_CLKGAT_MASK) >> SDP_SDPCR_CLKGAT_SHIFT)
52 
53 /*
54  * CIPDIS (RO)
55  *
56  * Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not.
57  * 1, Cipher is disabled in this chip.
58  * 0, Cipher is enabled in this chip.
59  */
60 #define SDP_SDPCR_CIPDIS_MASK (0x20000000UL)
61 #define SDP_SDPCR_CIPDIS_SHIFT (29U)
62 #define SDP_SDPCR_CIPDIS_GET(x) (((uint32_t)(x) & SDP_SDPCR_CIPDIS_MASK) >> SDP_SDPCR_CIPDIS_SHIFT)
63 
64 /*
65  * HASDIS (RO)
66  *
67  * HASH Disable, read the info, whether the HASH features is besing disable in this chip or not.
68  * 1, HASH is disabled in this chip.
69  * 0, HASH is enabled in this chip.
70  */
71 #define SDP_SDPCR_HASDIS_MASK (0x10000000UL)
72 #define SDP_SDPCR_HASDIS_SHIFT (28U)
73 #define SDP_SDPCR_HASDIS_GET(x) (((uint32_t)(x) & SDP_SDPCR_HASDIS_MASK) >> SDP_SDPCR_HASDIS_SHIFT)
74 
75 /*
76  * CIPHEN (RW)
77  *
78  * Cipher Enablement, controlled by SW.
79  * 1, Cipher is Enabled.
80  * 0, Cipher is Disabled.
81  */
82 #define SDP_SDPCR_CIPHEN_MASK (0x800000UL)
83 #define SDP_SDPCR_CIPHEN_SHIFT (23U)
84 #define SDP_SDPCR_CIPHEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_CIPHEN_SHIFT) & SDP_SDPCR_CIPHEN_MASK)
85 #define SDP_SDPCR_CIPHEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_CIPHEN_MASK) >> SDP_SDPCR_CIPHEN_SHIFT)
86 
87 /*
88  * HASHEN (RW)
89  *
90  * HASH Enablement, controlled by SW.
91  * 1, HASH is Enabled.
92  * 0, HASH is Disabled.
93  */
94 #define SDP_SDPCR_HASHEN_MASK (0x400000UL)
95 #define SDP_SDPCR_HASHEN_SHIFT (22U)
96 #define SDP_SDPCR_HASHEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_HASHEN_SHIFT) & SDP_SDPCR_HASHEN_MASK)
97 #define SDP_SDPCR_HASHEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_HASHEN_MASK) >> SDP_SDPCR_HASHEN_SHIFT)
98 
99 /*
100  * MCPEN (RW)
101  *
102  * Memory Copy Enablement, controlled by SW.
103  * 1, Memory copy is Enabled.
104  * 0, Memory copy is Disabled.
105  */
106 #define SDP_SDPCR_MCPEN_MASK (0x200000UL)
107 #define SDP_SDPCR_MCPEN_SHIFT (21U)
108 #define SDP_SDPCR_MCPEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_MCPEN_SHIFT) & SDP_SDPCR_MCPEN_MASK)
109 #define SDP_SDPCR_MCPEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_MCPEN_MASK) >> SDP_SDPCR_MCPEN_SHIFT)
110 
111 /*
112  * CONFEN (RW)
113  *
114  * Constant Fill to memory, controlled by SW.
115  * 1, Constant fill is Enabled.
116  * 0, Constant fill is Disabled.
117  */
118 #define SDP_SDPCR_CONFEN_MASK (0x100000UL)
119 #define SDP_SDPCR_CONFEN_SHIFT (20U)
120 #define SDP_SDPCR_CONFEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_CONFEN_SHIFT) & SDP_SDPCR_CONFEN_MASK)
121 #define SDP_SDPCR_CONFEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_CONFEN_MASK) >> SDP_SDPCR_CONFEN_SHIFT)
122 
123 /*
124  * DCRPDI (RW)
125  *
126  * Decryption Disable bit, Write to 1 to disable the decryption.
127  */
128 #define SDP_SDPCR_DCRPDI_MASK (0x80000UL)
129 #define SDP_SDPCR_DCRPDI_SHIFT (19U)
130 #define SDP_SDPCR_DCRPDI_SET(x) (((uint32_t)(x) << SDP_SDPCR_DCRPDI_SHIFT) & SDP_SDPCR_DCRPDI_MASK)
131 #define SDP_SDPCR_DCRPDI_GET(x) (((uint32_t)(x) & SDP_SDPCR_DCRPDI_MASK) >> SDP_SDPCR_DCRPDI_SHIFT)
132 
133 /*
134  * TSTPKT0IRQ (RW)
135  *
136  * Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet.
137  */
138 #define SDP_SDPCR_TSTPKT0IRQ_MASK (0x20000UL)
139 #define SDP_SDPCR_TSTPKT0IRQ_SHIFT (17U)
140 #define SDP_SDPCR_TSTPKT0IRQ_SET(x) (((uint32_t)(x) << SDP_SDPCR_TSTPKT0IRQ_SHIFT) & SDP_SDPCR_TSTPKT0IRQ_MASK)
141 #define SDP_SDPCR_TSTPKT0IRQ_GET(x) (((uint32_t)(x) & SDP_SDPCR_TSTPKT0IRQ_MASK) >> SDP_SDPCR_TSTPKT0IRQ_SHIFT)
142 
143 /*
144  * RDSCEN (RW)
145  *
146  * when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...)
147  * when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR)
148  */
149 #define SDP_SDPCR_RDSCEN_MASK (0x100U)
150 #define SDP_SDPCR_RDSCEN_SHIFT (8U)
151 #define SDP_SDPCR_RDSCEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_RDSCEN_SHIFT) & SDP_SDPCR_RDSCEN_MASK)
152 #define SDP_SDPCR_RDSCEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_RDSCEN_MASK) >> SDP_SDPCR_RDSCEN_SHIFT)
153 
154 /*
155  * INTEN (RW)
156  *
157  * Interrupt Enablement, controlled by SW.
158  * 1, SDP interrupt is enabled.
159  * 0, SDP interrupt is disabled.
160  */
161 #define SDP_SDPCR_INTEN_MASK (0x1U)
162 #define SDP_SDPCR_INTEN_SHIFT (0U)
163 #define SDP_SDPCR_INTEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_INTEN_SHIFT) & SDP_SDPCR_INTEN_MASK)
164 #define SDP_SDPCR_INTEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_INTEN_MASK) >> SDP_SDPCR_INTEN_SHIFT)
165 
166 /* Bitfield definition for register: MODCTRL */
167 /*
168  * AESALG (RW)
169  *
170  * AES algorithem selection.
171  * 0x0 = AES 128;
172  * 0x1 = AES 256;
173  * 0x8 = SM4；
174  * Others, reserved.
175  */
176 #define SDP_MODCTRL_AESALG_MASK (0xF0000000UL)
177 #define SDP_MODCTRL_AESALG_SHIFT (28U)
178 #define SDP_MODCTRL_AESALG_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESALG_SHIFT) & SDP_MODCTRL_AESALG_MASK)
179 #define SDP_MODCTRL_AESALG_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESALG_MASK) >> SDP_MODCTRL_AESALG_SHIFT)
180 
181 /*
182  * AESMOD (RW)
183  *
184  * AES mode selection.
185  * 0x0 = ECB;
186  * 0x1 = CBC;
187  * Others, reserved.
188  */
189 #define SDP_MODCTRL_AESMOD_MASK (0xF000000UL)
190 #define SDP_MODCTRL_AESMOD_SHIFT (24U)
191 #define SDP_MODCTRL_AESMOD_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESMOD_SHIFT) & SDP_MODCTRL_AESMOD_MASK)
192 #define SDP_MODCTRL_AESMOD_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESMOD_MASK) >> SDP_MODCTRL_AESMOD_SHIFT)
193 
194 /*
195  * AESKS (RW)
196  *
197  * AES Key Selection.
198  * These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following:
199  * 0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key.
200  * 0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286.
201  * ....
202  * 0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key.
203  * 0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286.
204  * 0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key.
205  * 0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256.
206  * 0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key.
207  * 0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256.
208  * 0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key.
209  * 0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256.
210  * 0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key.
211  * 0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256.
212  * 0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key.
213  * 0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256.
214  * 0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key.
215  * 0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256.
216  * Other values, reserved.
217  */
218 #define SDP_MODCTRL_AESKS_MASK (0xFC0000UL)
219 #define SDP_MODCTRL_AESKS_SHIFT (18U)
220 #define SDP_MODCTRL_AESKS_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESKS_SHIFT) & SDP_MODCTRL_AESKS_MASK)
221 #define SDP_MODCTRL_AESKS_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESKS_MASK) >> SDP_MODCTRL_AESKS_SHIFT)
222 
223 /*
224  * AESDIR (RW)
225  *
226  * AES direction
227  * 1x1, AES Decryption
228  * 1x0, AES Encryption.
229  */
230 #define SDP_MODCTRL_AESDIR_MASK (0x10000UL)
231 #define SDP_MODCTRL_AESDIR_SHIFT (16U)
232 #define SDP_MODCTRL_AESDIR_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESDIR_SHIFT) & SDP_MODCTRL_AESDIR_MASK)
233 #define SDP_MODCTRL_AESDIR_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESDIR_MASK) >> SDP_MODCTRL_AESDIR_SHIFT)
234 
235 /*
236  * HASALG (RW)
237  *
238  * HASH Algorithem selection.
239  * 0x0 SHA1 —
240  * 0x1 CRC32 —
241  * 0x2 SHA256 —
242  */
243 #define SDP_MODCTRL_HASALG_MASK (0xF000U)
244 #define SDP_MODCTRL_HASALG_SHIFT (12U)
245 #define SDP_MODCTRL_HASALG_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASALG_SHIFT) & SDP_MODCTRL_HASALG_MASK)
246 #define SDP_MODCTRL_HASALG_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASALG_MASK) >> SDP_MODCTRL_HASALG_SHIFT)
247 
248 /*
249  * CRCEN (RW)
250  *
251  * CRC enable.
252  * 1x1, CRC is enabled.
253  * 1x0, CRC is disabled.
254  */
255 #define SDP_MODCTRL_CRCEN_MASK (0x800U)
256 #define SDP_MODCTRL_CRCEN_SHIFT (11U)
257 #define SDP_MODCTRL_CRCEN_SET(x) (((uint32_t)(x) << SDP_MODCTRL_CRCEN_SHIFT) & SDP_MODCTRL_CRCEN_MASK)
258 #define SDP_MODCTRL_CRCEN_GET(x) (((uint32_t)(x) & SDP_MODCTRL_CRCEN_MASK) >> SDP_MODCTRL_CRCEN_SHIFT)
259 
260 /*
261  * HASCHK (RW)
262  *
263  * HASH Check Enable Bit.
264  * 1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers;
265  * 1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result.
266  * For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words.
267  */
268 #define SDP_MODCTRL_HASCHK_MASK (0x400U)
269 #define SDP_MODCTRL_HASCHK_SHIFT (10U)
270 #define SDP_MODCTRL_HASCHK_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASCHK_SHIFT) & SDP_MODCTRL_HASCHK_MASK)
271 #define SDP_MODCTRL_HASCHK_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASCHK_MASK) >> SDP_MODCTRL_HASCHK_SHIFT)
272 
273 /*
274  * HASOUT (RW)
275  *
276  * When hashing is enabled, this bit controls the input or output data of the AES engine is hashed.
277  * 0 INPUT HASH
278  * 1 OUTPUT HASH
279  */
280 #define SDP_MODCTRL_HASOUT_MASK (0x200U)
281 #define SDP_MODCTRL_HASOUT_SHIFT (9U)
282 #define SDP_MODCTRL_HASOUT_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASOUT_SHIFT) & SDP_MODCTRL_HASOUT_MASK)
283 #define SDP_MODCTRL_HASOUT_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASOUT_MASK) >> SDP_MODCTRL_HASOUT_SHIFT)
284 
285 /*
286  * DINSWP (RW)
287  *
288  * Decide whether the SDP byteswaps the input data (big-endian data);
289  * When all bits are set, the data is assumed to be in the big-endian format
290  */
291 #define SDP_MODCTRL_DINSWP_MASK (0x30U)
292 #define SDP_MODCTRL_DINSWP_SHIFT (4U)
293 #define SDP_MODCTRL_DINSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_DINSWP_SHIFT) & SDP_MODCTRL_DINSWP_MASK)
294 #define SDP_MODCTRL_DINSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_DINSWP_MASK) >> SDP_MODCTRL_DINSWP_SHIFT)
295 
296 /*
297  * DOUTSWP (RW)
298  *
299  * Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format
300  */
301 #define SDP_MODCTRL_DOUTSWP_MASK (0xCU)
302 #define SDP_MODCTRL_DOUTSWP_SHIFT (2U)
303 #define SDP_MODCTRL_DOUTSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_DOUTSWP_SHIFT) & SDP_MODCTRL_DOUTSWP_MASK)
304 #define SDP_MODCTRL_DOUTSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_DOUTSWP_MASK) >> SDP_MODCTRL_DOUTSWP_SHIFT)
305 
306 /*
307  * KEYSWP (RW)
308  *
309  * Decide whether the SDP byteswaps the Key (big-endian data).
310  * When all bits are set, the data is assumed to be in the big-endian format
311  */
312 #define SDP_MODCTRL_KEYSWP_MASK (0x3U)
313 #define SDP_MODCTRL_KEYSWP_SHIFT (0U)
314 #define SDP_MODCTRL_KEYSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_KEYSWP_SHIFT) & SDP_MODCTRL_KEYSWP_MASK)
315 #define SDP_MODCTRL_KEYSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_KEYSWP_MASK) >> SDP_MODCTRL_KEYSWP_SHIFT)
316 
317 /* Bitfield definition for register: PKTCNT */
318 /*
319  * CNTVAL (RO)
320  *
321  * This read-only field shows the current (instantaneous) value of the packet counter
322  */
323 #define SDP_PKTCNT_CNTVAL_MASK (0xFF0000UL)
324 #define SDP_PKTCNT_CNTVAL_SHIFT (16U)
325 #define SDP_PKTCNT_CNTVAL_GET(x) (((uint32_t)(x) & SDP_PKTCNT_CNTVAL_MASK) >> SDP_PKTCNT_CNTVAL_SHIFT)
326 
327 /*
328  * CNTINCR (RW)
329  *
330  * The value written to this field is added to the spacket count.
331  */
332 #define SDP_PKTCNT_CNTINCR_MASK (0xFFU)
333 #define SDP_PKTCNT_CNTINCR_SHIFT (0U)
334 #define SDP_PKTCNT_CNTINCR_SET(x) (((uint32_t)(x) << SDP_PKTCNT_CNTINCR_SHIFT) & SDP_PKTCNT_CNTINCR_MASK)
335 #define SDP_PKTCNT_CNTINCR_GET(x) (((uint32_t)(x) & SDP_PKTCNT_CNTINCR_MASK) >> SDP_PKTCNT_CNTINCR_SHIFT)
336 
337 /* Bitfield definition for register: STA */
338 /*
339  * TAG (RO)
340  *
341  * packet tag.
342  */
343 #define SDP_STA_TAG_MASK (0xFF000000UL)
344 #define SDP_STA_TAG_SHIFT (24U)
345 #define SDP_STA_TAG_GET(x) (((uint32_t)(x) & SDP_STA_TAG_MASK) >> SDP_STA_TAG_SHIFT)
346 
347 /*
348  * IRQ (W1C)
349  *
350  * interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero.
351  */
352 #define SDP_STA_IRQ_MASK (0x800000UL)
353 #define SDP_STA_IRQ_SHIFT (23U)
354 #define SDP_STA_IRQ_SET(x) (((uint32_t)(x) << SDP_STA_IRQ_SHIFT) & SDP_STA_IRQ_MASK)
355 #define SDP_STA_IRQ_GET(x) (((uint32_t)(x) & SDP_STA_IRQ_MASK) >> SDP_STA_IRQ_SHIFT)
356 
357 /*
358  * CHN1PKT0 (W1C)
359  *
360  * the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data.
361  */
362 #define SDP_STA_CHN1PKT0_MASK (0x100000UL)
363 #define SDP_STA_CHN1PKT0_SHIFT (20U)
364 #define SDP_STA_CHN1PKT0_SET(x) (((uint32_t)(x) << SDP_STA_CHN1PKT0_SHIFT) & SDP_STA_CHN1PKT0_MASK)
365 #define SDP_STA_CHN1PKT0_GET(x) (((uint32_t)(x) & SDP_STA_CHN1PKT0_MASK) >> SDP_STA_CHN1PKT0_SHIFT)
366 
367 /*
368  * AESBSY (RO)
369  *
370  * AES Busy
371  */
372 #define SDP_STA_AESBSY_MASK (0x80000UL)
373 #define SDP_STA_AESBSY_SHIFT (19U)
374 #define SDP_STA_AESBSY_GET(x) (((uint32_t)(x) & SDP_STA_AESBSY_MASK) >> SDP_STA_AESBSY_SHIFT)
375 
376 /*
377  * HASBSY (RO)
378  *
379  * Hashing Busy
380  */
381 #define SDP_STA_HASBSY_MASK (0x40000UL)
382 #define SDP_STA_HASBSY_SHIFT (18U)
383 #define SDP_STA_HASBSY_GET(x) (((uint32_t)(x) & SDP_STA_HASBSY_MASK) >> SDP_STA_HASBSY_SHIFT)
384 
385 /*
386  * PKTCNT0 (W1C)
387  *
388  * Packet Counter registers reachs to ZERO now.
389  */
390 #define SDP_STA_PKTCNT0_MASK (0x20000UL)
391 #define SDP_STA_PKTCNT0_SHIFT (17U)
392 #define SDP_STA_PKTCNT0_SET(x) (((uint32_t)(x) << SDP_STA_PKTCNT0_SHIFT) & SDP_STA_PKTCNT0_MASK)
393 #define SDP_STA_PKTCNT0_GET(x) (((uint32_t)(x) & SDP_STA_PKTCNT0_MASK) >> SDP_STA_PKTCNT0_SHIFT)
394 
395 /*
396  * PKTDON (W1C)
397  *
398  * Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word.
399  */
400 #define SDP_STA_PKTDON_MASK (0x10000UL)
401 #define SDP_STA_PKTDON_SHIFT (16U)
402 #define SDP_STA_PKTDON_SET(x) (((uint32_t)(x) << SDP_STA_PKTDON_SHIFT) & SDP_STA_PKTDON_MASK)
403 #define SDP_STA_PKTDON_GET(x) (((uint32_t)(x) & SDP_STA_PKTDON_MASK) >> SDP_STA_PKTDON_SHIFT)
404 
405 /*
406  * ERRSET (W1C)
407  *
408  * Working mode setup error.
409  */
410 #define SDP_STA_ERRSET_MASK (0x20U)
411 #define SDP_STA_ERRSET_SHIFT (5U)
412 #define SDP_STA_ERRSET_SET(x) (((uint32_t)(x) << SDP_STA_ERRSET_SHIFT) & SDP_STA_ERRSET_MASK)
413 #define SDP_STA_ERRSET_GET(x) (((uint32_t)(x) & SDP_STA_ERRSET_MASK) >> SDP_STA_ERRSET_SHIFT)
414 
415 /*
416  * ERRPKT (W1C)
417  *
418  * Packet head access error, or status update error.
419  */
420 #define SDP_STA_ERRPKT_MASK (0x10U)
421 #define SDP_STA_ERRPKT_SHIFT (4U)
422 #define SDP_STA_ERRPKT_SET(x) (((uint32_t)(x) << SDP_STA_ERRPKT_SHIFT) & SDP_STA_ERRPKT_MASK)
423 #define SDP_STA_ERRPKT_GET(x) (((uint32_t)(x) & SDP_STA_ERRPKT_MASK) >> SDP_STA_ERRPKT_SHIFT)
424 
425 /*
426  * ERRSRC (W1C)
427  *
428  * Source Buffer Access Error
429  */
430 #define SDP_STA_ERRSRC_MASK (0x8U)
431 #define SDP_STA_ERRSRC_SHIFT (3U)
432 #define SDP_STA_ERRSRC_SET(x) (((uint32_t)(x) << SDP_STA_ERRSRC_SHIFT) & SDP_STA_ERRSRC_MASK)
433 #define SDP_STA_ERRSRC_GET(x) (((uint32_t)(x) & SDP_STA_ERRSRC_MASK) >> SDP_STA_ERRSRC_SHIFT)
434 
435 /*
436  * ERRDST (W1C)
437  *
438  * Destination Buffer Error
439  */
440 #define SDP_STA_ERRDST_MASK (0x4U)
441 #define SDP_STA_ERRDST_SHIFT (2U)
442 #define SDP_STA_ERRDST_SET(x) (((uint32_t)(x) << SDP_STA_ERRDST_SHIFT) & SDP_STA_ERRDST_MASK)
443 #define SDP_STA_ERRDST_GET(x) (((uint32_t)(x) & SDP_STA_ERRDST_MASK) >> SDP_STA_ERRDST_SHIFT)
444 
445 /*
446  * ERRHAS (W1C)
447  *
448  * Hashing Check Error
449  */
450 #define SDP_STA_ERRHAS_MASK (0x2U)
451 #define SDP_STA_ERRHAS_SHIFT (1U)
452 #define SDP_STA_ERRHAS_SET(x) (((uint32_t)(x) << SDP_STA_ERRHAS_SHIFT) & SDP_STA_ERRHAS_MASK)
453 #define SDP_STA_ERRHAS_GET(x) (((uint32_t)(x) & SDP_STA_ERRHAS_MASK) >> SDP_STA_ERRHAS_SHIFT)
454 
455 /*
456  * ERRCHAIN (W1C)
457  *
458  * buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero.
459  */
460 #define SDP_STA_ERRCHAIN_MASK (0x1U)
461 #define SDP_STA_ERRCHAIN_SHIFT (0U)
462 #define SDP_STA_ERRCHAIN_SET(x) (((uint32_t)(x) << SDP_STA_ERRCHAIN_SHIFT) & SDP_STA_ERRCHAIN_MASK)
463 #define SDP_STA_ERRCHAIN_GET(x) (((uint32_t)(x) & SDP_STA_ERRCHAIN_MASK) >> SDP_STA_ERRCHAIN_SHIFT)
464 
465 /* Bitfield definition for register: KEYADDR */
466 /*
467  * INDEX (RW)
468  *
469  * To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register.
470  * Key index pointer. The valid indices are 0-[number_keys].
471  * In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses.
472  */
473 #define SDP_KEYADDR_INDEX_MASK (0xFF0000UL)
474 #define SDP_KEYADDR_INDEX_SHIFT (16U)
475 #define SDP_KEYADDR_INDEX_SET(x) (((uint32_t)(x) << SDP_KEYADDR_INDEX_SHIFT) & SDP_KEYADDR_INDEX_MASK)
476 #define SDP_KEYADDR_INDEX_GET(x) (((uint32_t)(x) & SDP_KEYADDR_INDEX_MASK) >> SDP_KEYADDR_INDEX_SHIFT)
477 
478 /*
479  * SUBWRD (RW)
480  *
481  * Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field
482  * increments; To write a key, the software must first write the desired key index/subword to this register.
483  */
484 #define SDP_KEYADDR_SUBWRD_MASK (0x3U)
485 #define SDP_KEYADDR_SUBWRD_SHIFT (0U)
486 #define SDP_KEYADDR_SUBWRD_SET(x) (((uint32_t)(x) << SDP_KEYADDR_SUBWRD_SHIFT) & SDP_KEYADDR_SUBWRD_MASK)
487 #define SDP_KEYADDR_SUBWRD_GET(x) (((uint32_t)(x) & SDP_KEYADDR_SUBWRD_MASK) >> SDP_KEYADDR_SUBWRD_SHIFT)
488 
489 /* Bitfield definition for register: KEYDAT */
490 /*
491  * KEYDAT (RW)
492  *
493  * This register provides the write access to the key/key subword specified by the key index register.
494  * Writing this location updates the selected subword for the key located at the index
495  * specified by the key index register. The write also triggers the SUBWORD field of the
496  * KEY register to increment to the next higher word in the key
497  */
498 #define SDP_KEYDAT_KEYDAT_MASK (0xFFFFFFFFUL)
499 #define SDP_KEYDAT_KEYDAT_SHIFT (0U)
500 #define SDP_KEYDAT_KEYDAT_SET(x) (((uint32_t)(x) << SDP_KEYDAT_KEYDAT_SHIFT) & SDP_KEYDAT_KEYDAT_MASK)
501 #define SDP_KEYDAT_KEYDAT_GET(x) (((uint32_t)(x) & SDP_KEYDAT_KEYDAT_MASK) >> SDP_KEYDAT_KEYDAT_SHIFT)
502 
503 /* Bitfield definition for register array: CIPHIV */
504 /*
505  * CIPHIV (RW)
506  *
507  * cipher initialization vector.
508  */
509 #define SDP_CIPHIV_CIPHIV_MASK (0xFFFFFFFFUL)
510 #define SDP_CIPHIV_CIPHIV_SHIFT (0U)
511 #define SDP_CIPHIV_CIPHIV_SET(x) (((uint32_t)(x) << SDP_CIPHIV_CIPHIV_SHIFT) & SDP_CIPHIV_CIPHIV_MASK)
512 #define SDP_CIPHIV_CIPHIV_GET(x) (((uint32_t)(x) & SDP_CIPHIV_CIPHIV_MASK) >> SDP_CIPHIV_CIPHIV_SHIFT)
513 
514 /* Bitfield definition for register array: HASWRD */
515 /*
516  * HASWRD (RW)
517  *
518  * Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled,  the hash engine will store the final hash result[31:0] here.
519  * If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result.
520  */
521 #define SDP_HASWRD_HASWRD_MASK (0xFFFFFFFFUL)
522 #define SDP_HASWRD_HASWRD_SHIFT (0U)
523 #define SDP_HASWRD_HASWRD_SET(x) (((uint32_t)(x) << SDP_HASWRD_HASWRD_SHIFT) & SDP_HASWRD_HASWRD_MASK)
524 #define SDP_HASWRD_HASWRD_GET(x) (((uint32_t)(x) & SDP_HASWRD_HASWRD_MASK) >> SDP_HASWRD_HASWRD_SHIFT)
525 
526 /* Bitfield definition for register: CMDPTR */
527 /*
528  * CMDPTR (RW)
529  *
530  * current command addresses the register points to the multiword
531  * descriptor that is to be executed (or is currently being executed)
532  */
533 #define SDP_CMDPTR_CMDPTR_MASK (0xFFFFFFFFUL)
534 #define SDP_CMDPTR_CMDPTR_SHIFT (0U)
535 #define SDP_CMDPTR_CMDPTR_SET(x) (((uint32_t)(x) << SDP_CMDPTR_CMDPTR_SHIFT) & SDP_CMDPTR_CMDPTR_MASK)
536 #define SDP_CMDPTR_CMDPTR_GET(x) (((uint32_t)(x) & SDP_CMDPTR_CMDPTR_MASK) >> SDP_CMDPTR_CMDPTR_SHIFT)
537 
538 /* Bitfield definition for register: NPKTPTR */
539 /*
540  * NPKTPTR (RW)
541  *
542  * Next Packet Address Pointer
543  */
544 #define SDP_NPKTPTR_NPKTPTR_MASK (0xFFFFFFFFUL)
545 #define SDP_NPKTPTR_NPKTPTR_SHIFT (0U)
546 #define SDP_NPKTPTR_NPKTPTR_SET(x) (((uint32_t)(x) << SDP_NPKTPTR_NPKTPTR_SHIFT) & SDP_NPKTPTR_NPKTPTR_MASK)
547 #define SDP_NPKTPTR_NPKTPTR_GET(x) (((uint32_t)(x) & SDP_NPKTPTR_NPKTPTR_MASK) >> SDP_NPKTPTR_NPKTPTR_SHIFT)
548 
549 /* Bitfield definition for register: PKTCTL */
550 /*
551  * PKTTAG (RW)
552  *
553  * packet tag
554  */
555 #define SDP_PKTCTL_PKTTAG_MASK (0xFF000000UL)
556 #define SDP_PKTCTL_PKTTAG_SHIFT (24U)
557 #define SDP_PKTCTL_PKTTAG_SET(x) (((uint32_t)(x) << SDP_PKTCTL_PKTTAG_SHIFT) & SDP_PKTCTL_PKTTAG_MASK)
558 #define SDP_PKTCTL_PKTTAG_GET(x) (((uint32_t)(x) & SDP_PKTCTL_PKTTAG_MASK) >> SDP_PKTCTL_PKTTAG_SHIFT)
559 
560 /*
561  * CIPHIV (RW)
562  *
563  * Load Initial Vector for the AES in this packet.
564  */
565 #define SDP_PKTCTL_CIPHIV_MASK (0x40U)
566 #define SDP_PKTCTL_CIPHIV_SHIFT (6U)
567 #define SDP_PKTCTL_CIPHIV_SET(x) (((uint32_t)(x) << SDP_PKTCTL_CIPHIV_SHIFT) & SDP_PKTCTL_CIPHIV_MASK)
568 #define SDP_PKTCTL_CIPHIV_GET(x) (((uint32_t)(x) & SDP_PKTCTL_CIPHIV_MASK) >> SDP_PKTCTL_CIPHIV_SHIFT)
569 
570 /*
571  * HASFNL (RW)
572  *
573  * Hash Termination packet
574  */
575 #define SDP_PKTCTL_HASFNL_MASK (0x20U)
576 #define SDP_PKTCTL_HASFNL_SHIFT (5U)
577 #define SDP_PKTCTL_HASFNL_SET(x) (((uint32_t)(x) << SDP_PKTCTL_HASFNL_SHIFT) & SDP_PKTCTL_HASFNL_MASK)
578 #define SDP_PKTCTL_HASFNL_GET(x) (((uint32_t)(x) & SDP_PKTCTL_HASFNL_MASK) >> SDP_PKTCTL_HASFNL_SHIFT)
579 
580 /*
581  * HASINI (RW)
582  *
583  * Hash Initialization packat
584  */
585 #define SDP_PKTCTL_HASINI_MASK (0x10U)
586 #define SDP_PKTCTL_HASINI_SHIFT (4U)
587 #define SDP_PKTCTL_HASINI_SET(x) (((uint32_t)(x) << SDP_PKTCTL_HASINI_SHIFT) & SDP_PKTCTL_HASINI_MASK)
588 #define SDP_PKTCTL_HASINI_GET(x) (((uint32_t)(x) & SDP_PKTCTL_HASINI_MASK) >> SDP_PKTCTL_HASINI_SHIFT)
589 
590 /*
591  * CHAIN (RW)
592  *
593  * whether the next command pointer register must be loaded into the channel's current descriptor
594  * pointer.
595  */
596 #define SDP_PKTCTL_CHAIN_MASK (0x8U)
597 #define SDP_PKTCTL_CHAIN_SHIFT (3U)
598 #define SDP_PKTCTL_CHAIN_SET(x) (((uint32_t)(x) << SDP_PKTCTL_CHAIN_SHIFT) & SDP_PKTCTL_CHAIN_MASK)
599 #define SDP_PKTCTL_CHAIN_GET(x) (((uint32_t)(x) & SDP_PKTCTL_CHAIN_MASK) >> SDP_PKTCTL_CHAIN_SHIFT)
600 
601 /*
602  * DCRSEMA (RW)
603  *
604  * whether the channel's semaphore must be decremented at the end of the current operation.
605  * When the semaphore reaches a value of zero, no more operations are issued from the channel.
606  */
607 #define SDP_PKTCTL_DCRSEMA_MASK (0x4U)
608 #define SDP_PKTCTL_DCRSEMA_SHIFT (2U)
609 #define SDP_PKTCTL_DCRSEMA_SET(x) (((uint32_t)(x) << SDP_PKTCTL_DCRSEMA_SHIFT) & SDP_PKTCTL_DCRSEMA_MASK)
610 #define SDP_PKTCTL_DCRSEMA_GET(x) (((uint32_t)(x) & SDP_PKTCTL_DCRSEMA_MASK) >> SDP_PKTCTL_DCRSEMA_SHIFT)
611 
612 /*
613  * PKTINT (RW)
614  *
615  * Reflects whether the channel must issue an interrupt upon the completion of the packet
616  */
617 #define SDP_PKTCTL_PKTINT_MASK (0x2U)
618 #define SDP_PKTCTL_PKTINT_SHIFT (1U)
619 #define SDP_PKTCTL_PKTINT_SET(x) (((uint32_t)(x) << SDP_PKTCTL_PKTINT_SHIFT) & SDP_PKTCTL_PKTINT_MASK)
620 #define SDP_PKTCTL_PKTINT_GET(x) (((uint32_t)(x) & SDP_PKTCTL_PKTINT_MASK) >> SDP_PKTCTL_PKTINT_SHIFT)
621 
622 /* Bitfield definition for register: PKTSRC */
623 /*
624  * PKTSRC (RW)
625  *
626  * Packet Memory Source Address
627  */
628 #define SDP_PKTSRC_PKTSRC_MASK (0xFFFFFFFFUL)
629 #define SDP_PKTSRC_PKTSRC_SHIFT (0U)
630 #define SDP_PKTSRC_PKTSRC_SET(x) (((uint32_t)(x) << SDP_PKTSRC_PKTSRC_SHIFT) & SDP_PKTSRC_PKTSRC_MASK)
631 #define SDP_PKTSRC_PKTSRC_GET(x) (((uint32_t)(x) & SDP_PKTSRC_PKTSRC_MASK) >> SDP_PKTSRC_PKTSRC_SHIFT)
632 
633 /* Bitfield definition for register: PKTDST */
634 /*
635  * PKTDST (RW)
636  *
637  * Packet Memory Destination Address
638  */
639 #define SDP_PKTDST_PKTDST_MASK (0xFFFFFFFFUL)
640 #define SDP_PKTDST_PKTDST_SHIFT (0U)
641 #define SDP_PKTDST_PKTDST_SET(x) (((uint32_t)(x) << SDP_PKTDST_PKTDST_SHIFT) & SDP_PKTDST_PKTDST_MASK)
642 #define SDP_PKTDST_PKTDST_GET(x) (((uint32_t)(x) & SDP_PKTDST_PKTDST_MASK) >> SDP_PKTDST_PKTDST_SHIFT)
643 
644 /* Bitfield definition for register: PKTBUF */
645 /*
646  * PKTBUF (RW)
647  *
648  */
649 #define SDP_PKTBUF_PKTBUF_MASK (0xFFFFFFFFUL)
650 #define SDP_PKTBUF_PKTBUF_SHIFT (0U)
651 #define SDP_PKTBUF_PKTBUF_SET(x) (((uint32_t)(x) << SDP_PKTBUF_PKTBUF_SHIFT) & SDP_PKTBUF_PKTBUF_MASK)
652 #define SDP_PKTBUF_PKTBUF_GET(x) (((uint32_t)(x) & SDP_PKTBUF_PKTBUF_MASK) >> SDP_PKTBUF_PKTBUF_SHIFT)
653 
654 
655 
656 /* CIPHIV register group index macro definition */
657 #define SDP_CIPHIV_CIPHIV0 (0UL)
658 #define SDP_CIPHIV_CIPHIV1 (1UL)
659 #define SDP_CIPHIV_CIPHIV2 (2UL)
660 #define SDP_CIPHIV_CIPHIV3 (3UL)
661 
662 /* HASWRD register group index macro definition */
663 #define SDP_HASWRD_HASWRD0 (0UL)
664 #define SDP_HASWRD_HASWRD1 (1UL)
665 #define SDP_HASWRD_HASWRD2 (2UL)
666 #define SDP_HASWRD_HASWRD3 (3UL)
667 #define SDP_HASWRD_HASWRD4 (4UL)
668 #define SDP_HASWRD_HASWRD5 (5UL)
669 #define SDP_HASWRD_HASWRD6 (6UL)
670 #define SDP_HASWRD_HASWRD7 (7UL)
671 
672 
673 #endif /* HPM_SDP_H */
674