1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_KEYM_H 10 #define HPM_KEYM_H 11 12 typedef struct { 13 __RW uint32_t SOFTMKEY[8]; /* 0x0 - 0x1C: software set symmetric key */ 14 __RW uint32_t SOFTPKEY[8]; /* 0x20 - 0x3C: system asymmetric key */ 15 __RW uint32_t SEC_KEY_CTL; /* 0x40: secure key generation */ 16 __RW uint32_t NSC_KEY_CTL; /* 0x44: non-secure key generation */ 17 __RW uint32_t RNG; /* 0x48: Random number interface behavior */ 18 __RW uint32_t READ_CONTROL; /* 0x4C: key read out control */ 19 } KEYM_Type; 20 21 22 /* Bitfield definition for register array: SOFTMKEY */ 23 /* 24 * KEY (RW) 25 * 26 * software symmetric key 27 * key will be scambled to 4 variants for software to use, and replicable on same chip. 28 * scramble keys are chip different, and not replicable on different chip 29 * must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 30 */ 31 #define KEYM_SOFTMKEY_KEY_MASK (0xFFFFFFFFUL) 32 #define KEYM_SOFTMKEY_KEY_SHIFT (0U) 33 #define KEYM_SOFTMKEY_KEY_SET(x) (((uint32_t)(x) << KEYM_SOFTMKEY_KEY_SHIFT) & KEYM_SOFTMKEY_KEY_MASK) 34 #define KEYM_SOFTMKEY_KEY_GET(x) (((uint32_t)(x) & KEYM_SOFTMKEY_KEY_MASK) >> KEYM_SOFTMKEY_KEY_SHIFT) 35 36 /* Bitfield definition for register array: SOFTPKEY */ 37 /* 38 * KEY (RW) 39 * 40 * software asymmetric key 41 * key is derived from scrambles of fuse private key, software input key, SRK, and system security status. 42 * This key os read once, sencondary read will read out 0 43 */ 44 #define KEYM_SOFTPKEY_KEY_MASK (0xFFFFFFFFUL) 45 #define KEYM_SOFTPKEY_KEY_SHIFT (0U) 46 #define KEYM_SOFTPKEY_KEY_SET(x) (((uint32_t)(x) << KEYM_SOFTPKEY_KEY_SHIFT) & KEYM_SOFTPKEY_KEY_MASK) 47 #define KEYM_SOFTPKEY_KEY_GET(x) (((uint32_t)(x) & KEYM_SOFTPKEY_KEY_MASK) >> KEYM_SOFTPKEY_KEY_SHIFT) 48 49 /* Bitfield definition for register: SEC_KEY_CTL */ 50 /* 51 * LOCK_SEC_CTL (RW) 52 * 53 * block secure state key setting being changed 54 */ 55 #define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK (0x80000000UL) 56 #define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT (31U) 57 #define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) & KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) 58 #define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) >> KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) 59 60 /* 61 * SK_VAL (RO) 62 * 63 * session key valid 64 * 0: session key is all 0's and not usable 65 * 1: session key is valid 66 */ 67 #define KEYM_SEC_KEY_CTL_SK_VAL_MASK (0x10000UL) 68 #define KEYM_SEC_KEY_CTL_SK_VAL_SHIFT (16U) 69 #define KEYM_SEC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_SK_VAL_MASK) >> KEYM_SEC_KEY_CTL_SK_VAL_SHIFT) 70 71 /* 72 * SMK_SEL (RW) 73 * 74 * software symmetric key selection 75 * 0: use origin value in software symmetric key 76 * 1: use scramble version of software symmetric key 77 */ 78 #define KEYM_SEC_KEY_CTL_SMK_SEL_MASK (0x1000U) 79 #define KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT (12U) 80 #define KEYM_SEC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_SMK_SEL_MASK) 81 #define KEYM_SEC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_SMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT) 82 83 /* 84 * ZMK_SEL (RW) 85 * 86 * batt symmetric key selection 87 * 0: use scramble version of software symmetric key 88 * 1: use origin value in software symmetric key 89 */ 90 #define KEYM_SEC_KEY_CTL_ZMK_SEL_MASK (0x100U) 91 #define KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT (8U) 92 #define KEYM_SEC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_ZMK_SEL_MASK) 93 #define KEYM_SEC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_ZMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT) 94 95 /* 96 * FMK_SEL (RW) 97 * 98 * fuse symmetric key selection 99 * 0: use scramble version of fuse symmetric key 100 * 1: use alnertave scramble of fuse symmetric key 101 */ 102 #define KEYM_SEC_KEY_CTL_FMK_SEL_MASK (0x10U) 103 #define KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT (4U) 104 #define KEYM_SEC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_FMK_SEL_MASK) 105 #define KEYM_SEC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_FMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT) 106 107 /* 108 * KEY_SEL (RW) 109 * 110 * secure symmtric key synthesize setting, key is a XOR of followings 111 * bit0: fuse mk, 0: not selected, 1:selected 112 * bit1: zmk from batt, 0: not selected, 1:selected 113 * bit2: software key 0: not selected, 1:selected 114 */ 115 #define KEYM_SEC_KEY_CTL_KEY_SEL_MASK (0x7U) 116 #define KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT (0U) 117 #define KEYM_SEC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT) & KEYM_SEC_KEY_CTL_KEY_SEL_MASK) 118 #define KEYM_SEC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_KEY_SEL_MASK) >> KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT) 119 120 /* Bitfield definition for register: NSC_KEY_CTL */ 121 /* 122 * LOCK_NSC_CTL (RW) 123 * 124 * block non-secure state key setting being changed 125 */ 126 #define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK (0x80000000UL) 127 #define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT (31U) 128 #define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) & KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) 129 #define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) >> KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) 130 131 /* 132 * SK_VAL (RO) 133 * 134 * session key valid 135 * 0: session key is all 0's and not usable 136 * 1: session key is valid 137 */ 138 #define KEYM_NSC_KEY_CTL_SK_VAL_MASK (0x10000UL) 139 #define KEYM_NSC_KEY_CTL_SK_VAL_SHIFT (16U) 140 #define KEYM_NSC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_SK_VAL_MASK) >> KEYM_NSC_KEY_CTL_SK_VAL_SHIFT) 141 142 /* 143 * SMK_SEL (RW) 144 * 145 * software symmetric key selection 146 * 0: use scramble version of software symmetric key 147 * 1: use origin value in software symmetric key 148 */ 149 #define KEYM_NSC_KEY_CTL_SMK_SEL_MASK (0x1000U) 150 #define KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT (12U) 151 #define KEYM_NSC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_SMK_SEL_MASK) 152 #define KEYM_NSC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_SMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT) 153 154 /* 155 * ZMK_SEL (RW) 156 * 157 * batt symmetric key selection 158 * 0: use scramble version of software symmetric key 159 * 1: use origin value in software symmetric key 160 */ 161 #define KEYM_NSC_KEY_CTL_ZMK_SEL_MASK (0x100U) 162 #define KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT (8U) 163 #define KEYM_NSC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_ZMK_SEL_MASK) 164 #define KEYM_NSC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_ZMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT) 165 166 /* 167 * FMK_SEL (RW) 168 * 169 * fuse symmetric key selection 170 * 0: use scramble version of fuse symmetric key 171 * 1: use origin value in fuse symmetric key 172 */ 173 #define KEYM_NSC_KEY_CTL_FMK_SEL_MASK (0x10U) 174 #define KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT (4U) 175 #define KEYM_NSC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_FMK_SEL_MASK) 176 #define KEYM_NSC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_FMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT) 177 178 /* 179 * KEY_SEL (RW) 180 * 181 * non-secure symmtric key synthesize setting, key is a XOR of followings 182 * bit0: fuse mk, 0: not selected, 1:selected 183 * bit1: zmk from batt, 0: not selected, 1:selected 184 * bit2: software key 0: not selected, 1:selected 185 */ 186 #define KEYM_NSC_KEY_CTL_KEY_SEL_MASK (0x7U) 187 #define KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT (0U) 188 #define KEYM_NSC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT) & KEYM_NSC_KEY_CTL_KEY_SEL_MASK) 189 #define KEYM_NSC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_KEY_SEL_MASK) >> KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT) 190 191 /* Bitfield definition for register: RNG */ 192 /* 193 * BLOCK_RNG_XOR (RW) 194 * 195 * block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset 196 * 0: RNG_XOR can be changed by software 197 * 1: RNG_XOR ignore software change from software 198 */ 199 #define KEYM_RNG_BLOCK_RNG_XOR_MASK (0x10000UL) 200 #define KEYM_RNG_BLOCK_RNG_XOR_SHIFT (16U) 201 #define KEYM_RNG_BLOCK_RNG_XOR_SET(x) (((uint32_t)(x) << KEYM_RNG_BLOCK_RNG_XOR_SHIFT) & KEYM_RNG_BLOCK_RNG_XOR_MASK) 202 #define KEYM_RNG_BLOCK_RNG_XOR_GET(x) (((uint32_t)(x) & KEYM_RNG_BLOCK_RNG_XOR_MASK) >> KEYM_RNG_BLOCK_RNG_XOR_SHIFT) 203 204 /* 205 * RNG_XOR (RW) 206 * 207 * control how SFK is accepted from random number generator 208 * 0: SFK value replaced by random number input 209 * 1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG 210 */ 211 #define KEYM_RNG_RNG_XOR_MASK (0x1U) 212 #define KEYM_RNG_RNG_XOR_SHIFT (0U) 213 #define KEYM_RNG_RNG_XOR_SET(x) (((uint32_t)(x) << KEYM_RNG_RNG_XOR_SHIFT) & KEYM_RNG_RNG_XOR_MASK) 214 #define KEYM_RNG_RNG_XOR_GET(x) (((uint32_t)(x) & KEYM_RNG_RNG_XOR_MASK) >> KEYM_RNG_RNG_XOR_SHIFT) 215 216 /* Bitfield definition for register: READ_CONTROL */ 217 /* 218 * BLOCK_PK_READ (RW) 219 * 220 * asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset 221 * 0: key can be read out 222 * 1: key cannot be read out 223 */ 224 #define KEYM_READ_CONTROL_BLOCK_PK_READ_MASK (0x10000UL) 225 #define KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT (16U) 226 #define KEYM_READ_CONTROL_BLOCK_PK_READ_SET(x) (((uint32_t)(x) << KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT) & KEYM_READ_CONTROL_BLOCK_PK_READ_MASK) 227 #define KEYM_READ_CONTROL_BLOCK_PK_READ_GET(x) (((uint32_t)(x) & KEYM_READ_CONTROL_BLOCK_PK_READ_MASK) >> KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT) 228 229 /* 230 * BLOCK_SMK_READ (RW) 231 * 232 * symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset 233 * 0: key can be read out 234 * 1: key cannot be read out 235 */ 236 #define KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK (0x1U) 237 #define KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT (0U) 238 #define KEYM_READ_CONTROL_BLOCK_SMK_READ_SET(x) (((uint32_t)(x) << KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT) & KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK) 239 #define KEYM_READ_CONTROL_BLOCK_SMK_READ_GET(x) (((uint32_t)(x) & KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK) >> KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT) 240 241 242 243 /* SOFTMKEY register group index macro definition */ 244 #define KEYM_SOFTMKEY_SFK0 (0UL) 245 #define KEYM_SOFTMKEY_SFK1 (1UL) 246 #define KEYM_SOFTMKEY_SFK2 (2UL) 247 #define KEYM_SOFTMKEY_SFK3 (3UL) 248 #define KEYM_SOFTMKEY_SFK4 (4UL) 249 #define KEYM_SOFTMKEY_SFK5 (5UL) 250 #define KEYM_SOFTMKEY_SFK6 (6UL) 251 #define KEYM_SOFTMKEY_SFK7 (7UL) 252 253 /* SOFTPKEY register group index macro definition */ 254 #define KEYM_SOFTPKEY_SPK0 (0UL) 255 #define KEYM_SOFTPKEY_SPK1 (1UL) 256 #define KEYM_SOFTPKEY_SPK2 (2UL) 257 #define KEYM_SOFTPKEY_SPK3 (3UL) 258 #define KEYM_SOFTPKEY_SPK4 (4UL) 259 #define KEYM_SOFTPKEY_SPK5 (5UL) 260 #define KEYM_SOFTPKEY_SPK6 (6UL) 261 #define KEYM_SOFTPKEY_SPK7 (7UL) 262 263 264 #endif /* HPM_KEYM_H */ 265