1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_LCB_H 10 #define HPM_LCB_H 11 12 typedef struct { 13 __RW uint32_t CTRL; /* 0x0: control register */ 14 __R uint8_t RESERVED0[96]; /* 0x4 - 0x63: Reserved */ 15 __R uint32_t PHY_STAT; /* 0x64: LVDS RX PHY Status register */ 16 __RW uint32_t PHY_POW_CTRL[2]; /* 0x68 - 0x6C: LVDS0 PHY power control register */ 17 __RW uint32_t PHY_D_CTRL[4]; /* 0x70 - 0x7C: LVDS0 PHY Data Channel RX0 Setting */ 18 __RW uint32_t PHY_CK_CTRL[2]; /* 0x80 - 0x84: LVDS0 PHY CK Channel Setting */ 19 __RW uint32_t PHY_ADJ_CTRL[2]; /* 0x88 - 0x8C: LVDS0 PHY ADJ Setting */ 20 __RW uint32_t PHY_SU_CTRL[2]; /* 0x90 - 0x94: LVDS0 PHY SU CTRL */ 21 } LCB_Type; 22 23 24 /* Bitfield definition for register: CTRL */ 25 /* 26 * LVDS_RXCK_SEL (RW) 27 * 28 * just for LVDS Display mode and CAM LINK mode, clock selection: 29 * 1: LVDS1 RXCK 30 * 0: LVDS0 RXCK 31 */ 32 #define LCB_CTRL_LVDS_RXCK_SEL_MASK (0x100U) 33 #define LCB_CTRL_LVDS_RXCK_SEL_SHIFT (8U) 34 #define LCB_CTRL_LVDS_RXCK_SEL_SET(x) (((uint32_t)(x) << LCB_CTRL_LVDS_RXCK_SEL_SHIFT) & LCB_CTRL_LVDS_RXCK_SEL_MASK) 35 #define LCB_CTRL_LVDS_RXCK_SEL_GET(x) (((uint32_t)(x) & LCB_CTRL_LVDS_RXCK_SEL_MASK) >> LCB_CTRL_LVDS_RXCK_SEL_SHIFT) 36 37 /* 38 * CAM_LINK_WIDTH (RW) 39 * 40 * just for CAM LINK mode, data width: 41 * 00: 24bit 42 * 01: 30bit 43 * 10: 36bit 44 * 11: reserved 45 */ 46 #define LCB_CTRL_CAM_LINK_WIDTH_MASK (0xC0U) 47 #define LCB_CTRL_CAM_LINK_WIDTH_SHIFT (6U) 48 #define LCB_CTRL_CAM_LINK_WIDTH_SET(x) (((uint32_t)(x) << LCB_CTRL_CAM_LINK_WIDTH_SHIFT) & LCB_CTRL_CAM_LINK_WIDTH_MASK) 49 #define LCB_CTRL_CAM_LINK_WIDTH_GET(x) (((uint32_t)(x) & LCB_CTRL_CAM_LINK_WIDTH_MASK) >> LCB_CTRL_CAM_LINK_WIDTH_SHIFT) 50 51 /* 52 * BIT_MAPPING (RW) 53 * 54 * just for LVDS Display mode, data protocol: 55 * 1: JEIDA standard 56 * 0: SPWG standard 57 */ 58 #define LCB_CTRL_BIT_MAPPING_MASK (0x20U) 59 #define LCB_CTRL_BIT_MAPPING_SHIFT (5U) 60 #define LCB_CTRL_BIT_MAPPING_SET(x) (((uint32_t)(x) << LCB_CTRL_BIT_MAPPING_SHIFT) & LCB_CTRL_BIT_MAPPING_MASK) 61 #define LCB_CTRL_BIT_MAPPING_GET(x) (((uint32_t)(x) & LCB_CTRL_BIT_MAPPING_MASK) >> LCB_CTRL_BIT_MAPPING_SHIFT) 62 63 /* 64 * DATA_WIDTH (RW) 65 * 66 * just for LVDS Display mode, data width: 67 * 1: 24bit 68 * 0: 18bit(3line) 69 */ 70 #define LCB_CTRL_DATA_WIDTH_MASK (0x10U) 71 #define LCB_CTRL_DATA_WIDTH_SHIFT (4U) 72 #define LCB_CTRL_DATA_WIDTH_SET(x) (((uint32_t)(x) << LCB_CTRL_DATA_WIDTH_SHIFT) & LCB_CTRL_DATA_WIDTH_MASK) 73 #define LCB_CTRL_DATA_WIDTH_GET(x) (((uint32_t)(x) & LCB_CTRL_DATA_WIDTH_MASK) >> LCB_CTRL_DATA_WIDTH_SHIFT) 74 75 /* 76 * MODE (RW) 77 * 78 * mode selection： 79 * 00: lvds display(4 line), two LVDS RX PHY must be LVDS display mode 80 * 01: cam link(4 line), two LVDS RX PHY must be LVDS display mode 81 * 10: sync code(2 line), LVDS RX PHY must be LVDS cameral mode 82 * 11: sync code(1line), LVDS RX PHY must be LVDS cameral mode 83 */ 84 #define LCB_CTRL_MODE_MASK (0x3U) 85 #define LCB_CTRL_MODE_SHIFT (0U) 86 #define LCB_CTRL_MODE_SET(x) (((uint32_t)(x) << LCB_CTRL_MODE_SHIFT) & LCB_CTRL_MODE_MASK) 87 #define LCB_CTRL_MODE_GET(x) (((uint32_t)(x) & LCB_CTRL_MODE_MASK) >> LCB_CTRL_MODE_SHIFT) 88 89 /* Bitfield definition for register: PHY_STAT */ 90 /* 91 * LVDS1_RX_PHY_DLL_LOCK (RO) 92 * 93 * LVDS1 RX PHY DLL Lock indication Signal, 1 means dll already locked 94 */ 95 #define LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_MASK (0x2U) 96 #define LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_SHIFT (1U) 97 #define LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_GET(x) (((uint32_t)(x) & LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_MASK) >> LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_SHIFT) 98 99 /* 100 * LVDS0_RX_PHY_DLL_LOCK (RO) 101 * 102 * LVDS0 RX PHY DLL Lock indication Signal, 1 means dll already locked 103 */ 104 #define LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_MASK (0x1U) 105 #define LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_SHIFT (0U) 106 #define LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_GET(x) (((uint32_t)(x) & LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_MASK) >> LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_SHIFT) 107 108 /* Bitfield definition for register array: PHY_POW_CTRL */ 109 /* 110 * IDDQ_EN (RW) 111 * 112 * Power down control signal of channel rxck/rx1/rx0 113 * 0: Normal operation 114 * 1: Power down channel 115 */ 116 #define LCB_PHY_POW_CTRL_IDDQ_EN_MASK (0x8U) 117 #define LCB_PHY_POW_CTRL_IDDQ_EN_SHIFT (3U) 118 #define LCB_PHY_POW_CTRL_IDDQ_EN_SET(x) (((uint32_t)(x) << LCB_PHY_POW_CTRL_IDDQ_EN_SHIFT) & LCB_PHY_POW_CTRL_IDDQ_EN_MASK) 119 #define LCB_PHY_POW_CTRL_IDDQ_EN_GET(x) (((uint32_t)(x) & LCB_PHY_POW_CTRL_IDDQ_EN_MASK) >> LCB_PHY_POW_CTRL_IDDQ_EN_SHIFT) 120 121 /* 122 * RXCK_PD (RW) 123 * 124 * Power down control signal of channel rxck 125 * 0: Normal operation 126 * 1: Power down channel 127 */ 128 #define LCB_PHY_POW_CTRL_RXCK_PD_MASK (0x4U) 129 #define LCB_PHY_POW_CTRL_RXCK_PD_SHIFT (2U) 130 #define LCB_PHY_POW_CTRL_RXCK_PD_SET(x) (((uint32_t)(x) << LCB_PHY_POW_CTRL_RXCK_PD_SHIFT) & LCB_PHY_POW_CTRL_RXCK_PD_MASK) 131 #define LCB_PHY_POW_CTRL_RXCK_PD_GET(x) (((uint32_t)(x) & LCB_PHY_POW_CTRL_RXCK_PD_MASK) >> LCB_PHY_POW_CTRL_RXCK_PD_SHIFT) 132 133 /* 134 * RX1_PD (RW) 135 * 136 * Power down control signal of channel rx1 137 * 0: Normal operation 138 * 1: Power down channel 139 */ 140 #define LCB_PHY_POW_CTRL_RX1_PD_MASK (0x2U) 141 #define LCB_PHY_POW_CTRL_RX1_PD_SHIFT (1U) 142 #define LCB_PHY_POW_CTRL_RX1_PD_SET(x) (((uint32_t)(x) << LCB_PHY_POW_CTRL_RX1_PD_SHIFT) & LCB_PHY_POW_CTRL_RX1_PD_MASK) 143 #define LCB_PHY_POW_CTRL_RX1_PD_GET(x) (((uint32_t)(x) & LCB_PHY_POW_CTRL_RX1_PD_MASK) >> LCB_PHY_POW_CTRL_RX1_PD_SHIFT) 144 145 /* 146 * RX0_PD (RW) 147 * 148 * Power down control signal of channel rx0 149 * 0: Normal operation 150 * 1: Power down channel 151 */ 152 #define LCB_PHY_POW_CTRL_RX0_PD_MASK (0x1U) 153 #define LCB_PHY_POW_CTRL_RX0_PD_SHIFT (0U) 154 #define LCB_PHY_POW_CTRL_RX0_PD_SET(x) (((uint32_t)(x) << LCB_PHY_POW_CTRL_RX0_PD_SHIFT) & LCB_PHY_POW_CTRL_RX0_PD_MASK) 155 #define LCB_PHY_POW_CTRL_RX0_PD_GET(x) (((uint32_t)(x) & LCB_PHY_POW_CTRL_RX0_PD_MASK) >> LCB_PHY_POW_CTRL_RX0_PD_SHIFT) 156 157 /* Bitfield definition for register array: PHY_D_CTRL */ 158 /* 159 * RX_VCOM (RW) 160 * 161 * bit 1: Receiver hysteresis enable signal. 0: enable; 1: disable 162 * bit 0: Terminal impedance common mode selection control signal. 0: floating; 1: Ground 163 */ 164 #define LCB_PHY_D_CTRL_RX_VCOM_MASK (0x300000UL) 165 #define LCB_PHY_D_CTRL_RX_VCOM_SHIFT (20U) 166 #define LCB_PHY_D_CTRL_RX_VCOM_SET(x) (((uint32_t)(x) << LCB_PHY_D_CTRL_RX_VCOM_SHIFT) & LCB_PHY_D_CTRL_RX_VCOM_MASK) 167 #define LCB_PHY_D_CTRL_RX_VCOM_GET(x) (((uint32_t)(x) & LCB_PHY_D_CTRL_RX_VCOM_MASK) >> LCB_PHY_D_CTRL_RX_VCOM_SHIFT) 168 169 /* 170 * RX_RTERM (RW) 171 * 172 * Terminal impedance regulation control signal 173 * 0000: hi-z; 174 * 0001: 150ohm; 175 * 1000:100ohm; 176 * 1111:75ohm 177 */ 178 #define LCB_PHY_D_CTRL_RX_RTERM_MASK (0xF0000UL) 179 #define LCB_PHY_D_CTRL_RX_RTERM_SHIFT (16U) 180 #define LCB_PHY_D_CTRL_RX_RTERM_SET(x) (((uint32_t)(x) << LCB_PHY_D_CTRL_RX_RTERM_SHIFT) & LCB_PHY_D_CTRL_RX_RTERM_MASK) 181 #define LCB_PHY_D_CTRL_RX_RTERM_GET(x) (((uint32_t)(x) & LCB_PHY_D_CTRL_RX_RTERM_MASK) >> LCB_PHY_D_CTRL_RX_RTERM_SHIFT) 182 183 /* 184 * RX_CTL (RW) 185 * 186 * bit 0 : Lane N Data MSB first enable signal. 0: LSB ; 1: MSB 187 * bit 1 : Lane N Data Polarity signal. 0: Not inverting; 1: Inverting 188 * bit [4:2] : Phase difference between the output first bit data (rxN[6:0]) and the input clock (RCKP/N) in LVDS Display Mode. 189 * bit 5 : Reserved 190 * bit 6 : Output data sampling clock control signal 191 * 0: Sampling using the rising edge of the clock pck. 192 * 1: Sampling using the falling edge of the clock pck. 193 * bit 7 : Reserved 194 * bit 8 : Data Lane N Skew adjust enable in LVDS Camera Mode. 195 * bit [12:9] : Data Lane N Skew adjust; 0000: min; 0111: default; 1111: max. 196 * bit [15:13] : Reserved 197 */ 198 #define LCB_PHY_D_CTRL_RX_CTL_MASK (0xFFFFU) 199 #define LCB_PHY_D_CTRL_RX_CTL_SHIFT (0U) 200 #define LCB_PHY_D_CTRL_RX_CTL_SET(x) (((uint32_t)(x) << LCB_PHY_D_CTRL_RX_CTL_SHIFT) & LCB_PHY_D_CTRL_RX_CTL_MASK) 201 #define LCB_PHY_D_CTRL_RX_CTL_GET(x) (((uint32_t)(x) & LCB_PHY_D_CTRL_RX_CTL_MASK) >> LCB_PHY_D_CTRL_RX_CTL_SHIFT) 202 203 /* Bitfield definition for register array: PHY_CK_CTRL */ 204 /* 205 * RX_VCOM (RW) 206 * 207 * bit 1: Receiver hysteresis enable signal. 0: enable; 1: disable 208 * bit 0: Terminal impedance common mode selection control signal. 0: floating; 1: Ground 209 */ 210 #define LCB_PHY_CK_CTRL_RX_VCOM_MASK (0x300000UL) 211 #define LCB_PHY_CK_CTRL_RX_VCOM_SHIFT (20U) 212 #define LCB_PHY_CK_CTRL_RX_VCOM_SET(x) (((uint32_t)(x) << LCB_PHY_CK_CTRL_RX_VCOM_SHIFT) & LCB_PHY_CK_CTRL_RX_VCOM_MASK) 213 #define LCB_PHY_CK_CTRL_RX_VCOM_GET(x) (((uint32_t)(x) & LCB_PHY_CK_CTRL_RX_VCOM_MASK) >> LCB_PHY_CK_CTRL_RX_VCOM_SHIFT) 214 215 /* 216 * RX_RTERM (RW) 217 * 218 * Terminal impedance regulation control signal 219 * 0000: hi-z; 220 * 0001: 150ohm; 221 * 1000:100ohm; 222 * 1111:75ohm 223 */ 224 #define LCB_PHY_CK_CTRL_RX_RTERM_MASK (0xF0000UL) 225 #define LCB_PHY_CK_CTRL_RX_RTERM_SHIFT (16U) 226 #define LCB_PHY_CK_CTRL_RX_RTERM_SET(x) (((uint32_t)(x) << LCB_PHY_CK_CTRL_RX_RTERM_SHIFT) & LCB_PHY_CK_CTRL_RX_RTERM_MASK) 227 #define LCB_PHY_CK_CTRL_RX_RTERM_GET(x) (((uint32_t)(x) & LCB_PHY_CK_CTRL_RX_RTERM_MASK) >> LCB_PHY_CK_CTRL_RX_RTERM_SHIFT) 228 229 /* 230 * RX_CTL (RW) 231 * 232 * bit 0 : DLL loop delay adjustment minimum control signal 233 * 0: used for RCKP/RCKN’s frequency is 40Mhz~70Mhz 234 * 1:used for RCKP/RCKN’s frequency is 70Mhz~110Mhz 235 * bit [2:1] : DLL loop delay adjustment current regulation control signal. 00: min; 11: max 236 * bit 3 : Reserved 237 * bit 4 : Clock Lane Skew adjust enable in LVDS Camera Mode. 238 * bit [7:5] : Bus width selection in LVDS Camera Mode 239 * 000: 4bit; 001:6bit; 010:7bit; 011:8bit; 100:9bit; 101:10bit; 110:11bit; 111:12bit. 240 * bit [10:8] : DDR Clock duty cycle adjust in LVDS Camera Mode. 241 * bit [15:11] : Reserved 242 */ 243 #define LCB_PHY_CK_CTRL_RX_CTL_MASK (0xFFFFU) 244 #define LCB_PHY_CK_CTRL_RX_CTL_SHIFT (0U) 245 #define LCB_PHY_CK_CTRL_RX_CTL_SET(x) (((uint32_t)(x) << LCB_PHY_CK_CTRL_RX_CTL_SHIFT) & LCB_PHY_CK_CTRL_RX_CTL_MASK) 246 #define LCB_PHY_CK_CTRL_RX_CTL_GET(x) (((uint32_t)(x) & LCB_PHY_CK_CTRL_RX_CTL_MASK) >> LCB_PHY_CK_CTRL_RX_CTL_SHIFT) 247 248 /* Bitfield definition for register array: PHY_ADJ_CTRL */ 249 /* 250 * LVDS_RX0_DLINE_ADJ (RW) 251 * 252 * LVDS RX PHY RX0 line: 253 * bit [7:0] : Lane N skew adjustment control signal between data and clock 254 * 0000000: max; 1111111: min 255 * bit 8 : Reserved 256 */ 257 #define LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_MASK (0xFF000000UL) 258 #define LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_SHIFT (24U) 259 #define LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_SET(x) (((uint32_t)(x) << LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_SHIFT) & LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_MASK) 260 #define LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_GET(x) (((uint32_t)(x) & LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_MASK) >> LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_SHIFT) 261 262 /* 263 * LVDS_RX1_DLINE_ADJ (RW) 264 * 265 * LVDS RX PHY RX1 line: 266 * bit [7:0] : Lane N skew adjustment control signal between data and clock 267 * 0000000: max; 1111111: min 268 * bit 8 : Reserved 269 */ 270 #define LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_MASK (0xFF0000UL) 271 #define LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_SHIFT (16U) 272 #define LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_SET(x) (((uint32_t)(x) << LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_SHIFT) & LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_MASK) 273 #define LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_GET(x) (((uint32_t)(x) & LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_MASK) >> LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_SHIFT) 274 275 /* 276 * LVDS_DLL_TUNING_INT (RW) 277 * 278 * LVDS RX PHY RXCK line: 279 * DLL loop delay coarse adjustment initial signal 280 * 00000000: min ; 11111111: max 281 */ 282 #define LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_MASK (0x1FFU) 283 #define LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_SHIFT (0U) 284 #define LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_SET(x) (((uint32_t)(x) << LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_SHIFT) & LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_MASK) 285 #define LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_GET(x) (((uint32_t)(x) & LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_MASK) >> LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_SHIFT) 286 287 /* Bitfield definition for register array: PHY_SU_CTRL */ 288 /* 289 * SU_CTRL (RW) 290 * 291 * bit [2:0] : Reference voltage/current adjustment control signal. 000: min; 111: max 292 * bit [3] : Internal bias circuit selection signal. 0: from Bandgap Mode; 1: from self-bias mode 293 * bit [7:4] : Reserved 294 */ 295 #define LCB_PHY_SU_CTRL_SU_CTRL_MASK (0xFFU) 296 #define LCB_PHY_SU_CTRL_SU_CTRL_SHIFT (0U) 297 #define LCB_PHY_SU_CTRL_SU_CTRL_SET(x) (((uint32_t)(x) << LCB_PHY_SU_CTRL_SU_CTRL_SHIFT) & LCB_PHY_SU_CTRL_SU_CTRL_MASK) 298 #define LCB_PHY_SU_CTRL_SU_CTRL_GET(x) (((uint32_t)(x) & LCB_PHY_SU_CTRL_SU_CTRL_MASK) >> LCB_PHY_SU_CTRL_SU_CTRL_SHIFT) 299 300 301 302 /* PHY_POW_CTRL register group index macro definition */ 303 #define LCB_PHY_POW_CTRL_LVDS0 (0UL) 304 #define LCB_PHY_POW_CTRL_LVDS1 (1UL) 305 306 /* PHY_D_CTRL register group index macro definition */ 307 #define LCB_PHY_D_CTRL_LVDS0_RX0 (0UL) 308 #define LCB_PHY_D_CTRL_LVDS0_RX1 (1UL) 309 #define LCB_PHY_D_CTRL_LVDS1_RX0 (2UL) 310 #define LCB_PHY_D_CTRL_LVDS1_RX1 (3UL) 311 312 /* PHY_CK_CTRL register group index macro definition */ 313 #define LCB_PHY_CK_CTRL_LVDS0_RXCK (0UL) 314 #define LCB_PHY_CK_CTRL_LVDS1_RXCK (1UL) 315 316 /* PHY_ADJ_CTRL register group index macro definition */ 317 #define LCB_PHY_ADJ_CTRL_LVDS0 (0UL) 318 #define LCB_PHY_ADJ_CTRL_LVDS1 (1UL) 319 320 /* PHY_SU_CTRL register group index macro definition */ 321 #define LCB_PHY_SU_CTRL_LVDS0 (0UL) 322 #define LCB_PHY_SU_CTRL_LVDS1 (1UL) 323 324 325 #endif /* HPM_LCB_H */ 326