1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_LCDC_H 10 #define HPM_LCDC_H 11 12 typedef struct { 13 __RW uint32_t CTRL; /* 0x0: Control Register */ 14 __RW uint32_t BGND_CL; /* 0x4: Background Color Register */ 15 __RW uint32_t DISP_WN_SIZE; /* 0x8: Display Window Size Register */ 16 __RW uint32_t HSYNC_PARA; /* 0xC: HSYNC Config Register */ 17 __RW uint32_t VSYNC_PARA; /* 0x10: VSYNC Config Register */ 18 __W uint32_t DMA_ST; /* 0x14: DMA Status Register */ 19 __RW uint32_t ST; /* 0x18: Status Register */ 20 __RW uint32_t INT_EN; /* 0x1C: Interrupt Enable Register */ 21 __RW uint32_t TXFIFO; /* 0x20: TX FIFO Register */ 22 __RW uint32_t CTRL_BP_V_RANGE; /* 0x24: BP_V range for CAMSYNC mode */ 23 __RW uint32_t CTRL_PW_V_RANGE; /* 0x28: PW_V range for CAMSYNC mode */ 24 __RW uint32_t CTRL_FP_V_RANGE; /* 0x2C: FP_V range for CAMSYNC mode */ 25 __RW uint32_t CAM_SYNC_HCNT_MIN; /* 0x30: min HCNT value for CAMSYNC mode */ 26 __RW uint32_t CAM_SYNC_HCNT_BEST; /* 0x34: best HCNT value for CAMSYNC mode */ 27 __RW uint32_t CAM_SYNC_HCNT_MAX; /* 0x38: max HCNT value for CAMSYNC mode */ 28 __R uint32_t CAM_SYNC_HCNT_ST; /* 0x3C: current HCNT value for CAMSYNC mode */ 29 __R uint32_t SHADOW_DONE_ST; /* 0x40: Shadow done status */ 30 __RW uint32_t SHADOW_DONE_INT_EN; /* 0x44: Shadow done interrupt enable */ 31 __R uint8_t RESERVED0[440]; /* 0x48 - 0x1FF: Reserved */ 32 struct { 33 __RW uint32_t LAYCTRL; /* 0x200: Layer Control Register */ 34 __RW uint32_t ALPHAS; /* 0x204: Layer Alpha Register */ 35 __RW uint32_t LAYSIZE; /* 0x208: Layer Size Register */ 36 __RW uint32_t LAYPOS; /* 0x20C: Layer Position Register */ 37 __RW uint32_t START0; /* 0x210: Layer Buffer Pointer Register */ 38 __R uint8_t RESERVED0[4]; /* 0x214 - 0x217: Reserved */ 39 __RW uint32_t LINECFG; /* 0x218: Layer Bus Config Register */ 40 __RW uint32_t BG_CL; /* 0x21C: Layer Background Color Register */ 41 __RW uint32_t CSC_COEF0; /* 0x220: Layer Color Space Conversion Config Register 0 */ 42 __RW uint32_t CSC_COEF1; /* 0x224: Layer Color Space Conversion Config Register 1 */ 43 __RW uint32_t CSC_COEF2; /* 0x228: Layer Color Space Conversion Config Register 2 */ 44 __R uint8_t RESERVED1[20]; /* 0x22C - 0x23F: Reserved */ 45 } LAYER[8]; 46 __RW uint32_t CLUT_LOAD; /* 0x400: Clut Load Control Register */ 47 } LCDC_Type; 48 49 50 /* Bitfield definition for register: CTRL */ 51 /* 52 * SW_RST (RW) 53 * 54 * Software reset, high active. When write 1 ,all internal logical will be reset. 55 * 0b - No action 56 * 1b - All LCDC internal registers are forced into their reset state. Interface registers are not affected. 57 */ 58 #define LCDC_CTRL_SW_RST_MASK (0x80000000UL) 59 #define LCDC_CTRL_SW_RST_SHIFT (31U) 60 #define LCDC_CTRL_SW_RST_SET(x) (((uint32_t)(x) << LCDC_CTRL_SW_RST_SHIFT) & LCDC_CTRL_SW_RST_MASK) 61 #define LCDC_CTRL_SW_RST_GET(x) (((uint32_t)(x) & LCDC_CTRL_SW_RST_MASK) >> LCDC_CTRL_SW_RST_SHIFT) 62 63 /* 64 * DISP_ON (RW) 65 * 66 * Display panel On/Off mode. 67 * 0b - Display Off. 68 * 1b - Display On. 69 * Display can be set off at any time, but it can only be set on after VS_BLANK status is asserted. 70 * So a good procedure to stop and turn on the display is: 71 * 1) clr VS_BLANK status 72 * 2) assert software reset 73 * 3) de-assert software reset 74 * 4) set display off 75 * 5) check VS_BLANK status until it is asserted, 76 * 6)reset the module, change settings 77 * 7) set display on 78 */ 79 #define LCDC_CTRL_DISP_ON_MASK (0x40000000UL) 80 #define LCDC_CTRL_DISP_ON_SHIFT (30U) 81 #define LCDC_CTRL_DISP_ON_SET(x) (((uint32_t)(x) << LCDC_CTRL_DISP_ON_SHIFT) & LCDC_CTRL_DISP_ON_MASK) 82 #define LCDC_CTRL_DISP_ON_GET(x) (((uint32_t)(x) & LCDC_CTRL_DISP_ON_MASK) >> LCDC_CTRL_DISP_ON_SHIFT) 83 84 /* 85 * LINE_PATTERN (RW) 86 * 87 * LCDIF line output order. 88 * 000b - RGB. 89 * 001b - RBG. 90 * 010b - GBR. 91 * 011b - GRB. 92 * 100b - BRG. 93 * 101b - BGR. 94 */ 95 #define LCDC_CTRL_LINE_PATTERN_MASK (0x38000000UL) 96 #define LCDC_CTRL_LINE_PATTERN_SHIFT (27U) 97 #define LCDC_CTRL_LINE_PATTERN_SET(x) (((uint32_t)(x) << LCDC_CTRL_LINE_PATTERN_SHIFT) & LCDC_CTRL_LINE_PATTERN_MASK) 98 #define LCDC_CTRL_LINE_PATTERN_GET(x) (((uint32_t)(x) & LCDC_CTRL_LINE_PATTERN_MASK) >> LCDC_CTRL_LINE_PATTERN_SHIFT) 99 100 /* 101 * DISP_MODE (RW) 102 * 103 * LCDIF operating mode. 104 * 00b - Normal mode. Panel content controlled by layer configuration. 105 * 01b - Test Mode1.(BGND Color Display) 106 * 10b - Test Mode2.(Column Color Bar) 107 * 11b - Test Mode3.(Row Color Bar) 108 */ 109 #define LCDC_CTRL_DISP_MODE_MASK (0x6000000UL) 110 #define LCDC_CTRL_DISP_MODE_SHIFT (25U) 111 #define LCDC_CTRL_DISP_MODE_SET(x) (((uint32_t)(x) << LCDC_CTRL_DISP_MODE_SHIFT) & LCDC_CTRL_DISP_MODE_MASK) 112 #define LCDC_CTRL_DISP_MODE_GET(x) (((uint32_t)(x) & LCDC_CTRL_DISP_MODE_MASK) >> LCDC_CTRL_DISP_MODE_SHIFT) 113 114 /* 115 * BGDCL4CLR (RW) 116 * 117 * background color for clear mode when the alpha channel is 0 118 */ 119 #define LCDC_CTRL_BGDCL4CLR_MASK (0x1000000UL) 120 #define LCDC_CTRL_BGDCL4CLR_SHIFT (24U) 121 #define LCDC_CTRL_BGDCL4CLR_SET(x) (((uint32_t)(x) << LCDC_CTRL_BGDCL4CLR_SHIFT) & LCDC_CTRL_BGDCL4CLR_MASK) 122 #define LCDC_CTRL_BGDCL4CLR_GET(x) (((uint32_t)(x) & LCDC_CTRL_BGDCL4CLR_MASK) >> LCDC_CTRL_BGDCL4CLR_SHIFT) 123 124 /* 125 * ARQOS (RW) 126 * 127 * ARQOS for bus fabric arbitration 128 */ 129 #define LCDC_CTRL_ARQOS_MASK (0xF00000UL) 130 #define LCDC_CTRL_ARQOS_SHIFT (20U) 131 #define LCDC_CTRL_ARQOS_SET(x) (((uint32_t)(x) << LCDC_CTRL_ARQOS_SHIFT) & LCDC_CTRL_ARQOS_MASK) 132 #define LCDC_CTRL_ARQOS_GET(x) (((uint32_t)(x) & LCDC_CTRL_ARQOS_MASK) >> LCDC_CTRL_ARQOS_SHIFT) 133 134 /* 135 * SHADOW_OP (RW) 136 * 137 * Shadow Option 138 * 1: Use physical VSYNC (ST[VS_BLANK]) as shadow time. 139 * 0: Use layer internal logic VSYNC as shadow time. In general, this type of shadow control will have longer memory read time, so less underflow risk. 140 */ 141 #define LCDC_CTRL_SHADOW_OP_MASK (0x20000UL) 142 #define LCDC_CTRL_SHADOW_OP_SHIFT (17U) 143 #define LCDC_CTRL_SHADOW_OP_SET(x) (((uint32_t)(x) << LCDC_CTRL_SHADOW_OP_SHIFT) & LCDC_CTRL_SHADOW_OP_MASK) 144 #define LCDC_CTRL_SHADOW_OP_GET(x) (((uint32_t)(x) & LCDC_CTRL_SHADOW_OP_MASK) >> LCDC_CTRL_SHADOW_OP_SHIFT) 145 146 /* 147 * B_LE_MODE (RW) 148 * 149 * Endianess mode for Blue Color Pads 150 * 1: Little endian. Pad 0 --> Color LSB 0 151 * 0: Big Endian. Pad 0--> Color MSB 7 152 */ 153 #define LCDC_CTRL_B_LE_MODE_MASK (0x10000UL) 154 #define LCDC_CTRL_B_LE_MODE_SHIFT (16U) 155 #define LCDC_CTRL_B_LE_MODE_SET(x) (((uint32_t)(x) << LCDC_CTRL_B_LE_MODE_SHIFT) & LCDC_CTRL_B_LE_MODE_MASK) 156 #define LCDC_CTRL_B_LE_MODE_GET(x) (((uint32_t)(x) & LCDC_CTRL_B_LE_MODE_MASK) >> LCDC_CTRL_B_LE_MODE_SHIFT) 157 158 /* 159 * G_LE_MODE (RW) 160 * 161 * Endianess mode for Green Color Pads 162 * 1: Little endian. Pad 0 --> Color LSB 0 163 * 0: Big Endian. Pad 0--> Color MSB 7 164 */ 165 #define LCDC_CTRL_G_LE_MODE_MASK (0x8000U) 166 #define LCDC_CTRL_G_LE_MODE_SHIFT (15U) 167 #define LCDC_CTRL_G_LE_MODE_SET(x) (((uint32_t)(x) << LCDC_CTRL_G_LE_MODE_SHIFT) & LCDC_CTRL_G_LE_MODE_MASK) 168 #define LCDC_CTRL_G_LE_MODE_GET(x) (((uint32_t)(x) & LCDC_CTRL_G_LE_MODE_MASK) >> LCDC_CTRL_G_LE_MODE_SHIFT) 169 170 /* 171 * R_LE_MODE (RW) 172 * 173 * Endianess mode for Red Color Pads 174 * 1: Little endian. Pad 0 --> Color LSB 0 175 * 0: Big Endian. Pad 0--> Color MSB 7 176 */ 177 #define LCDC_CTRL_R_LE_MODE_MASK (0x4000U) 178 #define LCDC_CTRL_R_LE_MODE_SHIFT (14U) 179 #define LCDC_CTRL_R_LE_MODE_SET(x) (((uint32_t)(x) << LCDC_CTRL_R_LE_MODE_SHIFT) & LCDC_CTRL_R_LE_MODE_MASK) 180 #define LCDC_CTRL_R_LE_MODE_GET(x) (((uint32_t)(x) & LCDC_CTRL_R_LE_MODE_MASK) >> LCDC_CTRL_R_LE_MODE_SHIFT) 181 182 /* 183 * CAM_SYNC_EN (RW) 184 * 185 * Enable the VSYNC synchronization of CAM and LCDC 186 */ 187 #define LCDC_CTRL_CAM_SYNC_EN_MASK (0x2000U) 188 #define LCDC_CTRL_CAM_SYNC_EN_SHIFT (13U) 189 #define LCDC_CTRL_CAM_SYNC_EN_SET(x) (((uint32_t)(x) << LCDC_CTRL_CAM_SYNC_EN_SHIFT) & LCDC_CTRL_CAM_SYNC_EN_MASK) 190 #define LCDC_CTRL_CAM_SYNC_EN_GET(x) (((uint32_t)(x) & LCDC_CTRL_CAM_SYNC_EN_MASK) >> LCDC_CTRL_CAM_SYNC_EN_SHIFT) 191 192 /* 193 * INV_PXDATA (RW) 194 * 195 * Indicates if value at the output (pixel data output) needs to be negated. 196 * 0b - Output is to remain same as the data inside memory 197 * 1b - Output to be negated from the data inside memory 198 */ 199 #define LCDC_CTRL_INV_PXDATA_MASK (0x10U) 200 #define LCDC_CTRL_INV_PXDATA_SHIFT (4U) 201 #define LCDC_CTRL_INV_PXDATA_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_PXDATA_SHIFT) & LCDC_CTRL_INV_PXDATA_MASK) 202 #define LCDC_CTRL_INV_PXDATA_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_PXDATA_MASK) >> LCDC_CTRL_INV_PXDATA_SHIFT) 203 204 /* 205 * INV_PXCLK (RW) 206 * 207 * Polarity change of Pixel Clock. 208 * 0b - LCDC outputs data on the rising edge, and Display samples data on the falling edge 209 * 1b - LCDC outputs data on the falling edge, Display samples data on the rising edge 210 */ 211 #define LCDC_CTRL_INV_PXCLK_MASK (0x8U) 212 #define LCDC_CTRL_INV_PXCLK_SHIFT (3U) 213 #define LCDC_CTRL_INV_PXCLK_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_PXCLK_SHIFT) & LCDC_CTRL_INV_PXCLK_MASK) 214 #define LCDC_CTRL_INV_PXCLK_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_PXCLK_MASK) >> LCDC_CTRL_INV_PXCLK_SHIFT) 215 216 /* 217 * INV_HREF (RW) 218 * 219 * Polarity of HREF 220 * 0b - HREF signal active HIGH, indicating active pixel data 221 * 1b - HREF signal active LOW 222 */ 223 #define LCDC_CTRL_INV_HREF_MASK (0x4U) 224 #define LCDC_CTRL_INV_HREF_SHIFT (2U) 225 #define LCDC_CTRL_INV_HREF_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_HREF_SHIFT) & LCDC_CTRL_INV_HREF_MASK) 226 #define LCDC_CTRL_INV_HREF_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_HREF_MASK) >> LCDC_CTRL_INV_HREF_SHIFT) 227 228 /* 229 * INV_VSYNC (RW) 230 * 231 * Polarity of VSYNC 232 * 0b - VSYNC signal active HIGH 233 * 1b - VSYNC signal active LOW 234 */ 235 #define LCDC_CTRL_INV_VSYNC_MASK (0x2U) 236 #define LCDC_CTRL_INV_VSYNC_SHIFT (1U) 237 #define LCDC_CTRL_INV_VSYNC_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_VSYNC_SHIFT) & LCDC_CTRL_INV_VSYNC_MASK) 238 #define LCDC_CTRL_INV_VSYNC_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_VSYNC_MASK) >> LCDC_CTRL_INV_VSYNC_SHIFT) 239 240 /* 241 * INV_HSYNC (RW) 242 * 243 * Polarity of HSYNC 244 * 0b - HSYNC signal active HIGH 245 * 1b - HSYNC signal active LOW 246 */ 247 #define LCDC_CTRL_INV_HSYNC_MASK (0x1U) 248 #define LCDC_CTRL_INV_HSYNC_SHIFT (0U) 249 #define LCDC_CTRL_INV_HSYNC_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_HSYNC_SHIFT) & LCDC_CTRL_INV_HSYNC_MASK) 250 #define LCDC_CTRL_INV_HSYNC_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_HSYNC_MASK) >> LCDC_CTRL_INV_HSYNC_SHIFT) 251 252 /* Bitfield definition for register: BGND_CL */ 253 /* 254 * R (RW) 255 * 256 * Red component of the default color displayed in the sectors where no layer is active. 257 */ 258 #define LCDC_BGND_CL_R_MASK (0xFF0000UL) 259 #define LCDC_BGND_CL_R_SHIFT (16U) 260 #define LCDC_BGND_CL_R_SET(x) (((uint32_t)(x) << LCDC_BGND_CL_R_SHIFT) & LCDC_BGND_CL_R_MASK) 261 #define LCDC_BGND_CL_R_GET(x) (((uint32_t)(x) & LCDC_BGND_CL_R_MASK) >> LCDC_BGND_CL_R_SHIFT) 262 263 /* 264 * G (RW) 265 * 266 * Green component of the default color displayed in the sectors where no layer is active. 267 */ 268 #define LCDC_BGND_CL_G_MASK (0xFF00U) 269 #define LCDC_BGND_CL_G_SHIFT (8U) 270 #define LCDC_BGND_CL_G_SET(x) (((uint32_t)(x) << LCDC_BGND_CL_G_SHIFT) & LCDC_BGND_CL_G_MASK) 271 #define LCDC_BGND_CL_G_GET(x) (((uint32_t)(x) & LCDC_BGND_CL_G_MASK) >> LCDC_BGND_CL_G_SHIFT) 272 273 /* 274 * B (RW) 275 * 276 * Blue component of the default color displayed in the sectors where no layer is active. 277 */ 278 #define LCDC_BGND_CL_B_MASK (0xFFU) 279 #define LCDC_BGND_CL_B_SHIFT (0U) 280 #define LCDC_BGND_CL_B_SET(x) (((uint32_t)(x) << LCDC_BGND_CL_B_SHIFT) & LCDC_BGND_CL_B_MASK) 281 #define LCDC_BGND_CL_B_GET(x) (((uint32_t)(x) & LCDC_BGND_CL_B_MASK) >> LCDC_BGND_CL_B_SHIFT) 282 283 /* Bitfield definition for register: DISP_WN_SIZE */ 284 /* 285 * Y (RW) 286 * 287 * Sets the display size vertical resolution in pixels. 288 */ 289 #define LCDC_DISP_WN_SIZE_Y_MASK (0xFFF0000UL) 290 #define LCDC_DISP_WN_SIZE_Y_SHIFT (16U) 291 #define LCDC_DISP_WN_SIZE_Y_SET(x) (((uint32_t)(x) << LCDC_DISP_WN_SIZE_Y_SHIFT) & LCDC_DISP_WN_SIZE_Y_MASK) 292 #define LCDC_DISP_WN_SIZE_Y_GET(x) (((uint32_t)(x) & LCDC_DISP_WN_SIZE_Y_MASK) >> LCDC_DISP_WN_SIZE_Y_SHIFT) 293 294 /* 295 * X (RW) 296 * 297 * Sets the display size horizontal resolution in pixels. 298 */ 299 #define LCDC_DISP_WN_SIZE_X_MASK (0xFFFU) 300 #define LCDC_DISP_WN_SIZE_X_SHIFT (0U) 301 #define LCDC_DISP_WN_SIZE_X_SET(x) (((uint32_t)(x) << LCDC_DISP_WN_SIZE_X_SHIFT) & LCDC_DISP_WN_SIZE_X_MASK) 302 #define LCDC_DISP_WN_SIZE_X_GET(x) (((uint32_t)(x) & LCDC_DISP_WN_SIZE_X_MASK) >> LCDC_DISP_WN_SIZE_X_SHIFT) 303 304 /* Bitfield definition for register: HSYNC_PARA */ 305 /* 306 * FP (RW) 307 * 308 * HSYNC front-porch pulse width (in pixel clock cycles). If zero, indicates no front-porch for HSYNC 309 */ 310 #define LCDC_HSYNC_PARA_FP_MASK (0x7FC00000UL) 311 #define LCDC_HSYNC_PARA_FP_SHIFT (22U) 312 #define LCDC_HSYNC_PARA_FP_SET(x) (((uint32_t)(x) << LCDC_HSYNC_PARA_FP_SHIFT) & LCDC_HSYNC_PARA_FP_MASK) 313 #define LCDC_HSYNC_PARA_FP_GET(x) (((uint32_t)(x) & LCDC_HSYNC_PARA_FP_MASK) >> LCDC_HSYNC_PARA_FP_SHIFT) 314 315 /* 316 * BP (RW) 317 * 318 * HSYNC back-porch pulse width (in pixel clock cycles). If zero, indicates no back-porch for HSYNC 319 */ 320 #define LCDC_HSYNC_PARA_BP_MASK (0xFF800UL) 321 #define LCDC_HSYNC_PARA_BP_SHIFT (11U) 322 #define LCDC_HSYNC_PARA_BP_SET(x) (((uint32_t)(x) << LCDC_HSYNC_PARA_BP_SHIFT) & LCDC_HSYNC_PARA_BP_MASK) 323 #define LCDC_HSYNC_PARA_BP_GET(x) (((uint32_t)(x) & LCDC_HSYNC_PARA_BP_MASK) >> LCDC_HSYNC_PARA_BP_SHIFT) 324 325 /* 326 * PW (RW) 327 * 328 * HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. 329 */ 330 #define LCDC_HSYNC_PARA_PW_MASK (0x1FFU) 331 #define LCDC_HSYNC_PARA_PW_SHIFT (0U) 332 #define LCDC_HSYNC_PARA_PW_SET(x) (((uint32_t)(x) << LCDC_HSYNC_PARA_PW_SHIFT) & LCDC_HSYNC_PARA_PW_MASK) 333 #define LCDC_HSYNC_PARA_PW_GET(x) (((uint32_t)(x) & LCDC_HSYNC_PARA_PW_MASK) >> LCDC_HSYNC_PARA_PW_SHIFT) 334 335 /* Bitfield definition for register: VSYNC_PARA */ 336 /* 337 * FP (RW) 338 * 339 * VSYNC front-porch pulse width (in horizontal line cycles). If zero, means no front-porch for VSYNC 340 */ 341 #define LCDC_VSYNC_PARA_FP_MASK (0x7FC00000UL) 342 #define LCDC_VSYNC_PARA_FP_SHIFT (22U) 343 #define LCDC_VSYNC_PARA_FP_SET(x) (((uint32_t)(x) << LCDC_VSYNC_PARA_FP_SHIFT) & LCDC_VSYNC_PARA_FP_MASK) 344 #define LCDC_VSYNC_PARA_FP_GET(x) (((uint32_t)(x) & LCDC_VSYNC_PARA_FP_MASK) >> LCDC_VSYNC_PARA_FP_SHIFT) 345 346 /* 347 * BP (RW) 348 * 349 * VSYNC back-porch pulse width (in horizontal line cycles). If zero, means no back-porch for VSYNC 350 */ 351 #define LCDC_VSYNC_PARA_BP_MASK (0xFF800UL) 352 #define LCDC_VSYNC_PARA_BP_SHIFT (11U) 353 #define LCDC_VSYNC_PARA_BP_SET(x) (((uint32_t)(x) << LCDC_VSYNC_PARA_BP_SHIFT) & LCDC_VSYNC_PARA_BP_MASK) 354 #define LCDC_VSYNC_PARA_BP_GET(x) (((uint32_t)(x) & LCDC_VSYNC_PARA_BP_MASK) >> LCDC_VSYNC_PARA_BP_SHIFT) 355 356 /* 357 * PW (RW) 358 * 359 * VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. 360 */ 361 #define LCDC_VSYNC_PARA_PW_MASK (0x1FFU) 362 #define LCDC_VSYNC_PARA_PW_SHIFT (0U) 363 #define LCDC_VSYNC_PARA_PW_SET(x) (((uint32_t)(x) << LCDC_VSYNC_PARA_PW_SHIFT) & LCDC_VSYNC_PARA_PW_MASK) 364 #define LCDC_VSYNC_PARA_PW_GET(x) (((uint32_t)(x) & LCDC_VSYNC_PARA_PW_MASK) >> LCDC_VSYNC_PARA_PW_SHIFT) 365 366 /* Bitfield definition for register: DMA_ST */ 367 /* 368 * DMA_ERR (W1C) 369 * 370 * plane n axi error. W1C. 371 */ 372 #define LCDC_DMA_ST_DMA_ERR_MASK (0xFF000000UL) 373 #define LCDC_DMA_ST_DMA_ERR_SHIFT (24U) 374 #define LCDC_DMA_ST_DMA_ERR_SET(x) (((uint32_t)(x) << LCDC_DMA_ST_DMA_ERR_SHIFT) & LCDC_DMA_ST_DMA_ERR_MASK) 375 #define LCDC_DMA_ST_DMA_ERR_GET(x) (((uint32_t)(x) & LCDC_DMA_ST_DMA_ERR_MASK) >> LCDC_DMA_ST_DMA_ERR_SHIFT) 376 377 /* 378 * DMA1_DONE (W1C) 379 * 380 * Plane n frame 1 dma done. W1C. 381 */ 382 #define LCDC_DMA_ST_DMA1_DONE_MASK (0xFF0000UL) 383 #define LCDC_DMA_ST_DMA1_DONE_SHIFT (16U) 384 #define LCDC_DMA_ST_DMA1_DONE_SET(x) (((uint32_t)(x) << LCDC_DMA_ST_DMA1_DONE_SHIFT) & LCDC_DMA_ST_DMA1_DONE_MASK) 385 #define LCDC_DMA_ST_DMA1_DONE_GET(x) (((uint32_t)(x) & LCDC_DMA_ST_DMA1_DONE_MASK) >> LCDC_DMA_ST_DMA1_DONE_SHIFT) 386 387 /* 388 * DMA0_DONE (W1C) 389 * 390 * Plane n frame 0 dma done. W1C. 391 */ 392 #define LCDC_DMA_ST_DMA0_DONE_MASK (0xFF00U) 393 #define LCDC_DMA_ST_DMA0_DONE_SHIFT (8U) 394 #define LCDC_DMA_ST_DMA0_DONE_SET(x) (((uint32_t)(x) << LCDC_DMA_ST_DMA0_DONE_SHIFT) & LCDC_DMA_ST_DMA0_DONE_MASK) 395 #define LCDC_DMA_ST_DMA0_DONE_GET(x) (((uint32_t)(x) & LCDC_DMA_ST_DMA0_DONE_MASK) >> LCDC_DMA_ST_DMA0_DONE_SHIFT) 396 397 /* Bitfield definition for register: ST */ 398 /* 399 * P1_HANDSHAKE_ABORT (W1C) 400 * 401 * Plane 1 handshake abort error. W1C 402 */ 403 #define LCDC_ST_P1_HANDSHAKE_ABORT_MASK (0x100U) 404 #define LCDC_ST_P1_HANDSHAKE_ABORT_SHIFT (8U) 405 #define LCDC_ST_P1_HANDSHAKE_ABORT_SET(x) (((uint32_t)(x) << LCDC_ST_P1_HANDSHAKE_ABORT_SHIFT) & LCDC_ST_P1_HANDSHAKE_ABORT_MASK) 406 #define LCDC_ST_P1_HANDSHAKE_ABORT_GET(x) (((uint32_t)(x) & LCDC_ST_P1_HANDSHAKE_ABORT_MASK) >> LCDC_ST_P1_HANDSHAKE_ABORT_SHIFT) 407 408 /* 409 * P0_HANDSHAKE_ABORT (W1C) 410 * 411 * Plane 0 handshake abort error. W1C 412 */ 413 #define LCDC_ST_P0_HANDSHAKE_ABORT_MASK (0x80U) 414 #define LCDC_ST_P0_HANDSHAKE_ABORT_SHIFT (7U) 415 #define LCDC_ST_P0_HANDSHAKE_ABORT_SET(x) (((uint32_t)(x) << LCDC_ST_P0_HANDSHAKE_ABORT_SHIFT) & LCDC_ST_P0_HANDSHAKE_ABORT_MASK) 416 #define LCDC_ST_P0_HANDSHAKE_ABORT_GET(x) (((uint32_t)(x) & LCDC_ST_P0_HANDSHAKE_ABORT_MASK) >> LCDC_ST_P0_HANDSHAKE_ABORT_SHIFT) 417 418 /* 419 * CAM_HCNT_FAIL (W1C) 420 * 421 * During cam_vsync mode, sync fail due to hcnt out of acceptable ranges. W1C 422 */ 423 #define LCDC_ST_CAM_HCNT_FAIL_MASK (0x40U) 424 #define LCDC_ST_CAM_HCNT_FAIL_SHIFT (6U) 425 #define LCDC_ST_CAM_HCNT_FAIL_SET(x) (((uint32_t)(x) << LCDC_ST_CAM_HCNT_FAIL_SHIFT) & LCDC_ST_CAM_HCNT_FAIL_MASK) 426 #define LCDC_ST_CAM_HCNT_FAIL_GET(x) (((uint32_t)(x) & LCDC_ST_CAM_HCNT_FAIL_MASK) >> LCDC_ST_CAM_HCNT_FAIL_SHIFT) 427 428 /* 429 * CAM_VSYNC_FAIL (W1C) 430 * 431 * During cam_vsync mode, sync fail due to out of vsync parameters. W1C 432 */ 433 #define LCDC_ST_CAM_VSYNC_FAIL_MASK (0x20U) 434 #define LCDC_ST_CAM_VSYNC_FAIL_SHIFT (5U) 435 #define LCDC_ST_CAM_VSYNC_FAIL_SET(x) (((uint32_t)(x) << LCDC_ST_CAM_VSYNC_FAIL_SHIFT) & LCDC_ST_CAM_VSYNC_FAIL_MASK) 436 #define LCDC_ST_CAM_VSYNC_FAIL_GET(x) (((uint32_t)(x) & LCDC_ST_CAM_VSYNC_FAIL_MASK) >> LCDC_ST_CAM_VSYNC_FAIL_SHIFT) 437 438 /* 439 * SHADOW_DONE (RO) 440 * 441 * Shadow done status. This is an OR-ed signals of all shadow_done signals of all planes, and it can only be cleared by writing 1 for all asserted bits in SHADOW_DONE_ST register. 442 */ 443 #define LCDC_ST_SHADOW_DONE_MASK (0x10U) 444 #define LCDC_ST_SHADOW_DONE_SHIFT (4U) 445 #define LCDC_ST_SHADOW_DONE_GET(x) (((uint32_t)(x) & LCDC_ST_SHADOW_DONE_MASK) >> LCDC_ST_SHADOW_DONE_SHIFT) 446 447 /* 448 * URGENT_UNDERRUN (W1C) 449 * 450 * Asserted when the output buffer urgent underrun condition encountered 451 */ 452 #define LCDC_ST_URGENT_UNDERRUN_MASK (0x8U) 453 #define LCDC_ST_URGENT_UNDERRUN_SHIFT (3U) 454 #define LCDC_ST_URGENT_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_ST_URGENT_UNDERRUN_SHIFT) & LCDC_ST_URGENT_UNDERRUN_MASK) 455 #define LCDC_ST_URGENT_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_ST_URGENT_UNDERRUN_MASK) >> LCDC_ST_URGENT_UNDERRUN_SHIFT) 456 457 /* 458 * VS_BLANK (W1C) 459 * 460 * Asserted when in vertical blanking period. At the start of VSYNC 461 */ 462 #define LCDC_ST_VS_BLANK_MASK (0x4U) 463 #define LCDC_ST_VS_BLANK_SHIFT (2U) 464 #define LCDC_ST_VS_BLANK_SET(x) (((uint32_t)(x) << LCDC_ST_VS_BLANK_SHIFT) & LCDC_ST_VS_BLANK_MASK) 465 #define LCDC_ST_VS_BLANK_GET(x) (((uint32_t)(x) & LCDC_ST_VS_BLANK_MASK) >> LCDC_ST_VS_BLANK_SHIFT) 466 467 /* 468 * UNDERRUN (W1C) 469 * 470 * Asserted when the output buffer underrun condition encountered 471 */ 472 #define LCDC_ST_UNDERRUN_MASK (0x2U) 473 #define LCDC_ST_UNDERRUN_SHIFT (1U) 474 #define LCDC_ST_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_ST_UNDERRUN_SHIFT) & LCDC_ST_UNDERRUN_MASK) 475 #define LCDC_ST_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_ST_UNDERRUN_MASK) >> LCDC_ST_UNDERRUN_SHIFT) 476 477 /* 478 * VSYNC (W1C) 479 * 480 * Asserted when in vertical blanking period. At the end of VSYNC 481 */ 482 #define LCDC_ST_VSYNC_MASK (0x1U) 483 #define LCDC_ST_VSYNC_SHIFT (0U) 484 #define LCDC_ST_VSYNC_SET(x) (((uint32_t)(x) << LCDC_ST_VSYNC_SHIFT) & LCDC_ST_VSYNC_MASK) 485 #define LCDC_ST_VSYNC_GET(x) (((uint32_t)(x) & LCDC_ST_VSYNC_MASK) >> LCDC_ST_VSYNC_SHIFT) 486 487 /* Bitfield definition for register: INT_EN */ 488 /* 489 * DMA_ERR (RW) 490 * 491 * Interrupt enable for DMA error 492 */ 493 #define LCDC_INT_EN_DMA_ERR_MASK (0xFF000000UL) 494 #define LCDC_INT_EN_DMA_ERR_SHIFT (24U) 495 #define LCDC_INT_EN_DMA_ERR_SET(x) (((uint32_t)(x) << LCDC_INT_EN_DMA_ERR_SHIFT) & LCDC_INT_EN_DMA_ERR_MASK) 496 #define LCDC_INT_EN_DMA_ERR_GET(x) (((uint32_t)(x) & LCDC_INT_EN_DMA_ERR_MASK) >> LCDC_INT_EN_DMA_ERR_SHIFT) 497 498 /* 499 * DMA_DONE (RW) 500 * 501 * Interrupt enable for DMA done 502 */ 503 #define LCDC_INT_EN_DMA_DONE_MASK (0xFF0000UL) 504 #define LCDC_INT_EN_DMA_DONE_SHIFT (16U) 505 #define LCDC_INT_EN_DMA_DONE_SET(x) (((uint32_t)(x) << LCDC_INT_EN_DMA_DONE_SHIFT) & LCDC_INT_EN_DMA_DONE_MASK) 506 #define LCDC_INT_EN_DMA_DONE_GET(x) (((uint32_t)(x) & LCDC_INT_EN_DMA_DONE_MASK) >> LCDC_INT_EN_DMA_DONE_SHIFT) 507 508 /* 509 * HANDSHAKE_ABORT (RW) 510 * 511 * Handshake abort error int enable 512 */ 513 #define LCDC_INT_EN_HANDSHAKE_ABORT_MASK (0x80U) 514 #define LCDC_INT_EN_HANDSHAKE_ABORT_SHIFT (7U) 515 #define LCDC_INT_EN_HANDSHAKE_ABORT_SET(x) (((uint32_t)(x) << LCDC_INT_EN_HANDSHAKE_ABORT_SHIFT) & LCDC_INT_EN_HANDSHAKE_ABORT_MASK) 516 #define LCDC_INT_EN_HANDSHAKE_ABORT_GET(x) (((uint32_t)(x) & LCDC_INT_EN_HANDSHAKE_ABORT_MASK) >> LCDC_INT_EN_HANDSHAKE_ABORT_SHIFT) 517 518 /* 519 * CAM_HCNT_FAIL (RW) 520 * 521 * hcnt out of acceptable ranges interrupt enable 522 */ 523 #define LCDC_INT_EN_CAM_HCNT_FAIL_MASK (0x40U) 524 #define LCDC_INT_EN_CAM_HCNT_FAIL_SHIFT (6U) 525 #define LCDC_INT_EN_CAM_HCNT_FAIL_SET(x) (((uint32_t)(x) << LCDC_INT_EN_CAM_HCNT_FAIL_SHIFT) & LCDC_INT_EN_CAM_HCNT_FAIL_MASK) 526 #define LCDC_INT_EN_CAM_HCNT_FAIL_GET(x) (((uint32_t)(x) & LCDC_INT_EN_CAM_HCNT_FAIL_MASK) >> LCDC_INT_EN_CAM_HCNT_FAIL_SHIFT) 527 528 /* 529 * CAM_VSYNC_FAIL (RW) 530 * 531 * cam_vsync fail interrupt enable 532 */ 533 #define LCDC_INT_EN_CAM_VSYNC_FAIL_MASK (0x20U) 534 #define LCDC_INT_EN_CAM_VSYNC_FAIL_SHIFT (5U) 535 #define LCDC_INT_EN_CAM_VSYNC_FAIL_SET(x) (((uint32_t)(x) << LCDC_INT_EN_CAM_VSYNC_FAIL_SHIFT) & LCDC_INT_EN_CAM_VSYNC_FAIL_MASK) 536 #define LCDC_INT_EN_CAM_VSYNC_FAIL_GET(x) (((uint32_t)(x) & LCDC_INT_EN_CAM_VSYNC_FAIL_MASK) >> LCDC_INT_EN_CAM_VSYNC_FAIL_SHIFT) 537 538 /* 539 * SHADOW_DONE (RW) 540 * 541 * Shadow done interrupt enable 542 */ 543 #define LCDC_INT_EN_SHADOW_DONE_MASK (0x10U) 544 #define LCDC_INT_EN_SHADOW_DONE_SHIFT (4U) 545 #define LCDC_INT_EN_SHADOW_DONE_SET(x) (((uint32_t)(x) << LCDC_INT_EN_SHADOW_DONE_SHIFT) & LCDC_INT_EN_SHADOW_DONE_MASK) 546 #define LCDC_INT_EN_SHADOW_DONE_GET(x) (((uint32_t)(x) & LCDC_INT_EN_SHADOW_DONE_MASK) >> LCDC_INT_EN_SHADOW_DONE_SHIFT) 547 548 /* 549 * URGENT_UNDERRUN (RW) 550 * 551 * Asserted when the output buffer urgent underrun condition encountered 552 */ 553 #define LCDC_INT_EN_URGENT_UNDERRUN_MASK (0x8U) 554 #define LCDC_INT_EN_URGENT_UNDERRUN_SHIFT (3U) 555 #define LCDC_INT_EN_URGENT_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_INT_EN_URGENT_UNDERRUN_SHIFT) & LCDC_INT_EN_URGENT_UNDERRUN_MASK) 556 #define LCDC_INT_EN_URGENT_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_INT_EN_URGENT_UNDERRUN_MASK) >> LCDC_INT_EN_URGENT_UNDERRUN_SHIFT) 557 558 /* 559 * VS_BLANK (RW) 560 * 561 * Interrupt enable for start of sof 562 */ 563 #define LCDC_INT_EN_VS_BLANK_MASK (0x4U) 564 #define LCDC_INT_EN_VS_BLANK_SHIFT (2U) 565 #define LCDC_INT_EN_VS_BLANK_SET(x) (((uint32_t)(x) << LCDC_INT_EN_VS_BLANK_SHIFT) & LCDC_INT_EN_VS_BLANK_MASK) 566 #define LCDC_INT_EN_VS_BLANK_GET(x) (((uint32_t)(x) & LCDC_INT_EN_VS_BLANK_MASK) >> LCDC_INT_EN_VS_BLANK_SHIFT) 567 568 /* 569 * UNDERRUN (RW) 570 * 571 * Interrupt enable for underrun 572 */ 573 #define LCDC_INT_EN_UNDERRUN_MASK (0x2U) 574 #define LCDC_INT_EN_UNDERRUN_SHIFT (1U) 575 #define LCDC_INT_EN_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_INT_EN_UNDERRUN_SHIFT) & LCDC_INT_EN_UNDERRUN_MASK) 576 #define LCDC_INT_EN_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_INT_EN_UNDERRUN_MASK) >> LCDC_INT_EN_UNDERRUN_SHIFT) 577 578 /* 579 * VSYNC (RW) 580 * 581 * Interrupt enable for end of sof 582 */ 583 #define LCDC_INT_EN_VSYNC_MASK (0x1U) 584 #define LCDC_INT_EN_VSYNC_SHIFT (0U) 585 #define LCDC_INT_EN_VSYNC_SET(x) (((uint32_t)(x) << LCDC_INT_EN_VSYNC_SHIFT) & LCDC_INT_EN_VSYNC_MASK) 586 #define LCDC_INT_EN_VSYNC_GET(x) (((uint32_t)(x) & LCDC_INT_EN_VSYNC_MASK) >> LCDC_INT_EN_VSYNC_SHIFT) 587 588 /* Bitfield definition for register: TXFIFO */ 589 /* 590 * THRSH (RW) 591 * 592 * Threshold to start the lcd raster (0--0x7F) 593 */ 594 #define LCDC_TXFIFO_THRSH_MASK (0xFFU) 595 #define LCDC_TXFIFO_THRSH_SHIFT (0U) 596 #define LCDC_TXFIFO_THRSH_SET(x) (((uint32_t)(x) << LCDC_TXFIFO_THRSH_SHIFT) & LCDC_TXFIFO_THRSH_MASK) 597 #define LCDC_TXFIFO_THRSH_GET(x) (((uint32_t)(x) & LCDC_TXFIFO_THRSH_MASK) >> LCDC_TXFIFO_THRSH_SHIFT) 598 599 /* Bitfield definition for register: CTRL_BP_V_RANGE */ 600 /* 601 * MAX (RW) 602 * 603 * Maximal BP_V values 604 */ 605 #define LCDC_CTRL_BP_V_RANGE_MAX_MASK (0x7FC0000UL) 606 #define LCDC_CTRL_BP_V_RANGE_MAX_SHIFT (18U) 607 #define LCDC_CTRL_BP_V_RANGE_MAX_SET(x) (((uint32_t)(x) << LCDC_CTRL_BP_V_RANGE_MAX_SHIFT) & LCDC_CTRL_BP_V_RANGE_MAX_MASK) 608 #define LCDC_CTRL_BP_V_RANGE_MAX_GET(x) (((uint32_t)(x) & LCDC_CTRL_BP_V_RANGE_MAX_MASK) >> LCDC_CTRL_BP_V_RANGE_MAX_SHIFT) 609 610 /* 611 * BEST (RW) 612 * 613 * Best BP_V values 614 */ 615 #define LCDC_CTRL_BP_V_RANGE_BEST_MASK (0x3FE00UL) 616 #define LCDC_CTRL_BP_V_RANGE_BEST_SHIFT (9U) 617 #define LCDC_CTRL_BP_V_RANGE_BEST_SET(x) (((uint32_t)(x) << LCDC_CTRL_BP_V_RANGE_BEST_SHIFT) & LCDC_CTRL_BP_V_RANGE_BEST_MASK) 618 #define LCDC_CTRL_BP_V_RANGE_BEST_GET(x) (((uint32_t)(x) & LCDC_CTRL_BP_V_RANGE_BEST_MASK) >> LCDC_CTRL_BP_V_RANGE_BEST_SHIFT) 619 620 /* 621 * MIN (RW) 622 * 623 * Minimal BP_V values 624 */ 625 #define LCDC_CTRL_BP_V_RANGE_MIN_MASK (0x1FFU) 626 #define LCDC_CTRL_BP_V_RANGE_MIN_SHIFT (0U) 627 #define LCDC_CTRL_BP_V_RANGE_MIN_SET(x) (((uint32_t)(x) << LCDC_CTRL_BP_V_RANGE_MIN_SHIFT) & LCDC_CTRL_BP_V_RANGE_MIN_MASK) 628 #define LCDC_CTRL_BP_V_RANGE_MIN_GET(x) (((uint32_t)(x) & LCDC_CTRL_BP_V_RANGE_MIN_MASK) >> LCDC_CTRL_BP_V_RANGE_MIN_SHIFT) 629 630 /* Bitfield definition for register: CTRL_PW_V_RANGE */ 631 /* 632 * MAX (RW) 633 * 634 * Maximal PW_V values 635 */ 636 #define LCDC_CTRL_PW_V_RANGE_MAX_MASK (0x7FC0000UL) 637 #define LCDC_CTRL_PW_V_RANGE_MAX_SHIFT (18U) 638 #define LCDC_CTRL_PW_V_RANGE_MAX_SET(x) (((uint32_t)(x) << LCDC_CTRL_PW_V_RANGE_MAX_SHIFT) & LCDC_CTRL_PW_V_RANGE_MAX_MASK) 639 #define LCDC_CTRL_PW_V_RANGE_MAX_GET(x) (((uint32_t)(x) & LCDC_CTRL_PW_V_RANGE_MAX_MASK) >> LCDC_CTRL_PW_V_RANGE_MAX_SHIFT) 640 641 /* 642 * BEST (RW) 643 * 644 * Best PW_V values 645 */ 646 #define LCDC_CTRL_PW_V_RANGE_BEST_MASK (0x3FE00UL) 647 #define LCDC_CTRL_PW_V_RANGE_BEST_SHIFT (9U) 648 #define LCDC_CTRL_PW_V_RANGE_BEST_SET(x) (((uint32_t)(x) << LCDC_CTRL_PW_V_RANGE_BEST_SHIFT) & LCDC_CTRL_PW_V_RANGE_BEST_MASK) 649 #define LCDC_CTRL_PW_V_RANGE_BEST_GET(x) (((uint32_t)(x) & LCDC_CTRL_PW_V_RANGE_BEST_MASK) >> LCDC_CTRL_PW_V_RANGE_BEST_SHIFT) 650 651 /* 652 * MIN (RW) 653 * 654 * Minimal PW_V values 655 */ 656 #define LCDC_CTRL_PW_V_RANGE_MIN_MASK (0x1FFU) 657 #define LCDC_CTRL_PW_V_RANGE_MIN_SHIFT (0U) 658 #define LCDC_CTRL_PW_V_RANGE_MIN_SET(x) (((uint32_t)(x) << LCDC_CTRL_PW_V_RANGE_MIN_SHIFT) & LCDC_CTRL_PW_V_RANGE_MIN_MASK) 659 #define LCDC_CTRL_PW_V_RANGE_MIN_GET(x) (((uint32_t)(x) & LCDC_CTRL_PW_V_RANGE_MIN_MASK) >> LCDC_CTRL_PW_V_RANGE_MIN_SHIFT) 660 661 /* Bitfield definition for register: CTRL_FP_V_RANGE */ 662 /* 663 * MAX (RW) 664 * 665 * Maximal FP_V values 666 */ 667 #define LCDC_CTRL_FP_V_RANGE_MAX_MASK (0x7FC0000UL) 668 #define LCDC_CTRL_FP_V_RANGE_MAX_SHIFT (18U) 669 #define LCDC_CTRL_FP_V_RANGE_MAX_SET(x) (((uint32_t)(x) << LCDC_CTRL_FP_V_RANGE_MAX_SHIFT) & LCDC_CTRL_FP_V_RANGE_MAX_MASK) 670 #define LCDC_CTRL_FP_V_RANGE_MAX_GET(x) (((uint32_t)(x) & LCDC_CTRL_FP_V_RANGE_MAX_MASK) >> LCDC_CTRL_FP_V_RANGE_MAX_SHIFT) 671 672 /* 673 * BEST (RW) 674 * 675 * Best FP_V values 676 */ 677 #define LCDC_CTRL_FP_V_RANGE_BEST_MASK (0x3FE00UL) 678 #define LCDC_CTRL_FP_V_RANGE_BEST_SHIFT (9U) 679 #define LCDC_CTRL_FP_V_RANGE_BEST_SET(x) (((uint32_t)(x) << LCDC_CTRL_FP_V_RANGE_BEST_SHIFT) & LCDC_CTRL_FP_V_RANGE_BEST_MASK) 680 #define LCDC_CTRL_FP_V_RANGE_BEST_GET(x) (((uint32_t)(x) & LCDC_CTRL_FP_V_RANGE_BEST_MASK) >> LCDC_CTRL_FP_V_RANGE_BEST_SHIFT) 681 682 /* 683 * MIN (RW) 684 * 685 * Minimal FP_V values 686 */ 687 #define LCDC_CTRL_FP_V_RANGE_MIN_MASK (0x1FFU) 688 #define LCDC_CTRL_FP_V_RANGE_MIN_SHIFT (0U) 689 #define LCDC_CTRL_FP_V_RANGE_MIN_SET(x) (((uint32_t)(x) << LCDC_CTRL_FP_V_RANGE_MIN_SHIFT) & LCDC_CTRL_FP_V_RANGE_MIN_MASK) 690 #define LCDC_CTRL_FP_V_RANGE_MIN_GET(x) (((uint32_t)(x) & LCDC_CTRL_FP_V_RANGE_MIN_MASK) >> LCDC_CTRL_FP_V_RANGE_MIN_SHIFT) 691 692 /* Bitfield definition for register: CAM_SYNC_HCNT_MIN */ 693 /* 694 * VAL (RW) 695 * 696 * minimal acceptable HCNT Value 697 */ 698 #define LCDC_CAM_SYNC_HCNT_MIN_VAL_MASK (0xFFFFU) 699 #define LCDC_CAM_SYNC_HCNT_MIN_VAL_SHIFT (0U) 700 #define LCDC_CAM_SYNC_HCNT_MIN_VAL_SET(x) (((uint32_t)(x) << LCDC_CAM_SYNC_HCNT_MIN_VAL_SHIFT) & LCDC_CAM_SYNC_HCNT_MIN_VAL_MASK) 701 #define LCDC_CAM_SYNC_HCNT_MIN_VAL_GET(x) (((uint32_t)(x) & LCDC_CAM_SYNC_HCNT_MIN_VAL_MASK) >> LCDC_CAM_SYNC_HCNT_MIN_VAL_SHIFT) 702 703 /* Bitfield definition for register: CAM_SYNC_HCNT_BEST */ 704 /* 705 * HYST (RW) 706 * 707 * hysteresys of acceptable HCNT Value 708 */ 709 #define LCDC_CAM_SYNC_HCNT_BEST_HYST_MASK (0xFF0000UL) 710 #define LCDC_CAM_SYNC_HCNT_BEST_HYST_SHIFT (16U) 711 #define LCDC_CAM_SYNC_HCNT_BEST_HYST_SET(x) (((uint32_t)(x) << LCDC_CAM_SYNC_HCNT_BEST_HYST_SHIFT) & LCDC_CAM_SYNC_HCNT_BEST_HYST_MASK) 712 #define LCDC_CAM_SYNC_HCNT_BEST_HYST_GET(x) (((uint32_t)(x) & LCDC_CAM_SYNC_HCNT_BEST_HYST_MASK) >> LCDC_CAM_SYNC_HCNT_BEST_HYST_SHIFT) 713 714 /* 715 * VAL (RW) 716 * 717 * best acceptable HCNT Value 718 */ 719 #define LCDC_CAM_SYNC_HCNT_BEST_VAL_MASK (0xFFFFU) 720 #define LCDC_CAM_SYNC_HCNT_BEST_VAL_SHIFT (0U) 721 #define LCDC_CAM_SYNC_HCNT_BEST_VAL_SET(x) (((uint32_t)(x) << LCDC_CAM_SYNC_HCNT_BEST_VAL_SHIFT) & LCDC_CAM_SYNC_HCNT_BEST_VAL_MASK) 722 #define LCDC_CAM_SYNC_HCNT_BEST_VAL_GET(x) (((uint32_t)(x) & LCDC_CAM_SYNC_HCNT_BEST_VAL_MASK) >> LCDC_CAM_SYNC_HCNT_BEST_VAL_SHIFT) 723 724 /* Bitfield definition for register: CAM_SYNC_HCNT_MAX */ 725 /* 726 * VAL (RW) 727 * 728 * maximal acceptable HCNT Value 729 */ 730 #define LCDC_CAM_SYNC_HCNT_MAX_VAL_MASK (0xFFFFU) 731 #define LCDC_CAM_SYNC_HCNT_MAX_VAL_SHIFT (0U) 732 #define LCDC_CAM_SYNC_HCNT_MAX_VAL_SET(x) (((uint32_t)(x) << LCDC_CAM_SYNC_HCNT_MAX_VAL_SHIFT) & LCDC_CAM_SYNC_HCNT_MAX_VAL_MASK) 733 #define LCDC_CAM_SYNC_HCNT_MAX_VAL_GET(x) (((uint32_t)(x) & LCDC_CAM_SYNC_HCNT_MAX_VAL_MASK) >> LCDC_CAM_SYNC_HCNT_MAX_VAL_SHIFT) 734 735 /* Bitfield definition for register: CAM_SYNC_HCNT_ST */ 736 /* 737 * VAL (RO) 738 * 739 * current HCNT value 740 */ 741 #define LCDC_CAM_SYNC_HCNT_ST_VAL_MASK (0xFFFFU) 742 #define LCDC_CAM_SYNC_HCNT_ST_VAL_SHIFT (0U) 743 #define LCDC_CAM_SYNC_HCNT_ST_VAL_GET(x) (((uint32_t)(x) & LCDC_CAM_SYNC_HCNT_ST_VAL_MASK) >> LCDC_CAM_SYNC_HCNT_ST_VAL_SHIFT) 744 745 /* Bitfield definition for register: SHADOW_DONE_ST */ 746 /* 747 * VAL (RO) 748 * 749 * current shadow_done value for plane 7,...,0 respectively 750 */ 751 #define LCDC_SHADOW_DONE_ST_VAL_MASK (0xFFU) 752 #define LCDC_SHADOW_DONE_ST_VAL_SHIFT (0U) 753 #define LCDC_SHADOW_DONE_ST_VAL_GET(x) (((uint32_t)(x) & LCDC_SHADOW_DONE_ST_VAL_MASK) >> LCDC_SHADOW_DONE_ST_VAL_SHIFT) 754 755 /* Bitfield definition for register: SHADOW_DONE_INT_EN */ 756 /* 757 * VAL (RW) 758 * 759 * shadow_done interrupt enable for plane 7,...,0 respectively 760 */ 761 #define LCDC_SHADOW_DONE_INT_EN_VAL_MASK (0xFFU) 762 #define LCDC_SHADOW_DONE_INT_EN_VAL_SHIFT (0U) 763 #define LCDC_SHADOW_DONE_INT_EN_VAL_SET(x) (((uint32_t)(x) << LCDC_SHADOW_DONE_INT_EN_VAL_SHIFT) & LCDC_SHADOW_DONE_INT_EN_VAL_MASK) 764 #define LCDC_SHADOW_DONE_INT_EN_VAL_GET(x) (((uint32_t)(x) & LCDC_SHADOW_DONE_INT_EN_VAL_MASK) >> LCDC_SHADOW_DONE_INT_EN_VAL_SHIFT) 765 766 /* Bitfield definition for register of struct array LAYER: LAYCTRL */ 767 /* 768 * RESAMPLE_VRATIO (RW) 769 * 770 * Resample the input data stream in the verticle direction 771 * 0: don't resample 772 * positive n: upsample-by-n+1 (2 to 8) 773 * negtive n: downsample-by-n+1 (2 to 8) 774 */ 775 #define LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_MASK (0xF0000000UL) 776 #define LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_SHIFT (28U) 777 #define LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_SHIFT) & LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_MASK) 778 #define LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_MASK) >> LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_SHIFT) 779 780 /* 781 * RESAMPLE_HRATIO (RW) 782 * 783 * Resample the input data stream in the horizontal direction 784 * 0: don't resample 785 * positive n: upsample-by-n+1 (2 to 8) 786 * negtive n: downsample-by-n+1 (2 to 8) 787 */ 788 #define LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_MASK (0xF000000UL) 789 #define LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_SHIFT (24U) 790 #define LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_SHIFT) & LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_MASK) 791 #define LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_MASK) >> LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_SHIFT) 792 793 /* 794 * NORMLZ_OUT (RW) 795 * 796 * Normalize the pixel out for the not-overlapped pixels 797 */ 798 #define LCDC_LAYER_LAYCTRL_NORMLZ_OUT_MASK (0x800000UL) 799 #define LCDC_LAYER_LAYCTRL_NORMLZ_OUT_SHIFT (23U) 800 #define LCDC_LAYER_LAYCTRL_NORMLZ_OUT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_NORMLZ_OUT_SHIFT) & LCDC_LAYER_LAYCTRL_NORMLZ_OUT_MASK) 801 #define LCDC_LAYER_LAYCTRL_NORMLZ_OUT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_NORMLZ_OUT_MASK) >> LCDC_LAYER_LAYCTRL_NORMLZ_OUT_SHIFT) 802 803 /* 804 * HANDSHAKE_ABORT_INT_EN (RW) 805 * 806 * 1: Enable the handshake abort error interrupt. 807 * 0: don't Enable the handshake abort error interrupt. 808 * Abort is generated when the LCDC is going to switch bank to a new bank, and the new bank data is not ready yet. 809 * Abort is only useful when communicating with the offline calculator (such as PDMA as the active pixel generator mode). 810 * PDMA as the active generator mode, means it is the first pixel generator with data sources from offline memory, and not from on-the-fly streaming data (such as camera captured data). 811 * While with on-the-fly streaming data, error condition is indicated by display buffer underflow. 812 */ 813 #define LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_MASK (0x400000UL) 814 #define LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_SHIFT (22U) 815 #define LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_SHIFT) & LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_MASK) 816 #define LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_MASK) >> LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_SHIFT) 817 818 /* 819 * HANDSHAKE_BUFSIZE (RW) 820 * 821 * 1: handshake buffer is 16 rows hight per ping or pang buf. 822 * 0: handshake buffer is 8 rows hight per ping or pang buf. 823 */ 824 #define LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_MASK (0x200000UL) 825 #define LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_SHIFT (21U) 826 #define LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_SHIFT) & LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_MASK) 827 #define LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_MASK) >> LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_SHIFT) 828 829 /* 830 * ENABLE_HANDSHAKE (RW) 831 * 832 * Enable handshake with input pixel controller. When this is set, the LCDC will not process an entire framebuffer, 833 * but will instead process rows of NxN blocks in a double-buffer handshake with the input pixel controlller. This enables 834 * the use of the onboard SRAM for a partial frame buffer. Only valid for Plane 0 & 1. 835 * 1: handshake enabled 836 * 0: handshake disabled 837 */ 838 #define LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_MASK (0x100000UL) 839 #define LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_SHIFT (20U) 840 #define LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_SHIFT) & LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_MASK) 841 #define LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_MASK) >> LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_SHIFT) 842 843 /* 844 * PACK_DIR (RW) 845 * 846 * The byte sequence of the 4 bytes in a 32-bit word. 847 * 1: {A0, A1, A2, A3} byte re-ordered. 848 * 0: {A3, A2, A1, A0} the normal case with no byte re-order 849 */ 850 #define LCDC_LAYER_LAYCTRL_PACK_DIR_MASK (0x80000UL) 851 #define LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT (19U) 852 #define LCDC_LAYER_LAYCTRL_PACK_DIR_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT) & LCDC_LAYER_LAYCTRL_PACK_DIR_MASK) 853 #define LCDC_LAYER_LAYCTRL_PACK_DIR_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_PACK_DIR_MASK) >> LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT) 854 855 /* 856 * SHADOW_LOAD_EN (RW) 857 * 858 * Shadow Load Enable 859 * The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. 860 */ 861 #define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK (0x10000UL) 862 #define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT (16U) 863 #define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT) & LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK) 864 #define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK) >> LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT) 865 866 /* 867 * YUV_FORMAT (RW) 868 * 869 * The YUV422 input format selection. 870 * 00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 871 * 01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 872 * 10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 873 * 11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 874 * If not YUV422 mode, 875 * FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) 876 * FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) 877 */ 878 #define LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK (0xC000U) 879 #define LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT (14U) 880 #define LCDC_LAYER_LAYCTRL_YUV_FORMAT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT) & LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK) 881 #define LCDC_LAYER_LAYCTRL_YUV_FORMAT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK) >> LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT) 882 883 /* 884 * PIXFORMAT (RW) 885 * 886 * Layer encoding format (bit per pixel) 887 * 0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. 888 * 0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. 889 * 0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. 890 * 0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. 891 * 0100b - 16 bpp (RGB565), the low byte contains teh full R component. 892 * 0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] 893 * 1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A 894 * 1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 895 */ 896 #define LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK (0x3C00U) 897 #define LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT (10U) 898 #define LCDC_LAYER_LAYCTRL_PIXFORMAT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT) & LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK) 899 #define LCDC_LAYER_LAYCTRL_PIXFORMAT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK) >> LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT) 900 901 /* 902 * LOCALPHA_OP (RW) 903 * 904 * The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) 905 * 0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream 906 * 1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) 907 * 2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream 908 * Others: Reserved 909 */ 910 #define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK (0x300U) 911 #define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT (8U) 912 #define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT) & LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK) 913 #define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK) >> LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT) 914 915 /* 916 * INALPHA_OP (RW) 917 * 918 * The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) 919 * 0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline 920 * 1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) 921 * 2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline 922 * Others: Reserved 923 */ 924 #define LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK (0xC0U) 925 #define LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT (6U) 926 #define LCDC_LAYER_LAYCTRL_INALPHA_OP_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT) & LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK) 927 #define LCDC_LAYER_LAYCTRL_INALPHA_OP_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK) >> LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT) 928 929 /* 930 * AB_MODE (RW) 931 * 932 * Alpha Blending Mode 933 * 0: SKBlendMode_Clear; 934 * 1: SKBlendMode_Src ; 935 * 2: SKBlendMode_Dst 936 * 3: SKBlendMode_SrcOver 937 * 4: SKBlendMode_DstOver 938 * 5: SKBlendMode_SrcIn 939 * 6: SKBlendMode_DstIn 940 * 7: SKBlendMode_SrcOut 941 * 8: SKBlendMode_DstOut 942 * 9: SKBlendMode_SrcATop 943 * 10: SKBlendMode_DstATop 944 * 11: SKBlendMode_Xor 945 * 12: SKBlendMode_Plus (The conventional blending mode) 946 * 13: SKBlendMode_Modulate 947 * 14: SRC org 948 * 15: DST org 949 * Others: Reserved. 950 */ 951 #define LCDC_LAYER_LAYCTRL_AB_MODE_MASK (0x3CU) 952 #define LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT (2U) 953 #define LCDC_LAYER_LAYCTRL_AB_MODE_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT) & LCDC_LAYER_LAYCTRL_AB_MODE_MASK) 954 #define LCDC_LAYER_LAYCTRL_AB_MODE_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_AB_MODE_MASK) >> LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT) 955 956 /* 957 * EN (RW) 958 * 959 * Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. 960 */ 961 #define LCDC_LAYER_LAYCTRL_EN_MASK (0x1U) 962 #define LCDC_LAYER_LAYCTRL_EN_SHIFT (0U) 963 #define LCDC_LAYER_LAYCTRL_EN_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_EN_SHIFT) & LCDC_LAYER_LAYCTRL_EN_MASK) 964 #define LCDC_LAYER_LAYCTRL_EN_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_EN_MASK) >> LCDC_LAYER_LAYCTRL_EN_SHIFT) 965 966 /* Bitfield definition for register of struct array LAYER: ALPHAS */ 967 /* 968 * LOCD (RW) 969 * 970 * The system alpha value for the data stream of current layer stream (SRC) 971 */ 972 #define LCDC_LAYER_ALPHAS_LOCD_MASK (0xFF00U) 973 #define LCDC_LAYER_ALPHAS_LOCD_SHIFT (8U) 974 #define LCDC_LAYER_ALPHAS_LOCD_SET(x) (((uint32_t)(x) << LCDC_LAYER_ALPHAS_LOCD_SHIFT) & LCDC_LAYER_ALPHAS_LOCD_MASK) 975 #define LCDC_LAYER_ALPHAS_LOCD_GET(x) (((uint32_t)(x) & LCDC_LAYER_ALPHAS_LOCD_MASK) >> LCDC_LAYER_ALPHAS_LOCD_SHIFT) 976 977 /* 978 * IND (RW) 979 * 980 * The system alpha value for the input stream from previous stage (DST) 981 */ 982 #define LCDC_LAYER_ALPHAS_IND_MASK (0xFFU) 983 #define LCDC_LAYER_ALPHAS_IND_SHIFT (0U) 984 #define LCDC_LAYER_ALPHAS_IND_SET(x) (((uint32_t)(x) << LCDC_LAYER_ALPHAS_IND_SHIFT) & LCDC_LAYER_ALPHAS_IND_MASK) 985 #define LCDC_LAYER_ALPHAS_IND_GET(x) (((uint32_t)(x) & LCDC_LAYER_ALPHAS_IND_MASK) >> LCDC_LAYER_ALPHAS_IND_SHIFT) 986 987 /* Bitfield definition for register of struct array LAYER: LAYSIZE */ 988 /* 989 * HEIGHT (RW) 990 * 991 * Height of the layer in pixels 992 */ 993 #define LCDC_LAYER_LAYSIZE_HEIGHT_MASK (0xFFF0000UL) 994 #define LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT (16U) 995 #define LCDC_LAYER_LAYSIZE_HEIGHT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT) & LCDC_LAYER_LAYSIZE_HEIGHT_MASK) 996 #define LCDC_LAYER_LAYSIZE_HEIGHT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYSIZE_HEIGHT_MASK) >> LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT) 997 998 /* 999 * WIDTH (RW) 1000 * 1001 * Width of the layer in pixels (Note: not actual width-1) 1002 * The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. 1003 */ 1004 #define LCDC_LAYER_LAYSIZE_WIDTH_MASK (0xFFFU) 1005 #define LCDC_LAYER_LAYSIZE_WIDTH_SHIFT (0U) 1006 #define LCDC_LAYER_LAYSIZE_WIDTH_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYSIZE_WIDTH_SHIFT) & LCDC_LAYER_LAYSIZE_WIDTH_MASK) 1007 #define LCDC_LAYER_LAYSIZE_WIDTH_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYSIZE_WIDTH_MASK) >> LCDC_LAYER_LAYSIZE_WIDTH_SHIFT) 1008 1009 /* Bitfield definition for register of struct array LAYER: LAYPOS */ 1010 /* 1011 * Y (RW) 1012 * 1013 * The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. 1014 */ 1015 #define LCDC_LAYER_LAYPOS_Y_MASK (0xFFFF0000UL) 1016 #define LCDC_LAYER_LAYPOS_Y_SHIFT (16U) 1017 #define LCDC_LAYER_LAYPOS_Y_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYPOS_Y_SHIFT) & LCDC_LAYER_LAYPOS_Y_MASK) 1018 #define LCDC_LAYER_LAYPOS_Y_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYPOS_Y_MASK) >> LCDC_LAYER_LAYPOS_Y_SHIFT) 1019 1020 /* 1021 * X (RW) 1022 * 1023 * The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. 1024 */ 1025 #define LCDC_LAYER_LAYPOS_X_MASK (0xFFFFU) 1026 #define LCDC_LAYER_LAYPOS_X_SHIFT (0U) 1027 #define LCDC_LAYER_LAYPOS_X_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYPOS_X_SHIFT) & LCDC_LAYER_LAYPOS_X_MASK) 1028 #define LCDC_LAYER_LAYPOS_X_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYPOS_X_MASK) >> LCDC_LAYER_LAYPOS_X_SHIFT) 1029 1030 /* Bitfield definition for register of struct array LAYER: START0 */ 1031 /* 1032 * ADDR0 (RW) 1033 * 1034 * Input buffer Start address 0 1035 */ 1036 #define LCDC_LAYER_START0_ADDR0_MASK (0xFFFFFFFFUL) 1037 #define LCDC_LAYER_START0_ADDR0_SHIFT (0U) 1038 #define LCDC_LAYER_START0_ADDR0_SET(x) (((uint32_t)(x) << LCDC_LAYER_START0_ADDR0_SHIFT) & LCDC_LAYER_START0_ADDR0_MASK) 1039 #define LCDC_LAYER_START0_ADDR0_GET(x) (((uint32_t)(x) & LCDC_LAYER_START0_ADDR0_MASK) >> LCDC_LAYER_START0_ADDR0_SHIFT) 1040 1041 /* Bitfield definition for register of struct array LAYER: LINECFG */ 1042 /* 1043 * MPT_SIZE (RW) 1044 * 1045 * Maximal Per Transfer Data Size: 1046 * 0: 64 bytes 1047 * 1: 128 bytes 1048 * 2: 256 bytes 1049 * 3: 512 bytes 1050 * 4: 1024 bytes 1051 */ 1052 #define LCDC_LAYER_LINECFG_MPT_SIZE_MASK (0xE0000000UL) 1053 #define LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT (29U) 1054 #define LCDC_LAYER_LINECFG_MPT_SIZE_SET(x) (((uint32_t)(x) << LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT) & LCDC_LAYER_LINECFG_MPT_SIZE_MASK) 1055 #define LCDC_LAYER_LINECFG_MPT_SIZE_GET(x) (((uint32_t)(x) & LCDC_LAYER_LINECFG_MPT_SIZE_MASK) >> LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT) 1056 1057 /* 1058 * MAX_OT (RW) 1059 * 1060 * the number of outstanding axi read transactions. 1061 * If zero, it means max 8. 1062 */ 1063 #define LCDC_LAYER_LINECFG_MAX_OT_MASK (0xE00000UL) 1064 #define LCDC_LAYER_LINECFG_MAX_OT_SHIFT (21U) 1065 #define LCDC_LAYER_LINECFG_MAX_OT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LINECFG_MAX_OT_SHIFT) & LCDC_LAYER_LINECFG_MAX_OT_MASK) 1066 #define LCDC_LAYER_LINECFG_MAX_OT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LINECFG_MAX_OT_MASK) >> LCDC_LAYER_LINECFG_MAX_OT_SHIFT) 1067 1068 /* 1069 * PITCH (RW) 1070 * 1071 * Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. 1072 */ 1073 #define LCDC_LAYER_LINECFG_PITCH_MASK (0xFFFFU) 1074 #define LCDC_LAYER_LINECFG_PITCH_SHIFT (0U) 1075 #define LCDC_LAYER_LINECFG_PITCH_SET(x) (((uint32_t)(x) << LCDC_LAYER_LINECFG_PITCH_SHIFT) & LCDC_LAYER_LINECFG_PITCH_MASK) 1076 #define LCDC_LAYER_LINECFG_PITCH_GET(x) (((uint32_t)(x) & LCDC_LAYER_LINECFG_PITCH_MASK) >> LCDC_LAYER_LINECFG_PITCH_SHIFT) 1077 1078 /* Bitfield definition for register of struct array LAYER: BG_CL */ 1079 /* 1080 * ARGB (RW) 1081 * 1082 * ARGB8888. It is only useful in the last active stage in the pipeline. 1083 */ 1084 #define LCDC_LAYER_BG_CL_ARGB_MASK (0xFFFFFFFFUL) 1085 #define LCDC_LAYER_BG_CL_ARGB_SHIFT (0U) 1086 #define LCDC_LAYER_BG_CL_ARGB_SET(x) (((uint32_t)(x) << LCDC_LAYER_BG_CL_ARGB_SHIFT) & LCDC_LAYER_BG_CL_ARGB_MASK) 1087 #define LCDC_LAYER_BG_CL_ARGB_GET(x) (((uint32_t)(x) & LCDC_LAYER_BG_CL_ARGB_MASK) >> LCDC_LAYER_BG_CL_ARGB_SHIFT) 1088 1089 /* Bitfield definition for register of struct array LAYER: CSC_COEF0 */ 1090 /* 1091 * YCBCR_MODE (RW) 1092 * 1093 * This bit changes the behavior when performing U/V converting. 1094 * 0b - Converting YUV to RGB data 1095 * 1b - Converting YCbCr to RGB data 1096 */ 1097 #define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK (0x80000000UL) 1098 #define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT (31U) 1099 #define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT) & LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK) 1100 #define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK) >> LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT) 1101 1102 /* 1103 * ENABLE (RW) 1104 * 1105 * Enable the CSC unit in the LCDC plane data path. 1106 * 0b - The CSC is bypassed and the input pixels are RGB data already 1107 * 1b - The CSC is enabled and the pixels will be converted to RGB data 1108 * This bit will be shadowed. 1109 */ 1110 #define LCDC_LAYER_CSC_COEF0_ENABLE_MASK (0x40000000UL) 1111 #define LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT (30U) 1112 #define LCDC_LAYER_CSC_COEF0_ENABLE_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT) & LCDC_LAYER_CSC_COEF0_ENABLE_MASK) 1113 #define LCDC_LAYER_CSC_COEF0_ENABLE_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_ENABLE_MASK) >> LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT) 1114 1115 /* 1116 * C0 (RW) 1117 * 1118 * Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) 1119 */ 1120 #define LCDC_LAYER_CSC_COEF0_C0_MASK (0x1FFC0000UL) 1121 #define LCDC_LAYER_CSC_COEF0_C0_SHIFT (18U) 1122 #define LCDC_LAYER_CSC_COEF0_C0_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_C0_SHIFT) & LCDC_LAYER_CSC_COEF0_C0_MASK) 1123 #define LCDC_LAYER_CSC_COEF0_C0_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_C0_MASK) >> LCDC_LAYER_CSC_COEF0_C0_SHIFT) 1124 1125 /* 1126 * UV_OFFSET (RW) 1127 * 1128 * Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. 1129 * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). 1130 */ 1131 #define LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK (0x3FE00UL) 1132 #define LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT (9U) 1133 #define LCDC_LAYER_CSC_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT) & LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK) 1134 #define LCDC_LAYER_CSC_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK) >> LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT) 1135 1136 /* 1137 * Y_OFFSET (RW) 1138 * 1139 * Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is 1140 * typically -16 (0x1F0). 1141 */ 1142 #define LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK (0x1FFU) 1143 #define LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT (0U) 1144 #define LCDC_LAYER_CSC_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT) & LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK) 1145 #define LCDC_LAYER_CSC_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK) >> LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT) 1146 1147 /* Bitfield definition for register of struct array LAYER: CSC_COEF1 */ 1148 /* 1149 * C1 (RW) 1150 * 1151 * Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). 1152 */ 1153 #define LCDC_LAYER_CSC_COEF1_C1_MASK (0x7FF0000UL) 1154 #define LCDC_LAYER_CSC_COEF1_C1_SHIFT (16U) 1155 #define LCDC_LAYER_CSC_COEF1_C1_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF1_C1_SHIFT) & LCDC_LAYER_CSC_COEF1_C1_MASK) 1156 #define LCDC_LAYER_CSC_COEF1_C1_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF1_C1_MASK) >> LCDC_LAYER_CSC_COEF1_C1_SHIFT) 1157 1158 /* 1159 * C4 (RW) 1160 * 1161 * Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). 1162 */ 1163 #define LCDC_LAYER_CSC_COEF1_C4_MASK (0x7FFU) 1164 #define LCDC_LAYER_CSC_COEF1_C4_SHIFT (0U) 1165 #define LCDC_LAYER_CSC_COEF1_C4_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF1_C4_SHIFT) & LCDC_LAYER_CSC_COEF1_C4_MASK) 1166 #define LCDC_LAYER_CSC_COEF1_C4_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF1_C4_MASK) >> LCDC_LAYER_CSC_COEF1_C4_SHIFT) 1167 1168 /* Bitfield definition for register of struct array LAYER: CSC_COEF2 */ 1169 /* 1170 * C2 (RW) 1171 * 1172 * Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). 1173 */ 1174 #define LCDC_LAYER_CSC_COEF2_C2_MASK (0x7FF0000UL) 1175 #define LCDC_LAYER_CSC_COEF2_C2_SHIFT (16U) 1176 #define LCDC_LAYER_CSC_COEF2_C2_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF2_C2_SHIFT) & LCDC_LAYER_CSC_COEF2_C2_MASK) 1177 #define LCDC_LAYER_CSC_COEF2_C2_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF2_C2_MASK) >> LCDC_LAYER_CSC_COEF2_C2_SHIFT) 1178 1179 /* 1180 * C3 (RW) 1181 * 1182 * Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). 1183 */ 1184 #define LCDC_LAYER_CSC_COEF2_C3_MASK (0x7FFU) 1185 #define LCDC_LAYER_CSC_COEF2_C3_SHIFT (0U) 1186 #define LCDC_LAYER_CSC_COEF2_C3_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF2_C3_SHIFT) & LCDC_LAYER_CSC_COEF2_C3_MASK) 1187 #define LCDC_LAYER_CSC_COEF2_C3_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF2_C3_MASK) >> LCDC_LAYER_CSC_COEF2_C3_SHIFT) 1188 1189 /* Bitfield definition for register: CLUT_LOAD */ 1190 /* 1191 * STR_HIGH (RW) 1192 * 1193 * 1'b1: Store 8+ CLUT tables through APB 1194 * 1'b0: Store 0-7 CLUT tables through APB 1195 */ 1196 #define LCDC_CLUT_LOAD_STR_HIGH_MASK (0x80000000UL) 1197 #define LCDC_CLUT_LOAD_STR_HIGH_SHIFT (31U) 1198 #define LCDC_CLUT_LOAD_STR_HIGH_SET(x) (((uint32_t)(x) << LCDC_CLUT_LOAD_STR_HIGH_SHIFT) & LCDC_CLUT_LOAD_STR_HIGH_MASK) 1199 #define LCDC_CLUT_LOAD_STR_HIGH_GET(x) (((uint32_t)(x) & LCDC_CLUT_LOAD_STR_HIGH_MASK) >> LCDC_CLUT_LOAD_STR_HIGH_SHIFT) 1200 1201 /* 1202 * SEL_NUM (RW) 1203 * 1204 * Selected CLUT Number 1205 * The SEL_CLUT_NUM is used to select which plane's CLUT need to be updated. The hardware can only backup one CLUT setting and load, so the SEL_CLUT_NUM can't be changed when CLUT_LOAD[UPDATE_EN] is 1. 1206 * . 3'h0 - PLANE 0 1207 * . 3'h1 - PLANE 1 1208 * . ------ 1209 * . 3'h7 - PLANE 7 1210 * CLUT 8 can be modified via APB even when display is on. 1211 * Currently CLUT for plane 0..7 cannot be modified via APB when display is on. Can only be updated via CLUT_LOAD[UPDATE_EN] bit. 1212 */ 1213 #define LCDC_CLUT_LOAD_SEL_NUM_MASK (0x70U) 1214 #define LCDC_CLUT_LOAD_SEL_NUM_SHIFT (4U) 1215 #define LCDC_CLUT_LOAD_SEL_NUM_SET(x) (((uint32_t)(x) << LCDC_CLUT_LOAD_SEL_NUM_SHIFT) & LCDC_CLUT_LOAD_SEL_NUM_MASK) 1216 #define LCDC_CLUT_LOAD_SEL_NUM_GET(x) (((uint32_t)(x) & LCDC_CLUT_LOAD_SEL_NUM_MASK) >> LCDC_CLUT_LOAD_SEL_NUM_SHIFT) 1217 1218 /* 1219 * UPDATE_EN (RW) 1220 * 1221 * CLUT Update Enable 1222 * The bit is written to 1 when software want to update the Color Look Up Tables during display. 1223 * If set to 1, software update selected CLUT due to SEL_CLUT_NUM setting, the table will be copied from CLUT8 during vertical blanking period after SHADOW_LOAD_EN is set to 1. 1224 * If set to 0, software can update CLUT8 directly according to the CLUT memory map. 1225 * Hardware will automatically clear this bit when selected CLUT is updated according to SEL_CLUT_NUM. 1226 */ 1227 #define LCDC_CLUT_LOAD_UPDATE_EN_MASK (0x1U) 1228 #define LCDC_CLUT_LOAD_UPDATE_EN_SHIFT (0U) 1229 #define LCDC_CLUT_LOAD_UPDATE_EN_SET(x) (((uint32_t)(x) << LCDC_CLUT_LOAD_UPDATE_EN_SHIFT) & LCDC_CLUT_LOAD_UPDATE_EN_MASK) 1230 #define LCDC_CLUT_LOAD_UPDATE_EN_GET(x) (((uint32_t)(x) & LCDC_CLUT_LOAD_UPDATE_EN_MASK) >> LCDC_CLUT_LOAD_UPDATE_EN_SHIFT) 1231 1232 1233 1234 /* LAYER register group index macro definition */ 1235 #define LCDC_LAYER_0 (0UL) 1236 #define LCDC_LAYER_1 (1UL) 1237 #define LCDC_LAYER_2 (2UL) 1238 #define LCDC_LAYER_3 (3UL) 1239 #define LCDC_LAYER_4 (4UL) 1240 #define LCDC_LAYER_5 (5UL) 1241 #define LCDC_LAYER_6 (6UL) 1242 #define LCDC_LAYER_7 (7UL) 1243 1244 1245 #endif /* HPM_LCDC_H */ 1246