1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_LINV2_H 10 #define HPM_LINV2_H 11 12 typedef struct { 13 union { 14 __RW uint32_t DATA[2]; /* 0x0 - 0x4: data byte */ 15 __RW uint8_t DATA_BYTE[8]; /* 0x0 - 0x7: */ 16 }; 17 __RW uint32_t DATA_LEN_ID; /* 0x8: data length and ID register */ 18 __RW uint32_t CONTROL_STATUS; /* 0xC: control and status register */ 19 __RW uint32_t TIMING_CONTROL; /* 0x10: timing control register */ 20 __RW uint32_t DMA_CONTROL; /* 0x14: dma control register */ 21 } LINV2_Type; 22 23 24 /* Bitfield definition for register: DATA0 */ 25 /* 26 * DATA (RW) 27 * 28 * data 29 */ 30 #define LINV2_DATA_DATA_MASK (0xFFFFFFFFUL) 31 #define LINV2_DATA_DATA_SHIFT (0U) 32 #define LINV2_DATA_DATA_SET(x) (((uint32_t)(x) << LINV2_DATA_DATA_SHIFT) & LINV2_DATA_DATA_MASK) 33 #define LINV2_DATA_DATA_GET(x) (((uint32_t)(x) & LINV2_DATA_DATA_MASK) >> LINV2_DATA_DATA_SHIFT) 34 35 /* Bitfield definition for register: DATA_BYTE0 */ 36 /* 37 * DATA_BYTE (RW) 38 * 39 * data byte 40 */ 41 #define LINV2_DATA_BYTE_DATA_BYTE_MASK (0xFFU) 42 #define LINV2_DATA_BYTE_DATA_BYTE_SHIFT (0U) 43 #define LINV2_DATA_BYTE_DATA_BYTE_SET(x) (((uint8_t)(x) << LINV2_DATA_BYTE_DATA_BYTE_SHIFT) & LINV2_DATA_BYTE_DATA_BYTE_MASK) 44 #define LINV2_DATA_BYTE_DATA_BYTE_GET(x) (((uint8_t)(x) & LINV2_DATA_BYTE_DATA_BYTE_MASK) >> LINV2_DATA_BYTE_DATA_BYTE_SHIFT) 45 46 /* Bitfield definition for register: DATA_LEN_ID */ 47 /* 48 * CHECKSUM (RO) 49 * 50 */ 51 #define LINV2_DATA_LEN_ID_CHECKSUM_MASK (0xFF0000UL) 52 #define LINV2_DATA_LEN_ID_CHECKSUM_SHIFT (16U) 53 #define LINV2_DATA_LEN_ID_CHECKSUM_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_CHECKSUM_MASK) >> LINV2_DATA_LEN_ID_CHECKSUM_SHIFT) 54 55 /* 56 * ID_PARITY (RO) 57 * 58 */ 59 #define LINV2_DATA_LEN_ID_ID_PARITY_MASK (0xC000U) 60 #define LINV2_DATA_LEN_ID_ID_PARITY_SHIFT (14U) 61 #define LINV2_DATA_LEN_ID_ID_PARITY_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_ID_PARITY_MASK) >> LINV2_DATA_LEN_ID_ID_PARITY_SHIFT) 62 63 /* 64 * ID (RW) 65 * 66 * ID register 67 */ 68 #define LINV2_DATA_LEN_ID_ID_MASK (0x3F00U) 69 #define LINV2_DATA_LEN_ID_ID_SHIFT (8U) 70 #define LINV2_DATA_LEN_ID_ID_SET(x) (((uint32_t)(x) << LINV2_DATA_LEN_ID_ID_SHIFT) & LINV2_DATA_LEN_ID_ID_MASK) 71 #define LINV2_DATA_LEN_ID_ID_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_ID_MASK) >> LINV2_DATA_LEN_ID_ID_SHIFT) 72 73 /* 74 * ENH_CHECK (RW) 75 * 76 * 1:enhance check mode 0:classical check mode 77 */ 78 #define LINV2_DATA_LEN_ID_ENH_CHECK_MASK (0x80U) 79 #define LINV2_DATA_LEN_ID_ENH_CHECK_SHIFT (7U) 80 #define LINV2_DATA_LEN_ID_ENH_CHECK_SET(x) (((uint32_t)(x) << LINV2_DATA_LEN_ID_ENH_CHECK_SHIFT) & LINV2_DATA_LEN_ID_ENH_CHECK_MASK) 81 #define LINV2_DATA_LEN_ID_ENH_CHECK_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_ENH_CHECK_MASK) >> LINV2_DATA_LEN_ID_ENH_CHECK_SHIFT) 82 83 /* 84 * DATA_LEN (RW) 85 * 86 * payload data length control register。The data length will decoded from ID[5:4] when all 1 is configured: 00-2 01-2 10-4 11-8 87 */ 88 #define LINV2_DATA_LEN_ID_DATA_LEN_MASK (0xFU) 89 #define LINV2_DATA_LEN_ID_DATA_LEN_SHIFT (0U) 90 #define LINV2_DATA_LEN_ID_DATA_LEN_SET(x) (((uint32_t)(x) << LINV2_DATA_LEN_ID_DATA_LEN_SHIFT) & LINV2_DATA_LEN_ID_DATA_LEN_MASK) 91 #define LINV2_DATA_LEN_ID_DATA_LEN_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_DATA_LEN_MASK) >> LINV2_DATA_LEN_ID_DATA_LEN_SHIFT) 92 93 /* Bitfield definition for register: CONTROL_STATUS */ 94 /* 95 * BREAK_ERR_DIS (RW) 96 * 97 */ 98 #define LINV2_CONTROL_STATUS_BREAK_ERR_DIS_MASK (0x200000UL) 99 #define LINV2_CONTROL_STATUS_BREAK_ERR_DIS_SHIFT (21U) 100 #define LINV2_CONTROL_STATUS_BREAK_ERR_DIS_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_BREAK_ERR_DIS_SHIFT) & LINV2_CONTROL_STATUS_BREAK_ERR_DIS_MASK) 101 #define LINV2_CONTROL_STATUS_BREAK_ERR_DIS_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_BREAK_ERR_DIS_MASK) >> LINV2_CONTROL_STATUS_BREAK_ERR_DIS_SHIFT) 102 103 /* 104 * BREAK_ERR (RO) 105 * 106 */ 107 #define LINV2_CONTROL_STATUS_BREAK_ERR_MASK (0x100000UL) 108 #define LINV2_CONTROL_STATUS_BREAK_ERR_SHIFT (20U) 109 #define LINV2_CONTROL_STATUS_BREAK_ERR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_BREAK_ERR_MASK) >> LINV2_CONTROL_STATUS_BREAK_ERR_SHIFT) 110 111 /* 112 * PARITY_ERROR (RO) 113 * 114 * slave only. identifier parity error 115 */ 116 #define LINV2_CONTROL_STATUS_PARITY_ERROR_MASK (0x80000UL) 117 #define LINV2_CONTROL_STATUS_PARITY_ERROR_SHIFT (19U) 118 #define LINV2_CONTROL_STATUS_PARITY_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_PARITY_ERROR_MASK) >> LINV2_CONTROL_STATUS_PARITY_ERROR_SHIFT) 119 120 /* 121 * TIME_OUT (RO) 122 * 123 * timeout error. The master detects a timeout error if it is expecting data from the bus but no slave does respond. The slave detects a timeout error if it is requesting a data acknowledge to the host controller. The slave detects a timeout if it has transmitted a wakeup signal and it detects no sync field within 150ms 124 */ 125 #define LINV2_CONTROL_STATUS_TIME_OUT_MASK (0x40000UL) 126 #define LINV2_CONTROL_STATUS_TIME_OUT_SHIFT (18U) 127 #define LINV2_CONTROL_STATUS_TIME_OUT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_TIME_OUT_MASK) >> LINV2_CONTROL_STATUS_TIME_OUT_SHIFT) 128 129 /* 130 * CHK_ERROR (RO) 131 * 132 * checksum error 133 */ 134 #define LINV2_CONTROL_STATUS_CHK_ERROR_MASK (0x20000UL) 135 #define LINV2_CONTROL_STATUS_CHK_ERROR_SHIFT (17U) 136 #define LINV2_CONTROL_STATUS_CHK_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_CHK_ERROR_MASK) >> LINV2_CONTROL_STATUS_CHK_ERROR_SHIFT) 137 138 /* 139 * BIT_ERROR (RO) 140 * 141 * bit error 142 */ 143 #define LINV2_CONTROL_STATUS_BIT_ERROR_MASK (0x10000UL) 144 #define LINV2_CONTROL_STATUS_BIT_ERROR_SHIFT (16U) 145 #define LINV2_CONTROL_STATUS_BIT_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_BIT_ERROR_MASK) >> LINV2_CONTROL_STATUS_BIT_ERROR_SHIFT) 146 147 /* 148 * LIN_ACTIVE (RO) 149 * 150 * The bit indicates whether the LIN bus is active or not 151 */ 152 #define LINV2_CONTROL_STATUS_LIN_ACTIVE_MASK (0x8000U) 153 #define LINV2_CONTROL_STATUS_LIN_ACTIVE_SHIFT (15U) 154 #define LINV2_CONTROL_STATUS_LIN_ACTIVE_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_LIN_ACTIVE_MASK) >> LINV2_CONTROL_STATUS_LIN_ACTIVE_SHIFT) 155 156 /* 157 * BUS_IDLE_TIMEOUT (RO) 158 * 159 * slave only. This bit is set by LIN core if bit sleep is not set and no bus activity is detected for 4s 160 */ 161 #define LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_MASK (0x4000U) 162 #define LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_SHIFT (14U) 163 #define LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_MASK) >> LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_SHIFT) 164 165 /* 166 * ABORTED (RO) 167 * 168 * slave only. This bit is set by LIN core slave if a transmission is aborted after the bneginning of the data field due to a timeout or bit error. 169 */ 170 #define LINV2_CONTROL_STATUS_ABORTED_MASK (0x2000U) 171 #define LINV2_CONTROL_STATUS_ABORTED_SHIFT (13U) 172 #define LINV2_CONTROL_STATUS_ABORTED_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_ABORTED_MASK) >> LINV2_CONTROL_STATUS_ABORTED_SHIFT) 173 174 /* 175 * DATA_REQ (RO) 176 * 177 * slave only. Sets after receiving the identifier and requests an interrupt to the host controller. 178 */ 179 #define LINV2_CONTROL_STATUS_DATA_REQ_MASK (0x1000U) 180 #define LINV2_CONTROL_STATUS_DATA_REQ_SHIFT (12U) 181 #define LINV2_CONTROL_STATUS_DATA_REQ_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_DATA_REQ_MASK) >> LINV2_CONTROL_STATUS_DATA_REQ_SHIFT) 182 183 /* 184 * INT (RO) 185 * 186 * set when request an interrupt. Reset by reset_int 187 */ 188 #define LINV2_CONTROL_STATUS_INT_MASK (0x800U) 189 #define LINV2_CONTROL_STATUS_INT_SHIFT (11U) 190 #define LINV2_CONTROL_STATUS_INT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_INT_MASK) >> LINV2_CONTROL_STATUS_INT_SHIFT) 191 192 /* 193 * ERROR (RO) 194 * 195 * set when detecte an error, clear by reset_error 196 */ 197 #define LINV2_CONTROL_STATUS_ERROR_MASK (0x400U) 198 #define LINV2_CONTROL_STATUS_ERROR_SHIFT (10U) 199 #define LINV2_CONTROL_STATUS_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_ERROR_MASK) >> LINV2_CONTROL_STATUS_ERROR_SHIFT) 200 201 /* 202 * WAKEUP (RO) 203 * 204 * set when transmitting a wakeup signal or when received a wakeup signal. Clear when reset_error bit is 1 205 */ 206 #define LINV2_CONTROL_STATUS_WAKEUP_MASK (0x200U) 207 #define LINV2_CONTROL_STATUS_WAKEUP_SHIFT (9U) 208 #define LINV2_CONTROL_STATUS_WAKEUP_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_WAKEUP_MASK) >> LINV2_CONTROL_STATUS_WAKEUP_SHIFT) 209 210 /* 211 * COMPLETE (RO) 212 * 213 * set after a transmission has been successful finished and it will reset at the start of a transmission. 214 */ 215 #define LINV2_CONTROL_STATUS_COMPLETE_MASK (0x100U) 216 #define LINV2_CONTROL_STATUS_COMPLETE_SHIFT (8U) 217 #define LINV2_CONTROL_STATUS_COMPLETE_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_COMPLETE_MASK) >> LINV2_CONTROL_STATUS_COMPLETE_SHIFT) 218 219 /* 220 * STOP (WO) 221 * 222 * slave only. Write 1 when the Host determin do not response to the data request according to a unkown ID 223 */ 224 #define LINV2_CONTROL_STATUS_STOP_MASK (0x80U) 225 #define LINV2_CONTROL_STATUS_STOP_SHIFT (7U) 226 #define LINV2_CONTROL_STATUS_STOP_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_STOP_SHIFT) & LINV2_CONTROL_STATUS_STOP_MASK) 227 #define LINV2_CONTROL_STATUS_STOP_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_STOP_MASK) >> LINV2_CONTROL_STATUS_STOP_SHIFT) 228 229 /* 230 * SLEEP (RW) 231 * 232 * The bit is used by the LIN core to determine whether the LIN bus is in sleep mode or not. Set this bit after sending or receiving a Sleep Mode frame or if a bus idle timeout interrupt is requested or if after a wakeup request there is no response from the master and a timeout is signaled. The bit will be automatically reset by the LIN core. 233 */ 234 #define LINV2_CONTROL_STATUS_SLEEP_MASK (0x40U) 235 #define LINV2_CONTROL_STATUS_SLEEP_SHIFT (6U) 236 #define LINV2_CONTROL_STATUS_SLEEP_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_SLEEP_SHIFT) & LINV2_CONTROL_STATUS_SLEEP_MASK) 237 #define LINV2_CONTROL_STATUS_SLEEP_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_SLEEP_MASK) >> LINV2_CONTROL_STATUS_SLEEP_SHIFT) 238 239 /* 240 * TRANSMIT (RW) 241 * 242 * 1: transmit operation 0: receive operation 243 */ 244 #define LINV2_CONTROL_STATUS_TRANSMIT_MASK (0x20U) 245 #define LINV2_CONTROL_STATUS_TRANSMIT_SHIFT (5U) 246 #define LINV2_CONTROL_STATUS_TRANSMIT_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_TRANSMIT_SHIFT) & LINV2_CONTROL_STATUS_TRANSMIT_MASK) 247 #define LINV2_CONTROL_STATUS_TRANSMIT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_TRANSMIT_MASK) >> LINV2_CONTROL_STATUS_TRANSMIT_SHIFT) 248 249 /* 250 * DATA_ACK (RW) 251 * 252 * slave only. Write 1 after handling a data request interrupt 253 */ 254 #define LINV2_CONTROL_STATUS_DATA_ACK_MASK (0x10U) 255 #define LINV2_CONTROL_STATUS_DATA_ACK_SHIFT (4U) 256 #define LINV2_CONTROL_STATUS_DATA_ACK_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_DATA_ACK_SHIFT) & LINV2_CONTROL_STATUS_DATA_ACK_MASK) 257 #define LINV2_CONTROL_STATUS_DATA_ACK_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_DATA_ACK_MASK) >> LINV2_CONTROL_STATUS_DATA_ACK_SHIFT) 258 259 /* 260 * RESET_INT (WO) 261 * 262 * set 1 will clear the int register 263 */ 264 #define LINV2_CONTROL_STATUS_RESET_INT_MASK (0x8U) 265 #define LINV2_CONTROL_STATUS_RESET_INT_SHIFT (3U) 266 #define LINV2_CONTROL_STATUS_RESET_INT_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_RESET_INT_SHIFT) & LINV2_CONTROL_STATUS_RESET_INT_MASK) 267 #define LINV2_CONTROL_STATUS_RESET_INT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_RESET_INT_MASK) >> LINV2_CONTROL_STATUS_RESET_INT_SHIFT) 268 269 /* 270 * RESET_ERROR (WO) 271 * 272 * set 1 will clear the error register, and also the timeout/complete/wakeup register 273 */ 274 #define LINV2_CONTROL_STATUS_RESET_ERROR_MASK (0x4U) 275 #define LINV2_CONTROL_STATUS_RESET_ERROR_SHIFT (2U) 276 #define LINV2_CONTROL_STATUS_RESET_ERROR_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_RESET_ERROR_SHIFT) & LINV2_CONTROL_STATUS_RESET_ERROR_MASK) 277 #define LINV2_CONTROL_STATUS_RESET_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_RESET_ERROR_MASK) >> LINV2_CONTROL_STATUS_RESET_ERROR_SHIFT) 278 279 /* 280 * WAKEUP_REQ (RW) 281 * 282 * set 1 will make LIN bus exit sleep mode, the bit auto cleared after a wakeup signal has been complete 283 */ 284 #define LINV2_CONTROL_STATUS_WAKEUP_REQ_MASK (0x2U) 285 #define LINV2_CONTROL_STATUS_WAKEUP_REQ_SHIFT (1U) 286 #define LINV2_CONTROL_STATUS_WAKEUP_REQ_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_WAKEUP_REQ_SHIFT) & LINV2_CONTROL_STATUS_WAKEUP_REQ_MASK) 287 #define LINV2_CONTROL_STATUS_WAKEUP_REQ_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_WAKEUP_REQ_MASK) >> LINV2_CONTROL_STATUS_WAKEUP_REQ_SHIFT) 288 289 /* 290 * START_REQ (RW) 291 * 292 * master only. Set 1 will start lin transmission, the bit will be auto cleared when an error occur or the trasmission complete 293 */ 294 #define LINV2_CONTROL_STATUS_START_REQ_MASK (0x1U) 295 #define LINV2_CONTROL_STATUS_START_REQ_SHIFT (0U) 296 #define LINV2_CONTROL_STATUS_START_REQ_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_START_REQ_SHIFT) & LINV2_CONTROL_STATUS_START_REQ_MASK) 297 #define LINV2_CONTROL_STATUS_START_REQ_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_START_REQ_MASK) >> LINV2_CONTROL_STATUS_START_REQ_SHIFT) 298 299 /* Bitfield definition for register: TIMING_CONTROL */ 300 /* 301 * WAKE_LEN (RW) 302 * 303 */ 304 #define LINV2_TIMING_CONTROL_WAKE_LEN_MASK (0x38000000UL) 305 #define LINV2_TIMING_CONTROL_WAKE_LEN_SHIFT (27U) 306 #define LINV2_TIMING_CONTROL_WAKE_LEN_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_WAKE_LEN_SHIFT) & LINV2_TIMING_CONTROL_WAKE_LEN_MASK) 307 #define LINV2_TIMING_CONTROL_WAKE_LEN_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_WAKE_LEN_MASK) >> LINV2_TIMING_CONTROL_WAKE_LEN_SHIFT) 308 309 /* 310 * BRK_LEN (RW) 311 * 312 */ 313 #define LINV2_TIMING_CONTROL_BRK_LEN_MASK (0x7000000UL) 314 #define LINV2_TIMING_CONTROL_BRK_LEN_SHIFT (24U) 315 #define LINV2_TIMING_CONTROL_BRK_LEN_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_BRK_LEN_SHIFT) & LINV2_TIMING_CONTROL_BRK_LEN_MASK) 316 #define LINV2_TIMING_CONTROL_BRK_LEN_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_BRK_LEN_MASK) >> LINV2_TIMING_CONTROL_BRK_LEN_SHIFT) 317 318 /* 319 * LINBUSDISABLE (RW) 320 * 321 * 1：lin rx is disable 322 */ 323 #define LINV2_TIMING_CONTROL_LINBUSDISABLE_MASK (0x400000UL) 324 #define LINV2_TIMING_CONTROL_LINBUSDISABLE_SHIFT (22U) 325 #define LINV2_TIMING_CONTROL_LINBUSDISABLE_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_LINBUSDISABLE_SHIFT) & LINV2_TIMING_CONTROL_LINBUSDISABLE_MASK) 326 #define LINV2_TIMING_CONTROL_LINBUSDISABLE_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_LINBUSDISABLE_MASK) >> LINV2_TIMING_CONTROL_LINBUSDISABLE_SHIFT) 327 328 /* 329 * LIN_INITIAL (RW) 330 * 331 * 1:initial lin controller 332 */ 333 #define LINV2_TIMING_CONTROL_LIN_INITIAL_MASK (0x200000UL) 334 #define LINV2_TIMING_CONTROL_LIN_INITIAL_SHIFT (21U) 335 #define LINV2_TIMING_CONTROL_LIN_INITIAL_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_LIN_INITIAL_SHIFT) & LINV2_TIMING_CONTROL_LIN_INITIAL_MASK) 336 #define LINV2_TIMING_CONTROL_LIN_INITIAL_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_LIN_INITIAL_MASK) >> LINV2_TIMING_CONTROL_LIN_INITIAL_SHIFT) 337 338 /* 339 * MASTER_MODE (RW) 340 * 341 * 1：master mode 342 */ 343 #define LINV2_TIMING_CONTROL_MASTER_MODE_MASK (0x100000UL) 344 #define LINV2_TIMING_CONTROL_MASTER_MODE_SHIFT (20U) 345 #define LINV2_TIMING_CONTROL_MASTER_MODE_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_MASTER_MODE_SHIFT) & LINV2_TIMING_CONTROL_MASTER_MODE_MASK) 346 #define LINV2_TIMING_CONTROL_MASTER_MODE_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_MASTER_MODE_MASK) >> LINV2_TIMING_CONTROL_MASTER_MODE_SHIFT) 347 348 /* 349 * BUS_INACTIVE_TIME (RW) 350 * 351 * slave only. LIN bus idle timeout register： 00-4s 01-6s 10-8s 11-10s 352 */ 353 #define LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_MASK (0xC0000UL) 354 #define LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SHIFT (18U) 355 #define LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SHIFT) & LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_MASK) 356 #define LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_MASK) >> LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SHIFT) 357 358 /* 359 * WUP_REPEAT_TIME (RW) 360 * 361 * slave only. wakeup repeat interval time 00-180ms 01-200ms 10-220ms 11-240ms 362 */ 363 #define LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_MASK (0x30000UL) 364 #define LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SHIFT (16U) 365 #define LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SHIFT) & LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_MASK) 366 #define LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_MASK) >> LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SHIFT) 367 368 /* 369 * PRESCL (RW) 370 * 371 * prescl register 372 */ 373 #define LINV2_TIMING_CONTROL_PRESCL_MASK (0xC000U) 374 #define LINV2_TIMING_CONTROL_PRESCL_SHIFT (14U) 375 #define LINV2_TIMING_CONTROL_PRESCL_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_PRESCL_SHIFT) & LINV2_TIMING_CONTROL_PRESCL_MASK) 376 #define LINV2_TIMING_CONTROL_PRESCL_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_PRESCL_MASK) >> LINV2_TIMING_CONTROL_PRESCL_SHIFT) 377 378 /* 379 * BT_MUL (RW) 380 * 381 * bt_mul register 382 */ 383 #define LINV2_TIMING_CONTROL_BT_MUL_MASK (0x3E00U) 384 #define LINV2_TIMING_CONTROL_BT_MUL_SHIFT (9U) 385 #define LINV2_TIMING_CONTROL_BT_MUL_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_BT_MUL_SHIFT) & LINV2_TIMING_CONTROL_BT_MUL_MASK) 386 #define LINV2_TIMING_CONTROL_BT_MUL_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_BT_MUL_MASK) >> LINV2_TIMING_CONTROL_BT_MUL_SHIFT) 387 388 /* 389 * BT_DIV (RW) 390 * 391 * bt_div register 392 */ 393 #define LINV2_TIMING_CONTROL_BT_DIV_MASK (0x1FFU) 394 #define LINV2_TIMING_CONTROL_BT_DIV_SHIFT (0U) 395 #define LINV2_TIMING_CONTROL_BT_DIV_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_BT_DIV_SHIFT) & LINV2_TIMING_CONTROL_BT_DIV_MASK) 396 #define LINV2_TIMING_CONTROL_BT_DIV_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_BT_DIV_MASK) >> LINV2_TIMING_CONTROL_BT_DIV_SHIFT) 397 398 /* Bitfield definition for register: DMA_CONTROL */ 399 /* 400 * DMA_REQ_ENH_CHK (RW) 401 * 402 * payload data checksum type for dma operation 403 */ 404 #define LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_MASK (0x1000U) 405 #define LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SHIFT (12U) 406 #define LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_MASK) 407 #define LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SHIFT) 408 409 /* 410 * DMA_REQ_LEN (RW) 411 * 412 * paylaod length for dma request 413 */ 414 #define LINV2_DMA_CONTROL_DMA_REQ_LEN_MASK (0xF00U) 415 #define LINV2_DMA_CONTROL_DMA_REQ_LEN_SHIFT (8U) 416 #define LINV2_DMA_CONTROL_DMA_REQ_LEN_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_LEN_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_LEN_MASK) 417 #define LINV2_DMA_CONTROL_DMA_REQ_LEN_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_LEN_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_LEN_SHIFT) 418 419 /* 420 * DMA_REQ_ID_TYPE (RW) 421 * 422 * 1：transmite 0：receive 423 */ 424 #define LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_MASK (0x80U) 425 #define LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SHIFT (7U) 426 #define LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_MASK) 427 #define LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SHIFT) 428 429 /* 430 * DMA_REQ_ID (RW) 431 * 432 * dma_req_id register 433 */ 434 #define LINV2_DMA_CONTROL_DMA_REQ_ID_MASK (0x7EU) 435 #define LINV2_DMA_CONTROL_DMA_REQ_ID_SHIFT (1U) 436 #define LINV2_DMA_CONTROL_DMA_REQ_ID_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_ID_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_ID_MASK) 437 #define LINV2_DMA_CONTROL_DMA_REQ_ID_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_ID_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_ID_SHIFT) 438 439 /* 440 * DMA_REQ_ENABLE (RW) 441 * 442 * slave mode only. 1: enable dma request for data request ID equal dma_req_id 443 */ 444 #define LINV2_DMA_CONTROL_DMA_REQ_ENABLE_MASK (0x1U) 445 #define LINV2_DMA_CONTROL_DMA_REQ_ENABLE_SHIFT (0U) 446 #define LINV2_DMA_CONTROL_DMA_REQ_ENABLE_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_ENABLE_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_ENABLE_MASK) 447 #define LINV2_DMA_CONTROL_DMA_REQ_ENABLE_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_ENABLE_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_ENABLE_SHIFT) 448 449 450 451 /* DATA register group index macro definition */ 452 #define LINV2_DATA_DATA0 (0UL) 453 #define LINV2_DATA_DATA1 (1UL) 454 455 /* DATA_BYTE register group index macro definition */ 456 #define LINV2_DATA_BYTE_DATA_BYTE0 (0UL) 457 #define LINV2_DATA_BYTE_DATA_BYTE1 (1UL) 458 #define LINV2_DATA_BYTE_DATA_BYTE2 (2UL) 459 #define LINV2_DATA_BYTE_DATA_BYTE3 (3UL) 460 #define LINV2_DATA_BYTE_DATA_BYTE4 (4UL) 461 #define LINV2_DATA_BYTE_DATA_BYTE5 (5UL) 462 #define LINV2_DATA_BYTE_DATA_BYTE6 (6UL) 463 #define LINV2_DATA_BYTE_DATA_BYTE7 (7UL) 464 465 466 #endif /* HPM_LINV2_H */ 467