1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_LIN_H 10 #define HPM_LIN_H 11 12 typedef struct { 13 __RW uint32_t DATABYTE[8]; /* 0x0 - 0x1C: data byte */ 14 __RW uint32_t CONTROL; /* 0x20: control register */ 15 __R uint32_t STATE; /* 0x24: state register */ 16 __R uint32_t ERROR; /* 0x28: error register */ 17 __RW uint32_t DATA_LEN; /* 0x2C: data lenth register */ 18 __RW uint32_t BAUDRATE_CTL_LOW; /* 0x30: baudrate control low register */ 19 __RW uint32_t BARDRATE_CTL_HIGH; /* 0x34: baudrate control high register */ 20 __RW uint32_t ID; /* 0x38: id register */ 21 __RW uint32_t TV; /* 0x3C: timeout control register */ 22 } LIN_Type; 23 24 25 /* Bitfield definition for register array: DATABYTE */ 26 /* 27 * DATA_BYTE (RW) 28 * 29 * data byte 30 */ 31 #define LIN_DATABYTE_DATA_BYTE_MASK (0xFFU) 32 #define LIN_DATABYTE_DATA_BYTE_SHIFT (0U) 33 #define LIN_DATABYTE_DATA_BYTE_SET(x) (((uint32_t)(x) << LIN_DATABYTE_DATA_BYTE_SHIFT) & LIN_DATABYTE_DATA_BYTE_MASK) 34 #define LIN_DATABYTE_DATA_BYTE_GET(x) (((uint32_t)(x) & LIN_DATABYTE_DATA_BYTE_MASK) >> LIN_DATABYTE_DATA_BYTE_SHIFT) 35 36 /* Bitfield definition for register: CONTROL */ 37 /* 38 * STOP (WO) 39 * 40 * slave only. Write 1 when the Host determin do not response to the data request according to a unkown ID 41 */ 42 #define LIN_CONTROL_STOP_MASK (0x80U) 43 #define LIN_CONTROL_STOP_SHIFT (7U) 44 #define LIN_CONTROL_STOP_SET(x) (((uint32_t)(x) << LIN_CONTROL_STOP_SHIFT) & LIN_CONTROL_STOP_MASK) 45 #define LIN_CONTROL_STOP_GET(x) (((uint32_t)(x) & LIN_CONTROL_STOP_MASK) >> LIN_CONTROL_STOP_SHIFT) 46 47 /* 48 * SLEEP (RW) 49 * 50 * The bit is used by the LIN core to determine whether the LIN bus is in sleep mode or not. Set this bit after sending or receiving a Sleep Mode frame or if a bus idle timeout interrupt is requested or if after a wakeup request there is no response from the master and a timeout is signaled. The bit will be automatically reset by the LIN core. 51 */ 52 #define LIN_CONTROL_SLEEP_MASK (0x40U) 53 #define LIN_CONTROL_SLEEP_SHIFT (6U) 54 #define LIN_CONTROL_SLEEP_SET(x) (((uint32_t)(x) << LIN_CONTROL_SLEEP_SHIFT) & LIN_CONTROL_SLEEP_MASK) 55 #define LIN_CONTROL_SLEEP_GET(x) (((uint32_t)(x) & LIN_CONTROL_SLEEP_MASK) >> LIN_CONTROL_SLEEP_SHIFT) 56 57 /* 58 * TRANSMIT (RW) 59 * 60 * 1: transmit operation 0: receive operation 61 */ 62 #define LIN_CONTROL_TRANSMIT_MASK (0x20U) 63 #define LIN_CONTROL_TRANSMIT_SHIFT (5U) 64 #define LIN_CONTROL_TRANSMIT_SET(x) (((uint32_t)(x) << LIN_CONTROL_TRANSMIT_SHIFT) & LIN_CONTROL_TRANSMIT_MASK) 65 #define LIN_CONTROL_TRANSMIT_GET(x) (((uint32_t)(x) & LIN_CONTROL_TRANSMIT_MASK) >> LIN_CONTROL_TRANSMIT_SHIFT) 66 67 /* 68 * DATA_ACK (RW) 69 * 70 * slave only. Write 1 after handling a data request interrupt 71 */ 72 #define LIN_CONTROL_DATA_ACK_MASK (0x10U) 73 #define LIN_CONTROL_DATA_ACK_SHIFT (4U) 74 #define LIN_CONTROL_DATA_ACK_SET(x) (((uint32_t)(x) << LIN_CONTROL_DATA_ACK_SHIFT) & LIN_CONTROL_DATA_ACK_MASK) 75 #define LIN_CONTROL_DATA_ACK_GET(x) (((uint32_t)(x) & LIN_CONTROL_DATA_ACK_MASK) >> LIN_CONTROL_DATA_ACK_SHIFT) 76 77 /* 78 * RESET_INT (WO) 79 * 80 * write 1 to reset the int bit in the status register and the interrupt request output of LIN 81 */ 82 #define LIN_CONTROL_RESET_INT_MASK (0x8U) 83 #define LIN_CONTROL_RESET_INT_SHIFT (3U) 84 #define LIN_CONTROL_RESET_INT_SET(x) (((uint32_t)(x) << LIN_CONTROL_RESET_INT_SHIFT) & LIN_CONTROL_RESET_INT_MASK) 85 #define LIN_CONTROL_RESET_INT_GET(x) (((uint32_t)(x) & LIN_CONTROL_RESET_INT_MASK) >> LIN_CONTROL_RESET_INT_SHIFT) 86 87 /* 88 * RESET_ERROR (WO) 89 * 90 * assert 1 to reset the error bits in status register and error register. A read access to this bit delivers always the value 0 91 */ 92 #define LIN_CONTROL_RESET_ERROR_MASK (0x4U) 93 #define LIN_CONTROL_RESET_ERROR_SHIFT (2U) 94 #define LIN_CONTROL_RESET_ERROR_SET(x) (((uint32_t)(x) << LIN_CONTROL_RESET_ERROR_SHIFT) & LIN_CONTROL_RESET_ERROR_MASK) 95 #define LIN_CONTROL_RESET_ERROR_GET(x) (((uint32_t)(x) & LIN_CONTROL_RESET_ERROR_MASK) >> LIN_CONTROL_RESET_ERROR_SHIFT) 96 97 /* 98 * WAKEUP_REQ (RW) 99 * 100 * wakeup request. Assert to terminate the Sleep mode of the LIN bus. The bit will be reset by core 101 */ 102 #define LIN_CONTROL_WAKEUP_REQ_MASK (0x2U) 103 #define LIN_CONTROL_WAKEUP_REQ_SHIFT (1U) 104 #define LIN_CONTROL_WAKEUP_REQ_SET(x) (((uint32_t)(x) << LIN_CONTROL_WAKEUP_REQ_SHIFT) & LIN_CONTROL_WAKEUP_REQ_MASK) 105 #define LIN_CONTROL_WAKEUP_REQ_GET(x) (((uint32_t)(x) & LIN_CONTROL_WAKEUP_REQ_MASK) >> LIN_CONTROL_WAKEUP_REQ_SHIFT) 106 107 /* 108 * START_REQ (RW) 109 * 110 * master only. Set by host controller of a LIN master to start the LIN transmission. The core will reset the bit after the transmission is finished or an error is occurred 111 */ 112 #define LIN_CONTROL_START_REQ_MASK (0x1U) 113 #define LIN_CONTROL_START_REQ_SHIFT (0U) 114 #define LIN_CONTROL_START_REQ_SET(x) (((uint32_t)(x) << LIN_CONTROL_START_REQ_SHIFT) & LIN_CONTROL_START_REQ_MASK) 115 #define LIN_CONTROL_START_REQ_GET(x) (((uint32_t)(x) & LIN_CONTROL_START_REQ_MASK) >> LIN_CONTROL_START_REQ_SHIFT) 116 117 /* Bitfield definition for register: STATE */ 118 /* 119 * LIN_ACTIVE (RO) 120 * 121 * The bit indicates whether the LIN bus is active or not 122 */ 123 #define LIN_STATE_LIN_ACTIVE_MASK (0x80U) 124 #define LIN_STATE_LIN_ACTIVE_SHIFT (7U) 125 #define LIN_STATE_LIN_ACTIVE_GET(x) (((uint32_t)(x) & LIN_STATE_LIN_ACTIVE_MASK) >> LIN_STATE_LIN_ACTIVE_SHIFT) 126 127 /* 128 * BUS_IDLE_TV (RO) 129 * 130 * slave only. This bit is set by LIN core if bit sleep is not set and no bus activity is detected for 4s 131 */ 132 #define LIN_STATE_BUS_IDLE_TV_MASK (0x40U) 133 #define LIN_STATE_BUS_IDLE_TV_SHIFT (6U) 134 #define LIN_STATE_BUS_IDLE_TV_GET(x) (((uint32_t)(x) & LIN_STATE_BUS_IDLE_TV_MASK) >> LIN_STATE_BUS_IDLE_TV_SHIFT) 135 136 /* 137 * ABORTED (RO) 138 * 139 * slave only. This bit is set by LIN core slave if a transmission is aborted after the bneginning of the data field due to a timeout or bit error. 140 */ 141 #define LIN_STATE_ABORTED_MASK (0x20U) 142 #define LIN_STATE_ABORTED_SHIFT (5U) 143 #define LIN_STATE_ABORTED_GET(x) (((uint32_t)(x) & LIN_STATE_ABORTED_MASK) >> LIN_STATE_ABORTED_SHIFT) 144 145 /* 146 * DATA_REQ (RO) 147 * 148 * slave only. Sets after receiving the identifier and requests an interrupt to the host controller. 149 */ 150 #define LIN_STATE_DATA_REQ_MASK (0x10U) 151 #define LIN_STATE_DATA_REQ_SHIFT (4U) 152 #define LIN_STATE_DATA_REQ_GET(x) (((uint32_t)(x) & LIN_STATE_DATA_REQ_MASK) >> LIN_STATE_DATA_REQ_SHIFT) 153 154 /* 155 * INT (RO) 156 * 157 * set when request an interrupt. Reset by reset_int 158 */ 159 #define LIN_STATE_INT_MASK (0x8U) 160 #define LIN_STATE_INT_SHIFT (3U) 161 #define LIN_STATE_INT_GET(x) (((uint32_t)(x) & LIN_STATE_INT_MASK) >> LIN_STATE_INT_SHIFT) 162 163 /* 164 * ERROR (RO) 165 * 166 * set when detecte an error, clear by reset_error 167 */ 168 #define LIN_STATE_ERROR_MASK (0x4U) 169 #define LIN_STATE_ERROR_SHIFT (2U) 170 #define LIN_STATE_ERROR_GET(x) (((uint32_t)(x) & LIN_STATE_ERROR_MASK) >> LIN_STATE_ERROR_SHIFT) 171 172 /* 173 * WAKEUP (RO) 174 * 175 * set when transmitting a wakeup signal or when received a wakeup signal. Clear when reset_error bit is 1 176 */ 177 #define LIN_STATE_WAKEUP_MASK (0x2U) 178 #define LIN_STATE_WAKEUP_SHIFT (1U) 179 #define LIN_STATE_WAKEUP_GET(x) (((uint32_t)(x) & LIN_STATE_WAKEUP_MASK) >> LIN_STATE_WAKEUP_SHIFT) 180 181 /* 182 * COMPLETE (RO) 183 * 184 * set after a transmission has been successful finished and it will reset at the start of a transmission. 185 */ 186 #define LIN_STATE_COMPLETE_MASK (0x1U) 187 #define LIN_STATE_COMPLETE_SHIFT (0U) 188 #define LIN_STATE_COMPLETE_GET(x) (((uint32_t)(x) & LIN_STATE_COMPLETE_MASK) >> LIN_STATE_COMPLETE_SHIFT) 189 190 /* Bitfield definition for register: ERROR */ 191 /* 192 * PARITY_ERROR (RO) 193 * 194 * slave only. identifier parity error 195 */ 196 #define LIN_ERROR_PARITY_ERROR_MASK (0x8U) 197 #define LIN_ERROR_PARITY_ERROR_SHIFT (3U) 198 #define LIN_ERROR_PARITY_ERROR_GET(x) (((uint32_t)(x) & LIN_ERROR_PARITY_ERROR_MASK) >> LIN_ERROR_PARITY_ERROR_SHIFT) 199 200 /* 201 * TIMEOUT (RO) 202 * 203 * timeout error. The master detects a timeout error if it is expecting data from the bus but no slave does respond. The slave detects a timeout error if it is requesting a data acknowledge to the host controller. The slave detects a timeout if it has transmitted a wakeup signal and it detects no sync field within 150ms 204 */ 205 #define LIN_ERROR_TIMEOUT_MASK (0x4U) 206 #define LIN_ERROR_TIMEOUT_SHIFT (2U) 207 #define LIN_ERROR_TIMEOUT_GET(x) (((uint32_t)(x) & LIN_ERROR_TIMEOUT_MASK) >> LIN_ERROR_TIMEOUT_SHIFT) 208 209 /* 210 * CHK_ERROR (RO) 211 * 212 * checksum error 213 */ 214 #define LIN_ERROR_CHK_ERROR_MASK (0x2U) 215 #define LIN_ERROR_CHK_ERROR_SHIFT (1U) 216 #define LIN_ERROR_CHK_ERROR_GET(x) (((uint32_t)(x) & LIN_ERROR_CHK_ERROR_MASK) >> LIN_ERROR_CHK_ERROR_SHIFT) 217 218 /* 219 * BIT_ERROR (RO) 220 * 221 * bit error 222 */ 223 #define LIN_ERROR_BIT_ERROR_MASK (0x1U) 224 #define LIN_ERROR_BIT_ERROR_SHIFT (0U) 225 #define LIN_ERROR_BIT_ERROR_GET(x) (((uint32_t)(x) & LIN_ERROR_BIT_ERROR_MASK) >> LIN_ERROR_BIT_ERROR_SHIFT) 226 227 /* Bitfield definition for register: DATA_LEN */ 228 /* 229 * ENH_CHECK (RW) 230 * 231 * 1:enhence check mode 232 */ 233 #define LIN_DATA_LEN_ENH_CHECK_MASK (0x80U) 234 #define LIN_DATA_LEN_ENH_CHECK_SHIFT (7U) 235 #define LIN_DATA_LEN_ENH_CHECK_SET(x) (((uint32_t)(x) << LIN_DATA_LEN_ENH_CHECK_SHIFT) & LIN_DATA_LEN_ENH_CHECK_MASK) 236 #define LIN_DATA_LEN_ENH_CHECK_GET(x) (((uint32_t)(x) & LIN_DATA_LEN_ENH_CHECK_MASK) >> LIN_DATA_LEN_ENH_CHECK_SHIFT) 237 238 /* 239 * DATA_LENGTH (RW) 240 * 241 * data length 242 */ 243 #define LIN_DATA_LEN_DATA_LENGTH_MASK (0xFU) 244 #define LIN_DATA_LEN_DATA_LENGTH_SHIFT (0U) 245 #define LIN_DATA_LEN_DATA_LENGTH_SET(x) (((uint32_t)(x) << LIN_DATA_LEN_DATA_LENGTH_SHIFT) & LIN_DATA_LEN_DATA_LENGTH_MASK) 246 #define LIN_DATA_LEN_DATA_LENGTH_GET(x) (((uint32_t)(x) & LIN_DATA_LEN_DATA_LENGTH_MASK) >> LIN_DATA_LEN_DATA_LENGTH_SHIFT) 247 248 /* Bitfield definition for register: BAUDRATE_CTL_LOW */ 249 /* 250 * BT_DIV_LOW (RW) 251 * 252 * bit div register 7:0 253 */ 254 #define LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_MASK (0xFFU) 255 #define LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_SHIFT (0U) 256 #define LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_SET(x) (((uint32_t)(x) << LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_SHIFT) & LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_MASK) 257 #define LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_GET(x) (((uint32_t)(x) & LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_MASK) >> LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_SHIFT) 258 259 /* Bitfield definition for register: BARDRATE_CTL_HIGH */ 260 /* 261 * PRESCL (RW) 262 * 263 * prescl register 264 */ 265 #define LIN_BARDRATE_CTL_HIGH_PRESCL_MASK (0xC0U) 266 #define LIN_BARDRATE_CTL_HIGH_PRESCL_SHIFT (6U) 267 #define LIN_BARDRATE_CTL_HIGH_PRESCL_SET(x) (((uint32_t)(x) << LIN_BARDRATE_CTL_HIGH_PRESCL_SHIFT) & LIN_BARDRATE_CTL_HIGH_PRESCL_MASK) 268 #define LIN_BARDRATE_CTL_HIGH_PRESCL_GET(x) (((uint32_t)(x) & LIN_BARDRATE_CTL_HIGH_PRESCL_MASK) >> LIN_BARDRATE_CTL_HIGH_PRESCL_SHIFT) 269 270 /* 271 * BT_MUL (RW) 272 * 273 * bt_mul register 274 */ 275 #define LIN_BARDRATE_CTL_HIGH_BT_MUL_MASK (0x3EU) 276 #define LIN_BARDRATE_CTL_HIGH_BT_MUL_SHIFT (1U) 277 #define LIN_BARDRATE_CTL_HIGH_BT_MUL_SET(x) (((uint32_t)(x) << LIN_BARDRATE_CTL_HIGH_BT_MUL_SHIFT) & LIN_BARDRATE_CTL_HIGH_BT_MUL_MASK) 278 #define LIN_BARDRATE_CTL_HIGH_BT_MUL_GET(x) (((uint32_t)(x) & LIN_BARDRATE_CTL_HIGH_BT_MUL_MASK) >> LIN_BARDRATE_CTL_HIGH_BT_MUL_SHIFT) 279 280 /* 281 * BT_DIV_HIGH (RW) 282 * 283 * bit div register 8 284 */ 285 #define LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_MASK (0x1U) 286 #define LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SHIFT (0U) 287 #define LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SET(x) (((uint32_t)(x) << LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SHIFT) & LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_MASK) 288 #define LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_GET(x) (((uint32_t)(x) & LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_MASK) >> LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SHIFT) 289 290 /* Bitfield definition for register: ID */ 291 /* 292 * ID (RW) 293 * 294 * id register 295 */ 296 #define LIN_ID_ID_MASK (0x3FU) 297 #define LIN_ID_ID_SHIFT (0U) 298 #define LIN_ID_ID_SET(x) (((uint32_t)(x) << LIN_ID_ID_SHIFT) & LIN_ID_ID_MASK) 299 #define LIN_ID_ID_GET(x) (((uint32_t)(x) & LIN_ID_ID_MASK) >> LIN_ID_ID_SHIFT) 300 301 /* Bitfield definition for register: TV */ 302 /* 303 * INITIAL_MODE (RW) 304 * 305 * initial_mode 306 */ 307 #define LIN_TV_INITIAL_MODE_MASK (0x80U) 308 #define LIN_TV_INITIAL_MODE_SHIFT (7U) 309 #define LIN_TV_INITIAL_MODE_SET(x) (((uint32_t)(x) << LIN_TV_INITIAL_MODE_SHIFT) & LIN_TV_INITIAL_MODE_MASK) 310 #define LIN_TV_INITIAL_MODE_GET(x) (((uint32_t)(x) & LIN_TV_INITIAL_MODE_MASK) >> LIN_TV_INITIAL_MODE_SHIFT) 311 312 /* 313 * MASTER_MODE (RW) 314 * 315 * master_mode 316 */ 317 #define LIN_TV_MASTER_MODE_MASK (0x40U) 318 #define LIN_TV_MASTER_MODE_SHIFT (6U) 319 #define LIN_TV_MASTER_MODE_SET(x) (((uint32_t)(x) << LIN_TV_MASTER_MODE_SHIFT) & LIN_TV_MASTER_MODE_MASK) 320 #define LIN_TV_MASTER_MODE_GET(x) (((uint32_t)(x) & LIN_TV_MASTER_MODE_MASK) >> LIN_TV_MASTER_MODE_SHIFT) 321 322 /* 323 * BUS_INACTIVITY_TIME (RW) 324 * 325 * slave only. LIN bus idle timeout register： 00-4s 01-6s 10-8s 11-10s 326 */ 327 #define LIN_TV_BUS_INACTIVITY_TIME_MASK (0xCU) 328 #define LIN_TV_BUS_INACTIVITY_TIME_SHIFT (2U) 329 #define LIN_TV_BUS_INACTIVITY_TIME_SET(x) (((uint32_t)(x) << LIN_TV_BUS_INACTIVITY_TIME_SHIFT) & LIN_TV_BUS_INACTIVITY_TIME_MASK) 330 #define LIN_TV_BUS_INACTIVITY_TIME_GET(x) (((uint32_t)(x) & LIN_TV_BUS_INACTIVITY_TIME_MASK) >> LIN_TV_BUS_INACTIVITY_TIME_SHIFT) 331 332 /* 333 * WUP_REPEAT_TIME (RW) 334 * 335 * slave only. wakeup repeat interval time 00-180ms 01-200ms 10-220ms 11-240ms 336 */ 337 #define LIN_TV_WUP_REPEAT_TIME_MASK (0x3U) 338 #define LIN_TV_WUP_REPEAT_TIME_SHIFT (0U) 339 #define LIN_TV_WUP_REPEAT_TIME_SET(x) (((uint32_t)(x) << LIN_TV_WUP_REPEAT_TIME_SHIFT) & LIN_TV_WUP_REPEAT_TIME_MASK) 340 #define LIN_TV_WUP_REPEAT_TIME_GET(x) (((uint32_t)(x) & LIN_TV_WUP_REPEAT_TIME_MASK) >> LIN_TV_WUP_REPEAT_TIME_SHIFT) 341 342 343 344 /* DATABYTE register group index macro definition */ 345 #define LIN_DATABYTE_DATA_BYTE0 (0UL) 346 #define LIN_DATABYTE_DATA_BYTE1 (1UL) 347 #define LIN_DATABYTE_DATA_BYTE2 (2UL) 348 #define LIN_DATABYTE_DATA_BYTE3 (3UL) 349 #define LIN_DATABYTE_DATA_BYTE4 (4UL) 350 #define LIN_DATABYTE_DATA_BYTE5 (5UL) 351 #define LIN_DATABYTE_DATA_BYTE6 (6UL) 352 #define LIN_DATABYTE_DATA_BYTE7 (7UL) 353 354 355 #endif /* HPM_LIN_H */ 356