1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f4xx_ll_adc.h"
23 #include "stm32f4xx_ll_bus.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif
30
31 /** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
36
37 /** @addtogroup ADC_LL ADC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45
46 /** @addtogroup ADC_LL_Private_Macros
47 * @{
48 */
49
50 /* Check of parameters for configuration of ADC hierarchical scope: */
51 /* common to several ADC instances. */
52 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
53 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
54 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
55 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \
56 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \
57 )
58
59 /* Check of parameters for configuration of ADC hierarchical scope: */
60 /* ADC instance. */
61 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
62 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
63 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
64 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
65 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
66 )
67
68 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
69 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
70 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
71 )
72
73 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
74 ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
75 || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
76 )
77
78 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
79 ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
80 || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
81 )
82
83 /* Check of parameters for configuration of ADC hierarchical scope: */
84 /* ADC group regular */
85 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
86 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
87 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
88 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
89 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
90 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
91 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
92 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
93 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
94 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
95 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
96 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
97 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \
98 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2) \
99 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \
100 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
101 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
102 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
103 )
104 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
105 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
106 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
107 )
108
109 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
110 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
111 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
112 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
113 )
114
115 #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \
116 ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \
117 || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \
118 )
119
120 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
121 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
122 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
123 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
124 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
125 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
126 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
127 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
128 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
129 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
130 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
131 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
132 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
133 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
134 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
135 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
136 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
137 )
138
139 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
140 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
141 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
142 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
143 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
144 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
145 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
146 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
147 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
148 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
149 )
150
151 /* Check of parameters for configuration of ADC hierarchical scope: */
152 /* ADC group injected */
153 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
154 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
155 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
156 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
157 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
158 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
159 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2) \
160 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
161 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \
162 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \
163 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
164 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
165 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \
166 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
167 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
168 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3) \
169 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
170 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
171 )
172
173 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
174 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
175 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
176 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
177 )
178
179 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
180 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
181 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
182 )
183
184 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
185 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
186 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
187 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
188 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
189 )
190
191 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
192 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
193 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
194 )
195
196 #if defined(ADC_MULTIMODE_SUPPORT)
197 /* Check of parameters for configuration of ADC hierarchical scope: */
198 /* multimode. */
199 #if defined(ADC3)
200 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
201 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
202 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
203 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
204 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
205 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
206 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
207 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
208 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
209 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \
210 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \
211 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \
212 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \
213 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \
214 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \
215 )
216 #else
217 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
218 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
219 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
220 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
221 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
222 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
223 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
224 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
225 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
226 )
227 #endif
228
229 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
230 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
231 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \
232 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \
233 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \
234 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \
235 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \
236 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \
237 )
238
239 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
240 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
241 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
242 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
243 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
244 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
245 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
246 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
247 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
248 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \
249 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \
250 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \
251 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \
252 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \
253 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \
254 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \
255 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \
256 )
257
258 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
259 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
260 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
261 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
262 )
263
264 #endif /* ADC_MULTIMODE_SUPPORT */
265 /**
266 * @}
267 */
268
269
270 /* Private function prototypes -----------------------------------------------*/
271
272 /* Exported functions --------------------------------------------------------*/
273 /** @addtogroup ADC_LL_Exported_Functions
274 * @{
275 */
276
277 /** @addtogroup ADC_LL_EF_Init
278 * @{
279 */
280
281 /**
282 * @brief De-initialize registers of all ADC instances belonging to
283 * the same ADC common instance to their default reset values.
284 * @param ADCxy_COMMON ADC common instance
285 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
286 * @retval An ErrorStatus enumeration value:
287 * - SUCCESS: ADC common registers are de-initialized
288 * - ERROR: not applicable
289 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)290 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
291 {
292 /* Check the parameters */
293 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
294
295
296 /* Force reset of ADC clock (core clock) */
297 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
298
299 /* Release reset of ADC clock (core clock) */
300 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
301
302 return SUCCESS;
303 }
304
305 /**
306 * @brief Initialize some features of ADC common parameters
307 * (all ADC instances belonging to the same ADC common instance)
308 * and multimode (for devices with several ADC instances available).
309 * @note The setting of ADC common parameters is conditioned to
310 * ADC instances state:
311 * All ADC instances belonging to the same ADC common instance
312 * must be disabled.
313 * @param ADCxy_COMMON ADC common instance
314 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
315 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
316 * @retval An ErrorStatus enumeration value:
317 * - SUCCESS: ADC common registers are initialized
318 * - ERROR: ADC common registers are not initialized
319 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)320 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
321 {
322 ErrorStatus status = SUCCESS;
323
324 /* Check the parameters */
325 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
326 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
327
328 #if defined(ADC_MULTIMODE_SUPPORT)
329 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
330 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
331 {
332 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
333 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
334 }
335 #endif /* ADC_MULTIMODE_SUPPORT */
336
337 /* Note: Hardware constraint (refer to description of functions */
338 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
339 /* On this STM32 series, setting of these features is conditioned to */
340 /* ADC state: */
341 /* All ADC instances of the ADC common group must be disabled. */
342 if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
343 {
344 /* Configuration of ADC hierarchical scope: */
345 /* - common to several ADC */
346 /* (all ADC instances belonging to the same ADC common instance) */
347 /* - Set ADC clock (conversion clock) */
348 /* - multimode (if several ADC instances available on the */
349 /* selected device) */
350 /* - Set ADC multimode configuration */
351 /* - Set ADC multimode DMA transfer */
352 /* - Set ADC multimode: delay between 2 sampling phases */
353 #if defined(ADC_MULTIMODE_SUPPORT)
354 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
355 {
356 MODIFY_REG(ADCxy_COMMON->CCR,
357 ADC_CCR_ADCPRE
358 | ADC_CCR_MULTI
359 | ADC_CCR_DMA
360 | ADC_CCR_DDS
361 | ADC_CCR_DELAY
362 ,
363 ADC_CommonInitStruct->CommonClock
364 | ADC_CommonInitStruct->Multimode
365 | ADC_CommonInitStruct->MultiDMATransfer
366 | ADC_CommonInitStruct->MultiTwoSamplingDelay
367 );
368 }
369 else
370 {
371 MODIFY_REG(ADCxy_COMMON->CCR,
372 ADC_CCR_ADCPRE
373 | ADC_CCR_MULTI
374 | ADC_CCR_DMA
375 | ADC_CCR_DDS
376 | ADC_CCR_DELAY
377 ,
378 ADC_CommonInitStruct->CommonClock
379 | LL_ADC_MULTI_INDEPENDENT
380 );
381 }
382 #else
383 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
384 #endif
385 }
386 else
387 {
388 /* Initialization error: One or several ADC instances belonging to */
389 /* the same ADC common instance are not disabled. */
390 status = ERROR;
391 }
392
393 return status;
394 }
395
396 /**
397 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
398 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
399 * whose fields will be set to default values.
400 * @retval None
401 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)402 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
403 {
404 /* Set ADC_CommonInitStruct fields to default values */
405 /* Set fields of ADC common */
406 /* (all ADC instances belonging to the same ADC common instance) */
407 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
408
409 #if defined(ADC_MULTIMODE_SUPPORT)
410 /* Set fields of ADC multimode */
411 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
412 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
413 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES;
414 #endif /* ADC_MULTIMODE_SUPPORT */
415 }
416
417 /**
418 * @brief De-initialize registers of the selected ADC instance
419 * to their default reset values.
420 * @note To reset all ADC instances quickly (perform a hard reset),
421 * use function @ref LL_ADC_CommonDeInit().
422 * @param ADCx ADC instance
423 * @retval An ErrorStatus enumeration value:
424 * - SUCCESS: ADC registers are de-initialized
425 * - ERROR: ADC registers are not de-initialized
426 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)427 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
428 {
429 ErrorStatus status = SUCCESS;
430
431 /* Check the parameters */
432 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
433
434 /* Disable ADC instance if not already disabled. */
435 if(LL_ADC_IsEnabled(ADCx) == 1UL)
436 {
437 /* Set ADC group regular trigger source to SW start to ensure to not */
438 /* have an external trigger event occurring during the conversion stop */
439 /* ADC disable process. */
440 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
441
442 /* Set ADC group injected trigger source to SW start to ensure to not */
443 /* have an external trigger event occurring during the conversion stop */
444 /* ADC disable process. */
445 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
446
447 /* Disable the ADC instance */
448 LL_ADC_Disable(ADCx);
449 }
450
451 /* Check whether ADC state is compliant with expected state */
452 /* (hardware requirements of bits state to reset registers below) */
453 if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0UL)
454 {
455 /* ========== Reset ADC registers ========== */
456 /* Reset register SR */
457 CLEAR_BIT(ADCx->SR,
458 ( LL_ADC_FLAG_STRT
459 | LL_ADC_FLAG_JSTRT
460 | LL_ADC_FLAG_EOCS
461 | LL_ADC_FLAG_OVR
462 | LL_ADC_FLAG_JEOS
463 | LL_ADC_FLAG_AWD1 )
464 );
465
466 /* Reset register CR1 */
467 CLEAR_BIT(ADCx->CR1,
468 ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN
469 | ADC_CR1_JAWDEN
470 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
471 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
472 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
473 | ADC_CR1_AWDCH )
474 );
475
476 /* Reset register CR2 */
477 CLEAR_BIT(ADCx->CR2,
478 ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL
479 | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL
480 | ADC_CR2_ALIGN | ADC_CR2_EOCS
481 | ADC_CR2_DDS | ADC_CR2_DMA
482 | ADC_CR2_CONT | ADC_CR2_ADON )
483 );
484
485 /* Reset register SMPR1 */
486 CLEAR_BIT(ADCx->SMPR1,
487 ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
488 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
489 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
490 );
491
492 /* Reset register SMPR2 */
493 CLEAR_BIT(ADCx->SMPR2,
494 ( ADC_SMPR2_SMP9
495 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
496 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
497 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
498 );
499
500 /* Reset register JOFR1 */
501 CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
502 /* Reset register JOFR2 */
503 CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
504 /* Reset register JOFR3 */
505 CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
506 /* Reset register JOFR4 */
507 CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
508
509 /* Reset register HTR */
510 SET_BIT(ADCx->HTR, ADC_HTR_HT);
511 /* Reset register LTR */
512 CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
513
514 /* Reset register SQR1 */
515 CLEAR_BIT(ADCx->SQR1,
516 ( ADC_SQR1_L
517 | ADC_SQR1_SQ16
518 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
519 );
520
521 /* Reset register SQR2 */
522 CLEAR_BIT(ADCx->SQR2,
523 ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
524 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
525 );
526
527 /* Reset register SQR3 */
528 CLEAR_BIT(ADCx->SQR3,
529 ( ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4
530 | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1)
531 );
532
533 /* Reset register JSQR */
534 CLEAR_BIT(ADCx->JSQR,
535 ( ADC_JSQR_JL
536 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
537 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
538 );
539
540 /* Reset register DR */
541 /* bits in access mode read only, no direct reset applicable */
542
543 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
544 /* bits in access mode read only, no direct reset applicable */
545
546 /* Reset register CCR */
547 CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE);
548 }
549
550 return status;
551 }
552
553 /**
554 * @brief Initialize some features of ADC instance.
555 * @note These parameters have an impact on ADC scope: ADC instance.
556 * Affects both group regular and group injected (availability
557 * of ADC group injected depends on STM32 families).
558 * Refer to corresponding unitary functions into
559 * @ref ADC_LL_EF_Configuration_ADC_Instance .
560 * @note The setting of these parameters by function @ref LL_ADC_Init()
561 * is conditioned to ADC state:
562 * ADC instance must be disabled.
563 * This condition is applied to all ADC features, for efficiency
564 * and compatibility over all STM32 families. However, the different
565 * features can be set under different ADC state conditions
566 * (setting possible with ADC enabled without conversion on going,
567 * ADC enabled with conversion on going, ...)
568 * Each feature can be updated afterwards with a unitary function
569 * and potentially with ADC in a different state than disabled,
570 * refer to description of each function for setting
571 * conditioned to ADC state.
572 * @note After using this function, some other features must be configured
573 * using LL unitary functions.
574 * The minimum configuration remaining to be done is:
575 * - Set ADC group regular or group injected sequencer:
576 * map channel on the selected sequencer rank.
577 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
578 * - Set ADC channel sampling time
579 * Refer to function LL_ADC_SetChannelSamplingTime();
580 * @param ADCx ADC instance
581 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
582 * @retval An ErrorStatus enumeration value:
583 * - SUCCESS: ADC registers are initialized
584 * - ERROR: ADC registers are not initialized
585 */
LL_ADC_Init(ADC_TypeDef * ADCx,LL_ADC_InitTypeDef * ADC_InitStruct)586 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
587 {
588 ErrorStatus status = SUCCESS;
589
590 /* Check the parameters */
591 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
592
593 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
594 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
595 assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
596
597 /* Note: Hardware constraint (refer to description of this function): */
598 /* ADC instance must be disabled. */
599 if(LL_ADC_IsEnabled(ADCx) == 0UL)
600 {
601 /* Configuration of ADC hierarchical scope: */
602 /* - ADC instance */
603 /* - Set ADC data resolution */
604 /* - Set ADC conversion data alignment */
605 MODIFY_REG(ADCx->CR1,
606 ADC_CR1_RES
607 | ADC_CR1_SCAN
608 ,
609 ADC_InitStruct->Resolution
610 | ADC_InitStruct->SequencersScanMode
611 );
612
613 MODIFY_REG(ADCx->CR2,
614 ADC_CR2_ALIGN
615 ,
616 ADC_InitStruct->DataAlignment
617 );
618
619 }
620 else
621 {
622 /* Initialization error: ADC instance is not disabled. */
623 status = ERROR;
624 }
625 return status;
626 }
627
628 /**
629 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
630 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
631 * whose fields will be set to default values.
632 * @retval None
633 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * ADC_InitStruct)634 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
635 {
636 /* Set ADC_InitStruct fields to default values */
637 /* Set fields of ADC instance */
638 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
639 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
640
641 /* Enable scan mode to have a generic behavior with ADC of other */
642 /* STM32 families, without this setting available: */
643 /* ADC group regular sequencer and ADC group injected sequencer depend */
644 /* only of their own configuration. */
645 ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
646
647 }
648
649 /**
650 * @brief Initialize some features of ADC group regular.
651 * @note These parameters have an impact on ADC scope: ADC group regular.
652 * Refer to corresponding unitary functions into
653 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
654 * (functions with prefix "REG").
655 * @note The setting of these parameters by function @ref LL_ADC_Init()
656 * is conditioned to ADC state:
657 * ADC instance must be disabled.
658 * This condition is applied to all ADC features, for efficiency
659 * and compatibility over all STM32 families. However, the different
660 * features can be set under different ADC state conditions
661 * (setting possible with ADC enabled without conversion on going,
662 * ADC enabled with conversion on going, ...)
663 * Each feature can be updated afterwards with a unitary function
664 * and potentially with ADC in a different state than disabled,
665 * refer to description of each function for setting
666 * conditioned to ADC state.
667 * @note After using this function, other features must be configured
668 * using LL unitary functions.
669 * The minimum configuration remaining to be done is:
670 * - Set ADC group regular or group injected sequencer:
671 * map channel on the selected sequencer rank.
672 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
673 * - Set ADC channel sampling time
674 * Refer to function LL_ADC_SetChannelSamplingTime();
675 * @param ADCx ADC instance
676 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
677 * @retval An ErrorStatus enumeration value:
678 * - SUCCESS: ADC registers are initialized
679 * - ERROR: ADC registers are not initialized
680 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)681 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
682 {
683 ErrorStatus status = SUCCESS;
684
685 /* Check the parameters */
686 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
687 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
688 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
689 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
690 {
691 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
692 }
693 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
694 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
695
696 /* ADC group regular continuous mode and discontinuous mode */
697 /* can not be enabled simultenaeously */
698 assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
699 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
700
701 /* Note: Hardware constraint (refer to description of this function): */
702 /* ADC instance must be disabled. */
703 if(LL_ADC_IsEnabled(ADCx) == 0UL)
704 {
705 /* Configuration of ADC hierarchical scope: */
706 /* - ADC group regular */
707 /* - Set ADC group regular trigger source */
708 /* - Set ADC group regular sequencer length */
709 /* - Set ADC group regular sequencer discontinuous mode */
710 /* - Set ADC group regular continuous mode */
711 /* - Set ADC group regular conversion data transfer: no transfer or */
712 /* transfer by DMA, and DMA requests mode */
713 /* Note: On this STM32 series, ADC trigger edge is set when starting */
714 /* ADC conversion. */
715 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
716 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
717 {
718 MODIFY_REG(ADCx->CR1,
719 ADC_CR1_DISCEN
720 | ADC_CR1_DISCNUM
721 ,
722 ADC_REG_InitStruct->SequencerDiscont
723 );
724 }
725 else
726 {
727 MODIFY_REG(ADCx->CR1,
728 ADC_CR1_DISCEN
729 | ADC_CR1_DISCNUM
730 ,
731 LL_ADC_REG_SEQ_DISCONT_DISABLE
732 );
733 }
734
735 MODIFY_REG(ADCx->CR2,
736 ADC_CR2_EXTSEL
737 | ADC_CR2_EXTEN
738 | ADC_CR2_CONT
739 | ADC_CR2_DMA
740 | ADC_CR2_DDS
741 ,
742 (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL)
743 | ADC_REG_InitStruct->ContinuousMode
744 | ADC_REG_InitStruct->DMATransfer
745 );
746
747 /* Set ADC group regular sequencer length and scan direction */
748 /* Note: Hardware constraint (refer to description of this function): */
749 /* Note: If ADC instance feature scan mode is disabled */
750 /* (refer to ADC instance initialization structure */
751 /* parameter @ref SequencersScanMode */
752 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
753 /* this parameter is discarded. */
754 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
755 }
756 else
757 {
758 /* Initialization error: ADC instance is not disabled. */
759 status = ERROR;
760 }
761 return status;
762 }
763
764 /**
765 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
766 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
767 * whose fields will be set to default values.
768 * @retval None
769 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)770 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
771 {
772 /* Set ADC_REG_InitStruct fields to default values */
773 /* Set fields of ADC group regular */
774 /* Note: On this STM32 series, ADC trigger edge is set when starting */
775 /* ADC conversion. */
776 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
777 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
778 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
779 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
780 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
781 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
782 }
783
784 /**
785 * @brief Initialize some features of ADC group injected.
786 * @note These parameters have an impact on ADC scope: ADC group injected.
787 * Refer to corresponding unitary functions into
788 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
789 * (functions with prefix "INJ").
790 * @note The setting of these parameters by function @ref LL_ADC_Init()
791 * is conditioned to ADC state:
792 * ADC instance must be disabled.
793 * This condition is applied to all ADC features, for efficiency
794 * and compatibility over all STM32 families. However, the different
795 * features can be set under different ADC state conditions
796 * (setting possible with ADC enabled without conversion on going,
797 * ADC enabled with conversion on going, ...)
798 * Each feature can be updated afterwards with a unitary function
799 * and potentially with ADC in a different state than disabled,
800 * refer to description of each function for setting
801 * conditioned to ADC state.
802 * @note After using this function, other features must be configured
803 * using LL unitary functions.
804 * The minimum configuration remaining to be done is:
805 * - Set ADC group injected sequencer:
806 * map channel on the selected sequencer rank.
807 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
808 * - Set ADC channel sampling time
809 * Refer to function LL_ADC_SetChannelSamplingTime();
810 * @param ADCx ADC instance
811 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
812 * @retval An ErrorStatus enumeration value:
813 * - SUCCESS: ADC registers are initialized
814 * - ERROR: ADC registers are not initialized
815 */
LL_ADC_INJ_Init(ADC_TypeDef * ADCx,LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)816 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
817 {
818 ErrorStatus status = SUCCESS;
819
820 /* Check the parameters */
821 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
822 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
823 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
824 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
825 {
826 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
827 }
828 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
829
830 /* Note: Hardware constraint (refer to description of this function): */
831 /* ADC instance must be disabled. */
832 if(LL_ADC_IsEnabled(ADCx) == 0UL)
833 {
834 /* Configuration of ADC hierarchical scope: */
835 /* - ADC group injected */
836 /* - Set ADC group injected trigger source */
837 /* - Set ADC group injected sequencer length */
838 /* - Set ADC group injected sequencer discontinuous mode */
839 /* - Set ADC group injected conversion trigger: independent or */
840 /* from ADC group regular */
841 /* Note: On this STM32 series, ADC trigger edge is set when starting */
842 /* ADC conversion. */
843 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
844 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
845 {
846 MODIFY_REG(ADCx->CR1,
847 ADC_CR1_JDISCEN
848 | ADC_CR1_JAUTO
849 ,
850 ADC_INJ_InitStruct->SequencerDiscont
851 | ADC_INJ_InitStruct->TrigAuto
852 );
853 }
854 else
855 {
856 MODIFY_REG(ADCx->CR1,
857 ADC_CR1_JDISCEN
858 | ADC_CR1_JAUTO
859 ,
860 LL_ADC_REG_SEQ_DISCONT_DISABLE
861 | ADC_INJ_InitStruct->TrigAuto
862 );
863 }
864
865 MODIFY_REG(ADCx->CR2,
866 ADC_CR2_JEXTSEL
867 | ADC_CR2_JEXTEN
868 ,
869 (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL)
870 );
871
872 /* Note: Hardware constraint (refer to description of this function): */
873 /* Note: If ADC instance feature scan mode is disabled */
874 /* (refer to ADC instance initialization structure */
875 /* parameter @ref SequencersScanMode */
876 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
877 /* this parameter is discarded. */
878 LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
879 }
880 else
881 {
882 /* Initialization error: ADC instance is not disabled. */
883 status = ERROR;
884 }
885 return status;
886 }
887
888 /**
889 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
890 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
891 * whose fields will be set to default values.
892 * @retval None
893 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)894 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
895 {
896 /* Set ADC_INJ_InitStruct fields to default values */
897 /* Set fields of ADC group injected */
898 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
899 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
900 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
901 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
902 }
903
904 /**
905 * @}
906 */
907
908 /**
909 * @}
910 */
911
912 /**
913 * @}
914 */
915
916 #endif /* ADC1 || ADC2 || ADC3 */
917
918 /**
919 * @}
920 */
921
922 #endif /* USE_FULL_LL_DRIVER */
923
924 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
925