1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_aes.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of AES LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_AES AES
47 * @brief AES LL module driver.
48 * @{
49 */
50 /* Define to prevent recursive inclusion -------------------------------------*/
51 #ifndef __GR55XX_LL_AES_H__
52 #define __GR55XX_LL_AES_H__
53
54 /* Includes ------------------------------------------------------------------*/
55 #include "gr55xx.h"
56
57 #ifdef __cplusplus
58 extern "C" {
59 #endif
60
61 #if defined (AES)
62
63 /** @defgroup AES_LL_STRUCTURES Structures
64 * @{
65 */
66
67 /* Exported types ------------------------------------------------------------*/
68 /** @defgroup AES_LL_ES_INIT AES Exported Init structures
69 * @{
70 */
71
72 /**
73 * @brief LL AES Init Structure definition
74 */
75 typedef struct _ll_aes_init {
76 uint32_t key_size; /**< 128, 192 or 256-bit key length.
77 This parameter can be a value of @ref AES_LL_EC_KEY_SIZE */
78
79 uint32_t *p_key; /**< Encryption/Decryption Key */
80
81 uint32_t *p_init_vector; /**< Initialization Vector used for CBC modes */
82
83 uint32_t *p_seed; /**< Random seeds */
84 } ll_aes_init_t;
85
86 /** @} */
87
88 /** @} */
89
90 /**
91 * @defgroup AES_LL_MACRO Defines
92 * @{
93 */
94
95 /* Exported constants --------------------------------------------------------*/
96 /** @defgroup AES_LL_Exported_Constants AES Exported Constants
97 * @{
98 */
99
100 /** @defgroup AES_LL_EC_GET_FLAG Get Flag Defines
101 * @brief Flag definitions which can be used with LL_AES_ReadReg function
102 * @{
103 */
104 #define LL_AES_FLAG_DATAREADY AES_STATUS_READY /**< AES result data out ready */
105 #define LL_AES_FLAG_DMA_DONE AES_STATUS_TRANSDONE /**< AES dma transfer done */
106 #define LL_AES_FLAG_DMA_ERR AES_STATUS_TRANSERR /**< AES dma transfer error */
107 #define LL_AES_FLAG_KEY_VALID AES_STATUS_KEYVALID /**< AES has fetched key */
108 /** @} */
109
110 /** @defgroup AES_LL_EC_KEY_SIZE Key Size
111 * @{
112 */
113 #define LL_AES_KEY_SIZE_128 0x00000000U /**< 128 bits */
114 #define LL_AES_KEY_SIZE_192 (1UL << AES_CONFIG_KEYMODE_Pos) /**< 192 bits */
115 #define LL_AES_KEY_SIZE_256 (2UL << AES_CONFIG_KEYMODE_Pos) /**< 256 bits */
116 /** @} */
117
118 /** @defgroup AES_LL_EC_OPERATION_MODE Operation Mode
119 * @{
120 */
121 #define LL_AES_OPERATION_MODE_ECB 0x00000000U /**< Electronic codebook (ECB) mode */
122 #define LL_AES_OPERATION_MODE_CBC (1UL << AES_CONFIG_OPMODE_Pos) /**< Cipher block chaining (CBC) mode */
123 /** @} */
124
125 /** @defgroup AES_LL_EC_KEY_TYPE Key Type
126 * @{
127 */
128 #define LL_AES_KEYTYPE_MCU 0x00000000U /**< MCU */
129 #define LL_AES_KEYTYPE_AHB (1UL << AES_CONFIG_KEYTYPE_Pos) /**< AHB master */
130 #define LL_AES_KEYTYPE_KRAM (2UL << AES_CONFIG_KEYTYPE_Pos) /**< Key Port */
131 /** @} */
132
133 /** @defgroup AES_LL_EC_TRANSFER_SIZE Transfer Size
134 * @{
135 */
136 #define LL_AES_DMA_TRANSIZE_MIN (1) /**< Min size = 1 block */
137 #define LL_AES_DMA_TRANSIZE_MAX (2048) /**< Max size = 2048 blocks */
138 /** @} */
139
140 /** @} */
141
142 /* Exported macro ------------------------------------------------------------*/
143 /** @defgroup AES_LL_Exported_Macros AES Exported Macros
144 * @{
145 */
146
147 /** @defgroup AES_LL_EM_WRITE_READ Common Write and read registers Macros
148 * @{
149 */
150
151 /**
152 * @brief Write a value in AES register
153 * @param __INSTANCE__ AES Instance
154 * @param __REG__ Register to be written
155 * @param __VALUE__ Value to be written in the register
156 * @retval None
157 */
158 #define LL_AES_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
159
160 /**
161 * @brief Read a value in AES register
162 * @param __INSTANCE__ AES Instance
163 * @param __REG__ Register to be read
164 * @retval Register value
165 */
166 #define LL_AES_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
167
168 /** @} */
169
170 /** @} */
171
172 /** @} */
173
174 /* Exported functions --------------------------------------------------------*/
175 /** @defgroup AES_LL_DRIVER_FUNCTIONS Functions
176 * @{
177 */
178
179 /** @defgroup AES_LL_EF_Configuration Configuration functions
180 * @{
181 */
182
183 /**
184 * @brief Enable AES.
185 *
186 * Register|BitsName
187 * --------|--------
188 * CTRL | ENABLE
189 *
190 * @param AESx AES instance
191 * @retval None
192 */
ll_aes_enable(aes_regs_t * AESx)193 __STATIC_INLINE void ll_aes_enable(aes_regs_t *AESx)
194 {
195 SET_BITS(AESx->CTRL, AES_CTRL_ENABLE);
196 }
197
198 /**
199 * @brief Disable AES.
200 *
201 * Register|BitsName
202 * --------|--------
203 * CTRL | ENABLE
204 *
205 * @param AESx AES instance
206 * @retval None
207 */
ll_aes_disable(aes_regs_t * AESx)208 __STATIC_INLINE void ll_aes_disable(aes_regs_t *AESx)
209 {
210 CLEAR_BITS(AESx->CTRL, AES_CTRL_ENABLE);
211 }
212
213 /**
214 * @brief Indicate whether the AES is enabled.
215 *
216 * Register|BitsName
217 * --------|--------
218 * CTRL | ENABLE
219 *
220 * @param AESx AES instance
221 * @retval State of bit (1 or 0).
222 */
ll_aes_is_enabled(aes_regs_t * AESx)223 __STATIC_INLINE uint32_t ll_aes_is_enabled(aes_regs_t *AESx)
224 {
225 return (READ_BITS(AESx->CTRL, AES_CTRL_ENABLE) == (AES_CTRL_ENABLE));
226 }
227
228 /**
229 * @brief Enable AES start in MCU mode.
230 *
231 * Register|BitsName
232 * --------|--------
233 * CTRL | START_NORMAL
234 *
235 * @param AESx AES instance
236 * @retval None
237 */
ll_aes_enable_start(aes_regs_t * AESx)238 __STATIC_INLINE void ll_aes_enable_start(aes_regs_t *AESx)
239 {
240 SET_BITS(AESx->CTRL, AES_CTRL_START_NORMAL);
241 }
242
243 /**
244 * @brief Disable AES start in MCU mode.
245 *
246 * Register|BitsName
247 * --------|--------
248 * CTRL | START_NORMAL
249 *
250 * @param AESx AES instance
251 * @retval None
252 */
ll_aes_disable_start(aes_regs_t * AESx)253 __STATIC_INLINE void ll_aes_disable_start(aes_regs_t *AESx)
254 {
255 CLEAR_BITS(AESx->CTRL, AES_CTRL_START_NORMAL);
256 }
257
258 /**
259 * @brief Indicate whether the AES start in MCU mode is enabled.
260 *
261 * Register|BitsName
262 * --------|--------
263 * CTRL | START_NORMAL
264 *
265 * @param AESx AES instance
266 * @retval State of bit (1 or 0).
267 */
ll_aes_is_enabled_start(aes_regs_t * AESx)268 __STATIC_INLINE uint32_t ll_aes_is_enabled_start(aes_regs_t *AESx)
269 {
270 return (READ_BITS(AESx->CTRL, AES_CTRL_START_NORMAL) == (AES_CTRL_START_NORMAL));
271 }
272
273 /**
274 * @brief Enable AES DMA mode.
275 *
276 * Register|BitsName
277 * --------|--------
278 * CTRL | START_DMA
279 *
280 * @param AESx AES instance
281 * @retval None
282 */
ll_aes_enable_dma_start(aes_regs_t * AESx)283 __STATIC_INLINE void ll_aes_enable_dma_start(aes_regs_t *AESx)
284 {
285 SET_BITS(AESx->CTRL, AES_CTRL_START_DMA);
286 }
287
288 /**
289 * @brief Disable AES DMA mode.
290 *
291 * Register|BitsName
292 * --------|--------
293 * CTRL | START_DMA
294 *
295 * @param AESx AES instance
296 * @retval None
297 */
ll_aes_disable_dma_start(aes_regs_t * AESx)298 __STATIC_INLINE void ll_aes_disable_dma_start(aes_regs_t *AESx)
299 {
300 CLEAR_BITS(AESx->CTRL, AES_CTRL_START_DMA);
301 }
302
303 /**
304 * @brief Indicate whether the AES DMA mode is enabled.
305 *
306 * Register|BitsName
307 * --------|--------
308 * CTRL | START_DMA
309 *
310 * @param AESx AES instance
311 * @retval State of bit (1 or 0).
312 */
ll_aes_is_enabled_dma_start(aes_regs_t * AESx)313 __STATIC_INLINE uint32_t ll_aes_is_enabled_dma_start(aes_regs_t *AESx)
314 {
315 return (READ_BITS(AESx->CTRL, AES_CTRL_START_DMA) == (AES_CTRL_START_DMA));
316 }
317
318 /**
319 * @brief Enable fetch key through AHB/key port.
320 *
321 * Register|BitsName
322 * --------|--------
323 * CTRL | ENABLE_RKEY
324 *
325 * @param AESx AES instance
326 * @retval None
327 */
ll_aes_enable_read_key(aes_regs_t * AESx)328 __STATIC_INLINE void ll_aes_enable_read_key(aes_regs_t *AESx)
329 {
330 SET_BITS(AESx->CTRL, AES_CTRL_ENABLE_RKEY);
331 }
332
333 /**
334 * @brief Set AES key size.
335 *
336 * Register|BitsName
337 * --------|--------
338 * CONFIG | KEYMODE
339 *
340 * @param AESx AES instance
341 * @param size This parameter can be one of the following values:
342 * @arg @ref LL_AES_KEY_SIZE_128
343 * @arg @ref LL_AES_KEY_SIZE_192
344 * @arg @ref LL_AES_KEY_SIZE_256
345 * @retval None
346 */
ll_aes_set_key_size(aes_regs_t * AESx,uint32_t size)347 __STATIC_INLINE void ll_aes_set_key_size(aes_regs_t *AESx, uint32_t size)
348 {
349 MODIFY_REG(AESx->CONFIG, AES_CONFIG_KEYMODE, size);
350 }
351
352 /**
353 * @brief Get AES key size.
354 *
355 * Register|BitsName
356 * --------|--------
357 * CONFIG | KEYMODE
358 *
359 * @param AESx AES instance
360 * @retval Returned value can be one of the following values:
361 * @arg @ref LL_AES_KEY_SIZE_128
362 * @arg @ref LL_AES_KEY_SIZE_192
363 * @arg @ref LL_AES_KEY_SIZE_256
364 */
ll_aes_get_key_size(aes_regs_t * AESx)365 __STATIC_INLINE uint32_t ll_aes_get_key_size(aes_regs_t *AESx)
366 {
367 return (READ_BITS(AESx->CONFIG, AES_CONFIG_KEYMODE));
368 }
369
370 /**
371 * @brief Enable AES full mask.
372 *
373 * Register|BitsName
374 * --------|--------
375 * CONFIG | ENABLE_FULLMASK
376 *
377 * @param AESx AES instance
378 * @retval None
379 */
ll_aes_enable_full_mask(aes_regs_t * AESx)380 __STATIC_INLINE void ll_aes_enable_full_mask(aes_regs_t *AESx)
381 {
382 SET_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_FULLMASK);
383 }
384
385 /**
386 * @brief Disable AES full mask.
387 *
388 * Register|BitsName
389 * --------|--------
390 * CONFIG | ENABLE_FULLMASK
391 *
392 * @param AESx AES instance
393 * @retval None
394 */
ll_aes_disable_full_mask(aes_regs_t * AESx)395 __STATIC_INLINE void ll_aes_disable_full_mask(aes_regs_t *AESx)
396 {
397 CLEAR_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_FULLMASK);
398 }
399
400 /**
401 * @brief Indicate whether the AES full mask is enabled.
402 *
403 * Register|BitsName
404 * --------|--------
405 * CONFIG | ENABLE_FULLMASK
406 *
407 * @param AESx AES instance
408 * @retval State of bit (1 or 0).
409 */
ll_aes_is_enabled_full_mask(aes_regs_t * AESx)410 __STATIC_INLINE uint32_t ll_aes_is_enabled_full_mask(aes_regs_t *AESx)
411 {
412 return (READ_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_FULLMASK) == (AES_CONFIG_ENABLE_FULLMASK));
413 }
414
415 /**
416 * @brief Enable AES encryption mode.
417 *
418 * Register|BitsName
419 * --------|--------
420 * CONFIG | ENABLE_ENCRYPTION
421 *
422 * @param AESx AES instance
423 * @retval None
424 */
ll_aes_enable_encryption(aes_regs_t * AESx)425 __STATIC_INLINE void ll_aes_enable_encryption(aes_regs_t *AESx)
426 {
427 SET_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_ENCRYPTION);
428 }
429
430 /**
431 * @brief Disable AES encryption mode.
432 *
433 * Register|BitsName
434 * --------|--------
435 * CONFIG | ENABLE_ENCRYPTION
436 *
437 * @param AESx AES instance
438 * @retval None
439 */
ll_aes_disable_encryption(aes_regs_t * AESx)440 __STATIC_INLINE void ll_aes_disable_encryption(aes_regs_t *AESx)
441 {
442 CLEAR_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_ENCRYPTION);
443 }
444
445 /**
446 * @brief Indicate whether the AES encryption mode is enabled.
447 *
448 * Register|BitsName
449 * --------|--------
450 * CONFIG | ENABLE_ENCRYPTION
451 *
452 * @param AESx AES instance
453 * @retval State of bit (1 or 0).
454 */
ll_aes_is_enabled_encryption(aes_regs_t * AESx)455 __STATIC_INLINE uint32_t ll_aes_is_enabled_encryption(aes_regs_t *AESx)
456 {
457 return (READ_BITS(AESx->CONFIG, AES_CONFIG_ENABLE_ENCRYPTION) == (AES_CONFIG_ENABLE_ENCRYPTION));
458 }
459
460 /**
461 * @brief Set AES to load seed for LFSR.
462 *
463 * Register|BitsName
464 * --------|--------
465 * CONFIG | LOADSEED
466 *
467 * @param AESx AES instance
468 * @retval None
469 */
ll_aes_set_load_seed(aes_regs_t * AESx)470 __STATIC_INLINE void ll_aes_set_load_seed(aes_regs_t *AESx)
471 {
472 SET_BITS(AESx->CONFIG, AES_CONFIG_LOADSEED);
473 }
474
475 /**
476 * @brief Set AES in first block before starting the first block in normal CBC and DMA CBC mode.
477 *
478 * Register|BitsName
479 * --------|--------
480 * CONFIG | FIRSTBLOCK
481 *
482 * @param AESx AES instance
483 * @retval None
484 */
ll_aes_set_first_block(aes_regs_t * AESx)485 __STATIC_INLINE void ll_aes_set_first_block(aes_regs_t *AESx)
486 {
487 SET_BITS(AESx->CONFIG, AES_CONFIG_FIRSTBLOCK);
488 }
489
490 /**
491 * @brief Enable AES in little endian.
492 *
493 * Register|BitsName
494 * --------|--------
495 * CONFIG | ENDIAN
496 *
497 * @param AESx AES instance
498 * @retval None
499 */
ll_aes_enable_little_endian(aes_regs_t * AESx)500 __STATIC_INLINE void ll_aes_enable_little_endian(aes_regs_t *AESx)
501 {
502 SET_BITS(AESx->CONFIG, AES_CONFIG_ENDIAN);
503 }
504
505 /**
506 * @brief Disable AES in little endian.
507 *
508 * Register|BitsName
509 * --------|--------
510 * CONFIG | ENDIAN
511 *
512 * @param AESx AES instance
513 * @retval None
514 */
ll_aes_disable_little_endian(aes_regs_t * AESx)515 __STATIC_INLINE void ll_aes_disable_little_endian(aes_regs_t *AESx)
516 {
517 CLEAR_BITS(AESx->CONFIG, AES_CONFIG_ENDIAN);
518 }
519
520 /**
521 * @brief Indicate whether the AES is in little endian.
522 *
523 * Register|BitsName
524 * --------|--------
525 * CONFIG | ENDIAN
526 *
527 * @param AESx AES instance
528 * @retval State of bit (1 or 0).
529 */
ll_aes_is_enabled_little_endian(aes_regs_t * AESx)530 __STATIC_INLINE uint32_t ll_aes_is_enabled_little_endian(aes_regs_t *AESx)
531 {
532 return (READ_BITS(AESx->CONFIG, AES_CONFIG_ENDIAN) == (AES_CONFIG_ENDIAN));
533 }
534
535 /**
536 * @brief Set AES operation mode.
537 *
538 * Register|BitsName
539 * --------|--------
540 * CONFIG | OPMODE
541 *
542 * @param AESx AES instance
543 * @param mode This parameter can be one of the following values:
544 * @arg @ref LL_AES_OPERATION_MODE_ECB
545 * @arg @ref LL_AES_OPERATION_MODE_CBC
546 * @retval None
547 */
ll_aes_set_operation_mode(aes_regs_t * AESx,uint32_t mode)548 __STATIC_INLINE void ll_aes_set_operation_mode(aes_regs_t *AESx, uint32_t mode)
549 {
550 MODIFY_REG(AESx->CONFIG, AES_CONFIG_OPMODE, mode);
551 }
552
553 /**
554 * @brief Get AES operation mode.
555 *
556 * Register|BitsName
557 * --------|--------
558 * CONFIG | OPMODE
559 *
560 * @param AESx AES instance
561 * @retval Returned value can be one of the following values:
562 * @arg @ref LL_AES_OPERATION_MODE_ECB
563 * @arg @ref LL_AES_OPERATION_MODE_CBC
564 */
ll_aes_get_operation_mode(aes_regs_t * AESx)565 __STATIC_INLINE uint32_t ll_aes_get_operation_mode(aes_regs_t *AESx)
566 {
567 return (READ_BITS(AESx->CONFIG, AES_CONFIG_OPMODE));
568 }
569
570 /**
571 * @brief Set ways to obtain AES key.
572 *
573 * Register|BitsName
574 * --------|--------
575 * CONFIG | KEYTYPE
576 *
577 * @param AESx AES instance
578 * @param Type This parameter can be one of the following values:
579 * @arg @ref LL_AES_KEYTYPE_MCU
580 * @arg @ref LL_AES_KEYTYPE_AHB
581 * @arg @ref LL_AES_KEYTYPE_KRAM
582 * @retval None
583 */
ll_aes_set_key_type(aes_regs_t * AESx,uint32_t Type)584 __STATIC_INLINE void ll_aes_set_key_type(aes_regs_t *AESx, uint32_t Type)
585 {
586 MODIFY_REG(AESx->CONFIG, AES_CONFIG_KEYTYPE, Type);
587 }
588
589 /**
590 * @brief Get ways to obtain AES key.
591 *
592 * Register|BitsName
593 * --------|--------
594 * CONFIG | KEYTYPE
595 *
596 * @param AESx AES instance
597 * @retval Returned value can be one of the following values:
598 * @arg @ref LL_AES_KEYTYPE_MCU
599 * @arg @ref LL_AES_KEYTYPE_AHB
600 * @arg @ref LL_AES_KEYTYPE_KRAM
601 */
ll_aes_get_key_type(aes_regs_t * AESx)602 __STATIC_INLINE uint32_t ll_aes_get_key_type(aes_regs_t *AESx)
603 {
604 return (READ_BITS(AESx->CONFIG, AES_CONFIG_KEYTYPE));
605 }
606
607 /** @} */
608
609 /** @defgroup AES_LL_EF_IT_Management IT_Management
610 * @{
611 */
612
613 /**
614 * @brief Enable AES the done interrupt.
615 *
616 * Register|BitsName
617 * --------|--------
618 * INTERRUPT | ENABLE
619 *
620 * @param AESx AES instance
621 * @retval None
622 */
ll_aes_enable_it_done(aes_regs_t * AESx)623 __STATIC_INLINE void ll_aes_enable_it_done(aes_regs_t *AESx)
624 {
625 SET_BITS(AESx->INTERRUPT, AES_INTERRUPT_ENABLE);
626 }
627
628 /**
629 * @brief Disable AES the done interrupt.
630 *
631 * Register|BitsName
632 * --------|--------
633 * INTERRUPT | ENABLE
634 *
635 * @param AESx AES instance
636 * @retval None
637 */
ll_aes_disable_it_done(aes_regs_t * AESx)638 __STATIC_INLINE void ll_aes_disable_it_done(aes_regs_t *AESx)
639 {
640 CLEAR_BITS(AESx->INTERRUPT, AES_INTERRUPT_ENABLE);
641 }
642
643 /**
644 * @brief Indicate whether the done interrupt is enabled.
645 *
646 * Register|BitsName
647 * --------|--------
648 * INTERRUPT | ENABLE
649 *
650 * @param AESx AES instance
651 * @retval State of bit (1 or 0).
652 */
ll_aes_is_enabled_it_done(aes_regs_t * AESx)653 __STATIC_INLINE uint32_t ll_aes_is_enabled_it_done(aes_regs_t *AESx)
654 {
655 return (READ_BITS(AESx->INTERRUPT, AES_INTERRUPT_ENABLE) == (AES_INTERRUPT_ENABLE));
656 }
657
658 /** @} */
659
660 /** @defgroup AES_LL_EF_FLAG_Management FLAG_Management
661 * @{
662 */
663
664 /**
665 * @brief Indicate whether the ready flag is set.
666 *
667 * Register|BitsName
668 * --------|--------
669 * STATUS | READY
670 *
671 * @param AESx AES instance
672 * @retval State of bit (1 or 0).
673 */
ll_aes_is_action_flag_ready(aes_regs_t * AESx)674 __STATIC_INLINE uint32_t ll_aes_is_action_flag_ready(aes_regs_t *AESx)
675 {
676 return (READ_BITS(AESx->STATUS, AES_STATUS_READY) == AES_STATUS_READY);
677 }
678
679 /**
680 * @brief Indicate whether the DMA transfer done flag is set.
681 *
682 * Register|BitsName
683 * --------|--------
684 * STATUS | TRANSDONE
685 *
686 * @param AESx AES instance
687 * @retval State of bit (1 or 0).
688 */
ll_aes_is_action_flag_dma_done(aes_regs_t * AESx)689 __STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_done(aes_regs_t *AESx)
690 {
691 return (READ_BITS(AESx->STATUS, AES_STATUS_TRANSDONE) == AES_STATUS_TRANSDONE);
692 }
693
694 /**
695 * @brief Indicate whether the DMA transfer error flag is set.
696 *
697 * Register|BitsName
698 * --------|--------
699 * STATUS | TRANSERR
700 *
701 * @param AESx AES instance
702 * @retval State of bit (1 or 0).
703 */
ll_aes_is_action_flag_dma_error(aes_regs_t * AESx)704 __STATIC_INLINE uint32_t ll_aes_is_action_flag_dma_error(aes_regs_t *AESx)
705 {
706 return (READ_BITS(AESx->STATUS, AES_STATUS_TRANSERR) == AES_STATUS_TRANSERR);
707 }
708
709 /**
710 * @brief Indicate whether the key valid flag is set.
711 *
712 * Register|BitsName
713 * --------|--------
714 * STATUS | KEYVALID
715 *
716 * @param AESx AES instance
717 * @retval State of bit (1 or 0).
718 */
ll_aes_is_action_flag_key_valid(aes_regs_t * AESx)719 __STATIC_INLINE uint32_t ll_aes_is_action_flag_key_valid(aes_regs_t *AESx)
720 {
721 return (READ_BITS(AESx->STATUS, AES_STATUS_KEYVALID) == AES_STATUS_KEYVALID);
722 }
723
724 /**
725 * @brief Indicate whether the done interrupt flag is set.
726 *
727 * Register|BitsName
728 * --------|--------
729 * INTERRUPT | DONE
730 *
731 * @param AESx AES instance
732 * @retval State of bit (1 or 0).
733 */
ll_aes_is_action_flag_it_done(aes_regs_t * AESx)734 __STATIC_INLINE uint32_t ll_aes_is_action_flag_it_done(aes_regs_t *AESx)
735 {
736 return (READ_BITS(AESx->INTERRUPT, AES_INTERRUPT_DONE) == AES_INTERRUPT_DONE);
737 }
738
739 /**
740 * @brief Clear the done interrupt flag.
741 *
742 * Register|BitsName
743 * --------|--------
744 * INTERRUPT | DONE
745 *
746 * @param AESx AES instance
747 * @retval None
748 */
ll_aes_clear_flag_it_done(aes_regs_t * AESx)749 __STATIC_INLINE void ll_aes_clear_flag_it_done(aes_regs_t *AESx)
750 {
751 SET_BITS(AESx->INTERRUPT, AES_INTERRUPT_DONE);
752 }
753
754 /** @} */
755
756 /** @defgroup AES_LL_EF_DMA_Management DMA_Management
757 * @{
758 */
759
760 /**
761 * @brief Set AES transfer blocks in DMA mode.
762 *
763 * Register|BitsName
764 * --------|--------
765 * TRAN_SIZE | TRAN_SIZE
766 *
767 * @param AESx AES instance
768 * @param block This parameter can be one of the following values: 1 ~ 2048.
769 * @retval None
770 */
ll_aes_set_dma_transfer_block(aes_regs_t * AESx,uint32_t block)771 __STATIC_INLINE void ll_aes_set_dma_transfer_block(aes_regs_t *AESx, uint32_t block)
772 {
773 MODIFY_REG(AESx->TRAN_SIZE, AES_TRAN_SIZE, (block << ITEM_4) - 1);
774 }
775
776 /**
777 * @brief Get AES transfer blocks in DMA mode.
778 *
779 * Register|BitsName
780 * --------|--------
781 * TRAN_SIZE | TRAN_SIZE
782 *
783 * @param AESx AES instance
784 * @retval Return value between 1 and 2048.
785 */
ll_aes_get_dma_transfer_block(aes_regs_t * AESx)786 __STATIC_INLINE uint32_t ll_aes_get_dma_transfer_block(aes_regs_t *AESx)
787 {
788 return ((READ_BITS(AESx->TRAN_SIZE, AES_TRAN_SIZE) + 1) >> ITEM_4);
789 }
790
791 /**
792 * @brief Set AES read address of RAM in DMA mode.
793 * @note This read address of RAM requires 4 byte alignment.
794 *
795 * Register|BitsName
796 * --------|--------
797 * RSTART_ADDR | RSTART_ADDR
798 *
799 * @param AESx AES instance
800 * @param address This parameter can be a address in RAM area (0x30000000 ~ 0x3003FFFF).
801 * @retval None
802 */
ll_aes_set_dma_read_address(aes_regs_t * AESx,uint32_t address)803 __STATIC_INLINE void ll_aes_set_dma_read_address(aes_regs_t *AESx, uint32_t address)
804 {
805 WRITE_REG(AESx->RSTART_ADDR, address);
806 }
807
808 /**
809 * @brief Get AES read address of RAM in DMA mode.
810 *
811 * Register|BitsName
812 * --------|--------
813 * RSTART_ADDR | RSTART_ADDR
814 *
815 * @param AESx AES instance
816 * @retval Returned value is the read address in RAM.
817 */
ll_aes_get_dma_read_address(aes_regs_t * AESx)818 __STATIC_INLINE uint32_t ll_aes_get_dma_read_address(aes_regs_t *AESx)
819 {
820 return (READ_REG(AESx->RSTART_ADDR));
821 }
822
823 /**
824 * @brief Set AES write address of RAM in DMA mode.
825 * @note This write address of RAM requires 4 byte alignment.
826 *
827 * Register|BitsName
828 * --------|--------
829 * WSTART_ADDR | WSTART_ADDR
830 *
831 * @param AESx AES instance
832 * @param address This parameter can be a address in RAM area (0x30000000 ~ 0x3003FFFF).
833 * @retval None
834 */
ll_aes_set_dma_write_address(aes_regs_t * AESx,uint32_t address)835 __STATIC_INLINE void ll_aes_set_dma_write_address(aes_regs_t *AESx, uint32_t address)
836 {
837 WRITE_REG(AESx->WSTART_ADDR, address);
838 }
839
840 /**
841 * @brief Get AES write address of RAM in DMA mode.
842 *
843 * Register|BitsName
844 * --------|--------
845 * WSTART_ADDR | WSTART_ADDR
846 *
847 * @param AESx AES instance
848 * @retval Returned value is the wrute address in RAM
849 */
ll_aes_get_dma_write_address(aes_regs_t * AESx)850 __STATIC_INLINE uint32_t ll_aes_get_dma_write_address(aes_regs_t *AESx)
851 {
852 return (READ_REG(AESx->WSTART_ADDR));
853 }
854
855 /** @} */
856
857 /** @defgroup AES_LL_EF_Data_Management Data_Management
858 * @{
859 */
860
861 /**
862 * @brief Set AES key address in memory.
863 *
864 * Register|BitsName
865 * --------|--------
866 * KEY_ADDR | KEY_ADDR
867 *
868 * @param AESx AES instance
869 * @param address This parameter can be one of the address in RAM
870 * @retval None
871 */
ll_aes_set_key_address(aes_regs_t * AESx,uint32_t address)872 __STATIC_INLINE void ll_aes_set_key_address(aes_regs_t *AESx, uint32_t address)
873 {
874 WRITE_REG(AESx->KEY_ADDR, address);
875 }
876
877 /**
878 * @brief Get AES key address in memory.
879 *
880 * Register|BitsName
881 * --------|--------
882 * KEY_ADDR | KEY_ADDR
883 *
884 * @param AESx AES instance
885 * @retval Returned value is the key address in RAM.
886 */
ll_aes_get_key_address(aes_regs_t * AESx)887 __STATIC_INLINE uint32_t ll_aes_get_key_address(aes_regs_t *AESx)
888 {
889 return (READ_REG(AESx->KEY_ADDR));
890 }
891
892 /**
893 * @brief Get AES output data[127:96].
894 *
895 * Register|BitsName
896 * --------|--------
897 * DATA_OUT[0] | DATA_OUT
898 *
899 * @param AESx AES instance
900 * @retval Output Data[127:96]
901 */
ll_aes_get_data_127_96(aes_regs_t * AESx)902 __STATIC_INLINE uint32_t ll_aes_get_data_127_96(aes_regs_t *AESx)
903 {
904 return (READ_REG(AESx->DATA_OUT[0]));
905 }
906
907 /**
908 * @brief Get AES output data[95:64].
909 *
910 * Register|BitsName
911 * --------|--------
912 * DATA_OUT[1] | DATA_OUT
913 *
914 * @param AESx AES instance
915 * @retval Output Data[95:64]
916 */
ll_aes_get_data_95_64(aes_regs_t * AESx)917 __STATIC_INLINE uint32_t ll_aes_get_data_95_64(aes_regs_t *AESx)
918 {
919 return (READ_REG(AESx->DATA_OUT[1]));
920 }
921
922 /**
923 * @brief Get AES output data[63:32].
924 *
925 * Register|BitsName
926 * --------|--------
927 * DATA_OUT[2] | DATA_OUT
928 *
929 * @param AESx AES instance
930 * @retval Output Data[63:32]
931 */
ll_aes_get_data_63_32(aes_regs_t * AESx)932 __STATIC_INLINE uint32_t ll_aes_get_data_63_32(aes_regs_t *AESx)
933 {
934 return (READ_REG(AESx->DATA_OUT[ITEM_2]));
935 }
936
937 /**
938 * @brief Get AES output data[31:0].
939 *
940 * Register|BitsName
941 * --------|--------
942 * DATA_OUT[3] | DATA_OUT
943 *
944 * @param AESx AES instance
945 * @retval Output Data[31:0]
946 */
ll_aes_get_data_31_0(aes_regs_t * AESx)947 __STATIC_INLINE uint32_t ll_aes_get_data_31_0(aes_regs_t *AESx)
948 {
949 return (READ_REG(AESx->DATA_OUT[ITEM_3]));
950 }
951
952 /**
953 * @brief Set AES key[255:224].
954 *
955 * Register|BitsName
956 * --------|--------
957 * KEY[0] | KEY
958 *
959 * @param AESx AES instance
960 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
961 * @retval None
962 */
ll_aes_set_key_255_224(aes_regs_t * AESx,uint32_t key)963 __STATIC_INLINE void ll_aes_set_key_255_224(aes_regs_t *AESx, uint32_t key)
964 {
965 WRITE_REG(AESx->KEY[0], key);
966 }
967
968 /**
969 * @brief Set AES key[223:192].
970 *
971 * Register|BitsName
972 * --------|--------
973 * KEY[1] | KEY
974 *
975 * @param AESx AES instance
976 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
977 * @retval None
978 */
ll_aes_set_key_223_192(aes_regs_t * AESx,uint32_t key)979 __STATIC_INLINE void ll_aes_set_key_223_192(aes_regs_t *AESx, uint32_t key)
980 {
981 WRITE_REG(AESx->KEY[1], key);
982 }
983
984 /**
985 * @brief Set AES key[191:160].
986 *
987 * Register|BitsName
988 * --------|--------
989 * KEY[2] | KEY
990 *
991 * @param AESx AES instance
992 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
993 * @retval None
994 */
ll_aes_set_key_191_160(aes_regs_t * AESx,uint32_t key)995 __STATIC_INLINE void ll_aes_set_key_191_160(aes_regs_t *AESx, uint32_t key)
996 {
997 WRITE_REG(AESx->KEY[ITEM_2], key);
998 }
999
1000 /**
1001 * @brief Set AES key[159:128].
1002 *
1003 * Register|BitsName
1004 * --------|--------
1005 * KEY[3] | KEY
1006 *
1007 * @param AESx AES instance
1008 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1009 * @retval None
1010 */
ll_aes_set_key_159_128(aes_regs_t * AESx,uint32_t key)1011 __STATIC_INLINE void ll_aes_set_key_159_128(aes_regs_t *AESx, uint32_t key)
1012 {
1013 WRITE_REG(AESx->KEY[ITEM_3], key);
1014 }
1015
1016 /**
1017 * @brief Set AES key[127:96].
1018 *
1019 * Register|BitsName
1020 * --------|--------
1021 * KEY[4] | KEY
1022 *
1023 * @param AESx AES instance
1024 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1025 * @retval None
1026 */
ll_aes_set_key_127_96(aes_regs_t * AESx,uint32_t key)1027 __STATIC_INLINE void ll_aes_set_key_127_96(aes_regs_t *AESx, uint32_t key)
1028 {
1029 WRITE_REG(AESx->KEY[ITEM_4], key);
1030 }
1031
1032 /**
1033 * @brief Set AES key[95:64].
1034 *
1035 * Register|BitsName
1036 * --------|--------
1037 * KEY[5] | KEY
1038 *
1039 * @param AESx AES instance
1040 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1041 * @retval None
1042 */
ll_aes_set_key_95_64(aes_regs_t * AESx,uint32_t key)1043 __STATIC_INLINE void ll_aes_set_key_95_64(aes_regs_t *AESx, uint32_t key)
1044 {
1045 WRITE_REG(AESx->KEY[ITEM_5], key);
1046 }
1047
1048 /**
1049 * @brief Set AES key[63:32].
1050 *
1051 * Register|BitsName
1052 * --------|--------
1053 * KEY[6] | KEY
1054 *
1055 * @param AESx AES instance
1056 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1057 * @retval None
1058 */
ll_aes_set_key_63_32(aes_regs_t * AESx,uint32_t key)1059 __STATIC_INLINE void ll_aes_set_key_63_32(aes_regs_t *AESx, uint32_t key)
1060 {
1061 WRITE_REG(AESx->KEY[ITEM_6], key);
1062 }
1063
1064 /**
1065 * @brief Set AES key[31:0].
1066 *
1067 * Register|BitsName
1068 * --------|--------
1069 * KEY[7] | KEY
1070 *
1071 * @param AESx AES instance
1072 * @param key This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1073 * @retval None
1074 */
ll_aes_set_key_31_0(aes_regs_t * AESx,uint32_t key)1075 __STATIC_INLINE void ll_aes_set_key_31_0(aes_regs_t *AESx, uint32_t key)
1076 {
1077 WRITE_REG(AESx->KEY[ITEM_7], key);
1078 }
1079
1080 /**
1081 * @brief Set AES input seed.
1082 *
1083 * Register|BitsName
1084 * --------|--------
1085 * SEED_IN | SEED_IN
1086 *
1087 * @param AESx AES instance
1088 * @param seed This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1089 * @retval None
1090 */
ll_aes_set_seed_in(aes_regs_t * AESx,uint32_t seed)1091 __STATIC_INLINE void ll_aes_set_seed_in(aes_regs_t *AESx, uint32_t seed)
1092 {
1093 WRITE_REG(AESx->SEED_IN, seed);
1094 }
1095
1096 /**
1097 * @brief Get AES input seed.
1098 *
1099 * Register|BitsName
1100 * --------|--------
1101 * SEED_IN | SEED_IN
1102 *
1103 * @param AESx AES instance
1104 * @retval Returned value is the input seed.
1105 */
ll_aes_get_seed_in(aes_regs_t * AESx)1106 __STATIC_INLINE uint32_t ll_aes_get_seed_in(aes_regs_t *AESx)
1107 {
1108 return (READ_REG(AESx->SEED_IN));
1109 }
1110
1111 /**
1112 * @brief Set AES output seed.
1113 *
1114 * Register|BitsName
1115 * --------|--------
1116 * SEED_OUT | SEED_OUT
1117 *
1118 * @param AESx AES instance
1119 * @param seed This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1120 * @retval None
1121 */
ll_aes_set_seed_out(aes_regs_t * AESx,uint32_t seed)1122 __STATIC_INLINE void ll_aes_set_seed_out(aes_regs_t *AESx, uint32_t seed)
1123 {
1124 WRITE_REG(AESx->SEED_OUT, seed);
1125 }
1126
1127 /**
1128 * @brief Get AES output seed.
1129 *
1130 * Register|BitsName
1131 * --------|--------
1132 * SEED_OUT | SEED_OUT
1133 *
1134 * @param AESx AES instance
1135 * @retval Returned value is the output seed.
1136 */
ll_aes_get_seed_out(aes_regs_t * AESx)1137 __STATIC_INLINE uint32_t ll_aes_get_seed_out(aes_regs_t *AESx)
1138 {
1139 return (READ_REG(AESx->SEED_OUT));
1140 }
1141
1142 /**
1143 * @brief Set sbox input data's mask.
1144 *
1145 * Register|BitsName
1146 * --------|--------
1147 * SEED_IMASK | SEED_IMASK
1148 *
1149 * @param AESx AES instance
1150 * @param mask This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1151 * @retval None
1152 */
ll_aes_set_seed_Imask(aes_regs_t * AESx,uint32_t mask)1153 __STATIC_INLINE void ll_aes_set_seed_Imask(aes_regs_t *AESx, uint32_t mask)
1154 {
1155 WRITE_REG(AESx->SEED_IMASK, mask);
1156 }
1157
1158 /**
1159 * @brief Get sbox input data's mask.
1160 *
1161 * Register|BitsName
1162 * --------|--------
1163 * SEED_IMASK | SEED_IMASK
1164 *
1165 * @param AESx AES instance
1166 * @retval Returned value is the input data's mask.
1167 */
ll_aes_get_seed_Imask(aes_regs_t * AESx)1168 __STATIC_INLINE uint32_t ll_aes_get_seed_Imask(aes_regs_t *AESx)
1169 {
1170 return (READ_REG(AESx->SEED_IMASK));
1171 }
1172
1173 /**
1174 * @brief Set sbox output data's mask.
1175 *
1176 * Register|BitsName
1177 * --------|--------
1178 * SEED_OSBOX | SEED_OSBOX
1179 *
1180 * @param AESx AES instance
1181 * @param mask This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1182 * @retval None
1183 */
ll_aes_set_seed_Osbox(aes_regs_t * AESx,uint32_t mask)1184 __STATIC_INLINE void ll_aes_set_seed_Osbox(aes_regs_t *AESx, uint32_t mask)
1185 {
1186 WRITE_REG(AESx->SEED_OSBOX, mask);
1187 }
1188
1189 /**
1190 * @brief Get sbox output data's mask.
1191 *
1192 * Register|BitsName
1193 * --------|--------
1194 * SEED_OSBOX | SEED_OSBOX
1195 *
1196 * @param AESx AES instance
1197 * @retval Returned value is the output data's mask.
1198 */
ll_aes_get_seed_Osbox(aes_regs_t * AESx)1199 __STATIC_INLINE uint32_t ll_aes_get_seed_Osbox(aes_regs_t *AESx)
1200 {
1201 return (READ_REG(AESx->SEED_OSBOX));
1202 }
1203
1204 /**
1205 * @brief Set AES initialization vector[127:96].
1206 *
1207 * Register|BitsName
1208 * --------|--------
1209 * VECTOR_INIT[0] | VECTOR_INIT
1210 *
1211 * @param AESx AES instance
1212 * @param vector This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1213 * @retval None
1214 */
ll_aes_set_vector_127_96(aes_regs_t * AESx,uint32_t vector)1215 __STATIC_INLINE void ll_aes_set_vector_127_96(aes_regs_t *AESx, uint32_t vector)
1216 {
1217 WRITE_REG(AESx->VECTOR_INIT[0], vector);
1218 }
1219
1220 /**
1221 * @brief Set AES initialization vector[95:64].
1222 *
1223 * Register|BitsName
1224 * --------|--------
1225 * VECTOR_INIT[1] | VECTOR_INIT
1226 *
1227 * @param AESx AES instance
1228 * @param vector This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1229 * @retval None
1230 */
ll_aes_set_vector_95_64(aes_regs_t * AESx,uint32_t vector)1231 __STATIC_INLINE void ll_aes_set_vector_95_64(aes_regs_t *AESx, uint32_t vector)
1232 {
1233 WRITE_REG(AESx->VECTOR_INIT[1], vector);
1234 }
1235
1236 /**
1237 * @brief Set AES initialization vector[63:32].
1238 *
1239 * Register|BitsName
1240 * --------|--------
1241 * VECTOR_INIT[2] | VECTOR_INIT
1242 *
1243 * @param AESx AES instance
1244 * @param vector This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1245 * @retval None
1246 */
ll_aes_set_vector_63_32(aes_regs_t * AESx,uint32_t vector)1247 __STATIC_INLINE void ll_aes_set_vector_63_32(aes_regs_t *AESx, uint32_t vector)
1248 {
1249 WRITE_REG(AESx->VECTOR_INIT[ITEM_2], vector);
1250 }
1251
1252 /**
1253 * @brief Set AES initialization vector[31:0].
1254 *
1255 * Register|BitsName
1256 * --------|--------
1257 * VECTOR_INIT[3] | VECTOR_INIT
1258 *
1259 * @param AESx AES instance
1260 * @param vector This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1261 * @retval None
1262 */
ll_aes_set_vector_31_0(aes_regs_t * AESx,uint32_t vector)1263 __STATIC_INLINE void ll_aes_set_vector_31_0(aes_regs_t *AESx, uint32_t vector)
1264 {
1265 WRITE_REG(AESx->VECTOR_INIT[ITEM_3], vector);
1266 }
1267
1268 /**
1269 * @brief Set AES input data[127:96].
1270 *
1271 * Register|BitsName
1272 * --------|--------
1273 * DATA_IN[0] | DATA_IN
1274 *
1275 * @param AESx AES instance
1276 * @param data This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1277 * @retval None
1278 */
ll_aes_set_data_127_96(aes_regs_t * AESx,uint32_t data)1279 __STATIC_INLINE void ll_aes_set_data_127_96(aes_regs_t *AESx, uint32_t data)
1280 {
1281 WRITE_REG(AESx->DATA_IN[0], data);
1282 }
1283
1284 /**
1285 * @brief Set AES input data[95:64].
1286 *
1287 * Register|BitsName
1288 * --------|--------
1289 * DATA_IN[1] | DATA_IN
1290 *
1291 * @param AESx AES instance
1292 * @param data This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1293 * @retval None
1294 */
ll_aes_set_data_95_64(aes_regs_t * AESx,uint32_t data)1295 __STATIC_INLINE void ll_aes_set_data_95_64(aes_regs_t *AESx, uint32_t data)
1296 {
1297 WRITE_REG(AESx->DATA_IN[1], data);
1298 }
1299
1300 /**
1301 * @brief Set AES input data[63:32].
1302 *
1303 * Register|BitsName
1304 * --------|--------
1305 * DATA_IN[2] | DATA_IN
1306 *
1307 * @param AESx AES instance
1308 * @param data This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1309 * @retval None
1310 */
ll_aes_set_data_63_32(aes_regs_t * AESx,uint32_t data)1311 __STATIC_INLINE void ll_aes_set_data_63_32(aes_regs_t *AESx, uint32_t data)
1312 {
1313 WRITE_REG(AESx->DATA_IN[ITEM_2], data);
1314 }
1315
1316 /**
1317 * @brief Set AES input data[31:0].
1318 *
1319 * Register|BitsName
1320 * --------|--------
1321 * DATA_IN[3] | DATA_IN
1322 *
1323 * @param AESx AES instance
1324 * @param data This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1325 * @retval None
1326 */
ll_aes_set_data_31_0(aes_regs_t * AESx,uint32_t data)1327 __STATIC_INLINE void ll_aes_set_data_31_0(aes_regs_t *AESx, uint32_t data)
1328 {
1329 WRITE_REG(AESx->DATA_IN[ITEM_3], data);
1330 }
1331
1332 /**
1333 * @brief Set AES fetch key port mask.
1334 *
1335 * Register|BitsName
1336 * --------|--------
1337 * KPORT_MASK | KPORT_MASK
1338 *
1339 * @param AESx AES instance
1340 * @param mask This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
1341 * @retval None
1342 */
ll_aes_set_key_port_mask(aes_regs_t * AESx,uint32_t mask)1343 __STATIC_INLINE void ll_aes_set_key_port_mask(aes_regs_t *AESx, uint32_t mask)
1344 {
1345 WRITE_REG(AESx->KPORT_MASK, mask);
1346 }
1347
1348 /** @} */
1349
1350 /** @defgroup AES_LL_EF_Init Initialization and de-initialization functions
1351 * @{
1352 */
1353
1354 /**
1355 * @brief De-initialize AES registers (Registers restored to their default values).
1356 * @param AESx AES Instance
1357 * @retval An error_status_t enumeration value:
1358 * - SUCCESS: AES registers are de-initialized
1359 * - ERROR: AES registers are not de-initialized
1360 */
1361 error_status_t ll_aes_deinit(aes_regs_t *AESx);
1362
1363 /**
1364 * @brief Initialize AES registers according to the specified
1365 * parameters in p_aes_init.
1366 * @param AESx AES Instance
1367 * @param p_aes_init Pointer to a ll_aes_init_t structure that contains the configuration
1368 * information for the specified AES peripheral.
1369 * @retval An error_status_t enumeration value:
1370 * - SUCCESS: AES registers are initialized according to p_aes_init content
1371 * - ERROR: Problem occurred during AES Registers initialization
1372 */
1373 error_status_t ll_aes_init(aes_regs_t *AESx, ll_aes_init_t *p_aes_init);
1374
1375 /**
1376 * @brief Set each field of a @ref ll_aes_init_t type structure to default value.
1377 * @param p_aes_init Pointer to a @ref ll_aes_init_t structure
1378 * whose fields will be set to default values.
1379 * @retval None
1380 */
1381 void ll_aes_struct_init(ll_aes_init_t *p_aes_init);
1382
1383 /** @} */
1384
1385 /** @} */
1386
1387 #endif /* AES */
1388
1389 #ifdef __cplusplus
1390 }
1391 #endif
1392
1393 #endif /* __GR55XX_LL_AES_H__ */
1394
1395 /** @} */
1396
1397 /** @} */
1398
1399 /** @} */
1400