1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F4xx_LL_TIM_H
22 #define __STM32F4xx_LL_TIM_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f4xx.h"
30
31 /** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
36
37 /** @defgroup TIM_LL TIM
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
44 * @{
45 */
46 static const uint8_t OFFSET_TAB_CCMRx[] =
47 {
48 0x00U, /* 0: TIMx_CH1 */
49 0x00U, /* 1: TIMx_CH1N */
50 0x00U, /* 2: TIMx_CH2 */
51 0x00U, /* 3: TIMx_CH2N */
52 0x04U, /* 4: TIMx_CH3 */
53 0x04U, /* 5: TIMx_CH3N */
54 0x04U /* 6: TIMx_CH4 */
55 };
56
57 static const uint8_t SHIFT_TAB_OCxx[] =
58 {
59 0U, /* 0: OC1M, OC1FE, OC1PE */
60 0U, /* 1: - NA */
61 8U, /* 2: OC2M, OC2FE, OC2PE */
62 0U, /* 3: - NA */
63 0U, /* 4: OC3M, OC3FE, OC3PE */
64 0U, /* 5: - NA */
65 8U /* 6: OC4M, OC4FE, OC4PE */
66 };
67
68 static const uint8_t SHIFT_TAB_ICxx[] =
69 {
70 0U, /* 0: CC1S, IC1PSC, IC1F */
71 0U, /* 1: - NA */
72 8U, /* 2: CC2S, IC2PSC, IC2F */
73 0U, /* 3: - NA */
74 0U, /* 4: CC3S, IC3PSC, IC3F */
75 0U, /* 5: - NA */
76 8U /* 6: CC4S, IC4PSC, IC4F */
77 };
78
79 static const uint8_t SHIFT_TAB_CCxP[] =
80 {
81 0U, /* 0: CC1P */
82 2U, /* 1: CC1NP */
83 4U, /* 2: CC2P */
84 6U, /* 3: CC2NP */
85 8U, /* 4: CC3P */
86 10U, /* 5: CC3NP */
87 12U /* 6: CC4P */
88 };
89
90 static const uint8_t SHIFT_TAB_OISx[] =
91 {
92 0U, /* 0: OIS1 */
93 1U, /* 1: OIS1N */
94 2U, /* 2: OIS2 */
95 3U, /* 3: OIS2N */
96 4U, /* 4: OIS3 */
97 5U, /* 5: OIS3N */
98 6U /* 6: OIS4 */
99 };
100 /**
101 * @}
102 */
103
104 /* Private constants ---------------------------------------------------------*/
105 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
106 * @{
107 */
108
109
110 /* Remap mask definitions */
111 #define TIMx_OR_RMP_SHIFT 16U
112 #define TIMx_OR_RMP_MASK 0x0000FFFFU
113 #define TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
114 #define TIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
115 #define TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
116
117 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
118 #define DT_DELAY_1 ((uint8_t)0x7F)
119 #define DT_DELAY_2 ((uint8_t)0x3F)
120 #define DT_DELAY_3 ((uint8_t)0x1F)
121 #define DT_DELAY_4 ((uint8_t)0x1F)
122
123 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
124 #define DT_RANGE_1 ((uint8_t)0x00)
125 #define DT_RANGE_2 ((uint8_t)0x80)
126 #define DT_RANGE_3 ((uint8_t)0xC0)
127 #define DT_RANGE_4 ((uint8_t)0xE0)
128
129
130 /**
131 * @}
132 */
133
134 /* Private macros ------------------------------------------------------------*/
135 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
136 * @{
137 */
138 /** @brief Convert channel id into channel index.
139 * @param __CHANNEL__ This parameter can be one of the following values:
140 * @arg @ref LL_TIM_CHANNEL_CH1
141 * @arg @ref LL_TIM_CHANNEL_CH1N
142 * @arg @ref LL_TIM_CHANNEL_CH2
143 * @arg @ref LL_TIM_CHANNEL_CH2N
144 * @arg @ref LL_TIM_CHANNEL_CH3
145 * @arg @ref LL_TIM_CHANNEL_CH3N
146 * @arg @ref LL_TIM_CHANNEL_CH4
147 * @retval none
148 */
149 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
150 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
151 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
152 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
153 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
154 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
155 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
156
157 /** @brief Calculate the deadtime sampling period(in ps).
158 * @param __TIMCLK__ timer input clock frequency (in Hz).
159 * @param __CKD__ This parameter can be one of the following values:
160 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
161 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
162 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
163 * @retval none
164 */
165 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
166 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
167 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
168 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
169 /**
170 * @}
171 */
172
173
174 /* Exported types ------------------------------------------------------------*/
175 #if defined(USE_FULL_LL_DRIVER)
176 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
177 * @{
178 */
179
180 /**
181 * @brief TIM Time Base configuration structure definition.
182 */
183 typedef struct
184 {
185 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
186 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
187
188 This feature can be modified afterwards using unitary function
189 @ref LL_TIM_SetPrescaler().*/
190
191 uint32_t CounterMode; /*!< Specifies the counter mode.
192 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
193
194 This feature can be modified afterwards using unitary function
195 @ref LL_TIM_SetCounterMode().*/
196
197 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
198 Auto-Reload Register at the next update event.
199 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
200 Some timer instances may support 32 bits counters. In that case this parameter must
201 be a number between 0x0000 and 0xFFFFFFFF.
202
203 This feature can be modified afterwards using unitary function
204 @ref LL_TIM_SetAutoReload().*/
205
206 uint32_t ClockDivision; /*!< Specifies the clock division.
207 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
208
209 This feature can be modified afterwards using unitary function
210 @ref LL_TIM_SetClockDivision().*/
211
212 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
213 reaches zero, an update event is generated and counting restarts
214 from the RCR value (N).
215 This means in PWM mode that (N+1) corresponds to:
216 - the number of PWM periods in edge-aligned mode
217 - the number of half PWM period in center-aligned mode
218 GP timers: this parameter must be a number between Min_Data = 0x00 and
219 Max_Data = 0xFF.
220 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
221 Max_Data = 0xFFFF.
222
223 This feature can be modified afterwards using unitary function
224 @ref LL_TIM_SetRepetitionCounter().*/
225 } LL_TIM_InitTypeDef;
226
227 /**
228 * @brief TIM Output Compare configuration structure definition.
229 */
230 typedef struct
231 {
232 uint32_t OCMode; /*!< Specifies the output mode.
233 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
234
235 This feature can be modified afterwards using unitary function
236 @ref LL_TIM_OC_SetMode().*/
237
238 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
239 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
240
241 This feature can be modified afterwards using unitary functions
242 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
243
244 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
245 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
246
247 This feature can be modified afterwards using unitary functions
248 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
249
250 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
251 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
252
253 This feature can be modified afterwards using unitary function
254 LL_TIM_OC_SetCompareCHx (x=1..6).*/
255
256 uint32_t OCPolarity; /*!< Specifies the output polarity.
257 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
258
259 This feature can be modified afterwards using unitary function
260 @ref LL_TIM_OC_SetPolarity().*/
261
262 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
263 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
264
265 This feature can be modified afterwards using unitary function
266 @ref LL_TIM_OC_SetPolarity().*/
267
268
269 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
270 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
271
272 This feature can be modified afterwards using unitary function
273 @ref LL_TIM_OC_SetIdleState().*/
274
275 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
276 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
277
278 This feature can be modified afterwards using unitary function
279 @ref LL_TIM_OC_SetIdleState().*/
280 } LL_TIM_OC_InitTypeDef;
281
282 /**
283 * @brief TIM Input Capture configuration structure definition.
284 */
285
286 typedef struct
287 {
288
289 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
290 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
291
292 This feature can be modified afterwards using unitary function
293 @ref LL_TIM_IC_SetPolarity().*/
294
295 uint32_t ICActiveInput; /*!< Specifies the input.
296 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
297
298 This feature can be modified afterwards using unitary function
299 @ref LL_TIM_IC_SetActiveInput().*/
300
301 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
302 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
303
304 This feature can be modified afterwards using unitary function
305 @ref LL_TIM_IC_SetPrescaler().*/
306
307 uint32_t ICFilter; /*!< Specifies the input capture filter.
308 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
309
310 This feature can be modified afterwards using unitary function
311 @ref LL_TIM_IC_SetFilter().*/
312 } LL_TIM_IC_InitTypeDef;
313
314
315 /**
316 * @brief TIM Encoder interface configuration structure definition.
317 */
318 typedef struct
319 {
320 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
321 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
322
323 This feature can be modified afterwards using unitary function
324 @ref LL_TIM_SetEncoderMode().*/
325
326 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
327 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
328
329 This feature can be modified afterwards using unitary function
330 @ref LL_TIM_IC_SetPolarity().*/
331
332 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
333 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
334
335 This feature can be modified afterwards using unitary function
336 @ref LL_TIM_IC_SetActiveInput().*/
337
338 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
339 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
340
341 This feature can be modified afterwards using unitary function
342 @ref LL_TIM_IC_SetPrescaler().*/
343
344 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
345 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
346
347 This feature can be modified afterwards using unitary function
348 @ref LL_TIM_IC_SetFilter().*/
349
350 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
351 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
352
353 This feature can be modified afterwards using unitary function
354 @ref LL_TIM_IC_SetPolarity().*/
355
356 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
357 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
358
359 This feature can be modified afterwards using unitary function
360 @ref LL_TIM_IC_SetActiveInput().*/
361
362 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
363 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
364
365 This feature can be modified afterwards using unitary function
366 @ref LL_TIM_IC_SetPrescaler().*/
367
368 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
369 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
370
371 This feature can be modified afterwards using unitary function
372 @ref LL_TIM_IC_SetFilter().*/
373
374 } LL_TIM_ENCODER_InitTypeDef;
375
376 /**
377 * @brief TIM Hall sensor interface configuration structure definition.
378 */
379 typedef struct
380 {
381
382 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
383 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
384
385 This feature can be modified afterwards using unitary function
386 @ref LL_TIM_IC_SetPolarity().*/
387
388 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
389 Prescaler must be set to get a maximum counter period longer than the
390 time interval between 2 consecutive changes on the Hall inputs.
391 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
392
393 This feature can be modified afterwards using unitary function
394 @ref LL_TIM_IC_SetPrescaler().*/
395
396 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
397 This parameter can be a value of
398 @ref TIM_LL_EC_IC_FILTER.
399
400 This feature can be modified afterwards using unitary function
401 @ref LL_TIM_IC_SetFilter().*/
402
403 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
404 A positive pulse (TRGO event) is generated with a programmable delay every time
405 a change occurs on the Hall inputs.
406 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
407
408 This feature can be modified afterwards using unitary function
409 @ref LL_TIM_OC_SetCompareCH2().*/
410 } LL_TIM_HALLSENSOR_InitTypeDef;
411
412 /**
413 * @brief BDTR (Break and Dead Time) structure definition
414 */
415 typedef struct
416 {
417 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
418 This parameter can be a value of @ref TIM_LL_EC_OSSR
419
420 This feature can be modified afterwards using unitary function
421 @ref LL_TIM_SetOffStates()
422
423 @note This bit-field cannot be modified as long as LOCK level 2 has been
424 programmed. */
425
426 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
427 This parameter can be a value of @ref TIM_LL_EC_OSSI
428
429 This feature can be modified afterwards using unitary function
430 @ref LL_TIM_SetOffStates()
431
432 @note This bit-field cannot be modified as long as LOCK level 2 has been
433 programmed. */
434
435 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
436 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
437
438 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
439 register has been written, their content is frozen until the next reset.*/
440
441 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
442 switching-on of the outputs.
443 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
444
445 This feature can be modified afterwards using unitary function
446 @ref LL_TIM_OC_SetDeadTime()
447
448 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
449 programmed. */
450
451 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
452 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
453
454 This feature can be modified afterwards using unitary functions
455 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
456
457 @note This bit-field can not be modified as long as LOCK level 1 has been
458 programmed. */
459
460 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
461 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
462
463 This feature can be modified afterwards using unitary function
464 @ref LL_TIM_ConfigBRK()
465
466 @note This bit-field can not be modified as long as LOCK level 1 has been
467 programmed. */
468
469 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
470 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
471
472 This feature can be modified afterwards using unitary functions
473 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
474
475 @note This bit-field can not be modified as long as LOCK level 1 has been
476 programmed. */
477 } LL_TIM_BDTR_InitTypeDef;
478
479 /**
480 * @}
481 */
482 #endif /* USE_FULL_LL_DRIVER */
483
484 /* Exported constants --------------------------------------------------------*/
485 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
486 * @{
487 */
488
489 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
490 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
491 * @{
492 */
493 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
494 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
495 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
496 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
497 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
498 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
499 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
500 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
501 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
502 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
503 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
504 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
505 /**
506 * @}
507 */
508
509 #if defined(USE_FULL_LL_DRIVER)
510 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
511 * @{
512 */
513 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
514 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
515 /**
516 * @}
517 */
518
519 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
520 * @{
521 */
522 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
523 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
524 /**
525 * @}
526 */
527 #endif /* USE_FULL_LL_DRIVER */
528
529 /** @defgroup TIM_LL_EC_IT IT Defines
530 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
531 * @{
532 */
533 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
534 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
535 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
536 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
537 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
538 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
539 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
540 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
541 /**
542 * @}
543 */
544
545 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
546 * @{
547 */
548 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
549 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
550 /**
551 * @}
552 */
553
554 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
555 * @{
556 */
557 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
558 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
559 /**
560 * @}
561 */
562
563 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
564 * @{
565 */
566 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
567 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
568 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
569 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
570 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
571 /**
572 * @}
573 */
574
575 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
576 * @{
577 */
578 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
579 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
580 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
581 /**
582 * @}
583 */
584
585 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
586 * @{
587 */
588 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
589 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
590 /**
591 * @}
592 */
593
594 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
595 * @{
596 */
597 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
598 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
599 /**
600 * @}
601 */
602
603 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
604 * @{
605 */
606 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
607 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
608 /**
609 * @}
610 */
611
612 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
613 * @{
614 */
615 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
616 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
617 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
618 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
619 /**
620 * @}
621 */
622
623 /** @defgroup TIM_LL_EC_CHANNEL Channel
624 * @{
625 */
626 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
627 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
628 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
629 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
630 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
631 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
632 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
633 /**
634 * @}
635 */
636
637 #if defined(USE_FULL_LL_DRIVER)
638 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
639 * @{
640 */
641 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
642 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
643 /**
644 * @}
645 */
646 #endif /* USE_FULL_LL_DRIVER */
647
648 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
649 * @{
650 */
651 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
652 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
653 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
654 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
655 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
656 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
657 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
658 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
659 /**
660 * @}
661 */
662
663 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
664 * @{
665 */
666 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
667 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
668 /**
669 * @}
670 */
671
672 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
673 * @{
674 */
675 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
676 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
677 /**
678 * @}
679 */
680
681
682 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
683 * @{
684 */
685 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
686 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
687 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
688 /**
689 * @}
690 */
691
692 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
693 * @{
694 */
695 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
696 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
697 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
698 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
699 /**
700 * @}
701 */
702
703 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
704 * @{
705 */
706 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
707 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
708 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
709 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
710 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
711 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
712 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
713 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
714 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
715 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
716 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
717 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
718 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
719 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
720 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
721 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
722 /**
723 * @}
724 */
725
726 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
727 * @{
728 */
729 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
730 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
731 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
732 /**
733 * @}
734 */
735
736 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
737 * @{
738 */
739 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
740 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
741 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
742 /**
743 * @}
744 */
745
746 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
747 * @{
748 */
749 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
750 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
751 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
752 /**
753 * @}
754 */
755
756 /** @defgroup TIM_LL_EC_TRGO Trigger Output
757 * @{
758 */
759 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
760 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
761 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
762 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
763 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
764 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
765 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
766 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
767 /**
768 * @}
769 */
770
771
772 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
773 * @{
774 */
775 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
776 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
777 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
778 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
779 /**
780 * @}
781 */
782
783 /** @defgroup TIM_LL_EC_TS Trigger Selection
784 * @{
785 */
786 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
787 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
788 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
789 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
790 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
791 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
792 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
793 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
794 /**
795 * @}
796 */
797
798 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
799 * @{
800 */
801 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
802 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
803 /**
804 * @}
805 */
806
807 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
808 * @{
809 */
810 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
811 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
812 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
813 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
814 /**
815 * @}
816 */
817
818 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
819 * @{
820 */
821 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
822 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
823 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
824 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
825 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
826 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
827 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
828 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
829 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
830 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
831 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
832 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
833 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
834 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
835 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
836 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
837 /**
838 * @}
839 */
840
841
842 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
843 * @{
844 */
845 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
846 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
847 /**
848 * @}
849 */
850
851
852
853
854 /** @defgroup TIM_LL_EC_OSSI OSSI
855 * @{
856 */
857 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
858 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
859 /**
860 * @}
861 */
862
863 /** @defgroup TIM_LL_EC_OSSR OSSR
864 * @{
865 */
866 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
867 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
868 /**
869 * @}
870 */
871
872
873 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
874 * @{
875 */
876 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
877 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
878 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
879 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
880 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
881 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
882 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
883 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
884 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
885 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
886 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
887 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
888 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
889 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
890 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
891 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
892 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
893 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
894 /**
895 * @}
896 */
897
898 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
899 * @{
900 */
901 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
902 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
903 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
904 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
905 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
906 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
907 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
908 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
909 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
910 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
911 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
912 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
913 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
914 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
915 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
916 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
917 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
918 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
919 /**
920 * @}
921 */
922
923
924 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8
925 * @{
926 */
927 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */
928 #define LL_TIM_TIM2_ITR1_RMP_ETH_PTP (TIM_OR_ITR1_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to ETH_PTP */
929 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM_OR_ITR1_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */
930 #define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM_OR_ITR1_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_HS SOF */
931 /**
932 * @}
933 */
934
935 /** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap
936 * @{
937 */
938 #define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /*!< TIM5 channel 4 is connected to GPIO */
939 #define LL_TIM_TIM5_TI4_RMP_LSI (TIM_OR_TI4_RMP_0 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSI internal clock */
940 #define LL_TIM_TIM5_TI4_RMP_LSE (TIM_OR_TI4_RMP_1 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSE */
941 #define LL_TIM_TIM5_TI4_RMP_RTC (TIM_OR_TI4_RMP | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to RTC wakeup interrupt */
942 /**
943 * @}
944 */
945
946 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap
947 * @{
948 */
949 #define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /*!< TIM11 channel 1 is connected to GPIO */
950 #if defined(SPDIFRX)
951 #define LL_TIM_TIM11_TI1_RMP_SPDIFRX (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to SPDIFRX */
952
953 /* Legacy define */
954 #define LL_TIM_TIM11_TI1_RMP_GPIO1 LL_TIM_TIM11_TI1_RMP_SPDIFRX /*!< Legacy define for LL_TIM_TIM11_TI1_RMP_SPDIFRX */
955
956 #else
957 #define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
958 #endif /* SPDIFRX */
959 #define LL_TIM_TIM11_TI1_RMP_GPIO2 (TIM_OR_TI1_RMP | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
960 #define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to HSE_RTC */
961 /**
962 * @}
963 */
964 #if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP)
965
966 #define LL_TIM_LPTIM_REMAP_MASK 0x10000000U
967
968 #define LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO LL_TIM_LPTIM_REMAP_MASK /*!< TIM9_ITR1 is connected to TIM3 TRGO */
969 #define LL_TIM_TIM9_ITR1_RMP_LPTIM (LL_TIM_LPTIM_REMAP_MASK | LPTIM_OR_TIM9_ITR1_RMP) /*!< TIM9_ITR1 is connected to LPTIM1 output */
970
971 #define LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO LL_TIM_LPTIM_REMAP_MASK /*!< TIM5_ITR1 is connected to TIM3 TRGO */
972 #define LL_TIM_TIM5_ITR1_RMP_LPTIM (LL_TIM_LPTIM_REMAP_MASK | LPTIM_OR_TIM5_ITR1_RMP) /*!< TIM5_ITR1 is connected to LPTIM1 output */
973
974 #define LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO LL_TIM_LPTIM_REMAP_MASK /*!< TIM1_ITR2 is connected to TIM3 TRGO */
975 #define LL_TIM_TIM1_ITR2_RMP_LPTIM (LL_TIM_LPTIM_REMAP_MASK | LPTIM_OR_TIM1_ITR2_RMP) /*!< TIM1_ITR2 is connected to LPTIM1 output */
976
977 #endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */
978
979 /**
980 * @}
981 */
982
983 /* Exported macro ------------------------------------------------------------*/
984 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
985 * @{
986 */
987
988 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
989 * @{
990 */
991 /**
992 * @brief Write a value in TIM register.
993 * @param __INSTANCE__ TIM Instance
994 * @param __REG__ Register to be written
995 * @param __VALUE__ Value to be written in the register
996 * @retval None
997 */
998 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
999
1000 /**
1001 * @brief Read a value in TIM register.
1002 * @param __INSTANCE__ TIM Instance
1003 * @param __REG__ Register to be read
1004 * @retval Register value
1005 */
1006 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1007 /**
1008 * @}
1009 */
1010
1011 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
1012 * @{
1013 */
1014
1015 /**
1016 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1017 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1018 * @param __TIMCLK__ timer input clock frequency (in Hz)
1019 * @param __CKD__ This parameter can be one of the following values:
1020 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1021 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1022 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1023 * @param __DT__ deadtime duration (in ns)
1024 * @retval DTG[0:7]
1025 */
1026 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1027 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1028 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1029 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1030 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1031 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1032 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1033 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1034 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1035 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1036 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1037 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1038 0U)
1039
1040 /**
1041 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1042 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1043 * @param __TIMCLK__ timer input clock frequency (in Hz)
1044 * @param __CNTCLK__ counter clock frequency (in Hz)
1045 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1046 */
1047 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1048 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
1049
1050 /**
1051 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1052 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1053 * @param __TIMCLK__ timer input clock frequency (in Hz)
1054 * @param __PSC__ prescaler
1055 * @param __FREQ__ output signal frequency (in Hz)
1056 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1057 */
1058 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1059 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1060
1061 /**
1062 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1063 * active/inactive delay.
1064 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1065 * @param __TIMCLK__ timer input clock frequency (in Hz)
1066 * @param __PSC__ prescaler
1067 * @param __DELAY__ timer output compare active/inactive delay (in us)
1068 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1069 */
1070 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1071 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1072 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1073
1074 /**
1075 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1076 * (when the timer operates in one pulse mode).
1077 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1078 * @param __TIMCLK__ timer input clock frequency (in Hz)
1079 * @param __PSC__ prescaler
1080 * @param __DELAY__ timer output compare active/inactive delay (in us)
1081 * @param __PULSE__ pulse duration (in us)
1082 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1083 */
1084 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1085 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1086 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1087
1088 /**
1089 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1090 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1091 * @param __ICPSC__ This parameter can be one of the following values:
1092 * @arg @ref LL_TIM_ICPSC_DIV1
1093 * @arg @ref LL_TIM_ICPSC_DIV2
1094 * @arg @ref LL_TIM_ICPSC_DIV4
1095 * @arg @ref LL_TIM_ICPSC_DIV8
1096 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1097 */
1098 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1099 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1100
1101
1102 /**
1103 * @}
1104 */
1105
1106
1107 /**
1108 * @}
1109 */
1110
1111 /* Exported functions --------------------------------------------------------*/
1112 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1113 * @{
1114 */
1115
1116 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1117 * @{
1118 */
1119 /**
1120 * @brief Enable timer counter.
1121 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1122 * @param TIMx Timer instance
1123 * @retval None
1124 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1125 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1126 {
1127 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1128 }
1129
1130 /**
1131 * @brief Disable timer counter.
1132 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1133 * @param TIMx Timer instance
1134 * @retval None
1135 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1136 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1137 {
1138 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1139 }
1140
1141 /**
1142 * @brief Indicates whether the timer counter is enabled.
1143 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1144 * @param TIMx Timer instance
1145 * @retval State of bit (1 or 0).
1146 */
LL_TIM_IsEnabledCounter(TIM_TypeDef * TIMx)1147 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
1148 {
1149 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1150 }
1151
1152 /**
1153 * @brief Enable update event generation.
1154 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1155 * @param TIMx Timer instance
1156 * @retval None
1157 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1158 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1159 {
1160 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1161 }
1162
1163 /**
1164 * @brief Disable update event generation.
1165 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1166 * @param TIMx Timer instance
1167 * @retval None
1168 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1169 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1170 {
1171 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1172 }
1173
1174 /**
1175 * @brief Indicates whether update event generation is enabled.
1176 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1177 * @param TIMx Timer instance
1178 * @retval Inverted state of bit (0 or 1).
1179 */
LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef * TIMx)1180 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
1181 {
1182 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1183 }
1184
1185 /**
1186 * @brief Set update event source
1187 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1188 * generate an update interrupt or DMA request if enabled:
1189 * - Counter overflow/underflow
1190 * - Setting the UG bit
1191 * - Update generation through the slave mode controller
1192 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1193 * overflow/underflow generates an update interrupt or DMA request if enabled.
1194 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1195 * @param TIMx Timer instance
1196 * @param UpdateSource This parameter can be one of the following values:
1197 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1198 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1199 * @retval None
1200 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1201 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1202 {
1203 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1204 }
1205
1206 /**
1207 * @brief Get actual event update source
1208 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1209 * @param TIMx Timer instance
1210 * @retval Returned value can be one of the following values:
1211 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1212 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1213 */
LL_TIM_GetUpdateSource(TIM_TypeDef * TIMx)1214 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
1215 {
1216 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1217 }
1218
1219 /**
1220 * @brief Set one pulse mode (one shot v.s. repetitive).
1221 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1222 * @param TIMx Timer instance
1223 * @param OnePulseMode This parameter can be one of the following values:
1224 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1225 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1226 * @retval None
1227 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1228 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1229 {
1230 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1231 }
1232
1233 /**
1234 * @brief Get actual one pulse mode.
1235 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1236 * @param TIMx Timer instance
1237 * @retval Returned value can be one of the following values:
1238 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1239 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1240 */
LL_TIM_GetOnePulseMode(TIM_TypeDef * TIMx)1241 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
1242 {
1243 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1244 }
1245
1246 /**
1247 * @brief Set the timer counter counting mode.
1248 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1249 * check whether or not the counter mode selection feature is supported
1250 * by a timer instance.
1251 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1252 * requires a timer reset to avoid unexpected direction
1253 * due to DIR bit readonly in center aligned mode.
1254 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1255 * CR1 CMS LL_TIM_SetCounterMode
1256 * @param TIMx Timer instance
1257 * @param CounterMode This parameter can be one of the following values:
1258 * @arg @ref LL_TIM_COUNTERMODE_UP
1259 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1260 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1261 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1262 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1263 * @retval None
1264 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1265 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1266 {
1267 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1268 }
1269
1270 /**
1271 * @brief Get actual counter mode.
1272 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1273 * check whether or not the counter mode selection feature is supported
1274 * by a timer instance.
1275 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1276 * CR1 CMS LL_TIM_GetCounterMode
1277 * @param TIMx Timer instance
1278 * @retval Returned value can be one of the following values:
1279 * @arg @ref LL_TIM_COUNTERMODE_UP
1280 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1281 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1282 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1283 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1284 */
LL_TIM_GetCounterMode(TIM_TypeDef * TIMx)1285 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
1286 {
1287 uint32_t counter_mode;
1288
1289 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1290
1291 if (counter_mode == 0U)
1292 {
1293 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1294 }
1295
1296 return counter_mode;
1297 }
1298
1299 /**
1300 * @brief Enable auto-reload (ARR) preload.
1301 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1302 * @param TIMx Timer instance
1303 * @retval None
1304 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1305 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1306 {
1307 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1308 }
1309
1310 /**
1311 * @brief Disable auto-reload (ARR) preload.
1312 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1313 * @param TIMx Timer instance
1314 * @retval None
1315 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1316 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1317 {
1318 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1319 }
1320
1321 /**
1322 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1323 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1324 * @param TIMx Timer instance
1325 * @retval State of bit (1 or 0).
1326 */
LL_TIM_IsEnabledARRPreload(TIM_TypeDef * TIMx)1327 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
1328 {
1329 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1330 }
1331
1332 /**
1333 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1334 * (when supported) and the digital filters.
1335 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1336 * whether or not the clock division feature is supported by the timer
1337 * instance.
1338 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1339 * @param TIMx Timer instance
1340 * @param ClockDivision This parameter can be one of the following values:
1341 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1342 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1343 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1344 * @retval None
1345 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1346 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1347 {
1348 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1349 }
1350
1351 /**
1352 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1353 * generators (when supported) and the digital filters.
1354 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1355 * whether or not the clock division feature is supported by the timer
1356 * instance.
1357 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1358 * @param TIMx Timer instance
1359 * @retval Returned value can be one of the following values:
1360 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1361 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1362 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1363 */
LL_TIM_GetClockDivision(TIM_TypeDef * TIMx)1364 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
1365 {
1366 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1367 }
1368
1369 /**
1370 * @brief Set the counter value.
1371 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1372 * whether or not a timer instance supports a 32 bits counter.
1373 * @rmtoll CNT CNT LL_TIM_SetCounter
1374 * @param TIMx Timer instance
1375 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1376 * @retval None
1377 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1378 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1379 {
1380 WRITE_REG(TIMx->CNT, Counter);
1381 }
1382
1383 /**
1384 * @brief Get the counter value.
1385 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1386 * whether or not a timer instance supports a 32 bits counter.
1387 * @rmtoll CNT CNT LL_TIM_GetCounter
1388 * @param TIMx Timer instance
1389 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1390 */
LL_TIM_GetCounter(TIM_TypeDef * TIMx)1391 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
1392 {
1393 return (uint32_t)(READ_REG(TIMx->CNT));
1394 }
1395
1396 /**
1397 * @brief Get the current direction of the counter
1398 * @rmtoll CR1 DIR LL_TIM_GetDirection
1399 * @param TIMx Timer instance
1400 * @retval Returned value can be one of the following values:
1401 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1402 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1403 */
LL_TIM_GetDirection(TIM_TypeDef * TIMx)1404 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
1405 {
1406 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1407 }
1408
1409 /**
1410 * @brief Set the prescaler value.
1411 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1412 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1413 * prescaler ratio is taken into account at the next update event.
1414 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1415 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1416 * @param TIMx Timer instance
1417 * @param Prescaler between Min_Data=0 and Max_Data=65535
1418 * @retval None
1419 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1420 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1421 {
1422 WRITE_REG(TIMx->PSC, Prescaler);
1423 }
1424
1425 /**
1426 * @brief Get the prescaler value.
1427 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1428 * @param TIMx Timer instance
1429 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1430 */
LL_TIM_GetPrescaler(TIM_TypeDef * TIMx)1431 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
1432 {
1433 return (uint32_t)(READ_REG(TIMx->PSC));
1434 }
1435
1436 /**
1437 * @brief Set the auto-reload value.
1438 * @note The counter is blocked while the auto-reload value is null.
1439 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1440 * whether or not a timer instance supports a 32 bits counter.
1441 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1442 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1443 * @param TIMx Timer instance
1444 * @param AutoReload between Min_Data=0 and Max_Data=65535
1445 * @retval None
1446 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1447 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1448 {
1449 WRITE_REG(TIMx->ARR, AutoReload);
1450 }
1451
1452 /**
1453 * @brief Get the auto-reload value.
1454 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1455 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1456 * whether or not a timer instance supports a 32 bits counter.
1457 * @param TIMx Timer instance
1458 * @retval Auto-reload value
1459 */
LL_TIM_GetAutoReload(TIM_TypeDef * TIMx)1460 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
1461 {
1462 return (uint32_t)(READ_REG(TIMx->ARR));
1463 }
1464
1465 /**
1466 * @brief Set the repetition counter value.
1467 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1468 * whether or not a timer instance supports a repetition counter.
1469 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1470 * @param TIMx Timer instance
1471 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1472 * @retval None
1473 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1474 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1475 {
1476 WRITE_REG(TIMx->RCR, RepetitionCounter);
1477 }
1478
1479 /**
1480 * @brief Get the repetition counter value.
1481 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1482 * whether or not a timer instance supports a repetition counter.
1483 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1484 * @param TIMx Timer instance
1485 * @retval Repetition counter value
1486 */
LL_TIM_GetRepetitionCounter(TIM_TypeDef * TIMx)1487 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
1488 {
1489 return (uint32_t)(READ_REG(TIMx->RCR));
1490 }
1491
1492 /**
1493 * @}
1494 */
1495
1496 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1497 * @{
1498 */
1499 /**
1500 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1501 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1502 * they are updated only when a commutation event (COM) occurs.
1503 * @note Only on channels that have a complementary output.
1504 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1505 * whether or not a timer instance is able to generate a commutation event.
1506 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1507 * @param TIMx Timer instance
1508 * @retval None
1509 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1510 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1511 {
1512 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1513 }
1514
1515 /**
1516 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1517 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1518 * whether or not a timer instance is able to generate a commutation event.
1519 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1520 * @param TIMx Timer instance
1521 * @retval None
1522 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1523 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1524 {
1525 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1526 }
1527
1528 /**
1529 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1530 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1531 * whether or not a timer instance is able to generate a commutation event.
1532 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1533 * @param TIMx Timer instance
1534 * @param CCUpdateSource This parameter can be one of the following values:
1535 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1536 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1537 * @retval None
1538 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1539 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1540 {
1541 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1542 }
1543
1544 /**
1545 * @brief Set the trigger of the capture/compare DMA request.
1546 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1547 * @param TIMx Timer instance
1548 * @param DMAReqTrigger This parameter can be one of the following values:
1549 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1550 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1551 * @retval None
1552 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1553 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1554 {
1555 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1556 }
1557
1558 /**
1559 * @brief Get actual trigger of the capture/compare DMA request.
1560 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1561 * @param TIMx Timer instance
1562 * @retval Returned value can be one of the following values:
1563 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1564 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1565 */
LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef * TIMx)1566 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
1567 {
1568 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1569 }
1570
1571 /**
1572 * @brief Set the lock level to freeze the
1573 * configuration of several capture/compare parameters.
1574 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1575 * the lock mechanism is supported by a timer instance.
1576 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1577 * @param TIMx Timer instance
1578 * @param LockLevel This parameter can be one of the following values:
1579 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1580 * @arg @ref LL_TIM_LOCKLEVEL_1
1581 * @arg @ref LL_TIM_LOCKLEVEL_2
1582 * @arg @ref LL_TIM_LOCKLEVEL_3
1583 * @retval None
1584 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1585 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1586 {
1587 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1588 }
1589
1590 /**
1591 * @brief Enable capture/compare channels.
1592 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1593 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1594 * CCER CC2E LL_TIM_CC_EnableChannel\n
1595 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1596 * CCER CC3E LL_TIM_CC_EnableChannel\n
1597 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1598 * CCER CC4E LL_TIM_CC_EnableChannel
1599 * @param TIMx Timer instance
1600 * @param Channels This parameter can be a combination of the following values:
1601 * @arg @ref LL_TIM_CHANNEL_CH1
1602 * @arg @ref LL_TIM_CHANNEL_CH1N
1603 * @arg @ref LL_TIM_CHANNEL_CH2
1604 * @arg @ref LL_TIM_CHANNEL_CH2N
1605 * @arg @ref LL_TIM_CHANNEL_CH3
1606 * @arg @ref LL_TIM_CHANNEL_CH3N
1607 * @arg @ref LL_TIM_CHANNEL_CH4
1608 * @retval None
1609 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1610 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1611 {
1612 SET_BIT(TIMx->CCER, Channels);
1613 }
1614
1615 /**
1616 * @brief Disable capture/compare channels.
1617 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1618 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1619 * CCER CC2E LL_TIM_CC_DisableChannel\n
1620 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1621 * CCER CC3E LL_TIM_CC_DisableChannel\n
1622 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1623 * CCER CC4E LL_TIM_CC_DisableChannel
1624 * @param TIMx Timer instance
1625 * @param Channels This parameter can be a combination of the following values:
1626 * @arg @ref LL_TIM_CHANNEL_CH1
1627 * @arg @ref LL_TIM_CHANNEL_CH1N
1628 * @arg @ref LL_TIM_CHANNEL_CH2
1629 * @arg @ref LL_TIM_CHANNEL_CH2N
1630 * @arg @ref LL_TIM_CHANNEL_CH3
1631 * @arg @ref LL_TIM_CHANNEL_CH3N
1632 * @arg @ref LL_TIM_CHANNEL_CH4
1633 * @retval None
1634 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1635 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1636 {
1637 CLEAR_BIT(TIMx->CCER, Channels);
1638 }
1639
1640 /**
1641 * @brief Indicate whether channel(s) is(are) enabled.
1642 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1643 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1644 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1645 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1646 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1647 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1648 * CCER CC4E LL_TIM_CC_IsEnabledChannel
1649 * @param TIMx Timer instance
1650 * @param Channels This parameter can be a combination of the following values:
1651 * @arg @ref LL_TIM_CHANNEL_CH1
1652 * @arg @ref LL_TIM_CHANNEL_CH1N
1653 * @arg @ref LL_TIM_CHANNEL_CH2
1654 * @arg @ref LL_TIM_CHANNEL_CH2N
1655 * @arg @ref LL_TIM_CHANNEL_CH3
1656 * @arg @ref LL_TIM_CHANNEL_CH3N
1657 * @arg @ref LL_TIM_CHANNEL_CH4
1658 * @retval State of bit (1 or 0).
1659 */
LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx,uint32_t Channels)1660 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1661 {
1662 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1663 }
1664
1665 /**
1666 * @}
1667 */
1668
1669 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1670 * @{
1671 */
1672 /**
1673 * @brief Configure an output channel.
1674 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1675 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1676 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1677 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1678 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1679 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1680 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1681 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1682 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
1683 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
1684 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
1685 * CR2 OIS4 LL_TIM_OC_ConfigOutput
1686 * @param TIMx Timer instance
1687 * @param Channel This parameter can be one of the following values:
1688 * @arg @ref LL_TIM_CHANNEL_CH1
1689 * @arg @ref LL_TIM_CHANNEL_CH2
1690 * @arg @ref LL_TIM_CHANNEL_CH3
1691 * @arg @ref LL_TIM_CHANNEL_CH4
1692 * @param Configuration This parameter must be a combination of all the following values:
1693 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1694 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
1695 * @retval None
1696 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)1697 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1698 {
1699 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1700 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1701 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
1702 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
1703 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
1704 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
1705 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
1706 }
1707
1708 /**
1709 * @brief Define the behavior of the output reference signal OCxREF from which
1710 * OCx and OCxN (when relevant) are derived.
1711 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
1712 * CCMR1 OC2M LL_TIM_OC_SetMode\n
1713 * CCMR2 OC3M LL_TIM_OC_SetMode\n
1714 * CCMR2 OC4M LL_TIM_OC_SetMode
1715 * @param TIMx Timer instance
1716 * @param Channel This parameter can be one of the following values:
1717 * @arg @ref LL_TIM_CHANNEL_CH1
1718 * @arg @ref LL_TIM_CHANNEL_CH2
1719 * @arg @ref LL_TIM_CHANNEL_CH3
1720 * @arg @ref LL_TIM_CHANNEL_CH4
1721 * @param Mode This parameter can be one of the following values:
1722 * @arg @ref LL_TIM_OCMODE_FROZEN
1723 * @arg @ref LL_TIM_OCMODE_ACTIVE
1724 * @arg @ref LL_TIM_OCMODE_INACTIVE
1725 * @arg @ref LL_TIM_OCMODE_TOGGLE
1726 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1727 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1728 * @arg @ref LL_TIM_OCMODE_PWM1
1729 * @arg @ref LL_TIM_OCMODE_PWM2
1730 * @retval None
1731 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)1732 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
1733 {
1734 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1735 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1736 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
1737 }
1738
1739 /**
1740 * @brief Get the output compare mode of an output channel.
1741 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
1742 * CCMR1 OC2M LL_TIM_OC_GetMode\n
1743 * CCMR2 OC3M LL_TIM_OC_GetMode\n
1744 * CCMR2 OC4M LL_TIM_OC_GetMode
1745 * @param TIMx Timer instance
1746 * @param Channel This parameter can be one of the following values:
1747 * @arg @ref LL_TIM_CHANNEL_CH1
1748 * @arg @ref LL_TIM_CHANNEL_CH2
1749 * @arg @ref LL_TIM_CHANNEL_CH3
1750 * @arg @ref LL_TIM_CHANNEL_CH4
1751 * @retval Returned value can be one of the following values:
1752 * @arg @ref LL_TIM_OCMODE_FROZEN
1753 * @arg @ref LL_TIM_OCMODE_ACTIVE
1754 * @arg @ref LL_TIM_OCMODE_INACTIVE
1755 * @arg @ref LL_TIM_OCMODE_TOGGLE
1756 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1757 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1758 * @arg @ref LL_TIM_OCMODE_PWM1
1759 * @arg @ref LL_TIM_OCMODE_PWM2
1760 */
LL_TIM_OC_GetMode(TIM_TypeDef * TIMx,uint32_t Channel)1761 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
1762 {
1763 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1764 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1765 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
1766 }
1767
1768 /**
1769 * @brief Set the polarity of an output channel.
1770 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
1771 * CCER CC1NP LL_TIM_OC_SetPolarity\n
1772 * CCER CC2P LL_TIM_OC_SetPolarity\n
1773 * CCER CC2NP LL_TIM_OC_SetPolarity\n
1774 * CCER CC3P LL_TIM_OC_SetPolarity\n
1775 * CCER CC3NP LL_TIM_OC_SetPolarity\n
1776 * CCER CC4P LL_TIM_OC_SetPolarity
1777 * @param TIMx Timer instance
1778 * @param Channel This parameter can be one of the following values:
1779 * @arg @ref LL_TIM_CHANNEL_CH1
1780 * @arg @ref LL_TIM_CHANNEL_CH1N
1781 * @arg @ref LL_TIM_CHANNEL_CH2
1782 * @arg @ref LL_TIM_CHANNEL_CH2N
1783 * @arg @ref LL_TIM_CHANNEL_CH3
1784 * @arg @ref LL_TIM_CHANNEL_CH3N
1785 * @arg @ref LL_TIM_CHANNEL_CH4
1786 * @param Polarity This parameter can be one of the following values:
1787 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1788 * @arg @ref LL_TIM_OCPOLARITY_LOW
1789 * @retval None
1790 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)1791 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
1792 {
1793 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1794 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
1795 }
1796
1797 /**
1798 * @brief Get the polarity of an output channel.
1799 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
1800 * CCER CC1NP LL_TIM_OC_GetPolarity\n
1801 * CCER CC2P LL_TIM_OC_GetPolarity\n
1802 * CCER CC2NP LL_TIM_OC_GetPolarity\n
1803 * CCER CC3P LL_TIM_OC_GetPolarity\n
1804 * CCER CC3NP LL_TIM_OC_GetPolarity\n
1805 * CCER CC4P LL_TIM_OC_GetPolarity
1806 * @param TIMx Timer instance
1807 * @param Channel This parameter can be one of the following values:
1808 * @arg @ref LL_TIM_CHANNEL_CH1
1809 * @arg @ref LL_TIM_CHANNEL_CH1N
1810 * @arg @ref LL_TIM_CHANNEL_CH2
1811 * @arg @ref LL_TIM_CHANNEL_CH2N
1812 * @arg @ref LL_TIM_CHANNEL_CH3
1813 * @arg @ref LL_TIM_CHANNEL_CH3N
1814 * @arg @ref LL_TIM_CHANNEL_CH4
1815 * @retval Returned value can be one of the following values:
1816 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1817 * @arg @ref LL_TIM_OCPOLARITY_LOW
1818 */
LL_TIM_OC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)1819 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
1820 {
1821 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1822 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
1823 }
1824
1825 /**
1826 * @brief Set the IDLE state of an output channel
1827 * @note This function is significant only for the timer instances
1828 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
1829 * can be used to check whether or not a timer instance provides
1830 * a break input.
1831 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
1832 * CR2 OIS1N LL_TIM_OC_SetIdleState\n
1833 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
1834 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
1835 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
1836 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
1837 * CR2 OIS4 LL_TIM_OC_SetIdleState
1838 * @param TIMx Timer instance
1839 * @param Channel This parameter can be one of the following values:
1840 * @arg @ref LL_TIM_CHANNEL_CH1
1841 * @arg @ref LL_TIM_CHANNEL_CH1N
1842 * @arg @ref LL_TIM_CHANNEL_CH2
1843 * @arg @ref LL_TIM_CHANNEL_CH2N
1844 * @arg @ref LL_TIM_CHANNEL_CH3
1845 * @arg @ref LL_TIM_CHANNEL_CH3N
1846 * @arg @ref LL_TIM_CHANNEL_CH4
1847 * @param IdleState This parameter can be one of the following values:
1848 * @arg @ref LL_TIM_OCIDLESTATE_LOW
1849 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
1850 * @retval None
1851 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)1852 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
1853 {
1854 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1855 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
1856 }
1857
1858 /**
1859 * @brief Get the IDLE state of an output channel
1860 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
1861 * CR2 OIS1N LL_TIM_OC_GetIdleState\n
1862 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
1863 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
1864 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
1865 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
1866 * CR2 OIS4 LL_TIM_OC_GetIdleState
1867 * @param TIMx Timer instance
1868 * @param Channel This parameter can be one of the following values:
1869 * @arg @ref LL_TIM_CHANNEL_CH1
1870 * @arg @ref LL_TIM_CHANNEL_CH1N
1871 * @arg @ref LL_TIM_CHANNEL_CH2
1872 * @arg @ref LL_TIM_CHANNEL_CH2N
1873 * @arg @ref LL_TIM_CHANNEL_CH3
1874 * @arg @ref LL_TIM_CHANNEL_CH3N
1875 * @arg @ref LL_TIM_CHANNEL_CH4
1876 * @retval Returned value can be one of the following values:
1877 * @arg @ref LL_TIM_OCIDLESTATE_LOW
1878 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
1879 */
LL_TIM_OC_GetIdleState(TIM_TypeDef * TIMx,uint32_t Channel)1880 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
1881 {
1882 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1883 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
1884 }
1885
1886 /**
1887 * @brief Enable fast mode for the output channel.
1888 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
1889 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
1890 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
1891 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
1892 * CCMR2 OC4FE LL_TIM_OC_EnableFast
1893 * @param TIMx Timer instance
1894 * @param Channel This parameter can be one of the following values:
1895 * @arg @ref LL_TIM_CHANNEL_CH1
1896 * @arg @ref LL_TIM_CHANNEL_CH2
1897 * @arg @ref LL_TIM_CHANNEL_CH3
1898 * @arg @ref LL_TIM_CHANNEL_CH4
1899 * @retval None
1900 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)1901 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1902 {
1903 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1904 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1905 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1906
1907 }
1908
1909 /**
1910 * @brief Disable fast mode for the output channel.
1911 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
1912 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
1913 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
1914 * CCMR2 OC4FE LL_TIM_OC_DisableFast
1915 * @param TIMx Timer instance
1916 * @param Channel This parameter can be one of the following values:
1917 * @arg @ref LL_TIM_CHANNEL_CH1
1918 * @arg @ref LL_TIM_CHANNEL_CH2
1919 * @arg @ref LL_TIM_CHANNEL_CH3
1920 * @arg @ref LL_TIM_CHANNEL_CH4
1921 * @retval None
1922 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)1923 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1924 {
1925 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1926 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1927 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1928
1929 }
1930
1931 /**
1932 * @brief Indicates whether fast mode is enabled for the output channel.
1933 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
1934 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
1935 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
1936 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
1937 * @param TIMx Timer instance
1938 * @param Channel This parameter can be one of the following values:
1939 * @arg @ref LL_TIM_CHANNEL_CH1
1940 * @arg @ref LL_TIM_CHANNEL_CH2
1941 * @arg @ref LL_TIM_CHANNEL_CH3
1942 * @arg @ref LL_TIM_CHANNEL_CH4
1943 * @retval State of bit (1 or 0).
1944 */
LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx,uint32_t Channel)1945 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
1946 {
1947 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1948 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1949 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
1950 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
1951 }
1952
1953 /**
1954 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
1955 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
1956 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
1957 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
1958 * CCMR2 OC4PE LL_TIM_OC_EnablePreload
1959 * @param TIMx Timer instance
1960 * @param Channel This parameter can be one of the following values:
1961 * @arg @ref LL_TIM_CHANNEL_CH1
1962 * @arg @ref LL_TIM_CHANNEL_CH2
1963 * @arg @ref LL_TIM_CHANNEL_CH3
1964 * @arg @ref LL_TIM_CHANNEL_CH4
1965 * @retval None
1966 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1967 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1968 {
1969 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1970 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1971 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1972 }
1973
1974 /**
1975 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
1976 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
1977 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
1978 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
1979 * CCMR2 OC4PE LL_TIM_OC_DisablePreload
1980 * @param TIMx Timer instance
1981 * @param Channel This parameter can be one of the following values:
1982 * @arg @ref LL_TIM_CHANNEL_CH1
1983 * @arg @ref LL_TIM_CHANNEL_CH2
1984 * @arg @ref LL_TIM_CHANNEL_CH3
1985 * @arg @ref LL_TIM_CHANNEL_CH4
1986 * @retval None
1987 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1988 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1989 {
1990 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1991 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1992 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1993 }
1994
1995 /**
1996 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
1997 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
1998 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
1999 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2000 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2001 * @param TIMx Timer instance
2002 * @param Channel This parameter can be one of the following values:
2003 * @arg @ref LL_TIM_CHANNEL_CH1
2004 * @arg @ref LL_TIM_CHANNEL_CH2
2005 * @arg @ref LL_TIM_CHANNEL_CH3
2006 * @arg @ref LL_TIM_CHANNEL_CH4
2007 * @retval State of bit (1 or 0).
2008 */
LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx,uint32_t Channel)2009 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
2010 {
2011 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2012 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2013 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2014 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2015 }
2016
2017 /**
2018 * @brief Enable clearing the output channel on an external event.
2019 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2020 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2021 * or not a timer instance can clear the OCxREF signal on an external event.
2022 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2023 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2024 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2025 * CCMR2 OC4CE LL_TIM_OC_EnableClear
2026 * @param TIMx Timer instance
2027 * @param Channel This parameter can be one of the following values:
2028 * @arg @ref LL_TIM_CHANNEL_CH1
2029 * @arg @ref LL_TIM_CHANNEL_CH2
2030 * @arg @ref LL_TIM_CHANNEL_CH3
2031 * @arg @ref LL_TIM_CHANNEL_CH4
2032 * @retval None
2033 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2034 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2035 {
2036 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2037 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2038 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2039 }
2040
2041 /**
2042 * @brief Disable clearing the output channel on an external event.
2043 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2044 * or not a timer instance can clear the OCxREF signal on an external event.
2045 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2046 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2047 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2048 * CCMR2 OC4CE LL_TIM_OC_DisableClear
2049 * @param TIMx Timer instance
2050 * @param Channel This parameter can be one of the following values:
2051 * @arg @ref LL_TIM_CHANNEL_CH1
2052 * @arg @ref LL_TIM_CHANNEL_CH2
2053 * @arg @ref LL_TIM_CHANNEL_CH3
2054 * @arg @ref LL_TIM_CHANNEL_CH4
2055 * @retval None
2056 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2057 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2058 {
2059 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2060 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2061 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2062 }
2063
2064 /**
2065 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2066 * @note This function enables clearing the output channel on an external event.
2067 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2068 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2069 * or not a timer instance can clear the OCxREF signal on an external event.
2070 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2071 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2072 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2073 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2074 * @param TIMx Timer instance
2075 * @param Channel This parameter can be one of the following values:
2076 * @arg @ref LL_TIM_CHANNEL_CH1
2077 * @arg @ref LL_TIM_CHANNEL_CH2
2078 * @arg @ref LL_TIM_CHANNEL_CH3
2079 * @arg @ref LL_TIM_CHANNEL_CH4
2080 * @retval State of bit (1 or 0).
2081 */
LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx,uint32_t Channel)2082 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2083 {
2084 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2085 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2086 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2087 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2088 }
2089
2090 /**
2091 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2092 * the Ocx and OCxN signals).
2093 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2094 * dead-time insertion feature is supported by a timer instance.
2095 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2096 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2097 * @param TIMx Timer instance
2098 * @param DeadTime between Min_Data=0 and Max_Data=255
2099 * @retval None
2100 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2101 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2102 {
2103 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2104 }
2105
2106 /**
2107 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2108 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2109 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2110 * whether or not a timer instance supports a 32 bits counter.
2111 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2112 * output channel 1 is supported by a timer instance.
2113 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2114 * @param TIMx Timer instance
2115 * @param CompareValue between Min_Data=0 and Max_Data=65535
2116 * @retval None
2117 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2118 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2119 {
2120 WRITE_REG(TIMx->CCR1, CompareValue);
2121 }
2122
2123 /**
2124 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2125 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2126 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2127 * whether or not a timer instance supports a 32 bits counter.
2128 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2129 * output channel 2 is supported by a timer instance.
2130 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2131 * @param TIMx Timer instance
2132 * @param CompareValue between Min_Data=0 and Max_Data=65535
2133 * @retval None
2134 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2135 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2136 {
2137 WRITE_REG(TIMx->CCR2, CompareValue);
2138 }
2139
2140 /**
2141 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2142 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2143 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2144 * whether or not a timer instance supports a 32 bits counter.
2145 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2146 * output channel is supported by a timer instance.
2147 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2148 * @param TIMx Timer instance
2149 * @param CompareValue between Min_Data=0 and Max_Data=65535
2150 * @retval None
2151 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2152 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2153 {
2154 WRITE_REG(TIMx->CCR3, CompareValue);
2155 }
2156
2157 /**
2158 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2159 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2160 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2161 * whether or not a timer instance supports a 32 bits counter.
2162 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2163 * output channel 4 is supported by a timer instance.
2164 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2165 * @param TIMx Timer instance
2166 * @param CompareValue between Min_Data=0 and Max_Data=65535
2167 * @retval None
2168 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2169 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2170 {
2171 WRITE_REG(TIMx->CCR4, CompareValue);
2172 }
2173
2174 /**
2175 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2176 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2177 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2178 * whether or not a timer instance supports a 32 bits counter.
2179 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2180 * output channel 1 is supported by a timer instance.
2181 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2182 * @param TIMx Timer instance
2183 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2184 */
LL_TIM_OC_GetCompareCH1(TIM_TypeDef * TIMx)2185 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
2186 {
2187 return (uint32_t)(READ_REG(TIMx->CCR1));
2188 }
2189
2190 /**
2191 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2192 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2193 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2194 * whether or not a timer instance supports a 32 bits counter.
2195 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2196 * output channel 2 is supported by a timer instance.
2197 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2198 * @param TIMx Timer instance
2199 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2200 */
LL_TIM_OC_GetCompareCH2(TIM_TypeDef * TIMx)2201 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
2202 {
2203 return (uint32_t)(READ_REG(TIMx->CCR2));
2204 }
2205
2206 /**
2207 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2208 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2209 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2210 * whether or not a timer instance supports a 32 bits counter.
2211 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2212 * output channel 3 is supported by a timer instance.
2213 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2214 * @param TIMx Timer instance
2215 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2216 */
LL_TIM_OC_GetCompareCH3(TIM_TypeDef * TIMx)2217 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
2218 {
2219 return (uint32_t)(READ_REG(TIMx->CCR3));
2220 }
2221
2222 /**
2223 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2224 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2225 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2226 * whether or not a timer instance supports a 32 bits counter.
2227 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2228 * output channel 4 is supported by a timer instance.
2229 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2230 * @param TIMx Timer instance
2231 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2232 */
LL_TIM_OC_GetCompareCH4(TIM_TypeDef * TIMx)2233 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
2234 {
2235 return (uint32_t)(READ_REG(TIMx->CCR4));
2236 }
2237
2238 /**
2239 * @}
2240 */
2241
2242 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2243 * @{
2244 */
2245 /**
2246 * @brief Configure input channel.
2247 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2248 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2249 * CCMR1 IC1F LL_TIM_IC_Config\n
2250 * CCMR1 CC2S LL_TIM_IC_Config\n
2251 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2252 * CCMR1 IC2F LL_TIM_IC_Config\n
2253 * CCMR2 CC3S LL_TIM_IC_Config\n
2254 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2255 * CCMR2 IC3F LL_TIM_IC_Config\n
2256 * CCMR2 CC4S LL_TIM_IC_Config\n
2257 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2258 * CCMR2 IC4F LL_TIM_IC_Config\n
2259 * CCER CC1P LL_TIM_IC_Config\n
2260 * CCER CC1NP LL_TIM_IC_Config\n
2261 * CCER CC2P LL_TIM_IC_Config\n
2262 * CCER CC2NP LL_TIM_IC_Config\n
2263 * CCER CC3P LL_TIM_IC_Config\n
2264 * CCER CC3NP LL_TIM_IC_Config\n
2265 * CCER CC4P LL_TIM_IC_Config\n
2266 * CCER CC4NP LL_TIM_IC_Config
2267 * @param TIMx Timer instance
2268 * @param Channel This parameter can be one of the following values:
2269 * @arg @ref LL_TIM_CHANNEL_CH1
2270 * @arg @ref LL_TIM_CHANNEL_CH2
2271 * @arg @ref LL_TIM_CHANNEL_CH3
2272 * @arg @ref LL_TIM_CHANNEL_CH4
2273 * @param Configuration This parameter must be a combination of all the following values:
2274 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2275 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2276 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2277 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2278 * @retval None
2279 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2280 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2281 {
2282 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2283 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2284 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2285 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2286 << SHIFT_TAB_ICxx[iChannel]);
2287 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2288 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2289 }
2290
2291 /**
2292 * @brief Set the active input.
2293 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2294 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2295 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2296 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2297 * @param TIMx Timer instance
2298 * @param Channel This parameter can be one of the following values:
2299 * @arg @ref LL_TIM_CHANNEL_CH1
2300 * @arg @ref LL_TIM_CHANNEL_CH2
2301 * @arg @ref LL_TIM_CHANNEL_CH3
2302 * @arg @ref LL_TIM_CHANNEL_CH4
2303 * @param ICActiveInput This parameter can be one of the following values:
2304 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2305 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2306 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2307 * @retval None
2308 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2309 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2310 {
2311 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2312 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2313 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2314 }
2315
2316 /**
2317 * @brief Get the current active input.
2318 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2319 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2320 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2321 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2322 * @param TIMx Timer instance
2323 * @param Channel This parameter can be one of the following values:
2324 * @arg @ref LL_TIM_CHANNEL_CH1
2325 * @arg @ref LL_TIM_CHANNEL_CH2
2326 * @arg @ref LL_TIM_CHANNEL_CH3
2327 * @arg @ref LL_TIM_CHANNEL_CH4
2328 * @retval Returned value can be one of the following values:
2329 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2330 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2331 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2332 */
LL_TIM_IC_GetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel)2333 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
2334 {
2335 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2336 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2337 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2338 }
2339
2340 /**
2341 * @brief Set the prescaler of input channel.
2342 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2343 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2344 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2345 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2346 * @param TIMx Timer instance
2347 * @param Channel This parameter can be one of the following values:
2348 * @arg @ref LL_TIM_CHANNEL_CH1
2349 * @arg @ref LL_TIM_CHANNEL_CH2
2350 * @arg @ref LL_TIM_CHANNEL_CH3
2351 * @arg @ref LL_TIM_CHANNEL_CH4
2352 * @param ICPrescaler This parameter can be one of the following values:
2353 * @arg @ref LL_TIM_ICPSC_DIV1
2354 * @arg @ref LL_TIM_ICPSC_DIV2
2355 * @arg @ref LL_TIM_ICPSC_DIV4
2356 * @arg @ref LL_TIM_ICPSC_DIV8
2357 * @retval None
2358 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2359 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2360 {
2361 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2362 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2363 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2364 }
2365
2366 /**
2367 * @brief Get the current prescaler value acting on an input channel.
2368 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2369 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2370 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2371 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2372 * @param TIMx Timer instance
2373 * @param Channel This parameter can be one of the following values:
2374 * @arg @ref LL_TIM_CHANNEL_CH1
2375 * @arg @ref LL_TIM_CHANNEL_CH2
2376 * @arg @ref LL_TIM_CHANNEL_CH3
2377 * @arg @ref LL_TIM_CHANNEL_CH4
2378 * @retval Returned value can be one of the following values:
2379 * @arg @ref LL_TIM_ICPSC_DIV1
2380 * @arg @ref LL_TIM_ICPSC_DIV2
2381 * @arg @ref LL_TIM_ICPSC_DIV4
2382 * @arg @ref LL_TIM_ICPSC_DIV8
2383 */
LL_TIM_IC_GetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel)2384 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
2385 {
2386 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2387 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2388 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2389 }
2390
2391 /**
2392 * @brief Set the input filter duration.
2393 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2394 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2395 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2396 * CCMR2 IC4F LL_TIM_IC_SetFilter
2397 * @param TIMx Timer instance
2398 * @param Channel This parameter can be one of the following values:
2399 * @arg @ref LL_TIM_CHANNEL_CH1
2400 * @arg @ref LL_TIM_CHANNEL_CH2
2401 * @arg @ref LL_TIM_CHANNEL_CH3
2402 * @arg @ref LL_TIM_CHANNEL_CH4
2403 * @param ICFilter This parameter can be one of the following values:
2404 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2405 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2406 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2407 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2408 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2409 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2410 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2411 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2412 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2413 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2414 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2415 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2416 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2417 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2418 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2419 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2420 * @retval None
2421 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2422 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2423 {
2424 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2425 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2426 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2427 }
2428
2429 /**
2430 * @brief Get the input filter duration.
2431 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2432 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2433 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2434 * CCMR2 IC4F LL_TIM_IC_GetFilter
2435 * @param TIMx Timer instance
2436 * @param Channel This parameter can be one of the following values:
2437 * @arg @ref LL_TIM_CHANNEL_CH1
2438 * @arg @ref LL_TIM_CHANNEL_CH2
2439 * @arg @ref LL_TIM_CHANNEL_CH3
2440 * @arg @ref LL_TIM_CHANNEL_CH4
2441 * @retval Returned value can be one of the following values:
2442 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2443 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2444 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2445 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2446 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2447 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2448 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2449 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2450 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2451 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2452 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2453 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2454 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2455 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2456 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2457 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2458 */
LL_TIM_IC_GetFilter(TIM_TypeDef * TIMx,uint32_t Channel)2459 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
2460 {
2461 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2462 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2463 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2464 }
2465
2466 /**
2467 * @brief Set the input channel polarity.
2468 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2469 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2470 * CCER CC2P LL_TIM_IC_SetPolarity\n
2471 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2472 * CCER CC3P LL_TIM_IC_SetPolarity\n
2473 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2474 * CCER CC4P LL_TIM_IC_SetPolarity\n
2475 * CCER CC4NP LL_TIM_IC_SetPolarity
2476 * @param TIMx Timer instance
2477 * @param Channel This parameter can be one of the following values:
2478 * @arg @ref LL_TIM_CHANNEL_CH1
2479 * @arg @ref LL_TIM_CHANNEL_CH2
2480 * @arg @ref LL_TIM_CHANNEL_CH3
2481 * @arg @ref LL_TIM_CHANNEL_CH4
2482 * @param ICPolarity This parameter can be one of the following values:
2483 * @arg @ref LL_TIM_IC_POLARITY_RISING
2484 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2485 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2486 * @retval None
2487 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2488 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2489 {
2490 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2491 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2492 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2493 }
2494
2495 /**
2496 * @brief Get the current input channel polarity.
2497 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2498 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2499 * CCER CC2P LL_TIM_IC_GetPolarity\n
2500 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2501 * CCER CC3P LL_TIM_IC_GetPolarity\n
2502 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2503 * CCER CC4P LL_TIM_IC_GetPolarity\n
2504 * CCER CC4NP LL_TIM_IC_GetPolarity
2505 * @param TIMx Timer instance
2506 * @param Channel This parameter can be one of the following values:
2507 * @arg @ref LL_TIM_CHANNEL_CH1
2508 * @arg @ref LL_TIM_CHANNEL_CH2
2509 * @arg @ref LL_TIM_CHANNEL_CH3
2510 * @arg @ref LL_TIM_CHANNEL_CH4
2511 * @retval Returned value can be one of the following values:
2512 * @arg @ref LL_TIM_IC_POLARITY_RISING
2513 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2514 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2515 */
LL_TIM_IC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)2516 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2517 {
2518 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2519 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2520 SHIFT_TAB_CCxP[iChannel]);
2521 }
2522
2523 /**
2524 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2525 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2526 * a timer instance provides an XOR input.
2527 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2528 * @param TIMx Timer instance
2529 * @retval None
2530 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)2531 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2532 {
2533 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2534 }
2535
2536 /**
2537 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
2538 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2539 * a timer instance provides an XOR input.
2540 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
2541 * @param TIMx Timer instance
2542 * @retval None
2543 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)2544 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
2545 {
2546 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
2547 }
2548
2549 /**
2550 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
2551 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2552 * a timer instance provides an XOR input.
2553 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
2554 * @param TIMx Timer instance
2555 * @retval State of bit (1 or 0).
2556 */
LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)2557 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
2558 {
2559 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
2560 }
2561
2562 /**
2563 * @brief Get captured value for input channel 1.
2564 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2565 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2566 * whether or not a timer instance supports a 32 bits counter.
2567 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2568 * input channel 1 is supported by a timer instance.
2569 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
2570 * @param TIMx Timer instance
2571 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2572 */
LL_TIM_IC_GetCaptureCH1(TIM_TypeDef * TIMx)2573 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
2574 {
2575 return (uint32_t)(READ_REG(TIMx->CCR1));
2576 }
2577
2578 /**
2579 * @brief Get captured value for input channel 2.
2580 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2581 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2582 * whether or not a timer instance supports a 32 bits counter.
2583 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2584 * input channel 2 is supported by a timer instance.
2585 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
2586 * @param TIMx Timer instance
2587 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2588 */
LL_TIM_IC_GetCaptureCH2(TIM_TypeDef * TIMx)2589 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
2590 {
2591 return (uint32_t)(READ_REG(TIMx->CCR2));
2592 }
2593
2594 /**
2595 * @brief Get captured value for input channel 3.
2596 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2597 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2598 * whether or not a timer instance supports a 32 bits counter.
2599 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2600 * input channel 3 is supported by a timer instance.
2601 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
2602 * @param TIMx Timer instance
2603 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2604 */
LL_TIM_IC_GetCaptureCH3(TIM_TypeDef * TIMx)2605 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
2606 {
2607 return (uint32_t)(READ_REG(TIMx->CCR3));
2608 }
2609
2610 /**
2611 * @brief Get captured value for input channel 4.
2612 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2613 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2614 * whether or not a timer instance supports a 32 bits counter.
2615 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2616 * input channel 4 is supported by a timer instance.
2617 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
2618 * @param TIMx Timer instance
2619 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2620 */
LL_TIM_IC_GetCaptureCH4(TIM_TypeDef * TIMx)2621 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
2622 {
2623 return (uint32_t)(READ_REG(TIMx->CCR4));
2624 }
2625
2626 /**
2627 * @}
2628 */
2629
2630 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
2631 * @{
2632 */
2633 /**
2634 * @brief Enable external clock mode 2.
2635 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
2636 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2637 * whether or not a timer instance supports external clock mode2.
2638 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
2639 * @param TIMx Timer instance
2640 * @retval None
2641 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)2642 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
2643 {
2644 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2645 }
2646
2647 /**
2648 * @brief Disable external clock mode 2.
2649 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2650 * whether or not a timer instance supports external clock mode2.
2651 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
2652 * @param TIMx Timer instance
2653 * @retval None
2654 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)2655 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
2656 {
2657 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2658 }
2659
2660 /**
2661 * @brief Indicate whether external clock mode 2 is enabled.
2662 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2663 * whether or not a timer instance supports external clock mode2.
2664 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
2665 * @param TIMx Timer instance
2666 * @retval State of bit (1 or 0).
2667 */
LL_TIM_IsEnabledExternalClock(TIM_TypeDef * TIMx)2668 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
2669 {
2670 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
2671 }
2672
2673 /**
2674 * @brief Set the clock source of the counter clock.
2675 * @note when selected clock source is external clock mode 1, the timer input
2676 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
2677 * function. This timer input must be configured by calling
2678 * the @ref LL_TIM_IC_Config() function.
2679 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
2680 * whether or not a timer instance supports external clock mode1.
2681 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2682 * whether or not a timer instance supports external clock mode2.
2683 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
2684 * SMCR ECE LL_TIM_SetClockSource
2685 * @param TIMx Timer instance
2686 * @param ClockSource This parameter can be one of the following values:
2687 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
2688 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
2689 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
2690 * @retval None
2691 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)2692 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
2693 {
2694 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
2695 }
2696
2697 /**
2698 * @brief Set the encoder interface mode.
2699 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
2700 * whether or not a timer instance supports the encoder mode.
2701 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
2702 * @param TIMx Timer instance
2703 * @param EncoderMode This parameter can be one of the following values:
2704 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
2705 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
2706 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
2707 * @retval None
2708 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)2709 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
2710 {
2711 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
2712 }
2713
2714 /**
2715 * @}
2716 */
2717
2718 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
2719 * @{
2720 */
2721 /**
2722 * @brief Set the trigger output (TRGO) used for timer synchronization .
2723 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
2724 * whether or not a timer instance can operate as a master timer.
2725 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
2726 * @param TIMx Timer instance
2727 * @param TimerSynchronization This parameter can be one of the following values:
2728 * @arg @ref LL_TIM_TRGO_RESET
2729 * @arg @ref LL_TIM_TRGO_ENABLE
2730 * @arg @ref LL_TIM_TRGO_UPDATE
2731 * @arg @ref LL_TIM_TRGO_CC1IF
2732 * @arg @ref LL_TIM_TRGO_OC1REF
2733 * @arg @ref LL_TIM_TRGO_OC2REF
2734 * @arg @ref LL_TIM_TRGO_OC3REF
2735 * @arg @ref LL_TIM_TRGO_OC4REF
2736 * @retval None
2737 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)2738 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
2739 {
2740 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
2741 }
2742
2743 /**
2744 * @brief Set the synchronization mode of a slave timer.
2745 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2746 * a timer instance can operate as a slave timer.
2747 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
2748 * @param TIMx Timer instance
2749 * @param SlaveMode This parameter can be one of the following values:
2750 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
2751 * @arg @ref LL_TIM_SLAVEMODE_RESET
2752 * @arg @ref LL_TIM_SLAVEMODE_GATED
2753 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
2754 * @retval None
2755 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)2756 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
2757 {
2758 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
2759 }
2760
2761 /**
2762 * @brief Set the selects the trigger input to be used to synchronize the counter.
2763 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2764 * a timer instance can operate as a slave timer.
2765 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
2766 * @param TIMx Timer instance
2767 * @param TriggerInput This parameter can be one of the following values:
2768 * @arg @ref LL_TIM_TS_ITR0
2769 * @arg @ref LL_TIM_TS_ITR1
2770 * @arg @ref LL_TIM_TS_ITR2
2771 * @arg @ref LL_TIM_TS_ITR3
2772 * @arg @ref LL_TIM_TS_TI1F_ED
2773 * @arg @ref LL_TIM_TS_TI1FP1
2774 * @arg @ref LL_TIM_TS_TI2FP2
2775 * @arg @ref LL_TIM_TS_ETRF
2776 * @retval None
2777 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)2778 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
2779 {
2780 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
2781 }
2782
2783 /**
2784 * @brief Enable the Master/Slave mode.
2785 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2786 * a timer instance can operate as a slave timer.
2787 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
2788 * @param TIMx Timer instance
2789 * @retval None
2790 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)2791 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
2792 {
2793 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2794 }
2795
2796 /**
2797 * @brief Disable the Master/Slave mode.
2798 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2799 * a timer instance can operate as a slave timer.
2800 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
2801 * @param TIMx Timer instance
2802 * @retval None
2803 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)2804 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
2805 {
2806 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2807 }
2808
2809 /**
2810 * @brief Indicates whether the Master/Slave mode is enabled.
2811 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2812 * a timer instance can operate as a slave timer.
2813 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
2814 * @param TIMx Timer instance
2815 * @retval State of bit (1 or 0).
2816 */
LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef * TIMx)2817 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
2818 {
2819 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
2820 }
2821
2822 /**
2823 * @brief Configure the external trigger (ETR) input.
2824 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
2825 * a timer instance provides an external trigger input.
2826 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
2827 * SMCR ETPS LL_TIM_ConfigETR\n
2828 * SMCR ETF LL_TIM_ConfigETR
2829 * @param TIMx Timer instance
2830 * @param ETRPolarity This parameter can be one of the following values:
2831 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
2832 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
2833 * @param ETRPrescaler This parameter can be one of the following values:
2834 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
2835 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
2836 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
2837 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
2838 * @param ETRFilter This parameter can be one of the following values:
2839 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
2840 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
2841 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
2842 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
2843 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
2844 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
2845 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
2846 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
2847 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
2848 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
2849 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
2850 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
2851 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
2852 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
2853 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
2854 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
2855 * @retval None
2856 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)2857 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
2858 uint32_t ETRFilter)
2859 {
2860 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
2861 }
2862
2863 /**
2864 * @}
2865 */
2866
2867 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
2868 * @{
2869 */
2870 /**
2871 * @brief Enable the break function.
2872 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2873 * a timer instance provides a break input.
2874 * @rmtoll BDTR BKE LL_TIM_EnableBRK
2875 * @param TIMx Timer instance
2876 * @retval None
2877 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)2878 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
2879 {
2880 __IO uint32_t tmpreg;
2881 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2882 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2883 tmpreg = READ_REG(TIMx->BDTR);
2884 (void)(tmpreg);
2885 }
2886
2887 /**
2888 * @brief Disable the break function.
2889 * @rmtoll BDTR BKE LL_TIM_DisableBRK
2890 * @param TIMx Timer instance
2891 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2892 * a timer instance provides a break input.
2893 * @retval None
2894 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)2895 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
2896 {
2897 __IO uint32_t tmpreg;
2898 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2899 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2900 tmpreg = READ_REG(TIMx->BDTR);
2901 (void)(tmpreg);
2902 }
2903
2904 /**
2905 * @brief Configure the break input.
2906 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2907 * a timer instance provides a break input.
2908 * @rmtoll BDTR BKP LL_TIM_ConfigBRK
2909 * @param TIMx Timer instance
2910 * @param BreakPolarity This parameter can be one of the following values:
2911 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
2912 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
2913 * @retval None
2914 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity)2915 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
2916 {
2917 __IO uint32_t tmpreg;
2918 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
2919 /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
2920 tmpreg = READ_REG(TIMx->BDTR);
2921 (void)(tmpreg);
2922 }
2923
2924 /**
2925 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
2926 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2927 * a timer instance provides a break input.
2928 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
2929 * BDTR OSSR LL_TIM_SetOffStates
2930 * @param TIMx Timer instance
2931 * @param OffStateIdle This parameter can be one of the following values:
2932 * @arg @ref LL_TIM_OSSI_DISABLE
2933 * @arg @ref LL_TIM_OSSI_ENABLE
2934 * @param OffStateRun This parameter can be one of the following values:
2935 * @arg @ref LL_TIM_OSSR_DISABLE
2936 * @arg @ref LL_TIM_OSSR_ENABLE
2937 * @retval None
2938 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)2939 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
2940 {
2941 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
2942 }
2943
2944 /**
2945 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
2946 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2947 * a timer instance provides a break input.
2948 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
2949 * @param TIMx Timer instance
2950 * @retval None
2951 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)2952 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
2953 {
2954 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2955 }
2956
2957 /**
2958 * @brief Disable automatic output (MOE can be set only by software).
2959 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2960 * a timer instance provides a break input.
2961 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
2962 * @param TIMx Timer instance
2963 * @retval None
2964 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)2965 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
2966 {
2967 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2968 }
2969
2970 /**
2971 * @brief Indicate whether automatic output is enabled.
2972 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2973 * a timer instance provides a break input.
2974 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
2975 * @param TIMx Timer instance
2976 * @retval State of bit (1 or 0).
2977 */
LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef * TIMx)2978 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
2979 {
2980 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
2981 }
2982
2983 /**
2984 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
2985 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
2986 * software and is reset in case of break or break2 event
2987 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2988 * a timer instance provides a break input.
2989 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
2990 * @param TIMx Timer instance
2991 * @retval None
2992 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)2993 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
2994 {
2995 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
2996 }
2997
2998 /**
2999 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3000 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3001 * software and is reset in case of break or break2 event.
3002 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3003 * a timer instance provides a break input.
3004 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3005 * @param TIMx Timer instance
3006 * @retval None
3007 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3008 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3009 {
3010 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3011 }
3012
3013 /**
3014 * @brief Indicates whether outputs are enabled.
3015 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3016 * a timer instance provides a break input.
3017 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3018 * @param TIMx Timer instance
3019 * @retval State of bit (1 or 0).
3020 */
LL_TIM_IsEnabledAllOutputs(TIM_TypeDef * TIMx)3021 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
3022 {
3023 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3024 }
3025
3026 /**
3027 * @}
3028 */
3029
3030 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3031 * @{
3032 */
3033 /**
3034 * @brief Configures the timer DMA burst feature.
3035 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3036 * not a timer instance supports the DMA burst mode.
3037 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3038 * DCR DBA LL_TIM_ConfigDMABurst
3039 * @param TIMx Timer instance
3040 * @param DMABurstBaseAddress This parameter can be one of the following values:
3041 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3042 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3043 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3044 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3045 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3046 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3047 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3048 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3049 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3050 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3051 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3052 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3053 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3054 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3055 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3056 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3057 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3058 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3059 * @param DMABurstLength This parameter can be one of the following values:
3060 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3061 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3062 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3063 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3064 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3065 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3066 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3067 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3068 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3069 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3070 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3071 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3072 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3073 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3074 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3075 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3076 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3077 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3078 * @retval None
3079 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3080 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3081 {
3082 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3083 }
3084
3085 /**
3086 * @}
3087 */
3088
3089 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3090 * @{
3091 */
3092 /**
3093 * @brief Remap TIM inputs (input channel, internal/external triggers).
3094 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3095 * a some timer inputs can be remapped.
3096 * @rmtoll TIM1_OR ITR2_RMP LL_TIM_SetRemap\n
3097 * TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
3098 * TIM5_OR ITR1_RMP LL_TIM_SetRemap\n
3099 * TIM5_OR TI4_RMP LL_TIM_SetRemap\n
3100 * TIM9_OR ITR1_RMP LL_TIM_SetRemap\n
3101 * TIM11_OR TI1_RMP LL_TIM_SetRemap\n
3102 * LPTIM1_OR OR LL_TIM_SetRemap
3103 * @param TIMx Timer instance
3104 * @param Remap Remap param depends on the TIMx. Description available only
3105 * in CHM version of the User Manual (not in .pdf).
3106 * Otherwise see Reference Manual description of OR registers.
3107 *
3108 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3109 *
3110 * TIM1: one of the following values
3111 *
3112 * ITR2_RMP can be one of the following values
3113 * @arg @ref LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO (*)
3114 * @arg @ref LL_TIM_TIM1_ITR2_RMP_LPTIM (*)
3115 *
3116 * TIM2: one of the following values
3117 *
3118 * ITR1_RMP can be one of the following values
3119 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
3120 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
3121 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
3122 *
3123 * TIM5: one of the following values
3124 *
3125 * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
3126 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
3127 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
3128 * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
3129 * @arg @ref LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO (*)
3130 * @arg @ref LL_TIM_TIM5_ITR1_RMP_LPTIM (*)
3131 *
3132 * TIM9: one of the following values
3133 *
3134 * ITR1_RMP can be one of the following values
3135 * @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO (*)
3136 * @arg @ref LL_TIM_TIM9_ITR1_RMP_LPTIM (*)
3137 *
3138 * TIM11: one of the following values
3139 *
3140 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
3141 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1 (*)
3142 * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
3143 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2
3144 * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX (*)
3145 *
3146 * (*) Value not defined in all devices. \n
3147 *
3148 * @retval None
3149 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3150 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3151 {
3152 #if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP)
3153 if ((Remap & LL_TIM_LPTIM_REMAP_MASK) == LL_TIM_LPTIM_REMAP_MASK)
3154 {
3155 /* Connect TIMx internal trigger to LPTIM1 output */
3156 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);
3157 MODIFY_REG(LPTIM1->OR,
3158 (LPTIM_OR_TIM1_ITR2_RMP | LPTIM_OR_TIM5_ITR1_RMP | LPTIM_OR_TIM9_ITR1_RMP),
3159 Remap & ~(LL_TIM_LPTIM_REMAP_MASK));
3160 }
3161 else
3162 {
3163 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3164 }
3165 #else
3166 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3167 #endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */
3168 }
3169
3170 /**
3171 * @}
3172 */
3173
3174 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3175 * @{
3176 */
3177 /**
3178 * @brief Clear the update interrupt flag (UIF).
3179 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3180 * @param TIMx Timer instance
3181 * @retval None
3182 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)3183 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3184 {
3185 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3186 }
3187
3188 /**
3189 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3190 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3191 * @param TIMx Timer instance
3192 * @retval State of bit (1 or 0).
3193 */
LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef * TIMx)3194 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
3195 {
3196 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3197 }
3198
3199 /**
3200 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3201 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3202 * @param TIMx Timer instance
3203 * @retval None
3204 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)3205 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3206 {
3207 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3208 }
3209
3210 /**
3211 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3212 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3213 * @param TIMx Timer instance
3214 * @retval State of bit (1 or 0).
3215 */
LL_TIM_IsActiveFlag_CC1(TIM_TypeDef * TIMx)3216 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
3217 {
3218 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
3219 }
3220
3221 /**
3222 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3223 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3224 * @param TIMx Timer instance
3225 * @retval None
3226 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)3227 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3228 {
3229 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3230 }
3231
3232 /**
3233 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3234 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3235 * @param TIMx Timer instance
3236 * @retval State of bit (1 or 0).
3237 */
LL_TIM_IsActiveFlag_CC2(TIM_TypeDef * TIMx)3238 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
3239 {
3240 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
3241 }
3242
3243 /**
3244 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3245 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3246 * @param TIMx Timer instance
3247 * @retval None
3248 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)3249 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3250 {
3251 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3252 }
3253
3254 /**
3255 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3256 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3257 * @param TIMx Timer instance
3258 * @retval State of bit (1 or 0).
3259 */
LL_TIM_IsActiveFlag_CC3(TIM_TypeDef * TIMx)3260 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
3261 {
3262 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
3263 }
3264
3265 /**
3266 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
3267 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
3268 * @param TIMx Timer instance
3269 * @retval None
3270 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)3271 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
3272 {
3273 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
3274 }
3275
3276 /**
3277 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
3278 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
3279 * @param TIMx Timer instance
3280 * @retval State of bit (1 or 0).
3281 */
LL_TIM_IsActiveFlag_CC4(TIM_TypeDef * TIMx)3282 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
3283 {
3284 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
3285 }
3286
3287 /**
3288 * @brief Clear the commutation interrupt flag (COMIF).
3289 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
3290 * @param TIMx Timer instance
3291 * @retval None
3292 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)3293 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
3294 {
3295 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
3296 }
3297
3298 /**
3299 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
3300 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
3301 * @param TIMx Timer instance
3302 * @retval State of bit (1 or 0).
3303 */
LL_TIM_IsActiveFlag_COM(TIM_TypeDef * TIMx)3304 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
3305 {
3306 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
3307 }
3308
3309 /**
3310 * @brief Clear the trigger interrupt flag (TIF).
3311 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
3312 * @param TIMx Timer instance
3313 * @retval None
3314 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)3315 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
3316 {
3317 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
3318 }
3319
3320 /**
3321 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
3322 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
3323 * @param TIMx Timer instance
3324 * @retval State of bit (1 or 0).
3325 */
LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef * TIMx)3326 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
3327 {
3328 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
3329 }
3330
3331 /**
3332 * @brief Clear the break interrupt flag (BIF).
3333 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
3334 * @param TIMx Timer instance
3335 * @retval None
3336 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)3337 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
3338 {
3339 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
3340 }
3341
3342 /**
3343 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
3344 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
3345 * @param TIMx Timer instance
3346 * @retval State of bit (1 or 0).
3347 */
LL_TIM_IsActiveFlag_BRK(TIM_TypeDef * TIMx)3348 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
3349 {
3350 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
3351 }
3352
3353 /**
3354 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
3355 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
3356 * @param TIMx Timer instance
3357 * @retval None
3358 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)3359 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
3360 {
3361 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
3362 }
3363
3364 /**
3365 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
3366 * (Capture/Compare 1 interrupt is pending).
3367 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
3368 * @param TIMx Timer instance
3369 * @retval State of bit (1 or 0).
3370 */
LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef * TIMx)3371 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
3372 {
3373 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
3374 }
3375
3376 /**
3377 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
3378 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
3379 * @param TIMx Timer instance
3380 * @retval None
3381 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)3382 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
3383 {
3384 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
3385 }
3386
3387 /**
3388 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
3389 * (Capture/Compare 2 over-capture interrupt is pending).
3390 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
3391 * @param TIMx Timer instance
3392 * @retval State of bit (1 or 0).
3393 */
LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef * TIMx)3394 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
3395 {
3396 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
3397 }
3398
3399 /**
3400 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
3401 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
3402 * @param TIMx Timer instance
3403 * @retval None
3404 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)3405 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
3406 {
3407 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
3408 }
3409
3410 /**
3411 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
3412 * (Capture/Compare 3 over-capture interrupt is pending).
3413 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
3414 * @param TIMx Timer instance
3415 * @retval State of bit (1 or 0).
3416 */
LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef * TIMx)3417 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
3418 {
3419 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
3420 }
3421
3422 /**
3423 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
3424 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
3425 * @param TIMx Timer instance
3426 * @retval None
3427 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)3428 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
3429 {
3430 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
3431 }
3432
3433 /**
3434 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
3435 * (Capture/Compare 4 over-capture interrupt is pending).
3436 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
3437 * @param TIMx Timer instance
3438 * @retval State of bit (1 or 0).
3439 */
LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef * TIMx)3440 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
3441 {
3442 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
3443 }
3444
3445 /**
3446 * @}
3447 */
3448
3449 /** @defgroup TIM_LL_EF_IT_Management IT-Management
3450 * @{
3451 */
3452 /**
3453 * @brief Enable update interrupt (UIE).
3454 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
3455 * @param TIMx Timer instance
3456 * @retval None
3457 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)3458 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
3459 {
3460 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
3461 }
3462
3463 /**
3464 * @brief Disable update interrupt (UIE).
3465 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
3466 * @param TIMx Timer instance
3467 * @retval None
3468 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)3469 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
3470 {
3471 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
3472 }
3473
3474 /**
3475 * @brief Indicates whether the update interrupt (UIE) is enabled.
3476 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
3477 * @param TIMx Timer instance
3478 * @retval State of bit (1 or 0).
3479 */
LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef * TIMx)3480 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
3481 {
3482 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
3483 }
3484
3485 /**
3486 * @brief Enable capture/compare 1 interrupt (CC1IE).
3487 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
3488 * @param TIMx Timer instance
3489 * @retval None
3490 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)3491 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
3492 {
3493 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3494 }
3495
3496 /**
3497 * @brief Disable capture/compare 1 interrupt (CC1IE).
3498 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
3499 * @param TIMx Timer instance
3500 * @retval None
3501 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)3502 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
3503 {
3504 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3505 }
3506
3507 /**
3508 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
3509 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
3510 * @param TIMx Timer instance
3511 * @retval State of bit (1 or 0).
3512 */
LL_TIM_IsEnabledIT_CC1(TIM_TypeDef * TIMx)3513 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
3514 {
3515 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
3516 }
3517
3518 /**
3519 * @brief Enable capture/compare 2 interrupt (CC2IE).
3520 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
3521 * @param TIMx Timer instance
3522 * @retval None
3523 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)3524 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
3525 {
3526 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3527 }
3528
3529 /**
3530 * @brief Disable capture/compare 2 interrupt (CC2IE).
3531 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
3532 * @param TIMx Timer instance
3533 * @retval None
3534 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)3535 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
3536 {
3537 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3538 }
3539
3540 /**
3541 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
3542 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
3543 * @param TIMx Timer instance
3544 * @retval State of bit (1 or 0).
3545 */
LL_TIM_IsEnabledIT_CC2(TIM_TypeDef * TIMx)3546 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
3547 {
3548 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
3549 }
3550
3551 /**
3552 * @brief Enable capture/compare 3 interrupt (CC3IE).
3553 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
3554 * @param TIMx Timer instance
3555 * @retval None
3556 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)3557 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
3558 {
3559 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3560 }
3561
3562 /**
3563 * @brief Disable capture/compare 3 interrupt (CC3IE).
3564 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
3565 * @param TIMx Timer instance
3566 * @retval None
3567 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)3568 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
3569 {
3570 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3571 }
3572
3573 /**
3574 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
3575 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
3576 * @param TIMx Timer instance
3577 * @retval State of bit (1 or 0).
3578 */
LL_TIM_IsEnabledIT_CC3(TIM_TypeDef * TIMx)3579 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
3580 {
3581 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
3582 }
3583
3584 /**
3585 * @brief Enable capture/compare 4 interrupt (CC4IE).
3586 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
3587 * @param TIMx Timer instance
3588 * @retval None
3589 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)3590 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
3591 {
3592 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3593 }
3594
3595 /**
3596 * @brief Disable capture/compare 4 interrupt (CC4IE).
3597 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
3598 * @param TIMx Timer instance
3599 * @retval None
3600 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)3601 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
3602 {
3603 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3604 }
3605
3606 /**
3607 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
3608 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
3609 * @param TIMx Timer instance
3610 * @retval State of bit (1 or 0).
3611 */
LL_TIM_IsEnabledIT_CC4(TIM_TypeDef * TIMx)3612 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
3613 {
3614 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
3615 }
3616
3617 /**
3618 * @brief Enable commutation interrupt (COMIE).
3619 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
3620 * @param TIMx Timer instance
3621 * @retval None
3622 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)3623 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
3624 {
3625 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
3626 }
3627
3628 /**
3629 * @brief Disable commutation interrupt (COMIE).
3630 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
3631 * @param TIMx Timer instance
3632 * @retval None
3633 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)3634 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
3635 {
3636 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
3637 }
3638
3639 /**
3640 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
3641 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
3642 * @param TIMx Timer instance
3643 * @retval State of bit (1 or 0).
3644 */
LL_TIM_IsEnabledIT_COM(TIM_TypeDef * TIMx)3645 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
3646 {
3647 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
3648 }
3649
3650 /**
3651 * @brief Enable trigger interrupt (TIE).
3652 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
3653 * @param TIMx Timer instance
3654 * @retval None
3655 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)3656 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
3657 {
3658 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
3659 }
3660
3661 /**
3662 * @brief Disable trigger interrupt (TIE).
3663 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
3664 * @param TIMx Timer instance
3665 * @retval None
3666 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)3667 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
3668 {
3669 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
3670 }
3671
3672 /**
3673 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
3674 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
3675 * @param TIMx Timer instance
3676 * @retval State of bit (1 or 0).
3677 */
LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef * TIMx)3678 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
3679 {
3680 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
3681 }
3682
3683 /**
3684 * @brief Enable break interrupt (BIE).
3685 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
3686 * @param TIMx Timer instance
3687 * @retval None
3688 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)3689 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
3690 {
3691 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
3692 }
3693
3694 /**
3695 * @brief Disable break interrupt (BIE).
3696 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
3697 * @param TIMx Timer instance
3698 * @retval None
3699 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)3700 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
3701 {
3702 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
3703 }
3704
3705 /**
3706 * @brief Indicates whether the break interrupt (BIE) is enabled.
3707 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
3708 * @param TIMx Timer instance
3709 * @retval State of bit (1 or 0).
3710 */
LL_TIM_IsEnabledIT_BRK(TIM_TypeDef * TIMx)3711 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
3712 {
3713 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
3714 }
3715
3716 /**
3717 * @}
3718 */
3719
3720 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
3721 * @{
3722 */
3723 /**
3724 * @brief Enable update DMA request (UDE).
3725 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
3726 * @param TIMx Timer instance
3727 * @retval None
3728 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)3729 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3730 {
3731 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
3732 }
3733
3734 /**
3735 * @brief Disable update DMA request (UDE).
3736 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
3737 * @param TIMx Timer instance
3738 * @retval None
3739 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)3740 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3741 {
3742 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
3743 }
3744
3745 /**
3746 * @brief Indicates whether the update DMA request (UDE) is enabled.
3747 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
3748 * @param TIMx Timer instance
3749 * @retval State of bit (1 or 0).
3750 */
LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef * TIMx)3751 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
3752 {
3753 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
3754 }
3755
3756 /**
3757 * @brief Enable capture/compare 1 DMA request (CC1DE).
3758 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
3759 * @param TIMx Timer instance
3760 * @retval None
3761 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)3762 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
3763 {
3764 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3765 }
3766
3767 /**
3768 * @brief Disable capture/compare 1 DMA request (CC1DE).
3769 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
3770 * @param TIMx Timer instance
3771 * @retval None
3772 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)3773 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
3774 {
3775 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3776 }
3777
3778 /**
3779 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
3780 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
3781 * @param TIMx Timer instance
3782 * @retval State of bit (1 or 0).
3783 */
LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef * TIMx)3784 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
3785 {
3786 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
3787 }
3788
3789 /**
3790 * @brief Enable capture/compare 2 DMA request (CC2DE).
3791 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
3792 * @param TIMx Timer instance
3793 * @retval None
3794 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)3795 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
3796 {
3797 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3798 }
3799
3800 /**
3801 * @brief Disable capture/compare 2 DMA request (CC2DE).
3802 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
3803 * @param TIMx Timer instance
3804 * @retval None
3805 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)3806 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
3807 {
3808 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3809 }
3810
3811 /**
3812 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
3813 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
3814 * @param TIMx Timer instance
3815 * @retval State of bit (1 or 0).
3816 */
LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef * TIMx)3817 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
3818 {
3819 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
3820 }
3821
3822 /**
3823 * @brief Enable capture/compare 3 DMA request (CC3DE).
3824 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
3825 * @param TIMx Timer instance
3826 * @retval None
3827 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)3828 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
3829 {
3830 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3831 }
3832
3833 /**
3834 * @brief Disable capture/compare 3 DMA request (CC3DE).
3835 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
3836 * @param TIMx Timer instance
3837 * @retval None
3838 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)3839 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
3840 {
3841 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3842 }
3843
3844 /**
3845 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
3846 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
3847 * @param TIMx Timer instance
3848 * @retval State of bit (1 or 0).
3849 */
LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef * TIMx)3850 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
3851 {
3852 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
3853 }
3854
3855 /**
3856 * @brief Enable capture/compare 4 DMA request (CC4DE).
3857 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
3858 * @param TIMx Timer instance
3859 * @retval None
3860 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)3861 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
3862 {
3863 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3864 }
3865
3866 /**
3867 * @brief Disable capture/compare 4 DMA request (CC4DE).
3868 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
3869 * @param TIMx Timer instance
3870 * @retval None
3871 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)3872 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
3873 {
3874 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3875 }
3876
3877 /**
3878 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
3879 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
3880 * @param TIMx Timer instance
3881 * @retval State of bit (1 or 0).
3882 */
LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef * TIMx)3883 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
3884 {
3885 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
3886 }
3887
3888 /**
3889 * @brief Enable commutation DMA request (COMDE).
3890 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
3891 * @param TIMx Timer instance
3892 * @retval None
3893 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)3894 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
3895 {
3896 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
3897 }
3898
3899 /**
3900 * @brief Disable commutation DMA request (COMDE).
3901 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
3902 * @param TIMx Timer instance
3903 * @retval None
3904 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)3905 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
3906 {
3907 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
3908 }
3909
3910 /**
3911 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
3912 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
3913 * @param TIMx Timer instance
3914 * @retval State of bit (1 or 0).
3915 */
LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef * TIMx)3916 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
3917 {
3918 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
3919 }
3920
3921 /**
3922 * @brief Enable trigger interrupt (TDE).
3923 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
3924 * @param TIMx Timer instance
3925 * @retval None
3926 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)3927 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
3928 {
3929 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
3930 }
3931
3932 /**
3933 * @brief Disable trigger interrupt (TDE).
3934 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
3935 * @param TIMx Timer instance
3936 * @retval None
3937 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)3938 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
3939 {
3940 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
3941 }
3942
3943 /**
3944 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
3945 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
3946 * @param TIMx Timer instance
3947 * @retval State of bit (1 or 0).
3948 */
LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef * TIMx)3949 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
3950 {
3951 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
3952 }
3953
3954 /**
3955 * @}
3956 */
3957
3958 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
3959 * @{
3960 */
3961 /**
3962 * @brief Generate an update event.
3963 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
3964 * @param TIMx Timer instance
3965 * @retval None
3966 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)3967 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
3968 {
3969 SET_BIT(TIMx->EGR, TIM_EGR_UG);
3970 }
3971
3972 /**
3973 * @brief Generate Capture/Compare 1 event.
3974 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
3975 * @param TIMx Timer instance
3976 * @retval None
3977 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)3978 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
3979 {
3980 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
3981 }
3982
3983 /**
3984 * @brief Generate Capture/Compare 2 event.
3985 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
3986 * @param TIMx Timer instance
3987 * @retval None
3988 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)3989 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
3990 {
3991 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
3992 }
3993
3994 /**
3995 * @brief Generate Capture/Compare 3 event.
3996 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
3997 * @param TIMx Timer instance
3998 * @retval None
3999 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4000 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4001 {
4002 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4003 }
4004
4005 /**
4006 * @brief Generate Capture/Compare 4 event.
4007 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4008 * @param TIMx Timer instance
4009 * @retval None
4010 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4011 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4012 {
4013 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4014 }
4015
4016 /**
4017 * @brief Generate commutation event.
4018 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4019 * @param TIMx Timer instance
4020 * @retval None
4021 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4022 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4023 {
4024 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4025 }
4026
4027 /**
4028 * @brief Generate trigger event.
4029 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4030 * @param TIMx Timer instance
4031 * @retval None
4032 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4033 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4034 {
4035 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4036 }
4037
4038 /**
4039 * @brief Generate break event.
4040 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4041 * @param TIMx Timer instance
4042 * @retval None
4043 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4044 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4045 {
4046 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4047 }
4048
4049 /**
4050 * @}
4051 */
4052
4053 #if defined(USE_FULL_LL_DRIVER)
4054 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4055 * @{
4056 */
4057
4058 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
4059 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4060 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
4061 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4062 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4063 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4064 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4065 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4066 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4067 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4068 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4069 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4070 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4071 /**
4072 * @}
4073 */
4074 #endif /* USE_FULL_LL_DRIVER */
4075
4076 /**
4077 * @}
4078 */
4079
4080 /**
4081 * @}
4082 */
4083
4084 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */
4085
4086 /**
4087 * @}
4088 */
4089
4090 #ifdef __cplusplus
4091 }
4092 #endif
4093
4094 #endif /* __STM32F4xx_LL_TIM_H */
4095 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
4096