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1 /*
2  * Copyright (c) 2021-2023 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_I2S_H
10 #define HPM_I2S_H
11 
12 typedef struct {
13     __RW uint32_t CTRL;                        /* 0x0: Control Register */
14     __R  uint32_t RFIFO_FILLINGS;              /* 0x4: Rx FIFO  Filling Level */
15     __R  uint32_t TFIFO_FILLINGS;              /* 0x8: Tx FIFO  Filling Level */
16     __RW uint32_t FIFO_THRESH;                 /* 0xC: TX/RX FIFO Threshold setting. */
17     __RW uint32_t STA;                         /* 0x10: Status Registers */
18     __R  uint8_t  RESERVED0[12];               /* 0x14 - 0x1F: Reserved */
19     __R  uint32_t RXD[4];                      /* 0x20 - 0x2C: Rx Data0 */
20     __W  uint32_t TXD[4];                      /* 0x30 - 0x3C: Tx Data0 */
21     __R  uint8_t  RESERVED1[16];               /* 0x40 - 0x4F: Reserved */
22     __RW uint32_t CFGR;                        /* 0x50: Configruation Regsiters */
23     __R  uint8_t  RESERVED2[4];                /* 0x54 - 0x57: Reserved */
24     __RW uint32_t MISC_CFGR;                   /* 0x58: Misc configuration Registers */
25     __R  uint8_t  RESERVED3[4];                /* 0x5C - 0x5F: Reserved */
26     __RW uint32_t RXDSLOT[4];                  /* 0x60 - 0x6C: Rx Slots Enable for Rx Data0 */
27     __RW uint32_t TXDSLOT[4];                  /* 0x70 - 0x7C: Tx Slots Enable for Tx Data0. */
28 } I2S_Type;
29 
30 
31 /* Bitfield definition for register: CTRL */
32 /*
33  * SFTRST_RX (RW)
34  *
35  * software reset the RX module if asserted to be 1'b1. Self-clear.
36  */
37 #define I2S_CTRL_SFTRST_RX_MASK (0x40000UL)
38 #define I2S_CTRL_SFTRST_RX_SHIFT (18U)
39 #define I2S_CTRL_SFTRST_RX_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_RX_SHIFT) & I2S_CTRL_SFTRST_RX_MASK)
40 #define I2S_CTRL_SFTRST_RX_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_RX_MASK) >> I2S_CTRL_SFTRST_RX_SHIFT)
41 
42 /*
43  * SFTRST_TX (RW)
44  *
45  * software reset the TX module if asserted to be 1'b1. Self-clear.
46  */
47 #define I2S_CTRL_SFTRST_TX_MASK (0x20000UL)
48 #define I2S_CTRL_SFTRST_TX_SHIFT (17U)
49 #define I2S_CTRL_SFTRST_TX_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_TX_SHIFT) & I2S_CTRL_SFTRST_TX_MASK)
50 #define I2S_CTRL_SFTRST_TX_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_TX_MASK) >> I2S_CTRL_SFTRST_TX_SHIFT)
51 
52 /*
53  * SFTRST_CLKGEN (RW)
54  *
55  * software reset the CLK GEN module if asserted to be 1'b1.  Self-clear.
56  */
57 #define I2S_CTRL_SFTRST_CLKGEN_MASK (0x10000UL)
58 #define I2S_CTRL_SFTRST_CLKGEN_SHIFT (16U)
59 #define I2S_CTRL_SFTRST_CLKGEN_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_CLKGEN_SHIFT) & I2S_CTRL_SFTRST_CLKGEN_MASK)
60 #define I2S_CTRL_SFTRST_CLKGEN_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_CLKGEN_MASK) >> I2S_CTRL_SFTRST_CLKGEN_SHIFT)
61 
62 /*
63  * TXDNIE (RW)
64  *
65  * TX buffer data needed interrupt enable
66  * 0: TXE interrupt masked
67  * 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set.
68  */
69 #define I2S_CTRL_TXDNIE_MASK (0x8000U)
70 #define I2S_CTRL_TXDNIE_SHIFT (15U)
71 #define I2S_CTRL_TXDNIE_SET(x) (((uint32_t)(x) << I2S_CTRL_TXDNIE_SHIFT) & I2S_CTRL_TXDNIE_MASK)
72 #define I2S_CTRL_TXDNIE_GET(x) (((uint32_t)(x) & I2S_CTRL_TXDNIE_MASK) >> I2S_CTRL_TXDNIE_SHIFT)
73 
74 /*
75  * RXDAIE (RW)
76  *
77  * RX buffer data available interrupt enable
78  * 0: RXNE interrupt masked
79  * 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set.
80  */
81 #define I2S_CTRL_RXDAIE_MASK (0x4000U)
82 #define I2S_CTRL_RXDAIE_SHIFT (14U)
83 #define I2S_CTRL_RXDAIE_SET(x) (((uint32_t)(x) << I2S_CTRL_RXDAIE_SHIFT) & I2S_CTRL_RXDAIE_MASK)
84 #define I2S_CTRL_RXDAIE_GET(x) (((uint32_t)(x) & I2S_CTRL_RXDAIE_MASK) >> I2S_CTRL_RXDAIE_SHIFT)
85 
86 /*
87  * ERRIE (RW)
88  *
89  * Error interrupt enable
90  * This bit controls the generation of an interrupt when an error condition  (UD, OV) occurs.
91  * 0: Error interrupt is masked
92  * 1: Error interrupt is enabled
93  */
94 #define I2S_CTRL_ERRIE_MASK (0x2000U)
95 #define I2S_CTRL_ERRIE_SHIFT (13U)
96 #define I2S_CTRL_ERRIE_SET(x) (((uint32_t)(x) << I2S_CTRL_ERRIE_SHIFT) & I2S_CTRL_ERRIE_MASK)
97 #define I2S_CTRL_ERRIE_GET(x) (((uint32_t)(x) & I2S_CTRL_ERRIE_MASK) >> I2S_CTRL_ERRIE_SHIFT)
98 
99 /*
100  * TX_DMA_EN (RW)
101  *
102  * Asserted to use DMA, else to use interrupt
103  */
104 #define I2S_CTRL_TX_DMA_EN_MASK (0x1000U)
105 #define I2S_CTRL_TX_DMA_EN_SHIFT (12U)
106 #define I2S_CTRL_TX_DMA_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_TX_DMA_EN_SHIFT) & I2S_CTRL_TX_DMA_EN_MASK)
107 #define I2S_CTRL_TX_DMA_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_TX_DMA_EN_MASK) >> I2S_CTRL_TX_DMA_EN_SHIFT)
108 
109 /*
110  * RX_DMA_EN (RW)
111  *
112  * Asserted to use DMA, else to use interrupt
113  */
114 #define I2S_CTRL_RX_DMA_EN_MASK (0x800U)
115 #define I2S_CTRL_RX_DMA_EN_SHIFT (11U)
116 #define I2S_CTRL_RX_DMA_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_RX_DMA_EN_SHIFT) & I2S_CTRL_RX_DMA_EN_MASK)
117 #define I2S_CTRL_RX_DMA_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_RX_DMA_EN_MASK) >> I2S_CTRL_RX_DMA_EN_SHIFT)
118 
119 /*
120  * TXFIFOCLR (RW)
121  *
122  * Self-clear
123  */
124 #define I2S_CTRL_TXFIFOCLR_MASK (0x400U)
125 #define I2S_CTRL_TXFIFOCLR_SHIFT (10U)
126 #define I2S_CTRL_TXFIFOCLR_SET(x) (((uint32_t)(x) << I2S_CTRL_TXFIFOCLR_SHIFT) & I2S_CTRL_TXFIFOCLR_MASK)
127 #define I2S_CTRL_TXFIFOCLR_GET(x) (((uint32_t)(x) & I2S_CTRL_TXFIFOCLR_MASK) >> I2S_CTRL_TXFIFOCLR_SHIFT)
128 
129 /*
130  * RXFIFOCLR (RW)
131  *
132  * Self-clear
133  */
134 #define I2S_CTRL_RXFIFOCLR_MASK (0x200U)
135 #define I2S_CTRL_RXFIFOCLR_SHIFT (9U)
136 #define I2S_CTRL_RXFIFOCLR_SET(x) (((uint32_t)(x) << I2S_CTRL_RXFIFOCLR_SHIFT) & I2S_CTRL_RXFIFOCLR_MASK)
137 #define I2S_CTRL_RXFIFOCLR_GET(x) (((uint32_t)(x) & I2S_CTRL_RXFIFOCLR_MASK) >> I2S_CTRL_RXFIFOCLR_SHIFT)
138 
139 /*
140  * TX_EN (RW)
141  *
142  * enable for each TX data pad
143  */
144 #define I2S_CTRL_TX_EN_MASK (0x1E0U)
145 #define I2S_CTRL_TX_EN_SHIFT (5U)
146 #define I2S_CTRL_TX_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_TX_EN_SHIFT) & I2S_CTRL_TX_EN_MASK)
147 #define I2S_CTRL_TX_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_TX_EN_MASK) >> I2S_CTRL_TX_EN_SHIFT)
148 
149 /*
150  * RX_EN (RW)
151  *
152  * enable for each RX data pad
153  */
154 #define I2S_CTRL_RX_EN_MASK (0x1EU)
155 #define I2S_CTRL_RX_EN_SHIFT (1U)
156 #define I2S_CTRL_RX_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_RX_EN_SHIFT) & I2S_CTRL_RX_EN_MASK)
157 #define I2S_CTRL_RX_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_RX_EN_MASK) >> I2S_CTRL_RX_EN_SHIFT)
158 
159 /*
160  * I2S_EN (RW)
161  *
162  * enable for the module
163  */
164 #define I2S_CTRL_I2S_EN_MASK (0x1U)
165 #define I2S_CTRL_I2S_EN_SHIFT (0U)
166 #define I2S_CTRL_I2S_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_I2S_EN_SHIFT) & I2S_CTRL_I2S_EN_MASK)
167 #define I2S_CTRL_I2S_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_I2S_EN_MASK) >> I2S_CTRL_I2S_EN_SHIFT)
168 
169 /* Bitfield definition for register: RFIFO_FILLINGS */
170 /*
171  * RX3 (RO)
172  *
173  * RX3 fifo fillings
174  */
175 #define I2S_RFIFO_FILLINGS_RX3_MASK (0xFF000000UL)
176 #define I2S_RFIFO_FILLINGS_RX3_SHIFT (24U)
177 #define I2S_RFIFO_FILLINGS_RX3_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX3_MASK) >> I2S_RFIFO_FILLINGS_RX3_SHIFT)
178 
179 /*
180  * RX2 (RO)
181  *
182  * RX2 fifo fillings
183  */
184 #define I2S_RFIFO_FILLINGS_RX2_MASK (0xFF0000UL)
185 #define I2S_RFIFO_FILLINGS_RX2_SHIFT (16U)
186 #define I2S_RFIFO_FILLINGS_RX2_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX2_MASK) >> I2S_RFIFO_FILLINGS_RX2_SHIFT)
187 
188 /*
189  * RX1 (RO)
190  *
191  * RX1 fifo fillings
192  */
193 #define I2S_RFIFO_FILLINGS_RX1_MASK (0xFF00U)
194 #define I2S_RFIFO_FILLINGS_RX1_SHIFT (8U)
195 #define I2S_RFIFO_FILLINGS_RX1_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX1_MASK) >> I2S_RFIFO_FILLINGS_RX1_SHIFT)
196 
197 /*
198  * RX0 (RO)
199  *
200  * RX0 fifo fillings
201  */
202 #define I2S_RFIFO_FILLINGS_RX0_MASK (0xFFU)
203 #define I2S_RFIFO_FILLINGS_RX0_SHIFT (0U)
204 #define I2S_RFIFO_FILLINGS_RX0_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX0_MASK) >> I2S_RFIFO_FILLINGS_RX0_SHIFT)
205 
206 /* Bitfield definition for register: TFIFO_FILLINGS */
207 /*
208  * TX3 (RO)
209  *
210  * TX3 fifo fillings
211  */
212 #define I2S_TFIFO_FILLINGS_TX3_MASK (0xFF000000UL)
213 #define I2S_TFIFO_FILLINGS_TX3_SHIFT (24U)
214 #define I2S_TFIFO_FILLINGS_TX3_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX3_MASK) >> I2S_TFIFO_FILLINGS_TX3_SHIFT)
215 
216 /*
217  * TX2 (RO)
218  *
219  * TX2 fifo fillings
220  */
221 #define I2S_TFIFO_FILLINGS_TX2_MASK (0xFF0000UL)
222 #define I2S_TFIFO_FILLINGS_TX2_SHIFT (16U)
223 #define I2S_TFIFO_FILLINGS_TX2_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX2_MASK) >> I2S_TFIFO_FILLINGS_TX2_SHIFT)
224 
225 /*
226  * TX1 (RO)
227  *
228  * TX1 fifo fillings
229  */
230 #define I2S_TFIFO_FILLINGS_TX1_MASK (0xFF00U)
231 #define I2S_TFIFO_FILLINGS_TX1_SHIFT (8U)
232 #define I2S_TFIFO_FILLINGS_TX1_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX1_MASK) >> I2S_TFIFO_FILLINGS_TX1_SHIFT)
233 
234 /*
235  * TX0 (RO)
236  *
237  * TX0 fifo fillings
238  */
239 #define I2S_TFIFO_FILLINGS_TX0_MASK (0xFFU)
240 #define I2S_TFIFO_FILLINGS_TX0_SHIFT (0U)
241 #define I2S_TFIFO_FILLINGS_TX0_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX0_MASK) >> I2S_TFIFO_FILLINGS_TX0_SHIFT)
242 
243 /* Bitfield definition for register: FIFO_THRESH */
244 /*
245  * TX (RW)
246  *
247  * TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag.
248  */
249 #define I2S_FIFO_THRESH_TX_MASK (0xFF00U)
250 #define I2S_FIFO_THRESH_TX_SHIFT (8U)
251 #define I2S_FIFO_THRESH_TX_SET(x) (((uint32_t)(x) << I2S_FIFO_THRESH_TX_SHIFT) & I2S_FIFO_THRESH_TX_MASK)
252 #define I2S_FIFO_THRESH_TX_GET(x) (((uint32_t)(x) & I2S_FIFO_THRESH_TX_MASK) >> I2S_FIFO_THRESH_TX_SHIFT)
253 
254 /*
255  * RX (RW)
256  *
257  * RX fifo threshold to trigger STA[rx_da].  When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag.
258  */
259 #define I2S_FIFO_THRESH_RX_MASK (0xFFU)
260 #define I2S_FIFO_THRESH_RX_SHIFT (0U)
261 #define I2S_FIFO_THRESH_RX_SET(x) (((uint32_t)(x) << I2S_FIFO_THRESH_RX_SHIFT) & I2S_FIFO_THRESH_RX_MASK)
262 #define I2S_FIFO_THRESH_RX_GET(x) (((uint32_t)(x) & I2S_FIFO_THRESH_RX_MASK) >> I2S_FIFO_THRESH_RX_SHIFT)
263 
264 /* Bitfield definition for register: STA */
265 /*
266  * TX_UD (W1C)
267  *
268  * Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error.
269  */
270 #define I2S_STA_TX_UD_MASK (0x1E000UL)
271 #define I2S_STA_TX_UD_SHIFT (13U)
272 #define I2S_STA_TX_UD_SET(x) (((uint32_t)(x) << I2S_STA_TX_UD_SHIFT) & I2S_STA_TX_UD_MASK)
273 #define I2S_STA_TX_UD_GET(x) (((uint32_t)(x) & I2S_STA_TX_UD_MASK) >> I2S_STA_TX_UD_SHIFT)
274 
275 /*
276  * RX_OV (W1C)
277  *
278  * Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error.
279  */
280 #define I2S_STA_RX_OV_MASK (0x1E00U)
281 #define I2S_STA_RX_OV_SHIFT (9U)
282 #define I2S_STA_RX_OV_SET(x) (((uint32_t)(x) << I2S_STA_RX_OV_SHIFT) & I2S_STA_RX_OV_MASK)
283 #define I2S_STA_RX_OV_GET(x) (((uint32_t)(x) & I2S_STA_RX_OV_MASK) >> I2S_STA_RX_OV_SHIFT)
284 
285 /*
286  * TX_DN (RO)
287  *
288  * Asserted when tx fifo data are needed.
289  */
290 #define I2S_STA_TX_DN_MASK (0x1E0U)
291 #define I2S_STA_TX_DN_SHIFT (5U)
292 #define I2S_STA_TX_DN_GET(x) (((uint32_t)(x) & I2S_STA_TX_DN_MASK) >> I2S_STA_TX_DN_SHIFT)
293 
294 /*
295  * RX_DA (RO)
296  *
297  * Asserted when rx fifo data are available.
298  */
299 #define I2S_STA_RX_DA_MASK (0x1EU)
300 #define I2S_STA_RX_DA_SHIFT (1U)
301 #define I2S_STA_RX_DA_GET(x) (((uint32_t)(x) & I2S_STA_RX_DA_MASK) >> I2S_STA_RX_DA_SHIFT)
302 
303 /* Bitfield definition for register array: RXD */
304 /*
305  * D (RO)
306  *
307  */
308 #define I2S_RXD_D_MASK (0xFFFFFFFFUL)
309 #define I2S_RXD_D_SHIFT (0U)
310 #define I2S_RXD_D_GET(x) (((uint32_t)(x) & I2S_RXD_D_MASK) >> I2S_RXD_D_SHIFT)
311 
312 /* Bitfield definition for register array: TXD */
313 /*
314  * D (WO)
315  *
316  */
317 #define I2S_TXD_D_MASK (0xFFFFFFFFUL)
318 #define I2S_TXD_D_SHIFT (0U)
319 #define I2S_TXD_D_SET(x) (((uint32_t)(x) << I2S_TXD_D_SHIFT) & I2S_TXD_D_MASK)
320 #define I2S_TXD_D_GET(x) (((uint32_t)(x) & I2S_TXD_D_MASK) >> I2S_TXD_D_SHIFT)
321 
322 /* Bitfield definition for register: CFGR */
323 /*
324  * BCLK_GATEOFF (RW)
325  *
326  * Gate off the bclk. Asserted to gate-off the BCLK.
327  */
328 #define I2S_CFGR_BCLK_GATEOFF_MASK (0x40000000UL)
329 #define I2S_CFGR_BCLK_GATEOFF_SHIFT (30U)
330 #define I2S_CFGR_BCLK_GATEOFF_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_GATEOFF_SHIFT) & I2S_CFGR_BCLK_GATEOFF_MASK)
331 #define I2S_CFGR_BCLK_GATEOFF_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_GATEOFF_MASK) >> I2S_CFGR_BCLK_GATEOFF_SHIFT)
332 
333 /*
334  * BCLK_DIV (RW)
335  *
336  * Linear prescaler to generate BCLK from MCLK.
337  * BCLK_DIV [8:0] = 0: BCLK=No CLK.
338  * BCLK_DIV [8:0] = 1: BCLK=MCLK/1
339  * BCLK_DIV [8:0] = n: BCLK=MCLK/(n).
340  * Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode.
341  */
342 #define I2S_CFGR_BCLK_DIV_MASK (0x3FE00000UL)
343 #define I2S_CFGR_BCLK_DIV_SHIFT (21U)
344 #define I2S_CFGR_BCLK_DIV_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_DIV_SHIFT) & I2S_CFGR_BCLK_DIV_MASK)
345 #define I2S_CFGR_BCLK_DIV_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_DIV_MASK) >> I2S_CFGR_BCLK_DIV_SHIFT)
346 
347 /*
348  * INV_BCLK_OUT (RW)
349  *
350  * Invert the BCLK before sending it out to pad. Only valid in BCLK master mode
351  */
352 #define I2S_CFGR_INV_BCLK_OUT_MASK (0x100000UL)
353 #define I2S_CFGR_INV_BCLK_OUT_SHIFT (20U)
354 #define I2S_CFGR_INV_BCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_BCLK_OUT_SHIFT) & I2S_CFGR_INV_BCLK_OUT_MASK)
355 #define I2S_CFGR_INV_BCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_BCLK_OUT_MASK) >> I2S_CFGR_INV_BCLK_OUT_SHIFT)
356 
357 /*
358  * INV_BCLK_IN (RW)
359  *
360  * Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode
361  */
362 #define I2S_CFGR_INV_BCLK_IN_MASK (0x80000UL)
363 #define I2S_CFGR_INV_BCLK_IN_SHIFT (19U)
364 #define I2S_CFGR_INV_BCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_BCLK_IN_SHIFT) & I2S_CFGR_INV_BCLK_IN_MASK)
365 #define I2S_CFGR_INV_BCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_BCLK_IN_MASK) >> I2S_CFGR_INV_BCLK_IN_SHIFT)
366 
367 /*
368  * INV_FCLK_OUT (RW)
369  *
370  * Invert the FCLK before sending it out to pad. Only valid in FCLK master mode
371  */
372 #define I2S_CFGR_INV_FCLK_OUT_MASK (0x40000UL)
373 #define I2S_CFGR_INV_FCLK_OUT_SHIFT (18U)
374 #define I2S_CFGR_INV_FCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_FCLK_OUT_SHIFT) & I2S_CFGR_INV_FCLK_OUT_MASK)
375 #define I2S_CFGR_INV_FCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_FCLK_OUT_MASK) >> I2S_CFGR_INV_FCLK_OUT_SHIFT)
376 
377 /*
378  * INV_FCLK_IN (RW)
379  *
380  * Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode
381  */
382 #define I2S_CFGR_INV_FCLK_IN_MASK (0x20000UL)
383 #define I2S_CFGR_INV_FCLK_IN_SHIFT (17U)
384 #define I2S_CFGR_INV_FCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_FCLK_IN_SHIFT) & I2S_CFGR_INV_FCLK_IN_MASK)
385 #define I2S_CFGR_INV_FCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_FCLK_IN_MASK) >> I2S_CFGR_INV_FCLK_IN_SHIFT)
386 
387 /*
388  * INV_MCLK_OUT (RW)
389  *
390  * Invert the MCLK before sending it out to pad. Only valid in MCLK master mode
391  */
392 #define I2S_CFGR_INV_MCLK_OUT_MASK (0x10000UL)
393 #define I2S_CFGR_INV_MCLK_OUT_SHIFT (16U)
394 #define I2S_CFGR_INV_MCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_MCLK_OUT_SHIFT) & I2S_CFGR_INV_MCLK_OUT_MASK)
395 #define I2S_CFGR_INV_MCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_MCLK_OUT_MASK) >> I2S_CFGR_INV_MCLK_OUT_SHIFT)
396 
397 /*
398  * INV_MCLK_IN (RW)
399  *
400  * Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode
401  */
402 #define I2S_CFGR_INV_MCLK_IN_MASK (0x8000U)
403 #define I2S_CFGR_INV_MCLK_IN_SHIFT (15U)
404 #define I2S_CFGR_INV_MCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_MCLK_IN_SHIFT) & I2S_CFGR_INV_MCLK_IN_MASK)
405 #define I2S_CFGR_INV_MCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_MCLK_IN_MASK) >> I2S_CFGR_INV_MCLK_IN_SHIFT)
406 
407 /*
408  * BCLK_SEL_OP (RW)
409  *
410  * asserted to use external clk source
411  */
412 #define I2S_CFGR_BCLK_SEL_OP_MASK (0x4000U)
413 #define I2S_CFGR_BCLK_SEL_OP_SHIFT (14U)
414 #define I2S_CFGR_BCLK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_SEL_OP_SHIFT) & I2S_CFGR_BCLK_SEL_OP_MASK)
415 #define I2S_CFGR_BCLK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_SEL_OP_MASK) >> I2S_CFGR_BCLK_SEL_OP_SHIFT)
416 
417 /*
418  * FCLK_SEL_OP (RW)
419  *
420  * asserted to use external clk source
421  */
422 #define I2S_CFGR_FCLK_SEL_OP_MASK (0x2000U)
423 #define I2S_CFGR_FCLK_SEL_OP_SHIFT (13U)
424 #define I2S_CFGR_FCLK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_FCLK_SEL_OP_SHIFT) & I2S_CFGR_FCLK_SEL_OP_MASK)
425 #define I2S_CFGR_FCLK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_FCLK_SEL_OP_MASK) >> I2S_CFGR_FCLK_SEL_OP_SHIFT)
426 
427 /*
428  * MCK_SEL_OP (RW)
429  *
430  * asserted to use external clk source
431  */
432 #define I2S_CFGR_MCK_SEL_OP_MASK (0x1000U)
433 #define I2S_CFGR_MCK_SEL_OP_SHIFT (12U)
434 #define I2S_CFGR_MCK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_MCK_SEL_OP_SHIFT) & I2S_CFGR_MCK_SEL_OP_MASK)
435 #define I2S_CFGR_MCK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_MCK_SEL_OP_MASK) >> I2S_CFGR_MCK_SEL_OP_SHIFT)
436 
437 /*
438  * FRAME_EDGE (RW)
439  *
440  * The start edge of a frame
441  * 0: Falling edge indicates a new frame (Just like standard I2S Philips standard)
442  * 1: Rising edge indicates a new frame
443  */
444 #define I2S_CFGR_FRAME_EDGE_MASK (0x800U)
445 #define I2S_CFGR_FRAME_EDGE_SHIFT (11U)
446 #define I2S_CFGR_FRAME_EDGE_SET(x) (((uint32_t)(x) << I2S_CFGR_FRAME_EDGE_SHIFT) & I2S_CFGR_FRAME_EDGE_MASK)
447 #define I2S_CFGR_FRAME_EDGE_GET(x) (((uint32_t)(x) & I2S_CFGR_FRAME_EDGE_MASK) >> I2S_CFGR_FRAME_EDGE_SHIFT)
448 
449 /*
450  * CH_MAX (RW)
451  *
452  * CH_MAX[4:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2.
453  * It must be an even number, so CH_MAX[0] is always 0.
454  * 5'h2: 2 channels
455  * 5'h4: 4 channels
456  * ...
457  * 5‘h10: 16 channels (max)
458  */
459 #define I2S_CFGR_CH_MAX_MASK (0x7C0U)
460 #define I2S_CFGR_CH_MAX_SHIFT (6U)
461 #define I2S_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << I2S_CFGR_CH_MAX_SHIFT) & I2S_CFGR_CH_MAX_MASK)
462 #define I2S_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & I2S_CFGR_CH_MAX_MASK) >> I2S_CFGR_CH_MAX_SHIFT)
463 
464 /*
465  * TDM_EN (RW)
466  *
467  * TDM mode
468  * 0: not TDM mode
469  * 1: TDM mode
470  */
471 #define I2S_CFGR_TDM_EN_MASK (0x20U)
472 #define I2S_CFGR_TDM_EN_SHIFT (5U)
473 #define I2S_CFGR_TDM_EN_SET(x) (((uint32_t)(x) << I2S_CFGR_TDM_EN_SHIFT) & I2S_CFGR_TDM_EN_MASK)
474 #define I2S_CFGR_TDM_EN_GET(x) (((uint32_t)(x) & I2S_CFGR_TDM_EN_MASK) >> I2S_CFGR_TDM_EN_SHIFT)
475 
476 /*
477  * STD (RW)
478  *
479  * I2S standard selection
480  * 00: I2S Philips standard.
481  * 01: MSB justified standard (left justified)
482  * 10: LSB justified standard (right justified)
483  * 11: PCM standard
484  * Note: For correct operation, these bits should be configured when the I2S is disabled.
485  */
486 #define I2S_CFGR_STD_MASK (0x18U)
487 #define I2S_CFGR_STD_SHIFT (3U)
488 #define I2S_CFGR_STD_SET(x) (((uint32_t)(x) << I2S_CFGR_STD_SHIFT) & I2S_CFGR_STD_MASK)
489 #define I2S_CFGR_STD_GET(x) (((uint32_t)(x) & I2S_CFGR_STD_MASK) >> I2S_CFGR_STD_SHIFT)
490 
491 /*
492  * DATSIZ (RW)
493  *
494  * Data length to be transferred
495  * 00: 16-bit data length
496  * 01: 24-bit data length
497  * 10: 32-bit data length
498  * 11: Not allowed
499  * Note: For correct operation, these bits should be configured when the I2S is disabled.
500  */
501 #define I2S_CFGR_DATSIZ_MASK (0x6U)
502 #define I2S_CFGR_DATSIZ_SHIFT (1U)
503 #define I2S_CFGR_DATSIZ_SET(x) (((uint32_t)(x) << I2S_CFGR_DATSIZ_SHIFT) & I2S_CFGR_DATSIZ_MASK)
504 #define I2S_CFGR_DATSIZ_GET(x) (((uint32_t)(x) & I2S_CFGR_DATSIZ_MASK) >> I2S_CFGR_DATSIZ_SHIFT)
505 
506 /*
507  * CHSIZ (RW)
508  *
509  * Channel length (number of bits per audio channel)
510  * 0: 16-bit wide
511  * 1: 32-bit wide
512  * The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in.
513  * Note: For correct operation, this bit should be configured when the I2S is disabled.
514  */
515 #define I2S_CFGR_CHSIZ_MASK (0x1U)
516 #define I2S_CFGR_CHSIZ_SHIFT (0U)
517 #define I2S_CFGR_CHSIZ_SET(x) (((uint32_t)(x) << I2S_CFGR_CHSIZ_SHIFT) & I2S_CFGR_CHSIZ_MASK)
518 #define I2S_CFGR_CHSIZ_GET(x) (((uint32_t)(x) & I2S_CFGR_CHSIZ_MASK) >> I2S_CFGR_CHSIZ_SHIFT)
519 
520 /* Bitfield definition for register: MISC_CFGR */
521 /*
522  * MCLK_GATEOFF (RW)
523  *
524  * Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk.
525  */
526 #define I2S_MISC_CFGR_MCLK_GATEOFF_MASK (0x2000U)
527 #define I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT (13U)
528 #define I2S_MISC_CFGR_MCLK_GATEOFF_SET(x) (((uint32_t)(x) << I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT) & I2S_MISC_CFGR_MCLK_GATEOFF_MASK)
529 #define I2S_MISC_CFGR_MCLK_GATEOFF_GET(x) (((uint32_t)(x) & I2S_MISC_CFGR_MCLK_GATEOFF_MASK) >> I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT)
530 
531 /*
532  * MCLKOE (RW)
533  *
534  * Master clock output to pad enable
535  * 0: Master clock output is disabled
536  * 1: Master clock output is enabled
537  * Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode.
538  */
539 #define I2S_MISC_CFGR_MCLKOE_MASK (0x1U)
540 #define I2S_MISC_CFGR_MCLKOE_SHIFT (0U)
541 #define I2S_MISC_CFGR_MCLKOE_SET(x) (((uint32_t)(x) << I2S_MISC_CFGR_MCLKOE_SHIFT) & I2S_MISC_CFGR_MCLKOE_MASK)
542 #define I2S_MISC_CFGR_MCLKOE_GET(x) (((uint32_t)(x) & I2S_MISC_CFGR_MCLKOE_MASK) >> I2S_MISC_CFGR_MCLKOE_SHIFT)
543 
544 /* Bitfield definition for register array: RXDSLOT */
545 /*
546  * EN (RW)
547  *
548  */
549 #define I2S_RXDSLOT_EN_MASK (0xFFFFU)
550 #define I2S_RXDSLOT_EN_SHIFT (0U)
551 #define I2S_RXDSLOT_EN_SET(x) (((uint32_t)(x) << I2S_RXDSLOT_EN_SHIFT) & I2S_RXDSLOT_EN_MASK)
552 #define I2S_RXDSLOT_EN_GET(x) (((uint32_t)(x) & I2S_RXDSLOT_EN_MASK) >> I2S_RXDSLOT_EN_SHIFT)
553 
554 /* Bitfield definition for register array: TXDSLOT */
555 /*
556  * EN (RW)
557  *
558  */
559 #define I2S_TXDSLOT_EN_MASK (0xFFFFU)
560 #define I2S_TXDSLOT_EN_SHIFT (0U)
561 #define I2S_TXDSLOT_EN_SET(x) (((uint32_t)(x) << I2S_TXDSLOT_EN_SHIFT) & I2S_TXDSLOT_EN_MASK)
562 #define I2S_TXDSLOT_EN_GET(x) (((uint32_t)(x) & I2S_TXDSLOT_EN_MASK) >> I2S_TXDSLOT_EN_SHIFT)
563 
564 
565 
566 /* RXD register group index macro definition */
567 #define I2S_RXD_DATA0 (0UL)
568 #define I2S_RXD_DATA1 (1UL)
569 #define I2S_RXD_DATA2 (2UL)
570 #define I2S_RXD_DATA3 (3UL)
571 
572 /* TXD register group index macro definition */
573 #define I2S_TXD_DATA0 (0UL)
574 #define I2S_TXD_DATA1 (1UL)
575 #define I2S_TXD_DATA2 (2UL)
576 #define I2S_TXD_DATA3 (3UL)
577 
578 /* RXDSLOT register group index macro definition */
579 #define I2S_RXDSLOT_DATA0 (0UL)
580 #define I2S_RXDSLOT_DATA1 (1UL)
581 #define I2S_RXDSLOT_DATA2 (2UL)
582 #define I2S_RXDSLOT_DATA3 (3UL)
583 
584 /* TXDSLOT register group index macro definition */
585 #define I2S_TXDSLOT_DATA0 (0UL)
586 #define I2S_TXDSLOT_DATA1 (1UL)
587 #define I2S_TXDSLOT_DATA2 (2UL)
588 #define I2S_TXDSLOT_DATA3 (3UL)
589 
590 
591 #endif /* HPM_I2S_H */
592