1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_FFA_H 10 #define HPM_FFA_H 11 12 typedef struct { 13 __RW uint32_t CTRL; /* 0x0: */ 14 __RW uint32_t STATUS; /* 0x4: */ 15 __RW uint32_t INT_EN; /* 0x8: */ 16 __R uint8_t RESERVED0[20]; /* 0xC - 0x1F: Reserved */ 17 __RW uint32_t OP_CTRL; /* 0x20: */ 18 __RW uint32_t OP_CMD; /* 0x24: */ 19 union { 20 __RW uint32_t OP_REG0; /* 0x28: */ 21 __RW uint32_t OP_FIR_MISC; /* 0x28: */ 22 __RW uint32_t OP_FFT_MISC; /* 0x28: */ 23 }; 24 union { 25 __RW uint32_t OP_REG1; /* 0x2C: */ 26 __RW uint32_t OP_FIR_MISC1; /* 0x2C: */ 27 }; 28 union { 29 __RW uint32_t OP_REG2; /* 0x30: */ 30 __RW uint32_t OP_FFT_INRBUF; /* 0x30: */ 31 }; 32 union { 33 __RW uint32_t OP_REG3; /* 0x34: */ 34 __RW uint32_t OP_FIR_INBUF; /* 0x34: */ 35 }; 36 union { 37 __RW uint32_t OP_REG4; /* 0x38: */ 38 __RW uint32_t OP_FIR_COEFBUF; /* 0x38: */ 39 __RW uint32_t OP_FFT_OUTRBUF; /* 0x38: */ 40 }; 41 union { 42 __RW uint32_t OP_REG5; /* 0x3C: */ 43 __RW uint32_t OP_FIR_OUTBUF; /* 0x3C: */ 44 }; 45 __RW uint32_t OP_REG6; /* 0x40: */ 46 __RW uint32_t OP_REG7; /* 0x44: */ 47 } FFA_Type; 48 49 50 /* Bitfield definition for register: CTRL */ 51 /* 52 * SFTRST (RW) 53 * 54 * software reset the module if asserted to be 1. 55 * EN is only active after this bit is zero. 56 */ 57 #define FFA_CTRL_SFTRST_MASK (0x80000000UL) 58 #define FFA_CTRL_SFTRST_SHIFT (31U) 59 #define FFA_CTRL_SFTRST_SET(x) (((uint32_t)(x) << FFA_CTRL_SFTRST_SHIFT) & FFA_CTRL_SFTRST_MASK) 60 #define FFA_CTRL_SFTRST_GET(x) (((uint32_t)(x) & FFA_CTRL_SFTRST_MASK) >> FFA_CTRL_SFTRST_SHIFT) 61 62 /* 63 * EN (RW) 64 * 65 * Asserted to enable the module 66 */ 67 #define FFA_CTRL_EN_MASK (0x1U) 68 #define FFA_CTRL_EN_SHIFT (0U) 69 #define FFA_CTRL_EN_SET(x) (((uint32_t)(x) << FFA_CTRL_EN_SHIFT) & FFA_CTRL_EN_MASK) 70 #define FFA_CTRL_EN_GET(x) (((uint32_t)(x) & FFA_CTRL_EN_MASK) >> FFA_CTRL_EN_SHIFT) 71 72 /* Bitfield definition for register: STATUS */ 73 /* 74 * FIR_OV (W1C) 75 * 76 * FIR Overflow err 77 */ 78 #define FFA_STATUS_FIR_OV_MASK (0x80U) 79 #define FFA_STATUS_FIR_OV_SHIFT (7U) 80 #define FFA_STATUS_FIR_OV_SET(x) (((uint32_t)(x) << FFA_STATUS_FIR_OV_SHIFT) & FFA_STATUS_FIR_OV_MASK) 81 #define FFA_STATUS_FIR_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FIR_OV_MASK) >> FFA_STATUS_FIR_OV_SHIFT) 82 83 /* 84 * FFT_OV (W1C) 85 * 86 * FFT Overflow Err 87 */ 88 #define FFA_STATUS_FFT_OV_MASK (0x40U) 89 #define FFA_STATUS_FFT_OV_SHIFT (6U) 90 #define FFA_STATUS_FFT_OV_SET(x) (((uint32_t)(x) << FFA_STATUS_FFT_OV_SHIFT) & FFA_STATUS_FFT_OV_MASK) 91 #define FFA_STATUS_FFT_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FFT_OV_MASK) >> FFA_STATUS_FFT_OV_SHIFT) 92 93 /* 94 * WR_ERR (W1C) 95 * 96 * AXI Data Write Error 97 */ 98 #define FFA_STATUS_WR_ERR_MASK (0x20U) 99 #define FFA_STATUS_WR_ERR_SHIFT (5U) 100 #define FFA_STATUS_WR_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_WR_ERR_SHIFT) & FFA_STATUS_WR_ERR_MASK) 101 #define FFA_STATUS_WR_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_WR_ERR_MASK) >> FFA_STATUS_WR_ERR_SHIFT) 102 103 /* 104 * RD_NXT_ERR (W1C) 105 * 106 * AXI Read Bus Error for NXT DATA 107 */ 108 #define FFA_STATUS_RD_NXT_ERR_MASK (0x10U) 109 #define FFA_STATUS_RD_NXT_ERR_SHIFT (4U) 110 #define FFA_STATUS_RD_NXT_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_RD_NXT_ERR_SHIFT) & FFA_STATUS_RD_NXT_ERR_MASK) 111 #define FFA_STATUS_RD_NXT_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_NXT_ERR_MASK) >> FFA_STATUS_RD_NXT_ERR_SHIFT) 112 113 /* 114 * RD_ERR (W1C) 115 * 116 * AXI Data Read Error 117 */ 118 #define FFA_STATUS_RD_ERR_MASK (0x8U) 119 #define FFA_STATUS_RD_ERR_SHIFT (3U) 120 #define FFA_STATUS_RD_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_RD_ERR_SHIFT) & FFA_STATUS_RD_ERR_MASK) 121 #define FFA_STATUS_RD_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_ERR_MASK) >> FFA_STATUS_RD_ERR_SHIFT) 122 123 /* 124 * NXT_CMD_RD_DONE (W1C) 125 * 126 * Indicate that next command sequence is already read into the module. 127 */ 128 #define FFA_STATUS_NXT_CMD_RD_DONE_MASK (0x2U) 129 #define FFA_STATUS_NXT_CMD_RD_DONE_SHIFT (1U) 130 #define FFA_STATUS_NXT_CMD_RD_DONE_SET(x) (((uint32_t)(x) << FFA_STATUS_NXT_CMD_RD_DONE_SHIFT) & FFA_STATUS_NXT_CMD_RD_DONE_MASK) 131 #define FFA_STATUS_NXT_CMD_RD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_NXT_CMD_RD_DONE_MASK) >> FFA_STATUS_NXT_CMD_RD_DONE_SHIFT) 132 133 /* 134 * OP_CMD_DONE (W1C) 135 * 136 * Indicate that operation cmd is done, and data are available in system memory. 137 */ 138 #define FFA_STATUS_OP_CMD_DONE_MASK (0x1U) 139 #define FFA_STATUS_OP_CMD_DONE_SHIFT (0U) 140 #define FFA_STATUS_OP_CMD_DONE_SET(x) (((uint32_t)(x) << FFA_STATUS_OP_CMD_DONE_SHIFT) & FFA_STATUS_OP_CMD_DONE_MASK) 141 #define FFA_STATUS_OP_CMD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_OP_CMD_DONE_MASK) >> FFA_STATUS_OP_CMD_DONE_SHIFT) 142 143 /* Bitfield definition for register: INT_EN */ 144 /* 145 * WRSV1 (RW) 146 * 147 * Reserved 148 */ 149 #define FFA_INT_EN_WRSV1_MASK (0xFFFFFF00UL) 150 #define FFA_INT_EN_WRSV1_SHIFT (8U) 151 #define FFA_INT_EN_WRSV1_SET(x) (((uint32_t)(x) << FFA_INT_EN_WRSV1_SHIFT) & FFA_INT_EN_WRSV1_MASK) 152 #define FFA_INT_EN_WRSV1_GET(x) (((uint32_t)(x) & FFA_INT_EN_WRSV1_MASK) >> FFA_INT_EN_WRSV1_SHIFT) 153 154 /* 155 * FIR_OV (RW) 156 * 157 * FIR Overflow err 158 */ 159 #define FFA_INT_EN_FIR_OV_MASK (0x80U) 160 #define FFA_INT_EN_FIR_OV_SHIFT (7U) 161 #define FFA_INT_EN_FIR_OV_SET(x) (((uint32_t)(x) << FFA_INT_EN_FIR_OV_SHIFT) & FFA_INT_EN_FIR_OV_MASK) 162 #define FFA_INT_EN_FIR_OV_GET(x) (((uint32_t)(x) & FFA_INT_EN_FIR_OV_MASK) >> FFA_INT_EN_FIR_OV_SHIFT) 163 164 /* 165 * FFT_OV (RW) 166 * 167 * FFT Overflow Err 168 */ 169 #define FFA_INT_EN_FFT_OV_MASK (0x40U) 170 #define FFA_INT_EN_FFT_OV_SHIFT (6U) 171 #define FFA_INT_EN_FFT_OV_SET(x) (((uint32_t)(x) << FFA_INT_EN_FFT_OV_SHIFT) & FFA_INT_EN_FFT_OV_MASK) 172 #define FFA_INT_EN_FFT_OV_GET(x) (((uint32_t)(x) & FFA_INT_EN_FFT_OV_MASK) >> FFA_INT_EN_FFT_OV_SHIFT) 173 174 /* 175 * WR_ERR (RW) 176 * 177 * Enable Data Write Error interrupt 178 */ 179 #define FFA_INT_EN_WR_ERR_MASK (0x20U) 180 #define FFA_INT_EN_WR_ERR_SHIFT (5U) 181 #define FFA_INT_EN_WR_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_WR_ERR_SHIFT) & FFA_INT_EN_WR_ERR_MASK) 182 #define FFA_INT_EN_WR_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_WR_ERR_MASK) >> FFA_INT_EN_WR_ERR_SHIFT) 183 184 /* 185 * RD_NXT_ERR (RW) 186 * 187 * Enable Read Bus Error for NXT DATA interrupt 188 */ 189 #define FFA_INT_EN_RD_NXT_ERR_MASK (0x10U) 190 #define FFA_INT_EN_RD_NXT_ERR_SHIFT (4U) 191 #define FFA_INT_EN_RD_NXT_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_RD_NXT_ERR_SHIFT) & FFA_INT_EN_RD_NXT_ERR_MASK) 192 #define FFA_INT_EN_RD_NXT_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_RD_NXT_ERR_MASK) >> FFA_INT_EN_RD_NXT_ERR_SHIFT) 193 194 /* 195 * RD_ERR (RW) 196 * 197 * Enable Data Read Error interrupt 198 */ 199 #define FFA_INT_EN_RD_ERR_MASK (0x8U) 200 #define FFA_INT_EN_RD_ERR_SHIFT (3U) 201 #define FFA_INT_EN_RD_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_RD_ERR_SHIFT) & FFA_INT_EN_RD_ERR_MASK) 202 #define FFA_INT_EN_RD_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_RD_ERR_MASK) >> FFA_INT_EN_RD_ERR_SHIFT) 203 204 /* 205 * NXT_CMD_RD_DONE (RW) 206 * 207 * Indicate that next command sequence is already read into the module. 208 */ 209 #define FFA_INT_EN_NXT_CMD_RD_DONE_MASK (0x2U) 210 #define FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT (1U) 211 #define FFA_INT_EN_NXT_CMD_RD_DONE_SET(x) (((uint32_t)(x) << FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT) & FFA_INT_EN_NXT_CMD_RD_DONE_MASK) 212 #define FFA_INT_EN_NXT_CMD_RD_DONE_GET(x) (((uint32_t)(x) & FFA_INT_EN_NXT_CMD_RD_DONE_MASK) >> FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT) 213 214 /* 215 * OP_CMD_DONE (RW) 216 * 217 * Indicate that operation cmd is done, and data are available in system memory. 218 */ 219 #define FFA_INT_EN_OP_CMD_DONE_MASK (0x1U) 220 #define FFA_INT_EN_OP_CMD_DONE_SHIFT (0U) 221 #define FFA_INT_EN_OP_CMD_DONE_SET(x) (((uint32_t)(x) << FFA_INT_EN_OP_CMD_DONE_SHIFT) & FFA_INT_EN_OP_CMD_DONE_MASK) 222 #define FFA_INT_EN_OP_CMD_DONE_GET(x) (((uint32_t)(x) & FFA_INT_EN_OP_CMD_DONE_MASK) >> FFA_INT_EN_OP_CMD_DONE_SHIFT) 223 224 /* Bitfield definition for register: OP_CTRL */ 225 /* 226 * NXT_ADDR (RW) 227 * 228 * The address for the next command. 229 * It will be processed after CUR_CMD is executed and done.. 230 */ 231 #define FFA_OP_CTRL_NXT_ADDR_MASK (0xFFFFFFFCUL) 232 #define FFA_OP_CTRL_NXT_ADDR_SHIFT (2U) 233 #define FFA_OP_CTRL_NXT_ADDR_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_NXT_ADDR_SHIFT) & FFA_OP_CTRL_NXT_ADDR_MASK) 234 #define FFA_OP_CTRL_NXT_ADDR_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_NXT_ADDR_MASK) >> FFA_OP_CTRL_NXT_ADDR_SHIFT) 235 236 /* 237 * NXT_EN (RW) 238 * 239 * Whether NXT_CMD is enabled. 240 * Asserted to enable the NXT_CMD when CUR_CMD is done, or CUR_CMD is not enabled.. 241 */ 242 #define FFA_OP_CTRL_NXT_EN_MASK (0x2U) 243 #define FFA_OP_CTRL_NXT_EN_SHIFT (1U) 244 #define FFA_OP_CTRL_NXT_EN_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_NXT_EN_SHIFT) & FFA_OP_CTRL_NXT_EN_MASK) 245 #define FFA_OP_CTRL_NXT_EN_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_NXT_EN_MASK) >> FFA_OP_CTRL_NXT_EN_SHIFT) 246 247 /* 248 * EN (RW) 249 * 250 * Whether CUR_CMD is enabled. 251 * Asserted to enable the CUR_CMD 252 */ 253 #define FFA_OP_CTRL_EN_MASK (0x1U) 254 #define FFA_OP_CTRL_EN_SHIFT (0U) 255 #define FFA_OP_CTRL_EN_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_EN_SHIFT) & FFA_OP_CTRL_EN_MASK) 256 #define FFA_OP_CTRL_EN_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_EN_MASK) >> FFA_OP_CTRL_EN_SHIFT) 257 258 /* Bitfield definition for register: OP_CMD */ 259 /* 260 * CONJ_C (RW) 261 * 262 * asserted to have conjuate value for coefs in computation 263 */ 264 #define FFA_OP_CMD_CONJ_C_MASK (0x1000000UL) 265 #define FFA_OP_CMD_CONJ_C_SHIFT (24U) 266 #define FFA_OP_CMD_CONJ_C_SET(x) (((uint32_t)(x) << FFA_OP_CMD_CONJ_C_SHIFT) & FFA_OP_CMD_CONJ_C_MASK) 267 #define FFA_OP_CMD_CONJ_C_GET(x) (((uint32_t)(x) & FFA_OP_CMD_CONJ_C_MASK) >> FFA_OP_CMD_CONJ_C_SHIFT) 268 269 /* 270 * CMD (RW) 271 * 272 * The Command Used: 273 * 0: FIR 274 * 2: FFT 275 * Others: Reserved 276 */ 277 #define FFA_OP_CMD_CMD_MASK (0xFC0000UL) 278 #define FFA_OP_CMD_CMD_SHIFT (18U) 279 #define FFA_OP_CMD_CMD_SET(x) (((uint32_t)(x) << FFA_OP_CMD_CMD_SHIFT) & FFA_OP_CMD_CMD_MASK) 280 #define FFA_OP_CMD_CMD_GET(x) (((uint32_t)(x) & FFA_OP_CMD_CMD_MASK) >> FFA_OP_CMD_CMD_SHIFT) 281 282 /* 283 * OUTD_TYPE (RW) 284 * 285 * Output data type: 286 * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 287 */ 288 #define FFA_OP_CMD_OUTD_TYPE_MASK (0x38000UL) 289 #define FFA_OP_CMD_OUTD_TYPE_SHIFT (15U) 290 #define FFA_OP_CMD_OUTD_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_OUTD_TYPE_SHIFT) & FFA_OP_CMD_OUTD_TYPE_MASK) 291 #define FFA_OP_CMD_OUTD_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_OUTD_TYPE_MASK) >> FFA_OP_CMD_OUTD_TYPE_SHIFT) 292 293 /* 294 * COEF_TYPE (RW) 295 * 296 * Coef data type (used for FIR): 297 * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 298 */ 299 #define FFA_OP_CMD_COEF_TYPE_MASK (0x7000U) 300 #define FFA_OP_CMD_COEF_TYPE_SHIFT (12U) 301 #define FFA_OP_CMD_COEF_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_COEF_TYPE_SHIFT) & FFA_OP_CMD_COEF_TYPE_MASK) 302 #define FFA_OP_CMD_COEF_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_COEF_TYPE_MASK) >> FFA_OP_CMD_COEF_TYPE_SHIFT) 303 304 /* 305 * IND_TYPE (RW) 306 * 307 * Input data type: 308 * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 309 */ 310 #define FFA_OP_CMD_IND_TYPE_MASK (0xE00U) 311 #define FFA_OP_CMD_IND_TYPE_SHIFT (9U) 312 #define FFA_OP_CMD_IND_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_IND_TYPE_SHIFT) & FFA_OP_CMD_IND_TYPE_MASK) 313 #define FFA_OP_CMD_IND_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_IND_TYPE_MASK) >> FFA_OP_CMD_IND_TYPE_SHIFT) 314 315 /* 316 * NXT_CMD_LEN (RW) 317 * 318 * The length of nxt commands in 32-bit words 319 */ 320 #define FFA_OP_CMD_NXT_CMD_LEN_MASK (0xFFU) 321 #define FFA_OP_CMD_NXT_CMD_LEN_SHIFT (0U) 322 #define FFA_OP_CMD_NXT_CMD_LEN_SET(x) (((uint32_t)(x) << FFA_OP_CMD_NXT_CMD_LEN_SHIFT) & FFA_OP_CMD_NXT_CMD_LEN_MASK) 323 #define FFA_OP_CMD_NXT_CMD_LEN_GET(x) (((uint32_t)(x) & FFA_OP_CMD_NXT_CMD_LEN_MASK) >> FFA_OP_CMD_NXT_CMD_LEN_SHIFT) 324 325 /* Bitfield definition for register: OP_REG0 */ 326 /* 327 * CT (RW) 328 * 329 * Contents 330 */ 331 #define FFA_OP_REG0_CT_MASK (0xFFFFFFFFUL) 332 #define FFA_OP_REG0_CT_SHIFT (0U) 333 #define FFA_OP_REG0_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG0_CT_SHIFT) & FFA_OP_REG0_CT_MASK) 334 #define FFA_OP_REG0_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG0_CT_MASK) >> FFA_OP_REG0_CT_SHIFT) 335 336 /* Bitfield definition for register: OP_FIR_MISC */ 337 /* 338 * FIR_COEF_TAPS (RW) 339 * 340 * Length of FIR coefs （max 256） 341 */ 342 #define FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK (0x3FFFU) 343 #define FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT (0U) 344 #define FFA_OP_FIR_MISC_FIR_COEF_TAPS_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT) & FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK) 345 #define FFA_OP_FIR_MISC_FIR_COEF_TAPS_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK) >> FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT) 346 347 /* Bitfield definition for register: OP_FFT_MISC */ 348 /* 349 * FFT_LEN (RW) 350 * 351 * FFT length 352 * 0:8, 353 * ..., 354 * n:2^(3+n) 355 */ 356 #define FFA_OP_FFT_MISC_FFT_LEN_MASK (0x780U) 357 #define FFA_OP_FFT_MISC_FFT_LEN_SHIFT (7U) 358 #define FFA_OP_FFT_MISC_FFT_LEN_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_FFT_LEN_SHIFT) & FFA_OP_FFT_MISC_FFT_LEN_MASK) 359 #define FFA_OP_FFT_MISC_FFT_LEN_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_FFT_LEN_MASK) >> FFA_OP_FFT_MISC_FFT_LEN_SHIFT) 360 361 /* 362 * IFFT (RW) 363 * 364 * Asserted to indicate IFFT 365 */ 366 #define FFA_OP_FFT_MISC_IFFT_MASK (0x40U) 367 #define FFA_OP_FFT_MISC_IFFT_SHIFT (6U) 368 #define FFA_OP_FFT_MISC_IFFT_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_IFFT_SHIFT) & FFA_OP_FFT_MISC_IFFT_MASK) 369 #define FFA_OP_FFT_MISC_IFFT_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_IFFT_MASK) >> FFA_OP_FFT_MISC_IFFT_SHIFT) 370 371 /* 372 * TMP_BLK (RW) 373 * 374 * Memory block for indata. Should be assigned as 1 375 */ 376 #define FFA_OP_FFT_MISC_TMP_BLK_MASK (0xCU) 377 #define FFA_OP_FFT_MISC_TMP_BLK_SHIFT (2U) 378 #define FFA_OP_FFT_MISC_TMP_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_TMP_BLK_SHIFT) & FFA_OP_FFT_MISC_TMP_BLK_MASK) 379 #define FFA_OP_FFT_MISC_TMP_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_TMP_BLK_MASK) >> FFA_OP_FFT_MISC_TMP_BLK_SHIFT) 380 381 /* 382 * IND_BLK (RW) 383 * 384 * Memory block for indata. Should be assigned as 0 385 */ 386 #define FFA_OP_FFT_MISC_IND_BLK_MASK (0x3U) 387 #define FFA_OP_FFT_MISC_IND_BLK_SHIFT (0U) 388 #define FFA_OP_FFT_MISC_IND_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_IND_BLK_SHIFT) & FFA_OP_FFT_MISC_IND_BLK_MASK) 389 #define FFA_OP_FFT_MISC_IND_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_IND_BLK_MASK) >> FFA_OP_FFT_MISC_IND_BLK_SHIFT) 390 391 /* Bitfield definition for register: OP_REG1 */ 392 /* 393 * CT (RW) 394 * 395 * Contents 396 */ 397 #define FFA_OP_REG1_CT_MASK (0xFFFFFFFFUL) 398 #define FFA_OP_REG1_CT_SHIFT (0U) 399 #define FFA_OP_REG1_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG1_CT_SHIFT) & FFA_OP_REG1_CT_MASK) 400 #define FFA_OP_REG1_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG1_CT_MASK) >> FFA_OP_REG1_CT_SHIFT) 401 402 /* Bitfield definition for register: OP_FIR_MISC1 */ 403 /* 404 * OUTD_MEM_BLK (RW) 405 * 406 * Should be assigned as 0 407 */ 408 #define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK (0x300000UL) 409 #define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT (20U) 410 #define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK) 411 #define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT) 412 413 /* 414 * COEF_MEM_BLK (RW) 415 * 416 * Should be assigned as 1 417 */ 418 #define FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK (0xC0000UL) 419 #define FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT (18U) 420 #define FFA_OP_FIR_MISC1_COEF_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK) 421 #define FFA_OP_FIR_MISC1_COEF_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT) 422 423 /* 424 * IND_MEM_BLK (RW) 425 * 426 * Should be assigned as 2 427 */ 428 #define FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK (0x30000UL) 429 #define FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT (16U) 430 #define FFA_OP_FIR_MISC1_IND_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK) 431 #define FFA_OP_FIR_MISC1_IND_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT) 432 433 /* 434 * FIR_DATA_TAPS (RW) 435 * 436 * The input data data length 437 */ 438 #define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK (0xFFFFU) 439 #define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT (0U) 440 #define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT) & FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK) 441 #define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK) >> FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT) 442 443 /* Bitfield definition for register: OP_REG2 */ 444 /* 445 * CT (RW) 446 * 447 * Contents 448 */ 449 #define FFA_OP_REG2_CT_MASK (0xFFFFFFFFUL) 450 #define FFA_OP_REG2_CT_SHIFT (0U) 451 #define FFA_OP_REG2_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG2_CT_SHIFT) & FFA_OP_REG2_CT_MASK) 452 #define FFA_OP_REG2_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG2_CT_MASK) >> FFA_OP_REG2_CT_SHIFT) 453 454 /* Bitfield definition for register: OP_FFT_INRBUF */ 455 /* 456 * LOC (RW) 457 * 458 * The input (real) data buffer pointer 459 */ 460 #define FFA_OP_FFT_INRBUF_LOC_MASK (0xFFFFFFFFUL) 461 #define FFA_OP_FFT_INRBUF_LOC_SHIFT (0U) 462 #define FFA_OP_FFT_INRBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FFT_INRBUF_LOC_SHIFT) & FFA_OP_FFT_INRBUF_LOC_MASK) 463 #define FFA_OP_FFT_INRBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FFT_INRBUF_LOC_MASK) >> FFA_OP_FFT_INRBUF_LOC_SHIFT) 464 465 /* Bitfield definition for register: OP_REG3 */ 466 /* 467 * CT (RW) 468 * 469 * Contents 470 */ 471 #define FFA_OP_REG3_CT_MASK (0xFFFFFFFFUL) 472 #define FFA_OP_REG3_CT_SHIFT (0U) 473 #define FFA_OP_REG3_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG3_CT_SHIFT) & FFA_OP_REG3_CT_MASK) 474 #define FFA_OP_REG3_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG3_CT_MASK) >> FFA_OP_REG3_CT_SHIFT) 475 476 /* Bitfield definition for register: OP_FIR_INBUF */ 477 /* 478 * LOC (RW) 479 * 480 * The input data buffer pointer 481 */ 482 #define FFA_OP_FIR_INBUF_LOC_MASK (0xFFFFFFFFUL) 483 #define FFA_OP_FIR_INBUF_LOC_SHIFT (0U) 484 #define FFA_OP_FIR_INBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_INBUF_LOC_SHIFT) & FFA_OP_FIR_INBUF_LOC_MASK) 485 #define FFA_OP_FIR_INBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_INBUF_LOC_MASK) >> FFA_OP_FIR_INBUF_LOC_SHIFT) 486 487 /* Bitfield definition for register: OP_REG4 */ 488 /* 489 * CT (RW) 490 * 491 * Contents 492 */ 493 #define FFA_OP_REG4_CT_MASK (0xFFFFFFFFUL) 494 #define FFA_OP_REG4_CT_SHIFT (0U) 495 #define FFA_OP_REG4_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG4_CT_SHIFT) & FFA_OP_REG4_CT_MASK) 496 #define FFA_OP_REG4_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG4_CT_MASK) >> FFA_OP_REG4_CT_SHIFT) 497 498 /* Bitfield definition for register: OP_FIR_COEFBUF */ 499 /* 500 * LOC (RW) 501 * 502 * The coef buf pointer 503 */ 504 #define FFA_OP_FIR_COEFBUF_LOC_MASK (0xFFFFFFFFUL) 505 #define FFA_OP_FIR_COEFBUF_LOC_SHIFT (0U) 506 #define FFA_OP_FIR_COEFBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_COEFBUF_LOC_SHIFT) & FFA_OP_FIR_COEFBUF_LOC_MASK) 507 #define FFA_OP_FIR_COEFBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_COEFBUF_LOC_MASK) >> FFA_OP_FIR_COEFBUF_LOC_SHIFT) 508 509 /* Bitfield definition for register: OP_FFT_OUTRBUF */ 510 /* 511 * LOC (RW) 512 * 513 * The output (real) data buffer pointer 514 */ 515 #define FFA_OP_FFT_OUTRBUF_LOC_MASK (0xFFFFFFFFUL) 516 #define FFA_OP_FFT_OUTRBUF_LOC_SHIFT (0U) 517 #define FFA_OP_FFT_OUTRBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FFT_OUTRBUF_LOC_SHIFT) & FFA_OP_FFT_OUTRBUF_LOC_MASK) 518 #define FFA_OP_FFT_OUTRBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FFT_OUTRBUF_LOC_MASK) >> FFA_OP_FFT_OUTRBUF_LOC_SHIFT) 519 520 /* Bitfield definition for register: OP_REG5 */ 521 /* 522 * CT (RW) 523 * 524 * Contents 525 */ 526 #define FFA_OP_REG5_CT_MASK (0xFFFFFFFFUL) 527 #define FFA_OP_REG5_CT_SHIFT (0U) 528 #define FFA_OP_REG5_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG5_CT_SHIFT) & FFA_OP_REG5_CT_MASK) 529 #define FFA_OP_REG5_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG5_CT_MASK) >> FFA_OP_REG5_CT_SHIFT) 530 531 /* Bitfield definition for register: OP_FIR_OUTBUF */ 532 /* 533 * LOC (RW) 534 * 535 * The output data buffer pointer. The length of the output buffer should be （FIR_DATA_TAPS - FIR_COEF_TAPS + 1） 536 */ 537 #define FFA_OP_FIR_OUTBUF_LOC_MASK (0xFFFFFFFFUL) 538 #define FFA_OP_FIR_OUTBUF_LOC_SHIFT (0U) 539 #define FFA_OP_FIR_OUTBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_OUTBUF_LOC_SHIFT) & FFA_OP_FIR_OUTBUF_LOC_MASK) 540 #define FFA_OP_FIR_OUTBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_OUTBUF_LOC_MASK) >> FFA_OP_FIR_OUTBUF_LOC_SHIFT) 541 542 /* Bitfield definition for register: OP_REG6 */ 543 /* 544 * CT (RW) 545 * 546 * Contents 547 */ 548 #define FFA_OP_REG6_CT_MASK (0xFFFFFFFFUL) 549 #define FFA_OP_REG6_CT_SHIFT (0U) 550 #define FFA_OP_REG6_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG6_CT_SHIFT) & FFA_OP_REG6_CT_MASK) 551 #define FFA_OP_REG6_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG6_CT_MASK) >> FFA_OP_REG6_CT_SHIFT) 552 553 /* Bitfield definition for register: OP_REG7 */ 554 /* 555 * CT (RW) 556 * 557 * Contents 558 */ 559 #define FFA_OP_REG7_CT_MASK (0xFFFFFFFFUL) 560 #define FFA_OP_REG7_CT_SHIFT (0U) 561 #define FFA_OP_REG7_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG7_CT_SHIFT) & FFA_OP_REG7_CT_MASK) 562 #define FFA_OP_REG7_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG7_CT_MASK) >> FFA_OP_REG7_CT_SHIFT) 563 564 565 566 567 #endif /* HPM_FFA_H */ 568