1 /* 2 // Copyright (C) 2022 Beken Corporation 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef _FLASH_H_ 16 #define _FLASH_H_ 17 18 #include <common/bk_include.h> 19 #if CONFIG_SOC_BK7256XX 20 #include <soc/soc.h> 21 #endif 22 23 #define MODE_STD 0 24 #define MODE_DUAL 1 25 #define MODE_QUAD 2 26 #if CONFIG_SOC_BK7256XX 27 #define FLASH_BASE SOC_FLASH_REG_BASE//(0x44030000) 28 #else 29 #define FLASH_BASE (0x00803000) 30 #endif 31 #define REG_FLASH_OPERATE_SW (FLASH_BASE + 0 * 4) 32 #define ADDR_SW_REG_POSI (0) 33 #define ADDR_SW_REG_MASK (0x00FFFFFF) 34 #define OP_TYPE_SW_POSI (24) 35 #define OP_TYPE_SW_MASK (0x1F) 36 #define OP_SW (0x01UL << 29) 37 #define WP_VALUE (0x01UL << 30) 38 #define BUSY_SW (0x01UL << 31) 39 40 #define REG_FLASH_DATA_SW_FLASH (FLASH_BASE + 1 * 4) 41 42 #define REG_FLASH_DATA_FLASH_SW (FLASH_BASE + 2 * 4) 43 44 #define REG_FLASH_SR_CMD (FLASH_BASE + 3 * 4) 45 46 #define REG_FLASH_RDID_DATA_FLASH (FLASH_BASE + 4 * 4) 47 48 #define REG_FLASH_SR_DATA_CRC_CNT (FLASH_BASE + 5 * 4) 49 #define SR_DATA_FLASH_POSI (0) 50 #define SR_DATA_FLASH_MASK (0xFF) 51 #define CRC_ERROR_COUNT_POSI (8) 52 #define CRC_ERROR_COUNT_MASK (0xFF) 53 #define DATA_FLASH_SW_SEL_POSI (16) 54 #define DATA_FLASH_SW_SEL_MASK (0x07) 55 #define DATA_SW_FLASH_SEL_POSI (19) 56 #define DATA_SW_FLASH_SEL_MASK (0x07) 57 58 #define REG_FLASH_CONF (FLASH_BASE + 7 * 4) 59 #define FLASH_CLK_CONF_POSI (0) 60 #define FLASH_CLK_CONF_MASK (0x0F) 61 #define MODEL_SEL_POSI (4) 62 #define MODEL_SEL_MASK (0x1F) 63 #define FWREN_FLASH_CPU (0x01UL << 9) 64 #define WRSR_DATA_POSI (10) 65 #define WRSR_DATA_MASK (0x00FFFF) 66 #define CRC_EN (0x01UL << 26) 67 68 #define CPU_DATA_WR_POSI (9) 69 #define CPU_DATA_WR_MASK (0x01) 70 71 #define M_VALUE_POST 22 72 #define M_VALUE_MASK 0xFF 73 74 #define LINE_MODE_TWO 2 75 #define LINE_MODE_FOUR 4 76 #define FLASH_DPLL_DIV_VALUE_TEN 3 77 78 typedef enum { 79 FLASH_OPCODE_WREN = 1, 80 FLASH_OPCODE_WRDI = 2, 81 FLASH_OPCODE_RDSR = 3, 82 FLASH_OPCODE_WRSR = 4, 83 FLASH_OPCODE_READ = 5, 84 FLASH_OPCODE_RDSR2 = 6, 85 FLASH_OPCODE_WRSR2 = 7, 86 FLASH_OPCODE_PP = 12, 87 FLASH_OPCODE_SE = 13, 88 FLASH_OPCODE_BE1 = 14, 89 FLASH_OPCODE_BE2 = 15, 90 FLASH_OPCODE_CE = 16, 91 FLASH_OPCODE_DP = 17, 92 FLASH_OPCODE_RFDP = 18, 93 FLASH_OPCODE_RDID = 20, 94 FLASH_OPCODE_HPM = 21, 95 FLASH_OPCODE_CRMR = 22, 96 FLASH_OPCODE_CRMR2 = 23, 97 } FLASH_OPCODE; 98 99 typedef struct { 100 uint32_t flash_id; 101 uint8_t sr_size; 102 uint32_t flash_size; 103 uint8_t line_mode; 104 uint8_t cmp_post; 105 uint8_t protect_post; 106 uint8_t protect_mask; 107 uint16_t protect_all; 108 uint16_t protect_none; 109 uint16_t protect_half; 110 uint16_t unprotect_last_block; 111 uint8_t qe_bit_post; 112 uint8_t qe_bit; 113 uint8_t m_value; 114 uint8_t mode_sel; 115 } flash_config_t; 116 117 /******************************************************************************* 118 * Function Declarations 119 *******************************************************************************/ 120 UINT32 flash_read(char *user_buf, UINT32 count, UINT32 address); 121 UINT32 flash_write(char *user_buf, UINT32 count, UINT32 address); 122 UINT32 flash_ctrl(UINT32 cmd, void *parm); 123 #endif //_FLASH_H_ 124 // eof 125 126