1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_UART_H 10 #define HPM_UART_H 11 12 typedef struct { 13 __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ 14 __RW uint32_t IDLE_CFG; /* 0x4: Idle Configuration Register */ 15 __RW uint32_t ADDR_CFG; /* 0x8: address match config register */ 16 __RW uint32_t IIR2; /* 0xC: Interrupt Identification Register2 */ 17 __RW uint32_t CFG; /* 0x10: Configuration Register */ 18 __RW uint32_t OSCR; /* 0x14: Over Sample Control Register */ 19 __RW uint32_t FCRR; /* 0x18: FIFO Control Register config */ 20 __RW uint32_t MOTO_CFG; /* 0x1C: moto system control register */ 21 union { 22 __R uint32_t RBR; /* 0x20: Receiver Buffer Register (when DLAB = 0) */ 23 __W uint32_t THR; /* 0x20: Transmitter Holding Register (when DLAB = 0) */ 24 __RW uint32_t DLL; /* 0x20: Divisor Latch LSB (when DLAB = 1) */ 25 }; 26 union { 27 __RW uint32_t IER; /* 0x24: Interrupt Enable Register (when DLAB = 0) */ 28 __RW uint32_t DLM; /* 0x24: Divisor Latch MSB (when DLAB = 1) */ 29 }; 30 union { 31 __RW uint32_t IIR; /* 0x28: Interrupt Identification Register */ 32 __W uint32_t FCR; /* 0x28: FIFO Control Register */ 33 }; 34 __RW uint32_t LCR; /* 0x2C: Line Control Register */ 35 __RW uint32_t MCR; /* 0x30: Modem Control Register ( */ 36 __R uint32_t LSR; /* 0x34: Line Status Register */ 37 __R uint32_t MSR; /* 0x38: Modem Status Register */ 38 __RW uint32_t GPR; /* 0x3C: GPR Register */ 39 } UART_Type; 40 41 42 /* Bitfield definition for register: IDLE_CFG */ 43 /* 44 * TX_IDLE_COND (RW) 45 * 46 * IDLE Detection Condition 47 * 0 - Treat as idle if TX pin is logic one 48 * 1 - Treat as idle if UART state machine state is idle 49 */ 50 #define UART_IDLE_CFG_TX_IDLE_COND_MASK (0x2000000UL) 51 #define UART_IDLE_CFG_TX_IDLE_COND_SHIFT (25U) 52 #define UART_IDLE_CFG_TX_IDLE_COND_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_TX_IDLE_COND_SHIFT) & UART_IDLE_CFG_TX_IDLE_COND_MASK) 53 #define UART_IDLE_CFG_TX_IDLE_COND_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_TX_IDLE_COND_MASK) >> UART_IDLE_CFG_TX_IDLE_COND_SHIFT) 54 55 /* 56 * TX_IDLE_EN (RW) 57 * 58 * UART TX Idle Detect Enable 59 * 0 - Disable 60 * 1 - Enable 61 */ 62 #define UART_IDLE_CFG_TX_IDLE_EN_MASK (0x1000000UL) 63 #define UART_IDLE_CFG_TX_IDLE_EN_SHIFT (24U) 64 #define UART_IDLE_CFG_TX_IDLE_EN_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_TX_IDLE_EN_SHIFT) & UART_IDLE_CFG_TX_IDLE_EN_MASK) 65 #define UART_IDLE_CFG_TX_IDLE_EN_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_TX_IDLE_EN_MASK) >> UART_IDLE_CFG_TX_IDLE_EN_SHIFT) 66 67 /* 68 * TX_IDLE_THR (RW) 69 * 70 * Threshold for UART transmit Idle detection (in terms of bits) 71 */ 72 #define UART_IDLE_CFG_TX_IDLE_THR_MASK (0xFF0000UL) 73 #define UART_IDLE_CFG_TX_IDLE_THR_SHIFT (16U) 74 #define UART_IDLE_CFG_TX_IDLE_THR_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_TX_IDLE_THR_SHIFT) & UART_IDLE_CFG_TX_IDLE_THR_MASK) 75 #define UART_IDLE_CFG_TX_IDLE_THR_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_TX_IDLE_THR_MASK) >> UART_IDLE_CFG_TX_IDLE_THR_SHIFT) 76 77 /* 78 * RXEN (RW) 79 * 80 * UART receive enable. 81 * 0 - hold RX input to high, avoide wrong data input when config pinmux 82 * 1 - bypass RX input from PIN 83 * software should set it after config pinmux 84 */ 85 #define UART_IDLE_CFG_RXEN_MASK (0x800U) 86 #define UART_IDLE_CFG_RXEN_SHIFT (11U) 87 #define UART_IDLE_CFG_RXEN_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RXEN_SHIFT) & UART_IDLE_CFG_RXEN_MASK) 88 #define UART_IDLE_CFG_RXEN_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RXEN_MASK) >> UART_IDLE_CFG_RXEN_SHIFT) 89 90 /* 91 * RX_IDLE_COND (RW) 92 * 93 * IDLE Detection Condition 94 * 0 - Treat as idle if RX pin is logic one 95 * 1 - Treat as idle if UART state machine state is idle 96 */ 97 #define UART_IDLE_CFG_RX_IDLE_COND_MASK (0x200U) 98 #define UART_IDLE_CFG_RX_IDLE_COND_SHIFT (9U) 99 #define UART_IDLE_CFG_RX_IDLE_COND_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_COND_SHIFT) & UART_IDLE_CFG_RX_IDLE_COND_MASK) 100 #define UART_IDLE_CFG_RX_IDLE_COND_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_COND_MASK) >> UART_IDLE_CFG_RX_IDLE_COND_SHIFT) 101 102 /* 103 * RX_IDLE_EN (RW) 104 * 105 * UART Idle Detect Enable 106 * 0 - Disable 107 * 1 - Enable 108 * it should be enabled if enable address match feature 109 */ 110 #define UART_IDLE_CFG_RX_IDLE_EN_MASK (0x100U) 111 #define UART_IDLE_CFG_RX_IDLE_EN_SHIFT (8U) 112 #define UART_IDLE_CFG_RX_IDLE_EN_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_EN_SHIFT) & UART_IDLE_CFG_RX_IDLE_EN_MASK) 113 #define UART_IDLE_CFG_RX_IDLE_EN_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_EN_MASK) >> UART_IDLE_CFG_RX_IDLE_EN_SHIFT) 114 115 /* 116 * RX_IDLE_THR (RW) 117 * 118 * Threshold for UART Receive Idle detection (in terms of bits) 119 */ 120 #define UART_IDLE_CFG_RX_IDLE_THR_MASK (0xFFU) 121 #define UART_IDLE_CFG_RX_IDLE_THR_SHIFT (0U) 122 #define UART_IDLE_CFG_RX_IDLE_THR_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_THR_SHIFT) & UART_IDLE_CFG_RX_IDLE_THR_MASK) 123 #define UART_IDLE_CFG_RX_IDLE_THR_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_THR_MASK) >> UART_IDLE_CFG_RX_IDLE_THR_SHIFT) 124 125 /* Bitfield definition for register: ADDR_CFG */ 126 /* 127 * TXEN_9BIT (RW) 128 * 129 * set to use 9bit mode for transmitter, 130 * will set the MSB for the first character as address flag, keep 0 for others. 131 */ 132 #define UART_ADDR_CFG_TXEN_9BIT_MASK (0x100000UL) 133 #define UART_ADDR_CFG_TXEN_9BIT_SHIFT (20U) 134 #define UART_ADDR_CFG_TXEN_9BIT_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_TXEN_9BIT_SHIFT) & UART_ADDR_CFG_TXEN_9BIT_MASK) 135 #define UART_ADDR_CFG_TXEN_9BIT_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_TXEN_9BIT_MASK) >> UART_ADDR_CFG_TXEN_9BIT_SHIFT) 136 137 /* 138 * RXEN_ADDR_MSB (RW) 139 * 140 * set to use MSB as address flag at receiver(actually this is done by software set correct MSB in addr0/addr1). 141 * Clr to use first character as address. 142 * Only needed if enable address match feature 143 */ 144 #define UART_ADDR_CFG_RXEN_ADDR_MSB_MASK (0x80000UL) 145 #define UART_ADDR_CFG_RXEN_ADDR_MSB_SHIFT (19U) 146 #define UART_ADDR_CFG_RXEN_ADDR_MSB_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_RXEN_ADDR_MSB_SHIFT) & UART_ADDR_CFG_RXEN_ADDR_MSB_MASK) 147 #define UART_ADDR_CFG_RXEN_ADDR_MSB_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_RXEN_ADDR_MSB_MASK) >> UART_ADDR_CFG_RXEN_ADDR_MSB_SHIFT) 148 149 /* 150 * RXEN_9BIT (RW) 151 * 152 * set to use 9bit mode for receiver, only valid if rxen_addr_msb is set 153 */ 154 #define UART_ADDR_CFG_RXEN_9BIT_MASK (0x40000UL) 155 #define UART_ADDR_CFG_RXEN_9BIT_SHIFT (18U) 156 #define UART_ADDR_CFG_RXEN_9BIT_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_RXEN_9BIT_SHIFT) & UART_ADDR_CFG_RXEN_9BIT_MASK) 157 #define UART_ADDR_CFG_RXEN_9BIT_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_RXEN_9BIT_MASK) >> UART_ADDR_CFG_RXEN_9BIT_SHIFT) 158 159 /* 160 * A1_EN (RW) 161 * 162 * enable addr1 compare for the first character. 163 * If a1_en OR a0_en, then do not receive data if address not match. 164 * If ~a1_en AND ~a0_en, the receive all data like before. 165 * NOTE: should set idle_tmout_en if enable address match feature 166 */ 167 #define UART_ADDR_CFG_A1_EN_MASK (0x20000UL) 168 #define UART_ADDR_CFG_A1_EN_SHIFT (17U) 169 #define UART_ADDR_CFG_A1_EN_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_A1_EN_SHIFT) & UART_ADDR_CFG_A1_EN_MASK) 170 #define UART_ADDR_CFG_A1_EN_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_A1_EN_MASK) >> UART_ADDR_CFG_A1_EN_SHIFT) 171 172 /* 173 * A0_EN (RW) 174 * 175 * enable addr0 compare for the first character 176 */ 177 #define UART_ADDR_CFG_A0_EN_MASK (0x10000UL) 178 #define UART_ADDR_CFG_A0_EN_SHIFT (16U) 179 #define UART_ADDR_CFG_A0_EN_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_A0_EN_SHIFT) & UART_ADDR_CFG_A0_EN_MASK) 180 #define UART_ADDR_CFG_A0_EN_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_A0_EN_MASK) >> UART_ADDR_CFG_A0_EN_SHIFT) 181 182 /* 183 * ADDR1 (RW) 184 * 185 * address 1 fileld. 186 * in 9bit mode, this is the full address byte. 187 * For other mode(8/7/6/5bit), MSB should be set for address flag. 188 * If want address==0 to be matched at 8bit mode, should set addr1=0x80 189 */ 190 #define UART_ADDR_CFG_ADDR1_MASK (0xFF00U) 191 #define UART_ADDR_CFG_ADDR1_SHIFT (8U) 192 #define UART_ADDR_CFG_ADDR1_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_ADDR1_SHIFT) & UART_ADDR_CFG_ADDR1_MASK) 193 #define UART_ADDR_CFG_ADDR1_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_ADDR1_MASK) >> UART_ADDR_CFG_ADDR1_SHIFT) 194 195 /* 196 * ADDR0 (RW) 197 * 198 * address 0 field. 199 */ 200 #define UART_ADDR_CFG_ADDR0_MASK (0xFFU) 201 #define UART_ADDR_CFG_ADDR0_SHIFT (0U) 202 #define UART_ADDR_CFG_ADDR0_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_ADDR0_SHIFT) & UART_ADDR_CFG_ADDR0_MASK) 203 #define UART_ADDR_CFG_ADDR0_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_ADDR0_MASK) >> UART_ADDR_CFG_ADDR0_SHIFT) 204 205 /* Bitfield definition for register: IIR2 */ 206 /* 207 * RXIDLE_FLAG (W1C) 208 * 209 * UART RX IDLE Flag, assert after rxd high and then rx idle timeout, write one clear 210 * 0 - UART RX is busy 211 * 1 - UART RX is idle 212 */ 213 #define UART_IIR2_RXIDLE_FLAG_MASK (0x80000000UL) 214 #define UART_IIR2_RXIDLE_FLAG_SHIFT (31U) 215 #define UART_IIR2_RXIDLE_FLAG_SET(x) (((uint32_t)(x) << UART_IIR2_RXIDLE_FLAG_SHIFT) & UART_IIR2_RXIDLE_FLAG_MASK) 216 #define UART_IIR2_RXIDLE_FLAG_GET(x) (((uint32_t)(x) & UART_IIR2_RXIDLE_FLAG_MASK) >> UART_IIR2_RXIDLE_FLAG_SHIFT) 217 218 /* 219 * TXIDLE_FLAG (W1C) 220 * 221 * UART TX IDLE Flag, assert after txd high and then tx idle timeout, write one clear 222 * 0 - UART TX is busy 223 * 1 - UART TX is idle 224 */ 225 #define UART_IIR2_TXIDLE_FLAG_MASK (0x40000000UL) 226 #define UART_IIR2_TXIDLE_FLAG_SHIFT (30U) 227 #define UART_IIR2_TXIDLE_FLAG_SET(x) (((uint32_t)(x) << UART_IIR2_TXIDLE_FLAG_SHIFT) & UART_IIR2_TXIDLE_FLAG_MASK) 228 #define UART_IIR2_TXIDLE_FLAG_GET(x) (((uint32_t)(x) & UART_IIR2_TXIDLE_FLAG_MASK) >> UART_IIR2_TXIDLE_FLAG_SHIFT) 229 230 /* 231 * ADDR_MATCH (W1C) 232 * 233 * address match irq status, assert if either address match(and enabled). Write one clear 234 * NOTE: the address byte may not moved by DMA at this point. 235 * User can wait next addr_match_idle irq for the whole data include address 236 */ 237 #define UART_IIR2_ADDR_MATCH_MASK (0x20000000UL) 238 #define UART_IIR2_ADDR_MATCH_SHIFT (29U) 239 #define UART_IIR2_ADDR_MATCH_SET(x) (((uint32_t)(x) << UART_IIR2_ADDR_MATCH_SHIFT) & UART_IIR2_ADDR_MATCH_MASK) 240 #define UART_IIR2_ADDR_MATCH_GET(x) (((uint32_t)(x) & UART_IIR2_ADDR_MATCH_MASK) >> UART_IIR2_ADDR_MATCH_SHIFT) 241 242 /* 243 * ADDR_MATCH_IDLE (W1C) 244 * 245 * address match and idle irq status, assert at rx bus idle if address match event triggered. 246 * Write one clear; 247 */ 248 #define UART_IIR2_ADDR_MATCH_IDLE_MASK (0x10000000UL) 249 #define UART_IIR2_ADDR_MATCH_IDLE_SHIFT (28U) 250 #define UART_IIR2_ADDR_MATCH_IDLE_SET(x) (((uint32_t)(x) << UART_IIR2_ADDR_MATCH_IDLE_SHIFT) & UART_IIR2_ADDR_MATCH_IDLE_MASK) 251 #define UART_IIR2_ADDR_MATCH_IDLE_GET(x) (((uint32_t)(x) & UART_IIR2_ADDR_MATCH_IDLE_MASK) >> UART_IIR2_ADDR_MATCH_IDLE_SHIFT) 252 253 /* 254 * DATA_LOST (W1C) 255 * 256 * assert if data lost before address match status, write one clear; 257 * It will not assert if no address match occurs 258 */ 259 #define UART_IIR2_DATA_LOST_MASK (0x8000000UL) 260 #define UART_IIR2_DATA_LOST_SHIFT (27U) 261 #define UART_IIR2_DATA_LOST_SET(x) (((uint32_t)(x) << UART_IIR2_DATA_LOST_SHIFT) & UART_IIR2_DATA_LOST_MASK) 262 #define UART_IIR2_DATA_LOST_GET(x) (((uint32_t)(x) & UART_IIR2_DATA_LOST_MASK) >> UART_IIR2_DATA_LOST_SHIFT) 263 264 /* 265 * FIFOED (RO) 266 * 267 * FIFOs enabled 268 * These two bits are 1 when bit 0 of the FIFO Control 269 * Register (FIFOE) is set to 1. 270 */ 271 #define UART_IIR2_FIFOED_MASK (0xC0U) 272 #define UART_IIR2_FIFOED_SHIFT (6U) 273 #define UART_IIR2_FIFOED_GET(x) (((uint32_t)(x) & UART_IIR2_FIFOED_MASK) >> UART_IIR2_FIFOED_SHIFT) 274 275 /* 276 * INTRID (RO) 277 * 278 * Interrupt ID, see IIR2 for detail decoding 279 */ 280 #define UART_IIR2_INTRID_MASK (0xFU) 281 #define UART_IIR2_INTRID_SHIFT (0U) 282 #define UART_IIR2_INTRID_GET(x) (((uint32_t)(x) & UART_IIR2_INTRID_MASK) >> UART_IIR2_INTRID_SHIFT) 283 284 /* Bitfield definition for register: CFG */ 285 /* 286 * FIFOSIZE (RO) 287 * 288 * The depth of RXFIFO and TXFIFO 289 * 0: 16-byte FIFO 290 * 1: 32-byte FIFO 291 * 2: 64-byte FIFO 292 * 3: 128-byte FIFO 293 */ 294 #define UART_CFG_FIFOSIZE_MASK (0x3U) 295 #define UART_CFG_FIFOSIZE_SHIFT (0U) 296 #define UART_CFG_FIFOSIZE_GET(x) (((uint32_t)(x) & UART_CFG_FIFOSIZE_MASK) >> UART_CFG_FIFOSIZE_SHIFT) 297 298 /* Bitfield definition for register: OSCR */ 299 /* 300 * OSC (RW) 301 * 302 * Over-sample control 303 * The value must be an even number; any odd value 304 * writes to this field will be converted to an even value. 305 * OSC=0: reserved 306 * OSC<=8: The over-sample ratio is 8 307 * 8 < OSC< 32: The over sample ratio is OSC 308 */ 309 #define UART_OSCR_OSC_MASK (0x1FU) 310 #define UART_OSCR_OSC_SHIFT (0U) 311 #define UART_OSCR_OSC_SET(x) (((uint32_t)(x) << UART_OSCR_OSC_SHIFT) & UART_OSCR_OSC_MASK) 312 #define UART_OSCR_OSC_GET(x) (((uint32_t)(x) & UART_OSCR_OSC_MASK) >> UART_OSCR_OSC_SHIFT) 313 314 /* Bitfield definition for register: FCRR */ 315 /* 316 * FIFOT4EN (RW) 317 * 318 * set to use new 4bit fifo threshold(TFIFOT4 and RFIFOT4) 319 * clr to use 2bit(TFIFOT and RFIFOT) 320 */ 321 #define UART_FCRR_FIFOT4EN_MASK (0x800000UL) 322 #define UART_FCRR_FIFOT4EN_SHIFT (23U) 323 #define UART_FCRR_FIFOT4EN_SET(x) (((uint32_t)(x) << UART_FCRR_FIFOT4EN_SHIFT) & UART_FCRR_FIFOT4EN_MASK) 324 #define UART_FCRR_FIFOT4EN_GET(x) (((uint32_t)(x) & UART_FCRR_FIFOT4EN_MASK) >> UART_FCRR_FIFOT4EN_SHIFT) 325 326 /* 327 * TFIFOT4 (RW) 328 * 329 * txfifo threshold(0 for 1byte, 0xF for 16bytes), uart will send tx_dma_req when data in fifo is less than threshold. 330 */ 331 #define UART_FCRR_TFIFOT4_MASK (0xF0000UL) 332 #define UART_FCRR_TFIFOT4_SHIFT (16U) 333 #define UART_FCRR_TFIFOT4_SET(x) (((uint32_t)(x) << UART_FCRR_TFIFOT4_SHIFT) & UART_FCRR_TFIFOT4_MASK) 334 #define UART_FCRR_TFIFOT4_GET(x) (((uint32_t)(x) & UART_FCRR_TFIFOT4_MASK) >> UART_FCRR_TFIFOT4_SHIFT) 335 336 /* 337 * RFIFOT4 (RW) 338 * 339 * rxfifo threshold(0 for 1byte, 0xF for 16bytes). 340 * Uart will send rx_dma_req if data in fifo reachs the threshold, also will set the rxdata irq if enabled 341 */ 342 #define UART_FCRR_RFIFOT4_MASK (0xF00U) 343 #define UART_FCRR_RFIFOT4_SHIFT (8U) 344 #define UART_FCRR_RFIFOT4_SET(x) (((uint32_t)(x) << UART_FCRR_RFIFOT4_SHIFT) & UART_FCRR_RFIFOT4_MASK) 345 #define UART_FCRR_RFIFOT4_GET(x) (((uint32_t)(x) & UART_FCRR_RFIFOT4_MASK) >> UART_FCRR_RFIFOT4_SHIFT) 346 347 /* 348 * RFIFOT (RW) 349 * 350 * Receiver FIFO trigger level 351 */ 352 #define UART_FCRR_RFIFOT_MASK (0xC0U) 353 #define UART_FCRR_RFIFOT_SHIFT (6U) 354 #define UART_FCRR_RFIFOT_SET(x) (((uint32_t)(x) << UART_FCRR_RFIFOT_SHIFT) & UART_FCRR_RFIFOT_MASK) 355 #define UART_FCRR_RFIFOT_GET(x) (((uint32_t)(x) & UART_FCRR_RFIFOT_MASK) >> UART_FCRR_RFIFOT_SHIFT) 356 357 /* 358 * TFIFOT (RW) 359 * 360 * Transmitter FIFO trigger level 361 */ 362 #define UART_FCRR_TFIFOT_MASK (0x30U) 363 #define UART_FCRR_TFIFOT_SHIFT (4U) 364 #define UART_FCRR_TFIFOT_SET(x) (((uint32_t)(x) << UART_FCRR_TFIFOT_SHIFT) & UART_FCRR_TFIFOT_MASK) 365 #define UART_FCRR_TFIFOT_GET(x) (((uint32_t)(x) & UART_FCRR_TFIFOT_MASK) >> UART_FCRR_TFIFOT_SHIFT) 366 367 /* 368 * DMAE (RW) 369 * 370 * DMA enable 371 * 0: Disable 372 * 1: Enable 373 */ 374 #define UART_FCRR_DMAE_MASK (0x8U) 375 #define UART_FCRR_DMAE_SHIFT (3U) 376 #define UART_FCRR_DMAE_SET(x) (((uint32_t)(x) << UART_FCRR_DMAE_SHIFT) & UART_FCRR_DMAE_MASK) 377 #define UART_FCRR_DMAE_GET(x) (((uint32_t)(x) & UART_FCRR_DMAE_MASK) >> UART_FCRR_DMAE_SHIFT) 378 379 /* 380 * TFIFORST (WO) 381 * 382 * Transmitter FIFO reset 383 * Write 1 to clear all bytes in the TXFIFO and resets its 384 * counter. The Transmitter Shift Register is not cleared. 385 * This bit will automatically be cleared. 386 */ 387 #define UART_FCRR_TFIFORST_MASK (0x4U) 388 #define UART_FCRR_TFIFORST_SHIFT (2U) 389 #define UART_FCRR_TFIFORST_SET(x) (((uint32_t)(x) << UART_FCRR_TFIFORST_SHIFT) & UART_FCRR_TFIFORST_MASK) 390 #define UART_FCRR_TFIFORST_GET(x) (((uint32_t)(x) & UART_FCRR_TFIFORST_MASK) >> UART_FCRR_TFIFORST_SHIFT) 391 392 /* 393 * RFIFORST (WO) 394 * 395 * Receiver FIFO reset 396 * Write 1 to clear all bytes in the RXFIFO and resets its 397 * counter. The Receiver Shift Register is not cleared. 398 * This bit will automatically be cleared. 399 */ 400 #define UART_FCRR_RFIFORST_MASK (0x2U) 401 #define UART_FCRR_RFIFORST_SHIFT (1U) 402 #define UART_FCRR_RFIFORST_SET(x) (((uint32_t)(x) << UART_FCRR_RFIFORST_SHIFT) & UART_FCRR_RFIFORST_MASK) 403 #define UART_FCRR_RFIFORST_GET(x) (((uint32_t)(x) & UART_FCRR_RFIFORST_MASK) >> UART_FCRR_RFIFORST_SHIFT) 404 405 /* 406 * FIFOE (RW) 407 * 408 * FIFO enable 409 * Write 1 to enable both the transmitter and receiver 410 * FIFOs. 411 * The FIFOs are reset when the value of this bit toggles. 412 */ 413 #define UART_FCRR_FIFOE_MASK (0x1U) 414 #define UART_FCRR_FIFOE_SHIFT (0U) 415 #define UART_FCRR_FIFOE_SET(x) (((uint32_t)(x) << UART_FCRR_FIFOE_SHIFT) & UART_FCRR_FIFOE_MASK) 416 #define UART_FCRR_FIFOE_GET(x) (((uint32_t)(x) & UART_FCRR_FIFOE_MASK) >> UART_FCRR_FIFOE_SHIFT) 417 418 /* Bitfield definition for register: MOTO_CFG */ 419 /* 420 * SWTRG (WO) 421 * 422 * software trigger. User should avoid use sw/hw trigger at same time, otherwise result unknown. 423 * Hardware auto reset. 424 */ 425 #define UART_MOTO_CFG_SWTRG_MASK (0x80000000UL) 426 #define UART_MOTO_CFG_SWTRG_SHIFT (31U) 427 #define UART_MOTO_CFG_SWTRG_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_SWTRG_SHIFT) & UART_MOTO_CFG_SWTRG_MASK) 428 #define UART_MOTO_CFG_SWTRG_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_SWTRG_MASK) >> UART_MOTO_CFG_SWTRG_SHIFT) 429 430 /* 431 * TXSTP_BITS (RW) 432 * 433 * if TXSTOP_INSERT is enabled, the STOP bits to be inserted between each byte. 0 for 1 bit; 0xFF for 256bits 434 */ 435 #define UART_MOTO_CFG_TXSTP_BITS_MASK (0xFF00U) 436 #define UART_MOTO_CFG_TXSTP_BITS_SHIFT (8U) 437 #define UART_MOTO_CFG_TXSTP_BITS_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_TXSTP_BITS_SHIFT) & UART_MOTO_CFG_TXSTP_BITS_MASK) 438 #define UART_MOTO_CFG_TXSTP_BITS_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_TXSTP_BITS_MASK) >> UART_MOTO_CFG_TXSTP_BITS_SHIFT) 439 440 /* 441 * HWTRG_EN (RW) 442 * 443 * set to enable hardware trigger(trigger from moto is shared by other UART) 444 */ 445 #define UART_MOTO_CFG_HWTRG_EN_MASK (0x80U) 446 #define UART_MOTO_CFG_HWTRG_EN_SHIFT (7U) 447 #define UART_MOTO_CFG_HWTRG_EN_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_HWTRG_EN_SHIFT) & UART_MOTO_CFG_HWTRG_EN_MASK) 448 #define UART_MOTO_CFG_HWTRG_EN_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_HWTRG_EN_MASK) >> UART_MOTO_CFG_HWTRG_EN_SHIFT) 449 450 /* 451 * TRG_MODE (RW) 452 * 453 * set to enable trigger mode. 454 * software should push needed data into txbuffer frist, uart will not start transmission at this time. 455 * User should send trigger signal(by hw or sw), uart will send all data in txfifo till empty 456 * NOTE: the hw_trigger should be pulse signal from trig mux. 457 */ 458 #define UART_MOTO_CFG_TRG_MODE_MASK (0x40U) 459 #define UART_MOTO_CFG_TRG_MODE_SHIFT (6U) 460 #define UART_MOTO_CFG_TRG_MODE_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_TRG_MODE_SHIFT) & UART_MOTO_CFG_TRG_MODE_MASK) 461 #define UART_MOTO_CFG_TRG_MODE_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_TRG_MODE_MASK) >> UART_MOTO_CFG_TRG_MODE_SHIFT) 462 463 /* 464 * TRG_CLR_RFIFO (RW) 465 * 466 * set to enable the feature that, clear rxfifo at tx trigger(sw or hw), avoid unexpected data in rxfifo. 467 */ 468 #define UART_MOTO_CFG_TRG_CLR_RFIFO_MASK (0x20U) 469 #define UART_MOTO_CFG_TRG_CLR_RFIFO_SHIFT (5U) 470 #define UART_MOTO_CFG_TRG_CLR_RFIFO_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_TRG_CLR_RFIFO_SHIFT) & UART_MOTO_CFG_TRG_CLR_RFIFO_MASK) 471 #define UART_MOTO_CFG_TRG_CLR_RFIFO_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_TRG_CLR_RFIFO_MASK) >> UART_MOTO_CFG_TRG_CLR_RFIFO_SHIFT) 472 473 /* 474 * TXSTOP_INSERT (RW) 475 * 476 * set to insert STOP bits between each tx byte till tx fifo empty. 477 * NOTE: there will be no 1.5/2 STOP bits if enabled this feature, LCR.STB should be set to 0 if this bit is set 478 */ 479 #define UART_MOTO_CFG_TXSTOP_INSERT_MASK (0x10U) 480 #define UART_MOTO_CFG_TXSTOP_INSERT_SHIFT (4U) 481 #define UART_MOTO_CFG_TXSTOP_INSERT_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_TXSTOP_INSERT_SHIFT) & UART_MOTO_CFG_TXSTOP_INSERT_MASK) 482 #define UART_MOTO_CFG_TXSTOP_INSERT_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_TXSTOP_INSERT_MASK) >> UART_MOTO_CFG_TXSTOP_INSERT_SHIFT) 483 484 /* Bitfield definition for register: RBR */ 485 /* 486 * RBR (RO) 487 * 488 * Receive data read port 489 */ 490 #define UART_RBR_RBR_MASK (0xFFU) 491 #define UART_RBR_RBR_SHIFT (0U) 492 #define UART_RBR_RBR_GET(x) (((uint32_t)(x) & UART_RBR_RBR_MASK) >> UART_RBR_RBR_SHIFT) 493 494 /* Bitfield definition for register: THR */ 495 /* 496 * THR (WO) 497 * 498 * Transmit data write port 499 */ 500 #define UART_THR_THR_MASK (0xFFU) 501 #define UART_THR_THR_SHIFT (0U) 502 #define UART_THR_THR_SET(x) (((uint32_t)(x) << UART_THR_THR_SHIFT) & UART_THR_THR_MASK) 503 #define UART_THR_THR_GET(x) (((uint32_t)(x) & UART_THR_THR_MASK) >> UART_THR_THR_SHIFT) 504 505 /* Bitfield definition for register: DLL */ 506 /* 507 * DLL (RW) 508 * 509 * Least significant byte of the Divisor Latch 510 */ 511 #define UART_DLL_DLL_MASK (0xFFU) 512 #define UART_DLL_DLL_SHIFT (0U) 513 #define UART_DLL_DLL_SET(x) (((uint32_t)(x) << UART_DLL_DLL_SHIFT) & UART_DLL_DLL_MASK) 514 #define UART_DLL_DLL_GET(x) (((uint32_t)(x) & UART_DLL_DLL_MASK) >> UART_DLL_DLL_SHIFT) 515 516 /* Bitfield definition for register: IER */ 517 /* 518 * ERXIDLE (RW) 519 * 520 * Enable Receive Idle interrupt 521 * 0 - Disable Idle interrupt 522 * 1 - Enable Idle interrupt 523 */ 524 #define UART_IER_ERXIDLE_MASK (0x80000000UL) 525 #define UART_IER_ERXIDLE_SHIFT (31U) 526 #define UART_IER_ERXIDLE_SET(x) (((uint32_t)(x) << UART_IER_ERXIDLE_SHIFT) & UART_IER_ERXIDLE_MASK) 527 #define UART_IER_ERXIDLE_GET(x) (((uint32_t)(x) & UART_IER_ERXIDLE_MASK) >> UART_IER_ERXIDLE_SHIFT) 528 529 /* 530 * ETXIDLE (RW) 531 * 532 * enable transmit idle interrupt 533 */ 534 #define UART_IER_ETXIDLE_MASK (0x40000000UL) 535 #define UART_IER_ETXIDLE_SHIFT (30U) 536 #define UART_IER_ETXIDLE_SET(x) (((uint32_t)(x) << UART_IER_ETXIDLE_SHIFT) & UART_IER_ETXIDLE_MASK) 537 #define UART_IER_ETXIDLE_GET(x) (((uint32_t)(x) & UART_IER_ETXIDLE_MASK) >> UART_IER_ETXIDLE_SHIFT) 538 539 /* 540 * EADDRM (RW) 541 * 542 * enable ADDR_MATCH interrupt 543 */ 544 #define UART_IER_EADDRM_MASK (0x20000000UL) 545 #define UART_IER_EADDRM_SHIFT (29U) 546 #define UART_IER_EADDRM_SET(x) (((uint32_t)(x) << UART_IER_EADDRM_SHIFT) & UART_IER_EADDRM_MASK) 547 #define UART_IER_EADDRM_GET(x) (((uint32_t)(x) & UART_IER_EADDRM_MASK) >> UART_IER_EADDRM_SHIFT) 548 549 /* 550 * EADDRM_IDLE (RW) 551 * 552 * enable ADDR_MATCH_IDLE interrupt 553 */ 554 #define UART_IER_EADDRM_IDLE_MASK (0x10000000UL) 555 #define UART_IER_EADDRM_IDLE_SHIFT (28U) 556 #define UART_IER_EADDRM_IDLE_SET(x) (((uint32_t)(x) << UART_IER_EADDRM_IDLE_SHIFT) & UART_IER_EADDRM_IDLE_MASK) 557 #define UART_IER_EADDRM_IDLE_GET(x) (((uint32_t)(x) & UART_IER_EADDRM_IDLE_MASK) >> UART_IER_EADDRM_IDLE_SHIFT) 558 559 /* 560 * EDATLOST (RW) 561 * 562 * enable DATA_LOST interrupt 563 */ 564 #define UART_IER_EDATLOST_MASK (0x8000000UL) 565 #define UART_IER_EDATLOST_SHIFT (27U) 566 #define UART_IER_EDATLOST_SET(x) (((uint32_t)(x) << UART_IER_EDATLOST_SHIFT) & UART_IER_EDATLOST_MASK) 567 #define UART_IER_EDATLOST_GET(x) (((uint32_t)(x) & UART_IER_EDATLOST_MASK) >> UART_IER_EDATLOST_SHIFT) 568 569 /* 570 * EMSI (RW) 571 * 572 * Enable modem status interrupt 573 * The interrupt asserts when the status of one of the 574 * following occurs: 575 * The status of modem_rin, modem_dcdn, 576 * modem_dsrn or modem_ctsn (If the auto-cts mode is 577 * disabled) has been changed. 578 * If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), 579 * modem_ctsn would be used to control the transmitter. 580 */ 581 #define UART_IER_EMSI_MASK (0x8U) 582 #define UART_IER_EMSI_SHIFT (3U) 583 #define UART_IER_EMSI_SET(x) (((uint32_t)(x) << UART_IER_EMSI_SHIFT) & UART_IER_EMSI_MASK) 584 #define UART_IER_EMSI_GET(x) (((uint32_t)(x) & UART_IER_EMSI_MASK) >> UART_IER_EMSI_SHIFT) 585 586 /* 587 * ELSI (RW) 588 * 589 * Enable receiver line status interrupt 590 */ 591 #define UART_IER_ELSI_MASK (0x4U) 592 #define UART_IER_ELSI_SHIFT (2U) 593 #define UART_IER_ELSI_SET(x) (((uint32_t)(x) << UART_IER_ELSI_SHIFT) & UART_IER_ELSI_MASK) 594 #define UART_IER_ELSI_GET(x) (((uint32_t)(x) & UART_IER_ELSI_MASK) >> UART_IER_ELSI_SHIFT) 595 596 /* 597 * ETHEI (RW) 598 * 599 * Enable transmitter holding register interrupt 600 */ 601 #define UART_IER_ETHEI_MASK (0x2U) 602 #define UART_IER_ETHEI_SHIFT (1U) 603 #define UART_IER_ETHEI_SET(x) (((uint32_t)(x) << UART_IER_ETHEI_SHIFT) & UART_IER_ETHEI_MASK) 604 #define UART_IER_ETHEI_GET(x) (((uint32_t)(x) & UART_IER_ETHEI_MASK) >> UART_IER_ETHEI_SHIFT) 605 606 /* 607 * ERBI (RW) 608 * 609 * Enable received data available interrupt and the 610 * character timeout interrupt 611 * 0: Disable 612 * 1: Enable 613 */ 614 #define UART_IER_ERBI_MASK (0x1U) 615 #define UART_IER_ERBI_SHIFT (0U) 616 #define UART_IER_ERBI_SET(x) (((uint32_t)(x) << UART_IER_ERBI_SHIFT) & UART_IER_ERBI_MASK) 617 #define UART_IER_ERBI_GET(x) (((uint32_t)(x) & UART_IER_ERBI_MASK) >> UART_IER_ERBI_SHIFT) 618 619 /* Bitfield definition for register: DLM */ 620 /* 621 * DLM (RW) 622 * 623 * Most significant byte of the Divisor Latch 624 */ 625 #define UART_DLM_DLM_MASK (0xFFU) 626 #define UART_DLM_DLM_SHIFT (0U) 627 #define UART_DLM_DLM_SET(x) (((uint32_t)(x) << UART_DLM_DLM_SHIFT) & UART_DLM_DLM_MASK) 628 #define UART_DLM_DLM_GET(x) (((uint32_t)(x) & UART_DLM_DLM_MASK) >> UART_DLM_DLM_SHIFT) 629 630 /* Bitfield definition for register: IIR */ 631 /* 632 * RXIDLE_FLAG (W1C) 633 * 634 * UART IDLE Flag 635 * 0 - UART is busy 636 * 1 - UART is idle 637 * NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR 638 */ 639 #define UART_IIR_RXIDLE_FLAG_MASK (0x80000000UL) 640 #define UART_IIR_RXIDLE_FLAG_SHIFT (31U) 641 #define UART_IIR_RXIDLE_FLAG_SET(x) (((uint32_t)(x) << UART_IIR_RXIDLE_FLAG_SHIFT) & UART_IIR_RXIDLE_FLAG_MASK) 642 #define UART_IIR_RXIDLE_FLAG_GET(x) (((uint32_t)(x) & UART_IIR_RXIDLE_FLAG_MASK) >> UART_IIR_RXIDLE_FLAG_SHIFT) 643 644 /* 645 * FIFOED (RO) 646 * 647 * FIFOs enabled 648 * These two bits are 1 when bit 0 of the FIFO Control 649 * Register (FIFOE) is set to 1. 650 */ 651 #define UART_IIR_FIFOED_MASK (0xC0U) 652 #define UART_IIR_FIFOED_SHIFT (6U) 653 #define UART_IIR_FIFOED_GET(x) (((uint32_t)(x) & UART_IIR_FIFOED_MASK) >> UART_IIR_FIFOED_SHIFT) 654 655 /* 656 * INTRID (RO) 657 * 658 * Interrupt ID, see IIR2 for detail decoding 659 */ 660 #define UART_IIR_INTRID_MASK (0xFU) 661 #define UART_IIR_INTRID_SHIFT (0U) 662 #define UART_IIR_INTRID_GET(x) (((uint32_t)(x) & UART_IIR_INTRID_MASK) >> UART_IIR_INTRID_SHIFT) 663 664 /* Bitfield definition for register: FCR */ 665 /* 666 * RFIFOT (WO) 667 * 668 * Receiver FIFO trigger level 669 */ 670 #define UART_FCR_RFIFOT_MASK (0xC0U) 671 #define UART_FCR_RFIFOT_SHIFT (6U) 672 #define UART_FCR_RFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_RFIFOT_SHIFT) & UART_FCR_RFIFOT_MASK) 673 #define UART_FCR_RFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_RFIFOT_MASK) >> UART_FCR_RFIFOT_SHIFT) 674 675 /* 676 * TFIFOT (WO) 677 * 678 * Transmitter FIFO trigger level 679 */ 680 #define UART_FCR_TFIFOT_MASK (0x30U) 681 #define UART_FCR_TFIFOT_SHIFT (4U) 682 #define UART_FCR_TFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_TFIFOT_SHIFT) & UART_FCR_TFIFOT_MASK) 683 #define UART_FCR_TFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_TFIFOT_MASK) >> UART_FCR_TFIFOT_SHIFT) 684 685 /* 686 * DMAE (WO) 687 * 688 * DMA enable 689 * 0: Disable 690 * 1: Enable 691 */ 692 #define UART_FCR_DMAE_MASK (0x8U) 693 #define UART_FCR_DMAE_SHIFT (3U) 694 #define UART_FCR_DMAE_SET(x) (((uint32_t)(x) << UART_FCR_DMAE_SHIFT) & UART_FCR_DMAE_MASK) 695 #define UART_FCR_DMAE_GET(x) (((uint32_t)(x) & UART_FCR_DMAE_MASK) >> UART_FCR_DMAE_SHIFT) 696 697 /* 698 * TFIFORST (WO) 699 * 700 * Transmitter FIFO reset 701 * Write 1 to clear all bytes in the TXFIFO and resets its 702 * counter. The Transmitter Shift Register is not cleared. 703 * This bit will automatically be cleared. 704 */ 705 #define UART_FCR_TFIFORST_MASK (0x4U) 706 #define UART_FCR_TFIFORST_SHIFT (2U) 707 #define UART_FCR_TFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_TFIFORST_SHIFT) & UART_FCR_TFIFORST_MASK) 708 #define UART_FCR_TFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_TFIFORST_MASK) >> UART_FCR_TFIFORST_SHIFT) 709 710 /* 711 * RFIFORST (WO) 712 * 713 * Receiver FIFO reset 714 * Write 1 to clear all bytes in the RXFIFO and resets its 715 * counter. The Receiver Shift Register is not cleared. 716 * This bit will automatically be cleared. 717 */ 718 #define UART_FCR_RFIFORST_MASK (0x2U) 719 #define UART_FCR_RFIFORST_SHIFT (1U) 720 #define UART_FCR_RFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_RFIFORST_SHIFT) & UART_FCR_RFIFORST_MASK) 721 #define UART_FCR_RFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_RFIFORST_MASK) >> UART_FCR_RFIFORST_SHIFT) 722 723 /* 724 * FIFOE (WO) 725 * 726 * FIFO enable 727 * Write 1 to enable both the transmitter and receiver 728 * FIFOs. 729 * The FIFOs are reset when the value of this bit toggles. 730 */ 731 #define UART_FCR_FIFOE_MASK (0x1U) 732 #define UART_FCR_FIFOE_SHIFT (0U) 733 #define UART_FCR_FIFOE_SET(x) (((uint32_t)(x) << UART_FCR_FIFOE_SHIFT) & UART_FCR_FIFOE_MASK) 734 #define UART_FCR_FIFOE_GET(x) (((uint32_t)(x) & UART_FCR_FIFOE_MASK) >> UART_FCR_FIFOE_SHIFT) 735 736 /* Bitfield definition for register: LCR */ 737 /* 738 * DLAB (RW) 739 * 740 * Divisor latch access bit 741 */ 742 #define UART_LCR_DLAB_MASK (0x80U) 743 #define UART_LCR_DLAB_SHIFT (7U) 744 #define UART_LCR_DLAB_SET(x) (((uint32_t)(x) << UART_LCR_DLAB_SHIFT) & UART_LCR_DLAB_MASK) 745 #define UART_LCR_DLAB_GET(x) (((uint32_t)(x) & UART_LCR_DLAB_MASK) >> UART_LCR_DLAB_SHIFT) 746 747 /* 748 * BC (RW) 749 * 750 * Break control 751 */ 752 #define UART_LCR_BC_MASK (0x40U) 753 #define UART_LCR_BC_SHIFT (6U) 754 #define UART_LCR_BC_SET(x) (((uint32_t)(x) << UART_LCR_BC_SHIFT) & UART_LCR_BC_MASK) 755 #define UART_LCR_BC_GET(x) (((uint32_t)(x) & UART_LCR_BC_MASK) >> UART_LCR_BC_SHIFT) 756 757 /* 758 * SPS (RW) 759 * 760 * Stick parity 761 * 1: Parity bit is constant 0 or 1, depending on bit4 (EPS). 762 * 0: Disable the sticky bit parity. 763 */ 764 #define UART_LCR_SPS_MASK (0x20U) 765 #define UART_LCR_SPS_SHIFT (5U) 766 #define UART_LCR_SPS_SET(x) (((uint32_t)(x) << UART_LCR_SPS_SHIFT) & UART_LCR_SPS_MASK) 767 #define UART_LCR_SPS_GET(x) (((uint32_t)(x) & UART_LCR_SPS_MASK) >> UART_LCR_SPS_SHIFT) 768 769 /* 770 * EPS (RW) 771 * 772 * Even parity select 773 * 1: Even parity (an even number of logic-1 is in the data 774 * and parity bits) 775 * 0: Old parity. 776 */ 777 #define UART_LCR_EPS_MASK (0x10U) 778 #define UART_LCR_EPS_SHIFT (4U) 779 #define UART_LCR_EPS_SET(x) (((uint32_t)(x) << UART_LCR_EPS_SHIFT) & UART_LCR_EPS_MASK) 780 #define UART_LCR_EPS_GET(x) (((uint32_t)(x) & UART_LCR_EPS_MASK) >> UART_LCR_EPS_SHIFT) 781 782 /* 783 * PEN (RW) 784 * 785 * Parity enable 786 * When this bit is set, a parity bit is generated in 787 * transmitted data before the first STOP bit and the parity 788 * bit would be checked for the received data. 789 */ 790 #define UART_LCR_PEN_MASK (0x8U) 791 #define UART_LCR_PEN_SHIFT (3U) 792 #define UART_LCR_PEN_SET(x) (((uint32_t)(x) << UART_LCR_PEN_SHIFT) & UART_LCR_PEN_MASK) 793 #define UART_LCR_PEN_GET(x) (((uint32_t)(x) & UART_LCR_PEN_MASK) >> UART_LCR_PEN_SHIFT) 794 795 /* 796 * STB (RW) 797 * 798 * Number of STOP bits 799 * 0: 1 bits 800 * 1: The number of STOP bit is based on the WLS setting 801 * When WLS = 0, STOP bit is 1.5 bits 802 * When WLS = 1, 2, 3, STOP bit is 2 bits 803 */ 804 #define UART_LCR_STB_MASK (0x4U) 805 #define UART_LCR_STB_SHIFT (2U) 806 #define UART_LCR_STB_SET(x) (((uint32_t)(x) << UART_LCR_STB_SHIFT) & UART_LCR_STB_MASK) 807 #define UART_LCR_STB_GET(x) (((uint32_t)(x) & UART_LCR_STB_MASK) >> UART_LCR_STB_SHIFT) 808 809 /* 810 * WLS (RW) 811 * 812 * Word length setting 813 * 0: 5 bits 814 * 1: 6 bits 815 * 2: 7 bits 816 * 3: 8 bits 817 */ 818 #define UART_LCR_WLS_MASK (0x3U) 819 #define UART_LCR_WLS_SHIFT (0U) 820 #define UART_LCR_WLS_SET(x) (((uint32_t)(x) << UART_LCR_WLS_SHIFT) & UART_LCR_WLS_MASK) 821 #define UART_LCR_WLS_GET(x) (((uint32_t)(x) & UART_LCR_WLS_MASK) >> UART_LCR_WLS_SHIFT) 822 823 /* Bitfield definition for register: MCR */ 824 /* 825 * AFE (RW) 826 * 827 * Auto flow control enable 828 * 0: Disable 829 * 1: The auto-CTS and auto-RTS setting is based on the 830 * RTS bit setting: 831 * When RTS = 0, auto-CTS only 832 * When RTS = 1, auto-CTS and auto-RTS 833 */ 834 #define UART_MCR_AFE_MASK (0x20U) 835 #define UART_MCR_AFE_SHIFT (5U) 836 #define UART_MCR_AFE_SET(x) (((uint32_t)(x) << UART_MCR_AFE_SHIFT) & UART_MCR_AFE_MASK) 837 #define UART_MCR_AFE_GET(x) (((uint32_t)(x) & UART_MCR_AFE_MASK) >> UART_MCR_AFE_SHIFT) 838 839 /* 840 * LOOP (RW) 841 * 842 * Enable loopback mode 843 * 0: Disable 844 * 1: Enable 845 */ 846 #define UART_MCR_LOOP_MASK (0x10U) 847 #define UART_MCR_LOOP_SHIFT (4U) 848 #define UART_MCR_LOOP_SET(x) (((uint32_t)(x) << UART_MCR_LOOP_SHIFT) & UART_MCR_LOOP_MASK) 849 #define UART_MCR_LOOP_GET(x) (((uint32_t)(x) & UART_MCR_LOOP_MASK) >> UART_MCR_LOOP_SHIFT) 850 851 /* 852 * RTS (RW) 853 * 854 * Request to send 855 * This bit controls the modem_rtsn output. 856 * 0: The modem_rtsn output signal will be driven HIGH 857 * 1: The modem_rtsn output signal will be driven LOW 858 */ 859 #define UART_MCR_RTS_MASK (0x2U) 860 #define UART_MCR_RTS_SHIFT (1U) 861 #define UART_MCR_RTS_SET(x) (((uint32_t)(x) << UART_MCR_RTS_SHIFT) & UART_MCR_RTS_MASK) 862 #define UART_MCR_RTS_GET(x) (((uint32_t)(x) & UART_MCR_RTS_MASK) >> UART_MCR_RTS_SHIFT) 863 864 /* Bitfield definition for register: LSR */ 865 /* 866 * RXIDLE (RO) 867 * 868 * rxidle after timeout, clear after rx idle condition not match 869 */ 870 #define UART_LSR_RXIDLE_MASK (0x80000000UL) 871 #define UART_LSR_RXIDLE_SHIFT (31U) 872 #define UART_LSR_RXIDLE_GET(x) (((uint32_t)(x) & UART_LSR_RXIDLE_MASK) >> UART_LSR_RXIDLE_SHIFT) 873 874 /* 875 * TXIDLE (RO) 876 * 877 * txidle after timeout, clear after tx idle condition not match 878 */ 879 #define UART_LSR_TXIDLE_MASK (0x40000000UL) 880 #define UART_LSR_TXIDLE_SHIFT (30U) 881 #define UART_LSR_TXIDLE_GET(x) (((uint32_t)(x) & UART_LSR_TXIDLE_MASK) >> UART_LSR_TXIDLE_SHIFT) 882 883 /* 884 * RFIFO_NUM (RO) 885 * 886 * data bytes in rxfifo not read 887 */ 888 #define UART_LSR_RFIFO_NUM_MASK (0x1F0000UL) 889 #define UART_LSR_RFIFO_NUM_SHIFT (16U) 890 #define UART_LSR_RFIFO_NUM_GET(x) (((uint32_t)(x) & UART_LSR_RFIFO_NUM_MASK) >> UART_LSR_RFIFO_NUM_SHIFT) 891 892 /* 893 * TFIFO_NUM (RO) 894 * 895 * data bytes in txfifo not sent 896 */ 897 #define UART_LSR_TFIFO_NUM_MASK (0x1F00U) 898 #define UART_LSR_TFIFO_NUM_SHIFT (8U) 899 #define UART_LSR_TFIFO_NUM_GET(x) (((uint32_t)(x) & UART_LSR_TFIFO_NUM_MASK) >> UART_LSR_TFIFO_NUM_SHIFT) 900 901 /* 902 * ERRF (RO) 903 * 904 * Error in RXFIFO 905 * In the FIFO mode, this bit is set when there is at least 906 * one parity error, framing error, or line break 907 * associated with data in the RXFIFO. It is cleared when 908 * this register is read and there is no more error for the 909 * rest of data in the RXFIFO. 910 */ 911 #define UART_LSR_ERRF_MASK (0x80U) 912 #define UART_LSR_ERRF_SHIFT (7U) 913 #define UART_LSR_ERRF_GET(x) (((uint32_t)(x) & UART_LSR_ERRF_MASK) >> UART_LSR_ERRF_SHIFT) 914 915 /* 916 * TEMT (RO) 917 * 918 * Transmitter empty 919 * This bit is 1 when the THR (TXFIFO in the FIFO 920 * mode) and the Transmitter Shift Register (TSR) are 921 * both empty. Otherwise, it is zero. 922 */ 923 #define UART_LSR_TEMT_MASK (0x40U) 924 #define UART_LSR_TEMT_SHIFT (6U) 925 #define UART_LSR_TEMT_GET(x) (((uint32_t)(x) & UART_LSR_TEMT_MASK) >> UART_LSR_TEMT_SHIFT) 926 927 /* 928 * THRE (RO) 929 * 930 * Transmitter Holding Register empty 931 * This bit is 1 when the THR (TXFIFO in the FIFO 932 * mode) is empty. Otherwise, it is zero. 933 * If the THRE interrupt is enabled, an interrupt is 934 * triggered when THRE becomes 1. 935 */ 936 #define UART_LSR_THRE_MASK (0x20U) 937 #define UART_LSR_THRE_SHIFT (5U) 938 #define UART_LSR_THRE_GET(x) (((uint32_t)(x) & UART_LSR_THRE_MASK) >> UART_LSR_THRE_SHIFT) 939 940 /* 941 * LBREAK (RO) 942 * 943 * Line break 944 * This bit is set when the uart_sin input signal was held 945 * LOWfor longer than the time for a full-word 946 * transmission. A full-word transmission is the 947 * transmission of the START, data, parity, and STOP 948 * bits. It is cleared when this register is read. 949 * In the FIFO mode, this bit indicates the line break for 950 * the received data at the top of the RXFIFO. 951 */ 952 #define UART_LSR_LBREAK_MASK (0x10U) 953 #define UART_LSR_LBREAK_SHIFT (4U) 954 #define UART_LSR_LBREAK_GET(x) (((uint32_t)(x) & UART_LSR_LBREAK_MASK) >> UART_LSR_LBREAK_SHIFT) 955 956 /* 957 * FE (RO) 958 * 959 * Framing error 960 * This bit is set when the received STOP bit is not 961 * HIGH. It is cleared when this register is read. 962 * In the FIFO mode, this bit indicates the framing error 963 * for the received data at the top of the RXFIFO. 964 */ 965 #define UART_LSR_FE_MASK (0x8U) 966 #define UART_LSR_FE_SHIFT (3U) 967 #define UART_LSR_FE_GET(x) (((uint32_t)(x) & UART_LSR_FE_MASK) >> UART_LSR_FE_SHIFT) 968 969 /* 970 * PE (RO) 971 * 972 * Parity error 973 * This bit is set when the received parity does not match 974 * with the parity selected in the LCR[5:4]. It is cleared 975 * when this register is read. 976 * In the FIFO mode, this bit indicates the parity error 977 * for the received data at the top of the RXFIFO. 978 */ 979 #define UART_LSR_PE_MASK (0x4U) 980 #define UART_LSR_PE_SHIFT (2U) 981 #define UART_LSR_PE_GET(x) (((uint32_t)(x) & UART_LSR_PE_MASK) >> UART_LSR_PE_SHIFT) 982 983 /* 984 * OE (RO) 985 * 986 * Overrun error 987 * This bit indicates that data in the Receiver Buffer 988 * Register (RBR) is overrun. 989 */ 990 #define UART_LSR_OE_MASK (0x2U) 991 #define UART_LSR_OE_SHIFT (1U) 992 #define UART_LSR_OE_GET(x) (((uint32_t)(x) & UART_LSR_OE_MASK) >> UART_LSR_OE_SHIFT) 993 994 /* 995 * DR (RO) 996 * 997 * Data ready. 998 * This bit is set when there are incoming received data 999 * in the Receiver Buffer Register (RBR). It is cleared 1000 * when all of the received data are read. 1001 */ 1002 #define UART_LSR_DR_MASK (0x1U) 1003 #define UART_LSR_DR_SHIFT (0U) 1004 #define UART_LSR_DR_GET(x) (((uint32_t)(x) & UART_LSR_DR_MASK) >> UART_LSR_DR_SHIFT) 1005 1006 /* Bitfield definition for register: MSR */ 1007 /* 1008 * CTS (RO) 1009 * 1010 * Clear to send 1011 * 0: The modem_ctsn input signal is HIGH. 1012 * 1: The modem_ctsn input signal is LOW. 1013 */ 1014 #define UART_MSR_CTS_MASK (0x10U) 1015 #define UART_MSR_CTS_SHIFT (4U) 1016 #define UART_MSR_CTS_GET(x) (((uint32_t)(x) & UART_MSR_CTS_MASK) >> UART_MSR_CTS_SHIFT) 1017 1018 /* 1019 * DCTS (RC) 1020 * 1021 * Delta clear to send 1022 * This bit is set when the state of the modem_ctsn input 1023 * signal has been changed since the last time this 1024 * register is read. 1025 */ 1026 #define UART_MSR_DCTS_MASK (0x1U) 1027 #define UART_MSR_DCTS_SHIFT (0U) 1028 #define UART_MSR_DCTS_GET(x) (((uint32_t)(x) & UART_MSR_DCTS_MASK) >> UART_MSR_DCTS_SHIFT) 1029 1030 /* Bitfield definition for register: GPR */ 1031 /* 1032 * DATA (RW) 1033 * 1034 * An one-byte storage register 1035 */ 1036 #define UART_GPR_DATA_MASK (0xFFU) 1037 #define UART_GPR_DATA_SHIFT (0U) 1038 #define UART_GPR_DATA_SET(x) (((uint32_t)(x) << UART_GPR_DATA_SHIFT) & UART_GPR_DATA_MASK) 1039 #define UART_GPR_DATA_GET(x) (((uint32_t)(x) & UART_GPR_DATA_MASK) >> UART_GPR_DATA_SHIFT) 1040 1041 1042 1043 1044 #endif /* HPM_UART_H */ 1045