1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_PDMA_H 10 #define HPM_PDMA_H 11 12 typedef struct { 13 __RW uint32_t CTRL; /* 0x0: Control Register */ 14 __RW uint32_t STAT; /* 0x4: Status Register */ 15 __RW uint32_t OUT_CTRL; /* 0x8: Out Layer Control Register */ 16 __RW uint32_t OUT_BUF; /* 0xC: Output buffer address */ 17 __R uint8_t RESERVED0[4]; /* 0x10 - 0x13: Reserved */ 18 __RW uint32_t OUT_PITCH; /* 0x14: Outlayer Pitch Register */ 19 __RW uint32_t OUT_LRC; /* 0x18: Output Lower Right Corner Register */ 20 struct { 21 __RW uint32_t ULC; /* 0x1C: Layer Upper Left Corner Register */ 22 __RW uint32_t LRC; /* 0x20: Layer Lower Right Corner Register */ 23 } OUT_PS[2]; 24 __R uint8_t RESERVED1[4]; /* 0x2C - 0x2F: Reserved */ 25 struct { 26 __RW uint32_t CTRL; /* 0x30: Layer Control Register */ 27 __RW uint32_t BUF; /* 0x34: Layer data buffer address */ 28 __R uint8_t RESERVED0[8]; /* 0x38 - 0x3F: Reserved */ 29 __RW uint32_t PITCH; /* 0x40: Layer data pitch register */ 30 __RW uint32_t BKGD; /* 0x44: Layer background color register */ 31 __RW uint32_t SCALE; /* 0x48: Layer scale register */ 32 __RW uint32_t OFFSET; /* 0x4C: Layer offset register */ 33 __RW uint32_t CLRKEY_LOW; /* 0x50: Layer low color key register */ 34 __RW uint32_t CLRKEY_HIGH; /* 0x54: Layer high color key register */ 35 __RW uint32_t ORG; /* 0x58: Layer original size register */ 36 __R uint8_t RESERVED1[4]; /* 0x5C - 0x5F: Reserved */ 37 } PS[2]; 38 __R uint8_t RESERVED2[16]; /* 0x90 - 0x9F: Reserved */ 39 __RW uint32_t YUV2RGB_COEF0; /* 0xA0: YUV2RGB coefficients register 0 */ 40 __RW uint32_t YUV2RGB_COEF1; /* 0xA4: YUV2RGB coefficients register 1 */ 41 __RW uint32_t YUV2RGB_COEF2; /* 0xA8: YUV2RGB coefficients register 2 */ 42 __RW uint32_t RGB2YUV_COEF0; /* 0xAC: RGB2YUV coefficients register 0 */ 43 __RW uint32_t RGB2YUV_COEF1; /* 0xB0: RGB2YUV coefficients register 1 */ 44 __RW uint32_t RGB2YUV_COEF2; /* 0xB4: RGB2YUV coefficients register 2 */ 45 __RW uint32_t RGB2YUV_COEF3; /* 0xB8: RGB2YUV coefficients register 3 */ 46 __RW uint32_t RGB2YUV_COEF4; /* 0xBC: RGB2YUV coefficients register 4 */ 47 } PDMA_Type; 48 49 50 /* Bitfield definition for register: CTRL */ 51 /* 52 * ARQOS (RW) 53 * 54 * QoS for AXI read bus 55 */ 56 #define PDMA_CTRL_ARQOS_MASK (0x780000UL) 57 #define PDMA_CTRL_ARQOS_SHIFT (19U) 58 #define PDMA_CTRL_ARQOS_SET(x) (((uint32_t)(x) << PDMA_CTRL_ARQOS_SHIFT) & PDMA_CTRL_ARQOS_MASK) 59 #define PDMA_CTRL_ARQOS_GET(x) (((uint32_t)(x) & PDMA_CTRL_ARQOS_MASK) >> PDMA_CTRL_ARQOS_SHIFT) 60 61 /* 62 * AWQOS (RW) 63 * 64 * QoS for AXI write bus 65 */ 66 #define PDMA_CTRL_AWQOS_MASK (0x78000UL) 67 #define PDMA_CTRL_AWQOS_SHIFT (15U) 68 #define PDMA_CTRL_AWQOS_SET(x) (((uint32_t)(x) << PDMA_CTRL_AWQOS_SHIFT) & PDMA_CTRL_AWQOS_MASK) 69 #define PDMA_CTRL_AWQOS_GET(x) (((uint32_t)(x) & PDMA_CTRL_AWQOS_MASK) >> PDMA_CTRL_AWQOS_SHIFT) 70 71 /* 72 * PACK_DIR (RW) 73 * 74 * Decide the byte sequence of the 32-bit output word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. 75 * 2'b00: no change {A3, A2, A1, A0} 76 * 2'b01: {A2, A3, A0, A1} 77 * 2'b10: {A1, A0, A3, A2} 78 * 2'b11: {A0, A1, A2, A3} 79 */ 80 #define PDMA_CTRL_PACK_DIR_MASK (0x6000U) 81 #define PDMA_CTRL_PACK_DIR_SHIFT (13U) 82 #define PDMA_CTRL_PACK_DIR_SET(x) (((uint32_t)(x) << PDMA_CTRL_PACK_DIR_SHIFT) & PDMA_CTRL_PACK_DIR_MASK) 83 #define PDMA_CTRL_PACK_DIR_GET(x) (((uint32_t)(x) & PDMA_CTRL_PACK_DIR_MASK) >> PDMA_CTRL_PACK_DIR_SHIFT) 84 85 /* 86 * AXIERR_IRQ_EN (RW) 87 * 88 * Enable interrupt of AXI bus error 89 */ 90 #define PDMA_CTRL_AXIERR_IRQ_EN_MASK (0x1000U) 91 #define PDMA_CTRL_AXIERR_IRQ_EN_SHIFT (12U) 92 #define PDMA_CTRL_AXIERR_IRQ_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_AXIERR_IRQ_EN_SHIFT) & PDMA_CTRL_AXIERR_IRQ_EN_MASK) 93 #define PDMA_CTRL_AXIERR_IRQ_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_AXIERR_IRQ_EN_MASK) >> PDMA_CTRL_AXIERR_IRQ_EN_SHIFT) 94 95 /* 96 * PDMA_DONE_IRQ_EN (RW) 97 * 98 * Enable interrupt of PDMA_DONE 99 */ 100 #define PDMA_CTRL_PDMA_DONE_IRQ_EN_MASK (0x800U) 101 #define PDMA_CTRL_PDMA_DONE_IRQ_EN_SHIFT (11U) 102 #define PDMA_CTRL_PDMA_DONE_IRQ_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_PDMA_DONE_IRQ_EN_SHIFT) & PDMA_CTRL_PDMA_DONE_IRQ_EN_MASK) 103 #define PDMA_CTRL_PDMA_DONE_IRQ_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_PDMA_DONE_IRQ_EN_MASK) >> PDMA_CTRL_PDMA_DONE_IRQ_EN_SHIFT) 104 105 /* 106 * CLKGATE (RW) 107 * 108 * Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. 109 */ 110 #define PDMA_CTRL_CLKGATE_MASK (0x200U) 111 #define PDMA_CTRL_CLKGATE_SHIFT (9U) 112 #define PDMA_CTRL_CLKGATE_SET(x) (((uint32_t)(x) << PDMA_CTRL_CLKGATE_SHIFT) & PDMA_CTRL_CLKGATE_MASK) 113 #define PDMA_CTRL_CLKGATE_GET(x) (((uint32_t)(x) & PDMA_CTRL_CLKGATE_MASK) >> PDMA_CTRL_CLKGATE_SHIFT) 114 115 /* 116 * IRQ_EN (RW) 117 * 118 * Enable normal interrupt 119 */ 120 #define PDMA_CTRL_IRQ_EN_MASK (0x40U) 121 #define PDMA_CTRL_IRQ_EN_SHIFT (6U) 122 #define PDMA_CTRL_IRQ_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_IRQ_EN_SHIFT) & PDMA_CTRL_IRQ_EN_MASK) 123 #define PDMA_CTRL_IRQ_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_IRQ_EN_MASK) >> PDMA_CTRL_IRQ_EN_SHIFT) 124 125 /* 126 * BS16 (RW) 127 * 128 * Asserted when the Block Size is 16x16, else 8x8 129 */ 130 #define PDMA_CTRL_BS16_MASK (0x20U) 131 #define PDMA_CTRL_BS16_SHIFT (5U) 132 #define PDMA_CTRL_BS16_SET(x) (((uint32_t)(x) << PDMA_CTRL_BS16_SHIFT) & PDMA_CTRL_BS16_MASK) 133 #define PDMA_CTRL_BS16_GET(x) (((uint32_t)(x) & PDMA_CTRL_BS16_MASK) >> PDMA_CTRL_BS16_SHIFT) 134 135 /* 136 * P1_EN (RW) 137 * 138 * Plane 1 Enable 139 */ 140 #define PDMA_CTRL_P1_EN_MASK (0x10U) 141 #define PDMA_CTRL_P1_EN_SHIFT (4U) 142 #define PDMA_CTRL_P1_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_P1_EN_SHIFT) & PDMA_CTRL_P1_EN_MASK) 143 #define PDMA_CTRL_P1_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_P1_EN_MASK) >> PDMA_CTRL_P1_EN_SHIFT) 144 145 /* 146 * P0_EN (RW) 147 * 148 * Plane 0 Enable 149 */ 150 #define PDMA_CTRL_P0_EN_MASK (0x8U) 151 #define PDMA_CTRL_P0_EN_SHIFT (3U) 152 #define PDMA_CTRL_P0_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_P0_EN_SHIFT) & PDMA_CTRL_P0_EN_MASK) 153 #define PDMA_CTRL_P0_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_P0_EN_MASK) >> PDMA_CTRL_P0_EN_SHIFT) 154 155 /* 156 * PDMA_SFTRST (RW) 157 * 158 * Software Reset. 159 * Write 1 to clear PDMA internal logic. 160 * Write 0 to exit software reset mode. 161 */ 162 #define PDMA_CTRL_PDMA_SFTRST_MASK (0x2U) 163 #define PDMA_CTRL_PDMA_SFTRST_SHIFT (1U) 164 #define PDMA_CTRL_PDMA_SFTRST_SET(x) (((uint32_t)(x) << PDMA_CTRL_PDMA_SFTRST_SHIFT) & PDMA_CTRL_PDMA_SFTRST_MASK) 165 #define PDMA_CTRL_PDMA_SFTRST_GET(x) (((uint32_t)(x) & PDMA_CTRL_PDMA_SFTRST_MASK) >> PDMA_CTRL_PDMA_SFTRST_SHIFT) 166 167 /* 168 * PDMA_EN (RW) 169 * 170 * 1b - Enabled 171 */ 172 #define PDMA_CTRL_PDMA_EN_MASK (0x1U) 173 #define PDMA_CTRL_PDMA_EN_SHIFT (0U) 174 #define PDMA_CTRL_PDMA_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_PDMA_EN_SHIFT) & PDMA_CTRL_PDMA_EN_MASK) 175 #define PDMA_CTRL_PDMA_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_PDMA_EN_MASK) >> PDMA_CTRL_PDMA_EN_SHIFT) 176 177 /* Bitfield definition for register: STAT */ 178 /* 179 * BLOCKY (RO) 180 * 181 * Y block that is processing 182 */ 183 #define PDMA_STAT_BLOCKY_MASK (0xFF000000UL) 184 #define PDMA_STAT_BLOCKY_SHIFT (24U) 185 #define PDMA_STAT_BLOCKY_GET(x) (((uint32_t)(x) & PDMA_STAT_BLOCKY_MASK) >> PDMA_STAT_BLOCKY_SHIFT) 186 187 /* 188 * BLOCKX (RO) 189 * 190 * X block that is processing 191 */ 192 #define PDMA_STAT_BLOCKX_MASK (0xFF0000UL) 193 #define PDMA_STAT_BLOCKX_SHIFT (16U) 194 #define PDMA_STAT_BLOCKX_GET(x) (((uint32_t)(x) & PDMA_STAT_BLOCKX_MASK) >> PDMA_STAT_BLOCKX_SHIFT) 195 196 /* 197 * PDMA_DONE (W1C) 198 * 199 * PDMA one image done 200 */ 201 #define PDMA_STAT_PDMA_DONE_MASK (0x200U) 202 #define PDMA_STAT_PDMA_DONE_SHIFT (9U) 203 #define PDMA_STAT_PDMA_DONE_SET(x) (((uint32_t)(x) << PDMA_STAT_PDMA_DONE_SHIFT) & PDMA_STAT_PDMA_DONE_MASK) 204 #define PDMA_STAT_PDMA_DONE_GET(x) (((uint32_t)(x) & PDMA_STAT_PDMA_DONE_MASK) >> PDMA_STAT_PDMA_DONE_SHIFT) 205 206 /* 207 * AXI_ERR_ID (RO) 208 * 209 * AXI error ID 210 */ 211 #define PDMA_STAT_AXI_ERR_ID_MASK (0x1E0U) 212 #define PDMA_STAT_AXI_ERR_ID_SHIFT (5U) 213 #define PDMA_STAT_AXI_ERR_ID_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_ERR_ID_MASK) >> PDMA_STAT_AXI_ERR_ID_SHIFT) 214 215 /* 216 * AXI_0_WRITE_ERR (W1C) 217 * 218 * AXI0 write err 219 */ 220 #define PDMA_STAT_AXI_0_WRITE_ERR_MASK (0x10U) 221 #define PDMA_STAT_AXI_0_WRITE_ERR_SHIFT (4U) 222 #define PDMA_STAT_AXI_0_WRITE_ERR_SET(x) (((uint32_t)(x) << PDMA_STAT_AXI_0_WRITE_ERR_SHIFT) & PDMA_STAT_AXI_0_WRITE_ERR_MASK) 223 #define PDMA_STAT_AXI_0_WRITE_ERR_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_0_WRITE_ERR_MASK) >> PDMA_STAT_AXI_0_WRITE_ERR_SHIFT) 224 225 /* 226 * AXI_1_READ_ERR (W1C) 227 * 228 * AXI1 read err 229 */ 230 #define PDMA_STAT_AXI_1_READ_ERR_MASK (0x8U) 231 #define PDMA_STAT_AXI_1_READ_ERR_SHIFT (3U) 232 #define PDMA_STAT_AXI_1_READ_ERR_SET(x) (((uint32_t)(x) << PDMA_STAT_AXI_1_READ_ERR_SHIFT) & PDMA_STAT_AXI_1_READ_ERR_MASK) 233 #define PDMA_STAT_AXI_1_READ_ERR_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_1_READ_ERR_MASK) >> PDMA_STAT_AXI_1_READ_ERR_SHIFT) 234 235 /* 236 * AXI_0_READ_ERR (W1C) 237 * 238 * AXI0 read err 239 */ 240 #define PDMA_STAT_AXI_0_READ_ERR_MASK (0x4U) 241 #define PDMA_STAT_AXI_0_READ_ERR_SHIFT (2U) 242 #define PDMA_STAT_AXI_0_READ_ERR_SET(x) (((uint32_t)(x) << PDMA_STAT_AXI_0_READ_ERR_SHIFT) & PDMA_STAT_AXI_0_READ_ERR_MASK) 243 #define PDMA_STAT_AXI_0_READ_ERR_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_0_READ_ERR_MASK) >> PDMA_STAT_AXI_0_READ_ERR_SHIFT) 244 245 /* 246 * IRQ (RO) 247 * 248 * Asserted to indicate a IRQ event 249 */ 250 #define PDMA_STAT_IRQ_MASK (0x1U) 251 #define PDMA_STAT_IRQ_SHIFT (0U) 252 #define PDMA_STAT_IRQ_GET(x) (((uint32_t)(x) & PDMA_STAT_IRQ_MASK) >> PDMA_STAT_IRQ_SHIFT) 253 254 /* Bitfield definition for register: OUT_CTRL */ 255 /* 256 * DSTALPHA (RW) 257 * 258 * The destination (P1) system ALPHA value. 259 */ 260 #define PDMA_OUT_CTRL_DSTALPHA_MASK (0xFF000000UL) 261 #define PDMA_OUT_CTRL_DSTALPHA_SHIFT (24U) 262 #define PDMA_OUT_CTRL_DSTALPHA_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_DSTALPHA_SHIFT) & PDMA_OUT_CTRL_DSTALPHA_MASK) 263 #define PDMA_OUT_CTRL_DSTALPHA_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_DSTALPHA_MASK) >> PDMA_OUT_CTRL_DSTALPHA_SHIFT) 264 265 /* 266 * SRCALPHA (RW) 267 * 268 * The source (P0) system ALPHA value. 269 */ 270 #define PDMA_OUT_CTRL_SRCALPHA_MASK (0xFF0000UL) 271 #define PDMA_OUT_CTRL_SRCALPHA_SHIFT (16U) 272 #define PDMA_OUT_CTRL_SRCALPHA_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_SRCALPHA_SHIFT) & PDMA_OUT_CTRL_SRCALPHA_MASK) 273 #define PDMA_OUT_CTRL_SRCALPHA_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_SRCALPHA_MASK) >> PDMA_OUT_CTRL_SRCALPHA_SHIFT) 274 275 /* 276 * DSTALPHA_OP (RW) 277 * 278 * The usage of the DSTALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) 279 * 0: the DSTALPHA[7:0] is invalid, use the alpha value embedded in the stream 280 * 1: the DSTALPHA[7:0] is used to override the alpha value embedded in the stream. (useful when the corresponding data stream has no alpha info) 281 * 2: the DSTALPHA[7:0] is used to scale the alpha value embedded in the stream 282 * 3: don't multiply the color data with any alpha values for blender inputs. 283 */ 284 #define PDMA_OUT_CTRL_DSTALPHA_OP_MASK (0xC000U) 285 #define PDMA_OUT_CTRL_DSTALPHA_OP_SHIFT (14U) 286 #define PDMA_OUT_CTRL_DSTALPHA_OP_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_DSTALPHA_OP_SHIFT) & PDMA_OUT_CTRL_DSTALPHA_OP_MASK) 287 #define PDMA_OUT_CTRL_DSTALPHA_OP_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_DSTALPHA_OP_MASK) >> PDMA_OUT_CTRL_DSTALPHA_OP_SHIFT) 288 289 /* 290 * SRCALPHA_OP (RW) 291 * 292 * The usage of the SRCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) 293 * 0: the SRCALPHA[7:0] is invalid, use the alpha value embedded in the stream 294 * 1: the SRCALPHA[7:0] is used to override the alpha value embedded in the stream . (useful when the corresponding data stream has no alpha info) 295 * 2: the SRCALPHA[7:0] is used to scale the alpha value embedded in the stream 296 * 3: don't multiply the color data with any alpha values for blender inputs. 297 */ 298 #define PDMA_OUT_CTRL_SRCALPHA_OP_MASK (0x3000U) 299 #define PDMA_OUT_CTRL_SRCALPHA_OP_SHIFT (12U) 300 #define PDMA_OUT_CTRL_SRCALPHA_OP_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_SRCALPHA_OP_SHIFT) & PDMA_OUT_CTRL_SRCALPHA_OP_MASK) 301 #define PDMA_OUT_CTRL_SRCALPHA_OP_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_SRCALPHA_OP_MASK) >> PDMA_OUT_CTRL_SRCALPHA_OP_SHIFT) 302 303 /* 304 * ABLEND_MODE (RW) 305 * 306 * Alpha Blending Mode 307 * 0: SKBlendMode_Clear (If PS1_CTRL[BKGNDCL4CLR] is asserted, use PS1_BKGRND color to fill the range determined by PS1, else fill the range determined by PS1 with zero); 308 * 1: SKBlendMode_Src ; 309 * 2: SKBlendMode_Dst 310 * 3: SKBlendMode_SrcOver 311 * 4: SKBlendMode_DstOver 312 * 5: SKBlendMode_SrcIn 313 * 6: SKBlendMode_DstIn 314 * 7: SKBlendMode_SrcOut 315 * 8: SKBlendMode_DstOut 316 * 9: SKBlendMode_SrcATop 317 * 10: SKBlendMode_DstATop 318 * 11: SKBlendMode_Xor 319 * 12: SKBlendMode_Plus (The conventional belding mode) 320 * 13: SKBlendMode_Modulate 321 * 14: SRC org 322 * 15: DST org 323 * Others: Reserved. 324 */ 325 #define PDMA_OUT_CTRL_ABLEND_MODE_MASK (0xF00U) 326 #define PDMA_OUT_CTRL_ABLEND_MODE_SHIFT (8U) 327 #define PDMA_OUT_CTRL_ABLEND_MODE_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_ABLEND_MODE_SHIFT) & PDMA_OUT_CTRL_ABLEND_MODE_MASK) 328 #define PDMA_OUT_CTRL_ABLEND_MODE_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_ABLEND_MODE_MASK) >> PDMA_OUT_CTRL_ABLEND_MODE_SHIFT) 329 330 /* 331 * NORM_OUT (RW) 332 * 333 * Asserted to normalize the output color channels with alpha channels 334 */ 335 #define PDMA_OUT_CTRL_NORM_OUT_MASK (0x80U) 336 #define PDMA_OUT_CTRL_NORM_OUT_SHIFT (7U) 337 #define PDMA_OUT_CTRL_NORM_OUT_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_NORM_OUT_SHIFT) & PDMA_OUT_CTRL_NORM_OUT_MASK) 338 #define PDMA_OUT_CTRL_NORM_OUT_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_NORM_OUT_MASK) >> PDMA_OUT_CTRL_NORM_OUT_SHIFT) 339 340 /* 341 * FORMAT (RW) 342 * 343 * Output buffer format. 344 * 0x0 ARGB8888 - 32-bit pixles, byte sequence as B,G,R,A 345 * 0xE RGB565 - 16-bit pixels, byte sequence as B,R 346 * 0x12 UYVY1P422 - 16-bit pixels (1-plane , byte sequence as U0,Y0,V0,Y1) 347 */ 348 #define PDMA_OUT_CTRL_FORMAT_MASK (0x3FU) 349 #define PDMA_OUT_CTRL_FORMAT_SHIFT (0U) 350 #define PDMA_OUT_CTRL_FORMAT_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_FORMAT_SHIFT) & PDMA_OUT_CTRL_FORMAT_MASK) 351 #define PDMA_OUT_CTRL_FORMAT_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_FORMAT_MASK) >> PDMA_OUT_CTRL_FORMAT_SHIFT) 352 353 /* Bitfield definition for register: OUT_BUF */ 354 /* 355 * ADDR (RW) 356 * 357 * Current address pointer for the output frame buffer. The address can have any byte alignment. 64B alignment is recommended for optimal performance. 358 */ 359 #define PDMA_OUT_BUF_ADDR_MASK (0xFFFFFFFFUL) 360 #define PDMA_OUT_BUF_ADDR_SHIFT (0U) 361 #define PDMA_OUT_BUF_ADDR_SET(x) (((uint32_t)(x) << PDMA_OUT_BUF_ADDR_SHIFT) & PDMA_OUT_BUF_ADDR_MASK) 362 #define PDMA_OUT_BUF_ADDR_GET(x) (((uint32_t)(x) & PDMA_OUT_BUF_ADDR_MASK) >> PDMA_OUT_BUF_ADDR_SHIFT) 363 364 /* Bitfield definition for register: OUT_PITCH */ 365 /* 366 * BYTELEN (RW) 367 * 368 * Indicates the number of bytes in memory between two vertically adjacent pixels. 369 */ 370 #define PDMA_OUT_PITCH_BYTELEN_MASK (0xFFFFU) 371 #define PDMA_OUT_PITCH_BYTELEN_SHIFT (0U) 372 #define PDMA_OUT_PITCH_BYTELEN_SET(x) (((uint32_t)(x) << PDMA_OUT_PITCH_BYTELEN_SHIFT) & PDMA_OUT_PITCH_BYTELEN_MASK) 373 #define PDMA_OUT_PITCH_BYTELEN_GET(x) (((uint32_t)(x) & PDMA_OUT_PITCH_BYTELEN_MASK) >> PDMA_OUT_PITCH_BYTELEN_SHIFT) 374 375 /* Bitfield definition for register: OUT_LRC */ 376 /* 377 * Y (RW) 378 * 379 * This field indicates the lower right Y-coordinate (in pixels) of the output frame buffer. 380 * The value is the height of the output image size. 381 */ 382 #define PDMA_OUT_LRC_Y_MASK (0x3FFF0000UL) 383 #define PDMA_OUT_LRC_Y_SHIFT (16U) 384 #define PDMA_OUT_LRC_Y_SET(x) (((uint32_t)(x) << PDMA_OUT_LRC_Y_SHIFT) & PDMA_OUT_LRC_Y_MASK) 385 #define PDMA_OUT_LRC_Y_GET(x) (((uint32_t)(x) & PDMA_OUT_LRC_Y_MASK) >> PDMA_OUT_LRC_Y_SHIFT) 386 387 /* 388 * X (RW) 389 * 390 * This field indicates the lower right X-coordinate (in pixels) of the output frame buffer. 391 * Should be the width of the output image size. 392 */ 393 #define PDMA_OUT_LRC_X_MASK (0x3FFFU) 394 #define PDMA_OUT_LRC_X_SHIFT (0U) 395 #define PDMA_OUT_LRC_X_SET(x) (((uint32_t)(x) << PDMA_OUT_LRC_X_SHIFT) & PDMA_OUT_LRC_X_MASK) 396 #define PDMA_OUT_LRC_X_GET(x) (((uint32_t)(x) & PDMA_OUT_LRC_X_MASK) >> PDMA_OUT_LRC_X_SHIFT) 397 398 /* Bitfield definition for register of struct array OUT_PS: ULC */ 399 /* 400 * Y (RW) 401 * 402 * This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output frame buffer. 403 */ 404 #define PDMA_OUT_PS_ULC_Y_MASK (0x3FFF0000UL) 405 #define PDMA_OUT_PS_ULC_Y_SHIFT (16U) 406 #define PDMA_OUT_PS_ULC_Y_SET(x) (((uint32_t)(x) << PDMA_OUT_PS_ULC_Y_SHIFT) & PDMA_OUT_PS_ULC_Y_MASK) 407 #define PDMA_OUT_PS_ULC_Y_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_ULC_Y_MASK) >> PDMA_OUT_PS_ULC_Y_SHIFT) 408 409 /* 410 * X (RW) 411 * 412 * This field indicates the upper left X-coordinate (in pixels) of the processed surface in the output frame buffer. 413 */ 414 #define PDMA_OUT_PS_ULC_X_MASK (0x3FFFU) 415 #define PDMA_OUT_PS_ULC_X_SHIFT (0U) 416 #define PDMA_OUT_PS_ULC_X_SET(x) (((uint32_t)(x) << PDMA_OUT_PS_ULC_X_SHIFT) & PDMA_OUT_PS_ULC_X_MASK) 417 #define PDMA_OUT_PS_ULC_X_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_ULC_X_MASK) >> PDMA_OUT_PS_ULC_X_SHIFT) 418 419 /* Bitfield definition for register of struct array OUT_PS: LRC */ 420 /* 421 * Y (RW) 422 * 423 * This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer. 424 */ 425 #define PDMA_OUT_PS_LRC_Y_MASK (0x3FFF0000UL) 426 #define PDMA_OUT_PS_LRC_Y_SHIFT (16U) 427 #define PDMA_OUT_PS_LRC_Y_SET(x) (((uint32_t)(x) << PDMA_OUT_PS_LRC_Y_SHIFT) & PDMA_OUT_PS_LRC_Y_MASK) 428 #define PDMA_OUT_PS_LRC_Y_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_LRC_Y_MASK) >> PDMA_OUT_PS_LRC_Y_SHIFT) 429 430 /* 431 * X (RW) 432 * 433 * This field indicates the lower right X-coordinate (in pixels) of the processed surface in the output frame buffer. 434 */ 435 #define PDMA_OUT_PS_LRC_X_MASK (0x3FFFU) 436 #define PDMA_OUT_PS_LRC_X_SHIFT (0U) 437 #define PDMA_OUT_PS_LRC_X_SET(x) (((uint32_t)(x) << PDMA_OUT_PS_LRC_X_SHIFT) & PDMA_OUT_PS_LRC_X_MASK) 438 #define PDMA_OUT_PS_LRC_X_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_LRC_X_MASK) >> PDMA_OUT_PS_LRC_X_SHIFT) 439 440 /* Bitfield definition for register of struct array PS: CTRL */ 441 /* 442 * PL_ONLY_BLENDOP (RW) 443 * 444 * 1: For those pixels that are this plane-only, use the colcor values and alpha values directly as blender output for un-normalized outputs configurations. 445 * 0: For those pixels that are this plane-only, the operations are determined by other operation configurations. 446 */ 447 #define PDMA_PS_CTRL_PL_ONLY_BLENDOP_MASK (0x1000000UL) 448 #define PDMA_PS_CTRL_PL_ONLY_BLENDOP_SHIFT (24U) 449 #define PDMA_PS_CTRL_PL_ONLY_BLENDOP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_PL_ONLY_BLENDOP_SHIFT) & PDMA_PS_CTRL_PL_ONLY_BLENDOP_MASK) 450 #define PDMA_PS_CTRL_PL_ONLY_BLENDOP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_PL_ONLY_BLENDOP_MASK) >> PDMA_PS_CTRL_PL_ONLY_BLENDOP_SHIFT) 451 452 /* 453 * INB13_SWAP (RW) 454 * 455 * Swap bit[31:24] and bit [15:8] before pack_dir operation. 456 */ 457 #define PDMA_PS_CTRL_INB13_SWAP_MASK (0x100000UL) 458 #define PDMA_PS_CTRL_INB13_SWAP_SHIFT (20U) 459 #define PDMA_PS_CTRL_INB13_SWAP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_INB13_SWAP_SHIFT) & PDMA_PS_CTRL_INB13_SWAP_MASK) 460 #define PDMA_PS_CTRL_INB13_SWAP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_INB13_SWAP_MASK) >> PDMA_PS_CTRL_INB13_SWAP_SHIFT) 461 462 /* 463 * PACK_DIR (RW) 464 * 465 * Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. 466 * 2'b00: no change {A3, A2, A1, A0} 467 * 2'b01: {A2, A3, A0, A1} 468 * 2'b10: {A1, A0, A3, A2} 469 * 2'b11: {A0, A1, A2, A3} 470 */ 471 #define PDMA_PS_CTRL_PACK_DIR_MASK (0xC0000UL) 472 #define PDMA_PS_CTRL_PACK_DIR_SHIFT (18U) 473 #define PDMA_PS_CTRL_PACK_DIR_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_PACK_DIR_SHIFT) & PDMA_PS_CTRL_PACK_DIR_MASK) 474 #define PDMA_PS_CTRL_PACK_DIR_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_PACK_DIR_MASK) >> PDMA_PS_CTRL_PACK_DIR_SHIFT) 475 476 /* 477 * BKGCL4CLR (RW) 478 * 479 * Enable to use background color for clear area 480 */ 481 #define PDMA_PS_CTRL_BKGCL4CLR_MASK (0x20000UL) 482 #define PDMA_PS_CTRL_BKGCL4CLR_SHIFT (17U) 483 #define PDMA_PS_CTRL_BKGCL4CLR_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_BKGCL4CLR_SHIFT) & PDMA_PS_CTRL_BKGCL4CLR_MASK) 484 #define PDMA_PS_CTRL_BKGCL4CLR_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_BKGCL4CLR_MASK) >> PDMA_PS_CTRL_BKGCL4CLR_SHIFT) 485 486 /* 487 * YCBCR_MODE (RW) 488 * 489 * YCbCr mode or YUV mode 490 */ 491 #define PDMA_PS_CTRL_YCBCR_MODE_MASK (0x10000UL) 492 #define PDMA_PS_CTRL_YCBCR_MODE_SHIFT (16U) 493 #define PDMA_PS_CTRL_YCBCR_MODE_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_YCBCR_MODE_SHIFT) & PDMA_PS_CTRL_YCBCR_MODE_MASK) 494 #define PDMA_PS_CTRL_YCBCR_MODE_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_YCBCR_MODE_MASK) >> PDMA_PS_CTRL_YCBCR_MODE_SHIFT) 495 496 /* 497 * BYPASS (RW) 498 * 499 * Asserted to bypass the CSC stage 500 */ 501 #define PDMA_PS_CTRL_BYPASS_MASK (0x8000U) 502 #define PDMA_PS_CTRL_BYPASS_SHIFT (15U) 503 #define PDMA_PS_CTRL_BYPASS_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_BYPASS_SHIFT) & PDMA_PS_CTRL_BYPASS_MASK) 504 #define PDMA_PS_CTRL_BYPASS_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_BYPASS_MASK) >> PDMA_PS_CTRL_BYPASS_SHIFT) 505 506 /* 507 * VFLIP (RW) 508 * 509 * Indicates that the input should be flipped vertically (effect applied before rotation). 510 */ 511 #define PDMA_PS_CTRL_VFLIP_MASK (0x4000U) 512 #define PDMA_PS_CTRL_VFLIP_SHIFT (14U) 513 #define PDMA_PS_CTRL_VFLIP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_VFLIP_SHIFT) & PDMA_PS_CTRL_VFLIP_MASK) 514 #define PDMA_PS_CTRL_VFLIP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_VFLIP_MASK) >> PDMA_PS_CTRL_VFLIP_SHIFT) 515 516 /* 517 * HFLIP (RW) 518 * 519 * Indicates that the input should be flipped horizontally (effect applied before rotation). 520 */ 521 #define PDMA_PS_CTRL_HFLIP_MASK (0x2000U) 522 #define PDMA_PS_CTRL_HFLIP_SHIFT (13U) 523 #define PDMA_PS_CTRL_HFLIP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_HFLIP_SHIFT) & PDMA_PS_CTRL_HFLIP_MASK) 524 #define PDMA_PS_CTRL_HFLIP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_HFLIP_MASK) >> PDMA_PS_CTRL_HFLIP_SHIFT) 525 526 /* 527 * ROTATE (RW) 528 * 529 * Indicates the clockwise rotation to be applied at the input buffer. The rotation effect is defined as occurring 530 * after the FLIP_X and FLIP_Y permutation. 531 * 0x0 ROT_0 532 * 0x1 ROT_90 533 * 0x2 ROT_180 534 * 0x3 ROT_270 535 */ 536 #define PDMA_PS_CTRL_ROTATE_MASK (0x1800U) 537 #define PDMA_PS_CTRL_ROTATE_SHIFT (11U) 538 #define PDMA_PS_CTRL_ROTATE_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_ROTATE_SHIFT) & PDMA_PS_CTRL_ROTATE_MASK) 539 #define PDMA_PS_CTRL_ROTATE_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_ROTATE_MASK) >> PDMA_PS_CTRL_ROTATE_SHIFT) 540 541 /* 542 * DECY (RW) 543 * 544 * Verticle pre decimation filter control. 545 * 0x0 DISABLE - Disable pre-decimation filter. 546 * 0x1 DECY2 - Decimate PS by 2. 547 * 0x2 DECY4 - Decimate PS by 4. 548 * 0x3 DECY8 - Decimate PS by 8. 549 */ 550 #define PDMA_PS_CTRL_DECY_MASK (0x600U) 551 #define PDMA_PS_CTRL_DECY_SHIFT (9U) 552 #define PDMA_PS_CTRL_DECY_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_DECY_SHIFT) & PDMA_PS_CTRL_DECY_MASK) 553 #define PDMA_PS_CTRL_DECY_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_DECY_MASK) >> PDMA_PS_CTRL_DECY_SHIFT) 554 555 /* 556 * DECX (RW) 557 * 558 * Horizontal pre decimation filter control. 559 * 0x0 DISABLE - Disable pre-decimation filter. 560 * 0x1 DECX2 - Decimate PS by 2. 561 * 0x2 DECX4 - Decimate PS by 4. 562 * 0x3 DECX8 - Decimate PS by 8. 563 */ 564 #define PDMA_PS_CTRL_DECX_MASK (0x180U) 565 #define PDMA_PS_CTRL_DECX_SHIFT (7U) 566 #define PDMA_PS_CTRL_DECX_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_DECX_SHIFT) & PDMA_PS_CTRL_DECX_MASK) 567 #define PDMA_PS_CTRL_DECX_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_DECX_MASK) >> PDMA_PS_CTRL_DECX_SHIFT) 568 569 /* 570 * HW_BYTE_SWAP (RW) 571 * 572 * Swap bytes in half-words. For each 16 bit half-word, the two bytes will be swapped. 573 */ 574 #define PDMA_PS_CTRL_HW_BYTE_SWAP_MASK (0x40U) 575 #define PDMA_PS_CTRL_HW_BYTE_SWAP_SHIFT (6U) 576 #define PDMA_PS_CTRL_HW_BYTE_SWAP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_HW_BYTE_SWAP_SHIFT) & PDMA_PS_CTRL_HW_BYTE_SWAP_MASK) 577 #define PDMA_PS_CTRL_HW_BYTE_SWAP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_HW_BYTE_SWAP_MASK) >> PDMA_PS_CTRL_HW_BYTE_SWAP_SHIFT) 578 579 /* 580 * FORMAT (RW) 581 * 582 * PS buffer format. To select between YUV and YCbCr formats, see bit 16 of this register. 583 * 0x0 ARGB888 - 32-bit pixels, byte sequence as B,G,R,A 584 * 0xE RGB565 - 16-bit pixels, byte sequence as B,R 585 * 0x13 YUYV1P422 - 16-bit pixels (1-plane byte sequence Y0,U0,Y1,V0 interleaved bytes) 586 */ 587 #define PDMA_PS_CTRL_FORMAT_MASK (0x3FU) 588 #define PDMA_PS_CTRL_FORMAT_SHIFT (0U) 589 #define PDMA_PS_CTRL_FORMAT_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_FORMAT_SHIFT) & PDMA_PS_CTRL_FORMAT_MASK) 590 #define PDMA_PS_CTRL_FORMAT_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_FORMAT_MASK) >> PDMA_PS_CTRL_FORMAT_SHIFT) 591 592 /* Bitfield definition for register of struct array PS: BUF */ 593 /* 594 * ADDR (RW) 595 * 596 * Address pointer for the PS RGB or Y (luma) input buffer. 597 */ 598 #define PDMA_PS_BUF_ADDR_MASK (0xFFFFFFFFUL) 599 #define PDMA_PS_BUF_ADDR_SHIFT (0U) 600 #define PDMA_PS_BUF_ADDR_SET(x) (((uint32_t)(x) << PDMA_PS_BUF_ADDR_SHIFT) & PDMA_PS_BUF_ADDR_MASK) 601 #define PDMA_PS_BUF_ADDR_GET(x) (((uint32_t)(x) & PDMA_PS_BUF_ADDR_MASK) >> PDMA_PS_BUF_ADDR_SHIFT) 602 603 /* Bitfield definition for register of struct array PS: PITCH */ 604 /* 605 * BYTELEN (RW) 606 * 607 * Indicates the number of bytes in memory between two vertically adjacent pixels. 608 */ 609 #define PDMA_PS_PITCH_BYTELEN_MASK (0xFFFFU) 610 #define PDMA_PS_PITCH_BYTELEN_SHIFT (0U) 611 #define PDMA_PS_PITCH_BYTELEN_SET(x) (((uint32_t)(x) << PDMA_PS_PITCH_BYTELEN_SHIFT) & PDMA_PS_PITCH_BYTELEN_MASK) 612 #define PDMA_PS_PITCH_BYTELEN_GET(x) (((uint32_t)(x) & PDMA_PS_PITCH_BYTELEN_MASK) >> PDMA_PS_PITCH_BYTELEN_SHIFT) 613 614 /* Bitfield definition for register of struct array PS: BKGD */ 615 /* 616 * COLOR (RW) 617 * 618 * Background color (in 32bpp format) for any pixels not within the scaled range of the picture, but within the buffer range specified by the PS ULC/LRC. The top 8-bit is the alpha channel. 619 */ 620 #define PDMA_PS_BKGD_COLOR_MASK (0xFFFFFFFFUL) 621 #define PDMA_PS_BKGD_COLOR_SHIFT (0U) 622 #define PDMA_PS_BKGD_COLOR_SET(x) (((uint32_t)(x) << PDMA_PS_BKGD_COLOR_SHIFT) & PDMA_PS_BKGD_COLOR_MASK) 623 #define PDMA_PS_BKGD_COLOR_GET(x) (((uint32_t)(x) & PDMA_PS_BKGD_COLOR_MASK) >> PDMA_PS_BKGD_COLOR_SHIFT) 624 625 /* Bitfield definition for register of struct array PS: SCALE */ 626 /* 627 * Y (RW) 628 * 629 * This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the X scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. 630 */ 631 #define PDMA_PS_SCALE_Y_MASK (0x7FFF0000UL) 632 #define PDMA_PS_SCALE_Y_SHIFT (16U) 633 #define PDMA_PS_SCALE_Y_SET(x) (((uint32_t)(x) << PDMA_PS_SCALE_Y_SHIFT) & PDMA_PS_SCALE_Y_MASK) 634 #define PDMA_PS_SCALE_Y_GET(x) (((uint32_t)(x) & PDMA_PS_SCALE_Y_MASK) >> PDMA_PS_SCALE_Y_SHIFT) 635 636 /* 637 * X (RW) 638 * 639 * This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the Y scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. 640 */ 641 #define PDMA_PS_SCALE_X_MASK (0x7FFFU) 642 #define PDMA_PS_SCALE_X_SHIFT (0U) 643 #define PDMA_PS_SCALE_X_SET(x) (((uint32_t)(x) << PDMA_PS_SCALE_X_SHIFT) & PDMA_PS_SCALE_X_MASK) 644 #define PDMA_PS_SCALE_X_GET(x) (((uint32_t)(x) & PDMA_PS_SCALE_X_MASK) >> PDMA_PS_SCALE_X_SHIFT) 645 646 /* Bitfield definition for register of struct array PS: OFFSET */ 647 /* 648 * Y (RW) 649 * 650 * This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. 651 * It is applied after the decimation filter stage, and before the bilinear filter stage. 652 */ 653 #define PDMA_PS_OFFSET_Y_MASK (0xFFF0000UL) 654 #define PDMA_PS_OFFSET_Y_SHIFT (16U) 655 #define PDMA_PS_OFFSET_Y_SET(x) (((uint32_t)(x) << PDMA_PS_OFFSET_Y_SHIFT) & PDMA_PS_OFFSET_Y_MASK) 656 #define PDMA_PS_OFFSET_Y_GET(x) (((uint32_t)(x) & PDMA_PS_OFFSET_Y_MASK) >> PDMA_PS_OFFSET_Y_SHIFT) 657 658 /* 659 * X (RW) 660 * 661 * This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. 662 * It is applied after the decimation filter stage, and before the bilinear filter stage. 663 */ 664 #define PDMA_PS_OFFSET_X_MASK (0xFFFU) 665 #define PDMA_PS_OFFSET_X_SHIFT (0U) 666 #define PDMA_PS_OFFSET_X_SET(x) (((uint32_t)(x) << PDMA_PS_OFFSET_X_SHIFT) & PDMA_PS_OFFSET_X_MASK) 667 #define PDMA_PS_OFFSET_X_GET(x) (((uint32_t)(x) & PDMA_PS_OFFSET_X_MASK) >> PDMA_PS_OFFSET_X_SHIFT) 668 669 /* Bitfield definition for register of struct array PS: CLRKEY_LOW */ 670 /* 671 * LIMIT (RW) 672 * 673 * Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. 674 */ 675 #define PDMA_PS_CLRKEY_LOW_LIMIT_MASK (0xFFFFFFUL) 676 #define PDMA_PS_CLRKEY_LOW_LIMIT_SHIFT (0U) 677 #define PDMA_PS_CLRKEY_LOW_LIMIT_SET(x) (((uint32_t)(x) << PDMA_PS_CLRKEY_LOW_LIMIT_SHIFT) & PDMA_PS_CLRKEY_LOW_LIMIT_MASK) 678 #define PDMA_PS_CLRKEY_LOW_LIMIT_GET(x) (((uint32_t)(x) & PDMA_PS_CLRKEY_LOW_LIMIT_MASK) >> PDMA_PS_CLRKEY_LOW_LIMIT_SHIFT) 679 680 /* Bitfield definition for register of struct array PS: CLRKEY_HIGH */ 681 /* 682 * LIMIT (RW) 683 * 684 * High range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000 685 */ 686 #define PDMA_PS_CLRKEY_HIGH_LIMIT_MASK (0xFFFFFFUL) 687 #define PDMA_PS_CLRKEY_HIGH_LIMIT_SHIFT (0U) 688 #define PDMA_PS_CLRKEY_HIGH_LIMIT_SET(x) (((uint32_t)(x) << PDMA_PS_CLRKEY_HIGH_LIMIT_SHIFT) & PDMA_PS_CLRKEY_HIGH_LIMIT_MASK) 689 #define PDMA_PS_CLRKEY_HIGH_LIMIT_GET(x) (((uint32_t)(x) & PDMA_PS_CLRKEY_HIGH_LIMIT_MASK) >> PDMA_PS_CLRKEY_HIGH_LIMIT_SHIFT) 690 691 /* Bitfield definition for register of struct array PS: ORG */ 692 /* 693 * HIGHT (RW) 694 * 695 * The number of vertical pixels of the original frame (not -1) 696 */ 697 #define PDMA_PS_ORG_HIGHT_MASK (0x3FFF0000UL) 698 #define PDMA_PS_ORG_HIGHT_SHIFT (16U) 699 #define PDMA_PS_ORG_HIGHT_SET(x) (((uint32_t)(x) << PDMA_PS_ORG_HIGHT_SHIFT) & PDMA_PS_ORG_HIGHT_MASK) 700 #define PDMA_PS_ORG_HIGHT_GET(x) (((uint32_t)(x) & PDMA_PS_ORG_HIGHT_MASK) >> PDMA_PS_ORG_HIGHT_SHIFT) 701 702 /* 703 * WIDTH (RW) 704 * 705 * The number of horizontal pixels of the original frame (not -1) 706 */ 707 #define PDMA_PS_ORG_WIDTH_MASK (0x3FFFU) 708 #define PDMA_PS_ORG_WIDTH_SHIFT (0U) 709 #define PDMA_PS_ORG_WIDTH_SET(x) (((uint32_t)(x) << PDMA_PS_ORG_WIDTH_SHIFT) & PDMA_PS_ORG_WIDTH_MASK) 710 #define PDMA_PS_ORG_WIDTH_GET(x) (((uint32_t)(x) & PDMA_PS_ORG_WIDTH_MASK) >> PDMA_PS_ORG_WIDTH_SHIFT) 711 712 /* Bitfield definition for register: YUV2RGB_COEF0 */ 713 /* 714 * C0 (RW) 715 * 716 * Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) 717 */ 718 #define PDMA_YUV2RGB_COEF0_C0_MASK (0x1FFC0000UL) 719 #define PDMA_YUV2RGB_COEF0_C0_SHIFT (18U) 720 #define PDMA_YUV2RGB_COEF0_C0_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF0_C0_SHIFT) & PDMA_YUV2RGB_COEF0_C0_MASK) 721 #define PDMA_YUV2RGB_COEF0_C0_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF0_C0_MASK) >> PDMA_YUV2RGB_COEF0_C0_SHIFT) 722 723 /* 724 * UV_OFFSET (RW) 725 * 726 * Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. 727 * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). 728 */ 729 #define PDMA_YUV2RGB_COEF0_UV_OFFSET_MASK (0x3FE00UL) 730 #define PDMA_YUV2RGB_COEF0_UV_OFFSET_SHIFT (9U) 731 #define PDMA_YUV2RGB_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF0_UV_OFFSET_SHIFT) & PDMA_YUV2RGB_COEF0_UV_OFFSET_MASK) 732 #define PDMA_YUV2RGB_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF0_UV_OFFSET_MASK) >> PDMA_YUV2RGB_COEF0_UV_OFFSET_SHIFT) 733 734 /* 735 * Y_OFFSET (RW) 736 * 737 * Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is 738 * typically -16 (0x1F0). 739 */ 740 #define PDMA_YUV2RGB_COEF0_Y_OFFSET_MASK (0x1FFU) 741 #define PDMA_YUV2RGB_COEF0_Y_OFFSET_SHIFT (0U) 742 #define PDMA_YUV2RGB_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF0_Y_OFFSET_SHIFT) & PDMA_YUV2RGB_COEF0_Y_OFFSET_MASK) 743 #define PDMA_YUV2RGB_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF0_Y_OFFSET_MASK) >> PDMA_YUV2RGB_COEF0_Y_OFFSET_SHIFT) 744 745 /* Bitfield definition for register: YUV2RGB_COEF1 */ 746 /* 747 * C1 (RW) 748 * 749 * Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). 750 */ 751 #define PDMA_YUV2RGB_COEF1_C1_MASK (0x7FF0000UL) 752 #define PDMA_YUV2RGB_COEF1_C1_SHIFT (16U) 753 #define PDMA_YUV2RGB_COEF1_C1_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF1_C1_SHIFT) & PDMA_YUV2RGB_COEF1_C1_MASK) 754 #define PDMA_YUV2RGB_COEF1_C1_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF1_C1_MASK) >> PDMA_YUV2RGB_COEF1_C1_SHIFT) 755 756 /* 757 * C4 (RW) 758 * 759 * Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). 760 */ 761 #define PDMA_YUV2RGB_COEF1_C4_MASK (0x7FFU) 762 #define PDMA_YUV2RGB_COEF1_C4_SHIFT (0U) 763 #define PDMA_YUV2RGB_COEF1_C4_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF1_C4_SHIFT) & PDMA_YUV2RGB_COEF1_C4_MASK) 764 #define PDMA_YUV2RGB_COEF1_C4_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF1_C4_MASK) >> PDMA_YUV2RGB_COEF1_C4_SHIFT) 765 766 /* Bitfield definition for register: YUV2RGB_COEF2 */ 767 /* 768 * C2 (RW) 769 * 770 * Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). 771 */ 772 #define PDMA_YUV2RGB_COEF2_C2_MASK (0x7FF0000UL) 773 #define PDMA_YUV2RGB_COEF2_C2_SHIFT (16U) 774 #define PDMA_YUV2RGB_COEF2_C2_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF2_C2_SHIFT) & PDMA_YUV2RGB_COEF2_C2_MASK) 775 #define PDMA_YUV2RGB_COEF2_C2_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF2_C2_MASK) >> PDMA_YUV2RGB_COEF2_C2_SHIFT) 776 777 /* 778 * C3 (RW) 779 * 780 * Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). 781 */ 782 #define PDMA_YUV2RGB_COEF2_C3_MASK (0x7FFU) 783 #define PDMA_YUV2RGB_COEF2_C3_SHIFT (0U) 784 #define PDMA_YUV2RGB_COEF2_C3_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF2_C3_SHIFT) & PDMA_YUV2RGB_COEF2_C3_MASK) 785 #define PDMA_YUV2RGB_COEF2_C3_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF2_C3_MASK) >> PDMA_YUV2RGB_COEF2_C3_SHIFT) 786 787 /* Bitfield definition for register: RGB2YUV_COEF0 */ 788 /* 789 * YCBCR_MODE (RW) 790 * 791 * Asserted to use YCrCb mode 792 */ 793 #define PDMA_RGB2YUV_COEF0_YCBCR_MODE_MASK (0x80000000UL) 794 #define PDMA_RGB2YUV_COEF0_YCBCR_MODE_SHIFT (31U) 795 #define PDMA_RGB2YUV_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_YCBCR_MODE_SHIFT) & PDMA_RGB2YUV_COEF0_YCBCR_MODE_MASK) 796 #define PDMA_RGB2YUV_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_YCBCR_MODE_MASK) >> PDMA_RGB2YUV_COEF0_YCBCR_MODE_SHIFT) 797 798 /* 799 * ENABLE (RW) 800 * 801 * Asserted to enable this RGB2YUV CSC stage 802 */ 803 #define PDMA_RGB2YUV_COEF0_ENABLE_MASK (0x40000000UL) 804 #define PDMA_RGB2YUV_COEF0_ENABLE_SHIFT (30U) 805 #define PDMA_RGB2YUV_COEF0_ENABLE_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_ENABLE_SHIFT) & PDMA_RGB2YUV_COEF0_ENABLE_MASK) 806 #define PDMA_RGB2YUV_COEF0_ENABLE_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_ENABLE_MASK) >> PDMA_RGB2YUV_COEF0_ENABLE_SHIFT) 807 808 /* 809 * C0 (RW) 810 * 811 * CSC parameters C0 812 */ 813 #define PDMA_RGB2YUV_COEF0_C0_MASK (0x1FFC0000UL) 814 #define PDMA_RGB2YUV_COEF0_C0_SHIFT (18U) 815 #define PDMA_RGB2YUV_COEF0_C0_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_C0_SHIFT) & PDMA_RGB2YUV_COEF0_C0_MASK) 816 #define PDMA_RGB2YUV_COEF0_C0_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_C0_MASK) >> PDMA_RGB2YUV_COEF0_C0_SHIFT) 817 818 /* 819 * UV_OFFSET (RW) 820 * 821 * CSC parameters UV_OFFSET 822 */ 823 #define PDMA_RGB2YUV_COEF0_UV_OFFSET_MASK (0x3FE00UL) 824 #define PDMA_RGB2YUV_COEF0_UV_OFFSET_SHIFT (9U) 825 #define PDMA_RGB2YUV_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_UV_OFFSET_SHIFT) & PDMA_RGB2YUV_COEF0_UV_OFFSET_MASK) 826 #define PDMA_RGB2YUV_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_UV_OFFSET_MASK) >> PDMA_RGB2YUV_COEF0_UV_OFFSET_SHIFT) 827 828 /* 829 * Y_OFFSET (RW) 830 * 831 * CSC parameters Y_OFFSET 832 */ 833 #define PDMA_RGB2YUV_COEF0_Y_OFFSET_MASK (0x1FFU) 834 #define PDMA_RGB2YUV_COEF0_Y_OFFSET_SHIFT (0U) 835 #define PDMA_RGB2YUV_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_Y_OFFSET_SHIFT) & PDMA_RGB2YUV_COEF0_Y_OFFSET_MASK) 836 #define PDMA_RGB2YUV_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_Y_OFFSET_MASK) >> PDMA_RGB2YUV_COEF0_Y_OFFSET_SHIFT) 837 838 /* Bitfield definition for register: RGB2YUV_COEF1 */ 839 /* 840 * C1 (RW) 841 * 842 * CSC parameters C1 843 */ 844 #define PDMA_RGB2YUV_COEF1_C1_MASK (0x7FF0000UL) 845 #define PDMA_RGB2YUV_COEF1_C1_SHIFT (16U) 846 #define PDMA_RGB2YUV_COEF1_C1_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF1_C1_SHIFT) & PDMA_RGB2YUV_COEF1_C1_MASK) 847 #define PDMA_RGB2YUV_COEF1_C1_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF1_C1_MASK) >> PDMA_RGB2YUV_COEF1_C1_SHIFT) 848 849 /* 850 * C4 (RW) 851 * 852 * CSC parameters C4 853 */ 854 #define PDMA_RGB2YUV_COEF1_C4_MASK (0x7FFU) 855 #define PDMA_RGB2YUV_COEF1_C4_SHIFT (0U) 856 #define PDMA_RGB2YUV_COEF1_C4_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF1_C4_SHIFT) & PDMA_RGB2YUV_COEF1_C4_MASK) 857 #define PDMA_RGB2YUV_COEF1_C4_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF1_C4_MASK) >> PDMA_RGB2YUV_COEF1_C4_SHIFT) 858 859 /* Bitfield definition for register: RGB2YUV_COEF2 */ 860 /* 861 * C2 (RW) 862 * 863 * CSC parameters C2 864 */ 865 #define PDMA_RGB2YUV_COEF2_C2_MASK (0x7FF0000UL) 866 #define PDMA_RGB2YUV_COEF2_C2_SHIFT (16U) 867 #define PDMA_RGB2YUV_COEF2_C2_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF2_C2_SHIFT) & PDMA_RGB2YUV_COEF2_C2_MASK) 868 #define PDMA_RGB2YUV_COEF2_C2_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF2_C2_MASK) >> PDMA_RGB2YUV_COEF2_C2_SHIFT) 869 870 /* 871 * C3 (RW) 872 * 873 * CSC parameters C3 874 */ 875 #define PDMA_RGB2YUV_COEF2_C3_MASK (0x7FFU) 876 #define PDMA_RGB2YUV_COEF2_C3_SHIFT (0U) 877 #define PDMA_RGB2YUV_COEF2_C3_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF2_C3_SHIFT) & PDMA_RGB2YUV_COEF2_C3_MASK) 878 #define PDMA_RGB2YUV_COEF2_C3_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF2_C3_MASK) >> PDMA_RGB2YUV_COEF2_C3_SHIFT) 879 880 /* Bitfield definition for register: RGB2YUV_COEF3 */ 881 /* 882 * C6 (RW) 883 * 884 * CSC parameters C6 885 */ 886 #define PDMA_RGB2YUV_COEF3_C6_MASK (0x7FF0000UL) 887 #define PDMA_RGB2YUV_COEF3_C6_SHIFT (16U) 888 #define PDMA_RGB2YUV_COEF3_C6_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF3_C6_SHIFT) & PDMA_RGB2YUV_COEF3_C6_MASK) 889 #define PDMA_RGB2YUV_COEF3_C6_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF3_C6_MASK) >> PDMA_RGB2YUV_COEF3_C6_SHIFT) 890 891 /* 892 * C5 (RW) 893 * 894 * CSC parameters C5 895 */ 896 #define PDMA_RGB2YUV_COEF3_C5_MASK (0x7FFU) 897 #define PDMA_RGB2YUV_COEF3_C5_SHIFT (0U) 898 #define PDMA_RGB2YUV_COEF3_C5_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF3_C5_SHIFT) & PDMA_RGB2YUV_COEF3_C5_MASK) 899 #define PDMA_RGB2YUV_COEF3_C5_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF3_C5_MASK) >> PDMA_RGB2YUV_COEF3_C5_SHIFT) 900 901 /* Bitfield definition for register: RGB2YUV_COEF4 */ 902 /* 903 * C8 (RW) 904 * 905 * CSC parameters C8 906 */ 907 #define PDMA_RGB2YUV_COEF4_C8_MASK (0x7FF0000UL) 908 #define PDMA_RGB2YUV_COEF4_C8_SHIFT (16U) 909 #define PDMA_RGB2YUV_COEF4_C8_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF4_C8_SHIFT) & PDMA_RGB2YUV_COEF4_C8_MASK) 910 #define PDMA_RGB2YUV_COEF4_C8_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF4_C8_MASK) >> PDMA_RGB2YUV_COEF4_C8_SHIFT) 911 912 /* 913 * C7 (RW) 914 * 915 * CSC parameters C7 916 */ 917 #define PDMA_RGB2YUV_COEF4_C7_MASK (0x7FFU) 918 #define PDMA_RGB2YUV_COEF4_C7_SHIFT (0U) 919 #define PDMA_RGB2YUV_COEF4_C7_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF4_C7_SHIFT) & PDMA_RGB2YUV_COEF4_C7_MASK) 920 #define PDMA_RGB2YUV_COEF4_C7_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF4_C7_MASK) >> PDMA_RGB2YUV_COEF4_C7_SHIFT) 921 922 923 924 /* OUT_PS register group index macro definition */ 925 #define PDMA_OUT_PS_0 (0UL) 926 #define PDMA_OUT_PS_1 (1UL) 927 928 /* PS register group index macro definition */ 929 #define PDMA_PS_0 (0UL) 930 #define PDMA_PS_1 (1UL) 931 932 933 #endif /* HPM_PDMA_H */ 934