1 /* 2 * combo rx module 3 * 4 * Copyright (c) 2017 by Allwinnertech Co., Ltd. http://www.allwinnertech.com 5 * 6 * Authors: Zhao Wei <zhaowei@allwinnertech.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include "combo_rx_reg_i.h" 14 15 #ifndef __COMBO_RX_REG__H__ 16 #define __COMBO_RX_REG__H__ 17 18 enum combo_rx_mode_sel { 19 D_PHY = 0x2, 20 SUB_LVDS = 0x3, 21 CMOS = 0x4, 22 }; 23 24 enum combo_rx_pix_num { 25 ONE_PIXEL = 0x0, 26 TWO_PIXEL = 0x1, 27 FOUR_PIXEL = 0x2, 28 EIGHT_PIXEL = 0x3, 29 }; 30 31 enum mipi_inter_lane0_map { 32 MIPI_IN_L0_USE_PAD_LANE0 = 0x0, 33 MIPI_IN_L0_USE_PAD_LANE1 = 0x1, 34 MIPI_IN_L0_USE_PAD_LANE2 = 0x2, 35 MIPI_IN_L0_USE_PAD_LANE3 = 0x3, 36 }; 37 38 enum mipi_inter_lane1_map { 39 MIPI_IN_L1_USE_PAD_LANE0 = 0x0, 40 MIPI_IN_L1_USE_PAD_LANE1 = 0x1, 41 MIPI_IN_L1_USE_PAD_LANE2 = 0x2, 42 MIPI_IN_L1_USE_PAD_LANE3 = 0x3, 43 }; 44 45 enum mipi_inter_lane2_map { 46 MIPI_IN_L2_USE_PAD_LANE0 = 0x0, 47 MIPI_IN_L2_USE_PAD_LANE1 = 0x1, 48 MIPI_IN_L2_USE_PAD_LANE2 = 0x2, 49 MIPI_IN_L2_USE_PAD_LANE3 = 0x3, 50 }; 51 52 enum mipi_inter_lane3_map { 53 MIPI_IN_L3_USE_PAD_LANE0 = 0x0, 54 MIPI_IN_L3_USE_PAD_LANE1 = 0x1, 55 MIPI_IN_L3_USE_PAD_LANE2 = 0x2, 56 MIPI_IN_L3_USE_PAD_LANE3 = 0x3, 57 }; 58 59 enum lvds_bit_width { 60 RAW8 = 0x0, 61 RAW10 = 0x1, 62 RAW12 = 0x2, 63 RAW14 = 0x3, 64 RAW16 = 0x4, 65 YUV8 = 0x5, 66 YUV10 = 0x6, 67 }; 68 69 enum lvds_lane_num { 70 LVDS_2LANE = 0x2, 71 LVDS_4LANE = 0x4, 72 LVDS_8LANE = 0x8, 73 LVDS_10LANE = 0x0a, 74 LVDS_12LANE = 0x0c, 75 }; 76 77 enum mipi_lane_num { 78 MIPI_1LANE = 0x0, 79 MIPI_2LANE = 0x1, 80 MIPI_3LANE = 0x2, 81 MIPI_4LANE = 0x3, 82 83 }; 84 85 enum hispi_trans_mode { 86 PACKETIZED_SP = 0x0, 87 STREAMING_SP = 0x1, 88 }; 89 90 struct lvds_ctr { 91 enum lvds_bit_width lvds_bit_width; 92 enum lvds_lane_num lvds_lane_num; 93 unsigned int lvds_line_code_mode;/*0:HiSPI SOF/EOF/SOL/EOL 1:SAV-EAV*/ 94 unsigned int lvds_pix_lsb;/*0:MSB,1:LSB*/ 95 unsigned int lvds_wdr_lbl_sel;/*0:normal operation 1:sync code 2:detect data*/ 96 unsigned int lvds_sync_code_line_cnt;/*when in WDR mode,this reg can extent frame valid signal by set 1,2,3,4*/ 97 unsigned int lvds_wdr_fid_mode_sel;/*0:1bit 1:2bits*/ 98 unsigned int lvds_wdr_fid_map_en;/*bit12:FID0 bit13:FID1 bit14:FID2 bit15:FID3*/ 99 unsigned int lvds_wdr_fid0_map_sel; 100 unsigned int lvds_wdr_fid1_map_sel; 101 unsigned int lvds_wdr_fid2_map_sel; 102 unsigned int lvds_wdr_fid3_map_sel; 103 unsigned int lvds_code_mask;/*set 1,mask this bit,sync code ignore this bit*/ 104 unsigned int lvds_wdr_en_multi_ch; 105 unsigned int lvds_wdr_ch0_height; 106 unsigned int lvds_wdr_ch1_height; 107 unsigned int lvds_wdr_ch2_height; 108 unsigned int lvds_wdr_ch3_height; 109 }; 110 111 struct mipi_ctr { 112 enum mipi_lane_num mipi_lane_num; 113 unsigned int mipi_msb_lsb_sel;/*PHA to controller MSB first*/ 114 unsigned int mipi_wdr_mode_sel;/*0:normal operation 1:sync code 2:detect data,when in DOL WDR mode,set 2*/ 115 unsigned int mipi_open_multi_ch; 116 unsigned int mipi_ch0_height; 117 unsigned int mipi_ch1_height; 118 unsigned int mipi_ch2_height; 119 unsigned int mipi_ch3_height; 120 }; 121 122 struct hispi_ctr { 123 enum hispi_trans_mode hispi_trans_mode; 124 unsigned int hispi_wdr_en; 125 unsigned int hispi_normal;/*switch lvds to hispi normal mode*/ 126 unsigned int hispi_wdr_eof_fild; 127 unsigned int hispi_wdr_sof_fild; 128 unsigned int hispi_code_mask; 129 }; 130 131 enum lvds_inter_lane0_map { 132 LVDS_LANE0_NO_USE = 0x0, 133 LVDS_MAPPING_A_D0_TO_LANE0 = 0x1, 134 LVDS_MAPPING_A_D1_TO_LANE0 = 0x2, 135 LVDS_MAPPING_A_D2_TO_LANE0 = 0x3, 136 LVDS_MAPPING_A_D3_TO_LANE0 = 0x4, 137 LVDS_MAPPING_B_D0_TO_LANE0 = 0x5, 138 LVDS_MAPPING_B_D1_TO_LANE0 = 0x6, 139 LVDS_MAPPING_B_D2_TO_LANE0 = 0x7, 140 LVDS_MAPPING_B_D3_TO_LANE0 = 0x8, 141 LVDS_MAPPING_C_D0_TO_LANE0 = 0x9, 142 LVDS_MAPPING_C_D1_TO_LANE0 = 0xa, 143 LVDS_MAPPING_C_D2_TO_LANE0 = 0xb, 144 LVDS_MAPPING_C_D3_TO_LANE0 = 0xc, 145 }; 146 147 enum lvds_inter_lane1_map { 148 LVDS_LANE1_NO_USE = 0x0, 149 LVDS_MAPPING_A_D0_TO_LANE1 = 0x1, 150 LVDS_MAPPING_A_D1_TO_LANE1 = 0x2, 151 LVDS_MAPPING_A_D2_TO_LANE1 = 0x3, 152 LVDS_MAPPING_A_D3_TO_LANE1 = 0x4, 153 LVDS_MAPPING_B_D0_TO_LANE1 = 0x5, 154 LVDS_MAPPING_B_D1_TO_LANE1 = 0x6, 155 LVDS_MAPPING_B_D2_TO_LANE1 = 0x7, 156 LVDS_MAPPING_B_D3_TO_LANE1 = 0x8, 157 LVDS_MAPPING_C_D0_TO_LANE1 = 0x9, 158 LVDS_MAPPING_C_D1_TO_LANE1 = 0xa, 159 LVDS_MAPPING_C_D2_TO_LANE1 = 0xb, 160 LVDS_MAPPING_C_D3_TO_LANE1 = 0xc, 161 }; 162 163 enum lvds_inter_lane2_map { 164 LVDS_LANE2_NO_USE = 0x0, 165 LVDS_MAPPING_A_D0_TO_LANE2 = 0x1, 166 LVDS_MAPPING_A_D1_TO_LANE2 = 0x2, 167 LVDS_MAPPING_A_D2_TO_LANE2 = 0x3, 168 LVDS_MAPPING_A_D3_TO_LANE2 = 0x4, 169 LVDS_MAPPING_B_D0_TO_LANE2 = 0x5, 170 LVDS_MAPPING_B_D1_TO_LANE2 = 0x6, 171 LVDS_MAPPING_B_D2_TO_LANE2 = 0x7, 172 LVDS_MAPPING_B_D3_TO_LANE2 = 0x8, 173 LVDS_MAPPING_C_D0_TO_LANE2 = 0x9, 174 LVDS_MAPPING_C_D1_TO_LANE2 = 0xa, 175 LVDS_MAPPING_C_D2_TO_LANE2 = 0xb, 176 LVDS_MAPPING_C_D3_TO_LANE2 = 0xc, 177 }; 178 179 enum lvds_inter_lane3_map { 180 LVDS_LANE3_NO_USE = 0x0, 181 LVDS_MAPPING_A_D0_TO_LANE3 = 0x1, 182 LVDS_MAPPING_A_D1_TO_LANE3 = 0x2, 183 LVDS_MAPPING_A_D2_TO_LANE3 = 0x3, 184 LVDS_MAPPING_A_D3_TO_LANE3 = 0x4, 185 LVDS_MAPPING_B_D0_TO_LANE3 = 0x5, 186 LVDS_MAPPING_B_D1_TO_LANE3 = 0x6, 187 LVDS_MAPPING_B_D2_TO_LANE3 = 0x7, 188 LVDS_MAPPING_B_D3_TO_LANE3 = 0x8, 189 LVDS_MAPPING_C_D0_TO_LANE3 = 0x9, 190 LVDS_MAPPING_C_D1_TO_LANE3 = 0xa, 191 LVDS_MAPPING_C_D2_TO_LANE3 = 0xb, 192 LVDS_MAPPING_C_D3_TO_LANE3 = 0xc, 193 }; 194 195 enum lvds_inter_lane4_map { 196 LVDS_LANE4_NO_USE = 0x0, 197 LVDS_MAPPING_A_D0_TO_LANE4 = 0x1, 198 LVDS_MAPPING_A_D1_TO_LANE4 = 0x2, 199 LVDS_MAPPING_A_D2_TO_LANE4 = 0x3, 200 LVDS_MAPPING_A_D3_TO_LANE4 = 0x4, 201 LVDS_MAPPING_B_D0_TO_LANE4 = 0x5, 202 LVDS_MAPPING_B_D1_TO_LANE4 = 0x6, 203 LVDS_MAPPING_B_D2_TO_LANE4 = 0x7, 204 LVDS_MAPPING_B_D3_TO_LANE4 = 0x8, 205 LVDS_MAPPING_C_D0_TO_LANE4 = 0x9, 206 LVDS_MAPPING_C_D1_TO_LANE4 = 0xa, 207 LVDS_MAPPING_C_D2_TO_LANE4 = 0xb, 208 LVDS_MAPPING_C_D3_TO_LANE4 = 0xc, 209 }; 210 211 enum lvds_inter_lane5_map { 212 LVDS_LANE5_NO_USE = 0x0, 213 LVDS_MAPPING_A_D0_TO_LANE5 = 0x1, 214 LVDS_MAPPING_A_D1_TO_LANE5 = 0x2, 215 LVDS_MAPPING_A_D2_TO_LANE5 = 0x3, 216 LVDS_MAPPING_A_D3_TO_LANE5 = 0x4, 217 LVDS_MAPPING_B_D0_TO_LANE5 = 0x5, 218 LVDS_MAPPING_B_D1_TO_LANE5 = 0x6, 219 LVDS_MAPPING_B_D2_TO_LANE5 = 0x7, 220 LVDS_MAPPING_B_D3_TO_LANE5 = 0x8, 221 LVDS_MAPPING_C_D0_TO_LANE5 = 0x9, 222 LVDS_MAPPING_C_D1_TO_LANE5 = 0xa, 223 LVDS_MAPPING_C_D2_TO_LANE5 = 0xb, 224 LVDS_MAPPING_C_D3_TO_LANE5 = 0xc, 225 }; 226 227 enum lvds_inter_lane6_map { 228 LVDS_LANE6_NO_USE = 0x0, 229 LVDS_MAPPING_A_D0_TO_LANE6 = 0x1, 230 LVDS_MAPPING_A_D1_TO_LANE6 = 0x2, 231 LVDS_MAPPING_A_D2_TO_LANE6 = 0x3, 232 LVDS_MAPPING_A_D3_TO_LANE6 = 0x4, 233 LVDS_MAPPING_B_D0_TO_LANE6 = 0x5, 234 LVDS_MAPPING_B_D1_TO_LANE6 = 0x6, 235 LVDS_MAPPING_B_D2_TO_LANE6 = 0x7, 236 LVDS_MAPPING_B_D3_TO_LANE6 = 0x8, 237 LVDS_MAPPING_C_D0_TO_LANE6 = 0x9, 238 LVDS_MAPPING_C_D1_TO_LANE6 = 0xa, 239 LVDS_MAPPING_C_D2_TO_LANE6 = 0xb, 240 LVDS_MAPPING_C_D3_TO_LANE6 = 0xc, 241 }; 242 243 enum lvds_inter_lane7_map { 244 LVDS_LANE7_NO_USE = 0x0, 245 LVDS_MAPPING_A_D0_TO_LANE7 = 0x1, 246 LVDS_MAPPING_A_D1_TO_LANE7 = 0x2, 247 LVDS_MAPPING_A_D2_TO_LANE7 = 0x3, 248 LVDS_MAPPING_A_D3_TO_LANE7 = 0x4, 249 LVDS_MAPPING_B_D0_TO_LANE7 = 0x5, 250 LVDS_MAPPING_B_D1_TO_LANE7 = 0x6, 251 LVDS_MAPPING_B_D2_TO_LANE7 = 0x7, 252 LVDS_MAPPING_B_D3_TO_LANE7 = 0x8, 253 LVDS_MAPPING_C_D0_TO_LANE7 = 0x9, 254 LVDS_MAPPING_C_D1_TO_LANE7 = 0xa, 255 LVDS_MAPPING_C_D2_TO_LANE7 = 0xb, 256 LVDS_MAPPING_C_D3_TO_LANE7 = 0xc, 257 }; 258 259 enum lvds_inter_lane8_map { 260 LVDS_LANE8_NO_USE = 0x0, 261 LVDS_MAPPING_A_D0_TO_LANE8 = 0x1, 262 LVDS_MAPPING_A_D1_TO_LANE8 = 0x2, 263 LVDS_MAPPING_A_D2_TO_LANE8 = 0x3, 264 LVDS_MAPPING_A_D3_TO_LANE8 = 0x4, 265 LVDS_MAPPING_B_D0_TO_LANE8 = 0x5, 266 LVDS_MAPPING_B_D1_TO_LANE8 = 0x6, 267 LVDS_MAPPING_B_D2_TO_LANE8 = 0x7, 268 LVDS_MAPPING_B_D3_TO_LANE8 = 0x8, 269 LVDS_MAPPING_C_D0_TO_LANE8 = 0x9, 270 LVDS_MAPPING_C_D1_TO_LANE8 = 0xa, 271 LVDS_MAPPING_C_D2_TO_LANE8 = 0xb, 272 LVDS_MAPPING_C_D3_TO_LANE8 = 0xc, 273 }; 274 275 enum lvds_inter_lane9_map { 276 LVDS_LANE9_NO_USE = 0x0, 277 LVDS_MAPPING_A_D0_TO_LANE9 = 0x1, 278 LVDS_MAPPING_A_D1_TO_LANE9 = 0x2, 279 LVDS_MAPPING_A_D2_TO_LANE9 = 0x3, 280 LVDS_MAPPING_A_D3_TO_LANE9 = 0x4, 281 LVDS_MAPPING_B_D0_TO_LANE9 = 0x5, 282 LVDS_MAPPING_B_D1_TO_LANE9 = 0x6, 283 LVDS_MAPPING_B_D2_TO_LANE9 = 0x7, 284 LVDS_MAPPING_B_D3_TO_LANE9 = 0x8, 285 LVDS_MAPPING_C_D0_TO_LANE9 = 0x9, 286 LVDS_MAPPING_C_D1_TO_LANE9 = 0xa, 287 LVDS_MAPPING_C_D2_TO_LANE9 = 0xb, 288 LVDS_MAPPING_C_D3_TO_LANE9 = 0xc, 289 }; 290 291 enum lvds_inter_lane10_map { 292 LVDS_LANE10_NO_USE = 0x0, 293 LVDS_MAPPING_A_D0_TO_LANE10 = 0x1, 294 LVDS_MAPPING_A_D1_TO_LANE10 = 0x2, 295 LVDS_MAPPING_A_D2_TO_LANE10 = 0x3, 296 LVDS_MAPPING_A_D3_TO_LANE10 = 0x4, 297 LVDS_MAPPING_B_D0_TO_LANE10 = 0x5, 298 LVDS_MAPPING_B_D1_TO_LANE10 = 0x6, 299 LVDS_MAPPING_B_D2_TO_LANE10 = 0x7, 300 LVDS_MAPPING_B_D3_TO_LANE10 = 0x8, 301 LVDS_MAPPING_C_D0_TO_LANE10 = 0x9, 302 LVDS_MAPPING_C_D1_TO_LANE10 = 0xa, 303 LVDS_MAPPING_C_D2_TO_LANE10 = 0xb, 304 LVDS_MAPPING_C_D3_TO_LANE10 = 0xc, 305 }; 306 307 enum lvds_inter_lane11_map { 308 LVDS_LANE11_NO_USE = 0x0, 309 LVDS_MAPPING_A_D0_TO_LANE11 = 0x1, 310 LVDS_MAPPING_A_D1_TO_LANE11 = 0x2, 311 LVDS_MAPPING_A_D2_TO_LANE11 = 0x3, 312 LVDS_MAPPING_A_D3_TO_LANE11 = 0x4, 313 LVDS_MAPPING_B_D0_TO_LANE11 = 0x5, 314 LVDS_MAPPING_B_D1_TO_LANE11 = 0x6, 315 LVDS_MAPPING_B_D2_TO_LANE11 = 0x7, 316 LVDS_MAPPING_B_D3_TO_LANE11 = 0x8, 317 LVDS_MAPPING_C_D0_TO_LANE11 = 0x9, 318 LVDS_MAPPING_C_D1_TO_LANE11 = 0xa, 319 LVDS_MAPPING_C_D2_TO_LANE11 = 0xb, 320 LVDS_MAPPING_C_D3_TO_LANE11 = 0xc, 321 }; 322 323 enum phya_a_clk_dly_set { 324 A_CLK_DELAY_0 = 0x0, 325 A_CLK_DELAY_1 = 0x1, 326 A_CLK_DELAY_2 = 0x2, 327 A_CLK_DELAY_3 = 0x3, 328 A_CLK_DELAY_4 = 0x4, 329 A_CLK_DELAY_5 = 0x5, 330 A_CLK_DELAY_6 = 0x6, 331 A_CLK_DELAY_7 = 0x7, 332 }; 333 334 enum phya_b_clk_dly_set { 335 B_CLK_DELAY_0 = 0x0, 336 B_CLK_DELAY_1 = 0x1, 337 B_CLK_DELAY_2 = 0x2, 338 B_CLK_DELAY_3 = 0x3, 339 B_CLK_DELAY_4 = 0x4, 340 B_CLK_DELAY_5 = 0x5, 341 B_CLK_DELAY_6 = 0x6, 342 B_CLK_DELAY_7 = 0x7, 343 }; 344 345 enum phya_c_clk_dly_set { 346 C_CLK_DELAY_0 = 0x0, 347 C_CLK_DELAY_1 = 0x1, 348 C_CLK_DELAY_2 = 0x2, 349 C_CLK_DELAY_3 = 0x3, 350 C_CLK_DELAY_4 = 0x4, 351 C_CLK_DELAY_5 = 0x5, 352 C_CLK_DELAY_6 = 0x6, 353 C_CLK_DELAY_7 = 0x7, 354 }; 355 356 enum phya_a_d0_dly_set { 357 A_D0_DELAY_0 = 0x0, 358 A_D0_DELAY_1 = 0x1, 359 A_D0_DELAY_2 = 0x2, 360 A_D0_DELAY_3 = 0x3, 361 A_D0_DELAY_4 = 0x4, 362 A_D0_DELAY_5 = 0x5, 363 A_D0_DELAY_6 = 0x6, 364 A_D0_DELAY_7 = 0x7, 365 }; 366 367 enum phya_b_d0_dly_set { 368 B_D0_DELAY_0 = 0x0, 369 B_D0_DELAY_1 = 0x1, 370 B_D0_DELAY_2 = 0x2, 371 B_D0_DELAY_3 = 0x3, 372 B_D0_DELAY_4 = 0x4, 373 B_D0_DELAY_5 = 0x5, 374 B_D0_DELAY_6 = 0x6, 375 B_D0_DELAY_7 = 0x7, 376 }; 377 378 enum phya_c_d0_dly_set { 379 C_D0_DELAY_0 = 0x0, 380 C_D0_DELAY_1 = 0x1, 381 C_D0_DELAY_2 = 0x2, 382 C_D0_DELAY_3 = 0x3, 383 C_D0_DELAY_4 = 0x4, 384 C_D0_DELAY_5 = 0x5, 385 C_D0_DELAY_6 = 0x6, 386 C_D0_DELAY_7 = 0x7, 387 }; 388 389 enum phya_a_d1_dly_set { 390 A_D1_DELAY_0 = 0x0, 391 A_D1_DELAY_1 = 0x1, 392 A_D1_DELAY_2 = 0x2, 393 A_D1_DELAY_3 = 0x3, 394 A_D1_DELAY_4 = 0x4, 395 A_D1_DELAY_5 = 0x5, 396 A_D1_DELAY_6 = 0x6, 397 A_D1_DELAY_7 = 0x7, 398 }; 399 400 enum phya_b_d1_dly_set { 401 B_D1_DELAY_0 = 0x0, 402 B_D1_DELAY_1 = 0x1, 403 B_D1_DELAY_2 = 0x2, 404 B_D1_DELAY_3 = 0x3, 405 B_D1_DELAY_4 = 0x4, 406 B_D1_DELAY_5 = 0x5, 407 B_D1_DELAY_6 = 0x6, 408 B_D1_DELAY_7 = 0x7, 409 }; 410 411 enum phya_c_d1_dly_set { 412 C_D1_DELAY_0 = 0x0, 413 C_D1_DELAY_1 = 0x1, 414 C_D1_DELAY_2 = 0x2, 415 C_D1_DELAY_3 = 0x3, 416 C_D1_DELAY_4 = 0x4, 417 C_D1_DELAY_5 = 0x5, 418 C_D1_DELAY_6 = 0x6, 419 C_D1_DELAY_7 = 0x7, 420 }; 421 422 enum phya_a_d2_dly_set { 423 A_D2_DELAY_0 = 0x0, 424 A_D2_DELAY_1 = 0x1, 425 A_D2_DELAY_2 = 0x2, 426 A_D2_DELAY_3 = 0x3, 427 A_D2_DELAY_4 = 0x4, 428 A_D2_DELAY_5 = 0x5, 429 A_D2_DELAY_6 = 0x6, 430 A_D2_DELAY_7 = 0x7, 431 }; 432 433 enum phya_b_d2_dly_set { 434 B_D2_DELAY_0 = 0x0, 435 B_D2_DELAY_1 = 0x1, 436 B_D2_DELAY_2 = 0x2, 437 B_D2_DELAY_3 = 0x3, 438 B_D2_DELAY_4 = 0x4, 439 B_D2_DELAY_5 = 0x5, 440 B_D2_DELAY_6 = 0x6, 441 B_D2_DELAY_7 = 0x7, 442 }; 443 444 enum phya_c_d2_dly_set { 445 C_D2_DELAY_0 = 0x0, 446 C_D2_DELAY_1 = 0x1, 447 C_D2_DELAY_2 = 0x2, 448 C_D2_DELAY_3 = 0x3, 449 C_D2_DELAY_4 = 0x4, 450 C_D2_DELAY_5 = 0x5, 451 C_D2_DELAY_6 = 0x6, 452 C_D2_DELAY_7 = 0x7, 453 }; 454 455 enum phya_a_d3_dly_set { 456 A_D3_DELAY_0 = 0x0, 457 A_D3_DELAY_1 = 0x1, 458 A_D3_DELAY_2 = 0x2, 459 A_D3_DELAY_3 = 0x3, 460 A_D3_DELAY_4 = 0x4, 461 A_D3_DELAY_5 = 0x5, 462 A_D3_DELAY_6 = 0x6, 463 A_D3_DELAY_7 = 0x7, 464 }; 465 466 enum phya_b_d3_dly_set { 467 B_D3_DELAY_0 = 0x0, 468 B_D3_DELAY_1 = 0x1, 469 B_D3_DELAY_2 = 0x2, 470 B_D3_DELAY_3 = 0x3, 471 B_D3_DELAY_4 = 0x4, 472 B_D3_DELAY_5 = 0x5, 473 B_D3_DELAY_6 = 0x6, 474 B_D3_DELAY_7 = 0x7, 475 }; 476 477 enum phya_c_d3_dly_set { 478 C_D3_DELAY_0 = 0x0, 479 C_D3_DELAY_1 = 0x1, 480 C_D3_DELAY_2 = 0x2, 481 C_D3_DELAY_3 = 0x3, 482 C_D3_DELAY_4 = 0x4, 483 C_D3_DELAY_5 = 0x5, 484 C_D3_DELAY_6 = 0x6, 485 C_D3_DELAY_7 = 0x7, 486 }; 487 488 struct phya_signal_dly_ctr { 489 enum phya_a_clk_dly_set a_clk_dly; 490 enum phya_b_clk_dly_set b_clk_dly; 491 enum phya_c_clk_dly_set c_clk_dly; 492 493 enum phya_a_d0_dly_set a_d0_dly; 494 enum phya_b_d0_dly_set b_d0_dly; 495 enum phya_c_d0_dly_set c_d0_dly; 496 497 enum phya_a_d1_dly_set a_d1_dly; 498 enum phya_b_d1_dly_set b_d1_dly; 499 enum phya_c_d1_dly_set c_d1_dly; 500 501 enum phya_a_d2_dly_set a_d2_dly; 502 enum phya_b_d2_dly_set b_d2_dly; 503 enum phya_c_d2_dly_set c_d2_dly; 504 505 enum phya_a_d3_dly_set a_d3_dly; 506 enum phya_b_d3_dly_set b_d3_dly; 507 enum phya_c_d3_dly_set c_d3_dly; 508 }; 509 510 511 struct combo_lane_map { 512 enum lvds_inter_lane0_map lvds_lane0; 513 enum lvds_inter_lane1_map lvds_lane1; 514 enum lvds_inter_lane2_map lvds_lane2; 515 enum lvds_inter_lane3_map lvds_lane3; 516 enum lvds_inter_lane4_map lvds_lane4; 517 enum lvds_inter_lane5_map lvds_lane5; 518 enum lvds_inter_lane6_map lvds_lane6; 519 enum lvds_inter_lane7_map lvds_lane7; 520 enum lvds_inter_lane8_map lvds_lane8; 521 enum lvds_inter_lane9_map lvds_lane9; 522 enum lvds_inter_lane10_map lvds_lane10; 523 enum lvds_inter_lane11_map lvds_lane11; 524 }; 525 526 struct mipi_lane_map { 527 enum mipi_inter_lane0_map mipi_lane0; 528 enum mipi_inter_lane1_map mipi_lane1; 529 enum mipi_inter_lane2_map mipi_lane2; 530 enum mipi_inter_lane3_map mipi_lane3; 531 }; 532 533 struct lane_code { 534 unsigned int high_bit; 535 unsigned int low_bit; 536 }; 537 538 struct combo_sync_code { 539 struct lane_code lane_sof[12]; 540 struct lane_code lane_eof[12]; 541 struct lane_code lane_sol[12]; 542 struct lane_code lane_eol[12]; 543 }; 544 545 int cmb_rx_set_base_addr(unsigned int sel, unsigned long addr); 546 547 void cmb_rx_phya_a_d0_en(unsigned int sel, unsigned int en); 548 void cmb_rx_phya_b_d0_en(unsigned int sel, unsigned int en); 549 void cmb_rx_phya_c_d0_en(unsigned int sel, unsigned int en); 550 551 void cmb_rx_phya_a_d1_en(unsigned int sel, unsigned int en); 552 void cmb_rx_phya_b_d1_en(unsigned int sel, unsigned int en); 553 void cmb_rx_phya_c_d1_en(unsigned int sel, unsigned int en); 554 555 void cmb_rx_phya_a_d2_en(unsigned int sel, unsigned int en); 556 void cmb_rx_phya_b_d2_en(unsigned int sel, unsigned int en); 557 void cmb_rx_phya_c_d2_en(unsigned int sel, unsigned int en); 558 559 void cmb_rx_phya_a_d3_en(unsigned int sel, unsigned int en); 560 void cmb_rx_phya_b_d3_en(unsigned int sel, unsigned int en); 561 void cmb_rx_phya_c_d3_en(unsigned int sel, unsigned int en); 562 563 void cmb_rx_phya_a_ck_en(unsigned int sel, unsigned int en); 564 void cmb_rx_phya_b_ck_en(unsigned int sel, unsigned int en); 565 void cmb_rx_phya_c_ck_en(unsigned int sel, unsigned int en); 566 void cmb_rx_te_auto_disable(unsigned int sel, unsigned int en); 567 568 void cmb_rx_phya_signal_dly_en(unsigned int sel, unsigned int en); 569 void cmb_rx_phya_signal_dly_ctr(unsigned int sel, struct phya_signal_dly_ctr *phya_signal_dly); 570 571 void cmb_rx_phya_config(unsigned int sel); 572 void cmb_rx_phya_ck_mode(unsigned int sel, unsigned int mode); 573 void cmb_rx_phya_ck_pol(unsigned int sel, unsigned int pol); 574 void cmb_rx_phya_offset(unsigned int sel, unsigned int offset); 575 576 void cmb_rx_enable(unsigned int sel); 577 578 void cmb_rx_disable(unsigned int sel); 579 580 void cmb_rx_mode_sel(unsigned int sel, enum combo_rx_mode_sel mode); 581 582 void cmb_rx_app_pixel_out(unsigned int sel, enum combo_rx_pix_num pix_num); 583 584 void cmb_rx_mipi_ctr(unsigned int sel, struct mipi_ctr *mipi_ctr); 585 void cmb_rx_mipi_stl_time(unsigned int sel, unsigned char time_hs); 586 void cmb_rx_mipi_dphy_mapping(unsigned int sel, struct mipi_lane_map *mipi_map); 587 588 void cmb_rx_mipi_csi2_status(unsigned int sel, unsigned int *mipi_csi2_status); 589 590 void cmb_rx_mipi_csi2_data_id(unsigned int sel, unsigned int *mipi_csi2_data_id); 591 592 void cmb_rx_mipi_csi2_word_cnt(unsigned int sel, unsigned int *mipi_csi2_word_cnt); 593 594 void cmb_rx_mipi_csi2_ecc_val(unsigned int sel, unsigned int *mipi_csi2_ecc_val); 595 596 void cmb_rx_mipi_csi2_line_lentgh(unsigned int sel, unsigned int *mipi_csi2_line_lentgh); 597 598 void cmb_rx_mipi_csi2_rcv_cnt(unsigned int sel, unsigned int *mipi_csi2_rcv_cnt); 599 600 void cmb_rx_mipi_csi2_ecc_err_cnt(unsigned int sel, unsigned int *mipi_csi2_ecc_err_cnt); 601 602 void cmb_rx_mipi_csi2_check_sum_err_cnt(unsigned int sel, unsigned int *mipi_csi2_check_sum_err_cnt); 603 604 void cmb_rx_lvds_ctr(unsigned int sel, struct lvds_ctr *lvds_ctr); 605 606 void cmb_rx_lvds_mapping(unsigned int sel, struct combo_lane_map *lvds_map); 607 608 void cmb_rx_lvds_sync_code(unsigned int sel, struct combo_sync_code *lvds_sync_code); 609 610 void cmb_rx_hispi_ctr(unsigned int sel, struct hispi_ctr *hispi_ctr); 611 612 #endif /*__COMBO_REG__H__*/ 613