1 /* 2 * pcicfg.h: PCI configuration constants and structures. 3 * 4 * Copyright (C) 2020, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * 21 * <<Broadcom-WL-IPTag/Dual:>> 22 */ 23 24 #ifndef _h_pcicfg_ 25 #define _h_pcicfg_ 26 27 /* The following inside ifndef's so we don't collide with NTDDK.H */ 28 #ifndef PCI_MAX_BUS 29 #define PCI_MAX_BUS 0x100 30 #endif 31 #ifndef PCI_MAX_DEVICES 32 #define PCI_MAX_DEVICES 0x20 33 #endif 34 #ifndef PCI_MAX_FUNCTION 35 #define PCI_MAX_FUNCTION 0x8 36 #endif 37 38 #ifndef PCI_INVALID_VENDORID 39 #define PCI_INVALID_VENDORID 0xffff 40 #endif 41 #ifndef PCI_INVALID_DEVICEID 42 #define PCI_INVALID_DEVICEID 0xffff 43 #endif 44 45 /* Convert between bus-slot-function-register and config addresses */ 46 47 #define PCICFG_BUS_SHIFT 16 /* Bus shift */ 48 #define PCICFG_SLOT_SHIFT 11 /* Slot shift */ 49 #define PCICFG_FUN_SHIFT 8 /* Function shift */ 50 #define PCICFG_OFF_SHIFT 0 /* Register shift */ 51 52 #define PCICFG_BUS_MASK 0xff /* Bus mask */ 53 #define PCICFG_SLOT_MASK 0x1f /* Slot mask */ 54 #define PCICFG_FUN_MASK 7 /* Function mask */ 55 #define PCICFG_OFF_MASK 0xff /* Bus mask */ 56 57 #define PCI_CONFIG_ADDR(b, s, f, o) \ 58 ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \ 59 | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \ 60 | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \ 61 | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT)) 62 63 #define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK) 64 #define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK) 65 #define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK) 66 #define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK) 67 68 /* PCIE Config space accessing MACROS */ 69 70 #define PCIECFG_BUS_SHIFT 24 /* Bus shift */ 71 #define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */ 72 #define PCIECFG_FUN_SHIFT 16 /* Function shift */ 73 #define PCIECFG_OFF_SHIFT 0 /* Register shift */ 74 75 #define PCIECFG_BUS_MASK 0xff /* Bus mask */ 76 #define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */ 77 #define PCIECFG_FUN_MASK 7 /* Function mask */ 78 #define PCIECFG_OFF_MASK 0xfff /* Register mask */ 79 80 #define PCIE_CONFIG_ADDR(b, s, f, o) \ 81 ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \ 82 | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \ 83 | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \ 84 | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT)) 85 86 #define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK) 87 #define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK) 88 #define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK) 89 #define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK) 90 91 /* The actual config space */ 92 93 #define PCI_BAR_MAX 6 94 95 #define PCI_ROM_BAR 8 96 97 #define PCR_RSVDA_MAX 2 98 99 /* Bits in PCI bars' flags */ 100 101 #define PCIBAR_FLAGS 0xf 102 #define PCIBAR_IO 0x1 103 #define PCIBAR_MEM1M 0x2 104 #define PCIBAR_MEM64 0x4 105 #define PCIBAR_PREFETCH 0x8 106 #define PCIBAR_MEM32_MASK 0xFFFFFF80 107 108 typedef struct _pci_config_regs { 109 uint16 vendor; 110 uint16 device; 111 uint16 command; 112 uint16 status; 113 uint8 rev_id; 114 uint8 prog_if; 115 uint8 sub_class; 116 uint8 base_class; 117 uint8 cache_line_size; 118 uint8 latency_timer; 119 uint8 header_type; 120 uint8 bist; 121 uint32 base[PCI_BAR_MAX]; 122 uint32 cardbus_cis; 123 uint16 subsys_vendor; 124 uint16 subsys_id; 125 uint32 baserom; 126 uint32 rsvd_a[PCR_RSVDA_MAX]; 127 uint8 int_line; 128 uint8 int_pin; 129 uint8 min_gnt; 130 uint8 max_lat; 131 uint8 dev_dep[192]; 132 } pci_config_regs; 133 134 #define SZPCR (sizeof (pci_config_regs)) 135 #define MINSZPCR 64 /* offsetof (dev_dep[0] */ 136 137 /* pci config status reg has a bit to indicate that capability ptr is present */ 138 139 #define PCI_CAPPTR_PRESENT 0x0010 140 141 /* A structure for the config registers is nice, but in most 142 * systems the config space is not memory mapped, so we need 143 * field offsetts. :-( 144 */ 145 #define PCI_CFG_VID 0 146 #define PCI_CFG_DID 2 147 #define PCI_CFG_CMD 4 148 #define PCI_CFG_STAT 6 149 #define PCI_CFG_REV 8 150 #define PCI_CFG_PROGIF 9 151 #define PCI_CFG_SUBCL 0xa 152 #define PCI_CFG_BASECL 0xb 153 #define PCI_CFG_CLSZ 0xc 154 #define PCI_CFG_LATTIM 0xd 155 #define PCI_CFG_HDR 0xe 156 #define PCI_CFG_BIST 0xf 157 #define PCI_CFG_BAR0 0x10 158 #define PCI_CFG_BAR1 0x18 159 #define PCI_CFG_BAR2 0x20 160 #define PCI_CFG_CIS 0x28 161 #define PCI_CFG_SVID 0x2c 162 #define PCI_CFG_SSID 0x2e 163 #define PCI_CFG_ROMBAR 0x30 164 #define PCI_CFG_CAPPTR 0x34 165 #define PCI_CFG_INT 0x3c 166 #define PCI_CFG_PIN 0x3d 167 #define PCI_CFG_MINGNT 0x3e 168 #define PCI_CFG_MAXLAT 0x3f 169 #define PCI_CFG_DEVCTRL 0xd8 170 #define PCI_CFG_TLCNTRL_5 0x814 171 #define PCI_CFG_ERRATTN_MASK_FN0 0x8a0 172 #define PCI_CFG_ERRATTN_STATUS_FN0 0x8a4 173 #define PCI_CFG_ERRATTN_MASK_FN1 0x8a8 174 #define PCI_CFG_ERRATTN_STATUS_FN1 0x8ac 175 #define PCI_CFG_ERRATTN_MASK_CMN 0x8b0 176 #define PCI_CFG_ERRATTN_STATUS_CMN 0x8b4 177 178 #ifdef EFI 179 #undef PCI_CLASS_BRIDGE 180 #undef PCI_CLASS_OLD 181 #undef PCI_CLASS_DISPLAY 182 #undef PCI_CLASS_SERIAL 183 #undef PCI_CLASS_SATELLITE 184 #endif /* EFI */ 185 186 /* Classes and subclasses */ 187 188 typedef enum { 189 PCI_CLASS_OLD = 0, 190 PCI_CLASS_DASDI, 191 PCI_CLASS_NET, 192 PCI_CLASS_DISPLAY, 193 PCI_CLASS_MMEDIA, 194 PCI_CLASS_MEMORY, 195 PCI_CLASS_BRIDGE, 196 PCI_CLASS_COMM, 197 PCI_CLASS_BASE, 198 PCI_CLASS_INPUT, 199 PCI_CLASS_DOCK, 200 PCI_CLASS_CPU, 201 PCI_CLASS_SERIAL, 202 PCI_CLASS_INTELLIGENT = 0xe, 203 PCI_CLASS_SATELLITE, 204 PCI_CLASS_CRYPT, 205 PCI_CLASS_DSP, 206 PCI_CLASS_XOR = 0xfe 207 } pci_classes; 208 209 typedef enum { 210 PCI_DASDI_SCSI, 211 PCI_DASDI_IDE, 212 PCI_DASDI_FLOPPY, 213 PCI_DASDI_IPI, 214 PCI_DASDI_RAID, 215 PCI_DASDI_OTHER = 0x80 216 } pci_dasdi_subclasses; 217 218 typedef enum { 219 PCI_NET_ETHER, 220 PCI_NET_TOKEN, 221 PCI_NET_FDDI, 222 PCI_NET_ATM, 223 PCI_NET_OTHER = 0x80 224 } pci_net_subclasses; 225 226 typedef enum { 227 PCI_DISPLAY_VGA, 228 PCI_DISPLAY_XGA, 229 PCI_DISPLAY_3D, 230 PCI_DISPLAY_OTHER = 0x80 231 } pci_display_subclasses; 232 233 typedef enum { 234 PCI_MMEDIA_VIDEO, 235 PCI_MMEDIA_AUDIO, 236 PCI_MMEDIA_PHONE, 237 PCI_MEDIA_OTHER = 0x80 238 } pci_mmedia_subclasses; 239 240 typedef enum { 241 PCI_MEMORY_RAM, 242 PCI_MEMORY_FLASH, 243 PCI_MEMORY_OTHER = 0x80 244 } pci_memory_subclasses; 245 246 typedef enum { 247 PCI_BRIDGE_HOST, 248 PCI_BRIDGE_ISA, 249 PCI_BRIDGE_EISA, 250 PCI_BRIDGE_MC, 251 PCI_BRIDGE_PCI, 252 PCI_BRIDGE_PCMCIA, 253 PCI_BRIDGE_NUBUS, 254 PCI_BRIDGE_CARDBUS, 255 PCI_BRIDGE_RACEWAY, 256 PCI_BRIDGE_OTHER = 0x80 257 } pci_bridge_subclasses; 258 259 typedef enum { 260 PCI_COMM_UART, 261 PCI_COMM_PARALLEL, 262 PCI_COMM_MULTIUART, 263 PCI_COMM_MODEM, 264 PCI_COMM_OTHER = 0x80 265 } pci_comm_subclasses; 266 267 typedef enum { 268 PCI_BASE_PIC, 269 PCI_BASE_DMA, 270 PCI_BASE_TIMER, 271 PCI_BASE_RTC, 272 PCI_BASE_PCI_HOTPLUG, 273 PCI_BASE_OTHER = 0x80 274 } pci_base_subclasses; 275 276 typedef enum { 277 PCI_INPUT_KBD, 278 PCI_INPUT_PEN, 279 PCI_INPUT_MOUSE, 280 PCI_INPUT_SCANNER, 281 PCI_INPUT_GAMEPORT, 282 PCI_INPUT_OTHER = 0x80 283 } pci_input_subclasses; 284 285 typedef enum { 286 PCI_DOCK_GENERIC, 287 PCI_DOCK_OTHER = 0x80 288 } pci_dock_subclasses; 289 290 typedef enum { 291 PCI_CPU_386, 292 PCI_CPU_486, 293 PCI_CPU_PENTIUM, 294 PCI_CPU_ALPHA = 0x10, 295 PCI_CPU_POWERPC = 0x20, 296 PCI_CPU_MIPS = 0x30, 297 PCI_CPU_COPROC = 0x40, 298 PCI_CPU_OTHER = 0x80 299 } pci_cpu_subclasses; 300 301 typedef enum { 302 PCI_SERIAL_IEEE1394, 303 PCI_SERIAL_ACCESS, 304 PCI_SERIAL_SSA, 305 PCI_SERIAL_USB, 306 PCI_SERIAL_FIBER, 307 PCI_SERIAL_SMBUS, 308 PCI_SERIAL_OTHER = 0x80 309 } pci_serial_subclasses; 310 311 typedef enum { 312 PCI_INTELLIGENT_I2O 313 } pci_intelligent_subclasses; 314 315 typedef enum { 316 PCI_SATELLITE_TV, 317 PCI_SATELLITE_AUDIO, 318 PCI_SATELLITE_VOICE, 319 PCI_SATELLITE_DATA, 320 PCI_SATELLITE_OTHER = 0x80 321 } pci_satellite_subclasses; 322 323 typedef enum { 324 PCI_CRYPT_NETWORK, 325 PCI_CRYPT_ENTERTAINMENT, 326 PCI_CRYPT_OTHER = 0x80 327 } pci_crypt_subclasses; 328 329 typedef enum { 330 PCI_DSP_DPIO, 331 PCI_DSP_OTHER = 0x80 332 } pci_dsp_subclasses; 333 334 typedef enum { 335 PCI_XOR_QDMA, 336 PCI_XOR_OTHER = 0x80 337 } pci_xor_subclasses; 338 339 /* Overlay for a PCI-to-PCI bridge */ 340 341 #define PPB_RSVDA_MAX 2 342 #define PPB_RSVDD_MAX 8 343 344 typedef struct _ppb_config_regs { 345 uint16 vendor; 346 uint16 device; 347 uint16 command; 348 uint16 status; 349 uint8 rev_id; 350 uint8 prog_if; 351 uint8 sub_class; 352 uint8 base_class; 353 uint8 cache_line_size; 354 uint8 latency_timer; 355 uint8 header_type; 356 uint8 bist; 357 uint32 rsvd_a[PPB_RSVDA_MAX]; 358 uint8 prim_bus; 359 uint8 sec_bus; 360 uint8 sub_bus; 361 uint8 sec_lat; 362 uint8 io_base; 363 uint8 io_lim; 364 uint16 sec_status; 365 uint16 mem_base; 366 uint16 mem_lim; 367 uint16 pf_mem_base; 368 uint16 pf_mem_lim; 369 uint32 pf_mem_base_hi; 370 uint32 pf_mem_lim_hi; 371 uint16 io_base_hi; 372 uint16 io_lim_hi; 373 uint16 subsys_vendor; 374 uint16 subsys_id; 375 uint32 rsvd_b; 376 uint8 rsvd_c; 377 uint8 int_pin; 378 uint16 bridge_ctrl; 379 uint8 chip_ctrl; 380 uint8 diag_ctrl; 381 uint16 arb_ctrl; 382 uint32 rsvd_d[PPB_RSVDD_MAX]; 383 uint8 dev_dep[192]; 384 } ppb_config_regs; 385 386 /* Everything below is BRCM HND proprietary */ 387 388 /* Brcm PCI configuration registers */ 389 #define cap_list rsvd_a[0] 390 #define bar0_window dev_dep[0x80 - 0x40] 391 #define bar1_window dev_dep[0x84 - 0x40] 392 #define sprom_control dev_dep[0x88 - 0x40] 393 394 /* PCI CAPABILITY DEFINES */ 395 #define PCI_CAP_POWERMGMTCAP_ID 0x01 396 #define PCI_CAP_MSICAP_ID 0x05 397 #define PCI_CAP_VENDSPEC_ID 0x09 398 #define PCI_CAP_PCIECAP_ID 0x10 399 #define PCI_CAP_MSIXCAP_ID 0x11 400 401 /* Data structure to define the Message Signalled Interrupt facility 402 * Valid for PCI and PCIE configurations 403 */ 404 typedef struct _pciconfig_cap_msi { 405 uint8 capID; 406 uint8 nextptr; 407 uint16 msgctrl; 408 uint32 msgaddr; 409 } pciconfig_cap_msi; 410 #define MSI_ENABLE 0x1 /* bit 0 of msgctrl */ 411 412 /* Data structure to define the Power managment facility 413 * Valid for PCI and PCIE configurations 414 */ 415 typedef struct _pciconfig_cap_pwrmgmt { 416 uint8 capID; 417 uint8 nextptr; 418 uint16 pme_cap; 419 uint16 pme_sts_ctrl; 420 uint8 pme_bridge_ext; 421 uint8 data; 422 } pciconfig_cap_pwrmgmt; 423 424 #define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */ 425 #define PME_CSR_OFFSET 0x4 /* 4-bytes offset */ 426 #define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */ 427 #define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */ 428 429 /* Data structure to define the PCIE capability */ 430 typedef struct _pciconfig_cap_pcie { 431 uint8 capID; 432 uint8 nextptr; 433 uint16 pcie_cap; 434 uint32 dev_cap; 435 uint16 dev_ctrl; 436 uint16 dev_status; 437 uint32 link_cap; 438 uint16 link_ctrl; 439 uint16 link_status; 440 uint32 slot_cap; 441 uint16 slot_ctrl; 442 uint16 slot_status; 443 uint16 root_ctrl; 444 uint16 root_cap; 445 uint32 root_status; 446 } pciconfig_cap_pcie; 447 448 /* PCIE Enhanced CAPABILITY DEFINES */ 449 #define PCIE_EXTCFG_OFFSET 0x100 450 #define PCIE_ADVERRREP_CAPID 0x0001 451 #define PCIE_VC_CAPID 0x0002 452 #define PCIE_DEVSNUM_CAPID 0x0003 453 #define PCIE_PWRBUDGET_CAPID 0x0004 454 455 /* PCIE Extended configuration */ 456 #define PCIE_ADV_CORR_ERR_MASK 0x114 457 #define PCIE_ADV_CORR_ERR_MASK_OFFSET 0x14 458 #define CORR_ERR_RE (1 << 0) /* Receiver */ 459 #define CORR_ERR_BT (1 << 6) /* Bad TLP */ 460 #define CORR_ERR_BD (1 << 7) /* Bad DLLP */ 461 #define CORR_ERR_RR (1 << 8) /* REPLAY_NUM rollover */ 462 #define CORR_ERR_RT (1 << 12) /* Reply timer timeout */ 463 #define CORR_ERR_AE (1 << 13) /* Adviosry Non-Fital Error Mask */ 464 #define ALL_CORR_ERRORS (CORR_ERR_RE | CORR_ERR_BT | CORR_ERR_BD | \ 465 CORR_ERR_RR | CORR_ERR_RT) 466 467 /* PCIE Root Control Register bits (Host mode only) */ 468 #define PCIE_RC_CORR_SERR_EN 0x0001 469 #define PCIE_RC_NONFATAL_SERR_EN 0x0002 470 #define PCIE_RC_FATAL_SERR_EN 0x0004 471 #define PCIE_RC_PME_INT_EN 0x0008 472 #define PCIE_RC_CRS_EN 0x0010 473 474 /* PCIE Root Capability Register bits (Host mode only) */ 475 #define PCIE_RC_CRS_VISIBILITY 0x0001 476 477 /* PCIe PMCSR Register bits */ 478 #define PCIE_PMCSR_PMESTAT 0x8000 479 480 /* Header to define the PCIE specific capabilities in the extended config space */ 481 typedef struct _pcie_enhanced_caphdr { 482 uint16 capID; 483 uint16 cap_ver : 4; 484 uint16 next_ptr : 12; 485 } pcie_enhanced_caphdr; 486 487 #define PCIE_CFG_PMCSR 0x4C 488 #define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */ 489 #define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */ 490 #define PCI_SPROM_CONTROL 0x88 /* sprom property control */ 491 #define PCIE_CFG_SUBSYSTEM_CONTROL 0x88 /* used as subsystem control in PCIE devices */ 492 #define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */ 493 #define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */ 494 #define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */ 495 #define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */ 496 #define PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */ 497 #define PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */ 498 #define PCI_CLK_CTL_ST 0xa8 /* pci config space clock control/status (>=rev14) */ 499 #define PCI_BAR0_WIN2 0xac /* backplane addres space accessed by second 4KB of BAR0 */ 500 #define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */ 501 #define PCIE_CFG_DEVICE_CAPABILITY 0xb0 /* used as device capability in PCIE devices */ 502 #define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */ 503 #define PCIE_CFG_DEVICE_CONTROL 0xb4 /* 0xb4 is used as device control in PCIE devices */ 504 #define PCIE_DC_AER_CORR_EN (1u << 0u) 505 #define PCIE_DC_AER_NON_FATAL_EN (1u << 1u) 506 #define PCIE_DC_AER_FATAL_EN (1u << 2u) 507 #define PCIE_DC_AER_UNSUP_EN (1u << 3u) 508 509 #define PCI_BAR0_WIN2_OFFSET 0x1000u 510 #define PCIE2_BAR0_CORE2_WIN2_OFFSET 0x5000u 511 512 #define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */ 513 #define PCI_L1SS_CTRL2 0x24c /* The L1 PM Substates Control register */ 514 515 /* Private Registers */ 516 #define PCI_STAT_CTRL 0xa80 517 #define PCI_L0_EVENTCNT 0xa84 518 #define PCI_L0_STATETMR 0xa88 519 #define PCI_L1_EVENTCNT 0xa8c 520 #define PCI_L1_STATETMR 0xa90 521 #define PCI_L1_1_EVENTCNT 0xa94 522 #define PCI_L1_1_STATETMR 0xa98 523 #define PCI_L1_2_EVENTCNT 0xa9c 524 #define PCI_L1_2_STATETMR 0xaa0 525 #define PCI_L2_EVENTCNT 0xaa4 526 #define PCI_L2_STATETMR 0xaa8 527 528 #define PCI_LINK_STATUS 0x4dc 529 #define PCI_LINK_SPEED_MASK (15u << 0u) 530 #define PCI_LINK_SPEED_SHIFT (0) 531 #define PCIE_LNK_SPEED_GEN1 0x1 532 #define PCIE_LNK_SPEED_GEN2 0x2 533 #define PCIE_LNK_SPEED_GEN3 0x3 534 535 #define PCI_PL_SPARE 0x1808 /* Config to Increase external clkreq deasserted minimum time */ 536 #define PCI_CONFIG_EXT_CLK_MIN_TIME_MASK (1u << 31u) 537 #define PCI_CONFIG_EXT_CLK_MIN_TIME_SHIFT (31) 538 539 #define PCI_ADV_ERR_CAP 0x100 540 #define PCI_UC_ERR_STATUS 0x104 541 #define PCI_UNCORR_ERR_MASK 0x108 542 #define PCI_UCORR_ERR_SEVR 0x10c 543 #define PCI_CORR_ERR_STATUS 0x110 544 #define PCI_CORR_ERR_MASK 0x114 545 #define PCI_ERR_CAP_CTRL 0x118 546 #define PCI_TLP_HDR_LOG1 0x11c 547 #define PCI_TLP_HDR_LOG2 0x120 548 #define PCI_TLP_HDR_LOG3 0x124 549 #define PCI_TLP_HDR_LOG4 0x128 550 #define PCI_TL_CTRL_5 0x814 551 #define PCI_TL_HDR_FC_ST 0x980 552 #define PCI_TL_TGT_CRDT_ST 0x990 553 #define PCI_TL_SMLOGIC_ST 0x998 554 #define PCI_DL_ATTN_VEC 0x1040 555 #define PCI_DL_STATUS 0x1048 556 557 #define PCI_PHY_CTL_0 0x1800 558 #define PCI_SLOW_PMCLK_EXT_RLOCK (1 << 7) 559 #define PCI_REG_TX_DEEMPH_3_5_DB (1 << 21) 560 561 #define PCI_LINK_STATE_DEBUG 0x1c24 562 #define PCI_RECOVERY_HIST 0x1ce4 563 #define PCI_PHY_LTSSM_HIST_0 0x1cec 564 #define PCI_PHY_LTSSM_HIST_1 0x1cf0 565 #define PCI_PHY_LTSSM_HIST_2 0x1cf4 566 #define PCI_PHY_LTSSM_HIST_3 0x1cf8 567 #define PCI_PHY_DBG_CLKREG_0 0x1e10 568 #define PCI_PHY_DBG_CLKREG_1 0x1e14 569 #define PCI_PHY_DBG_CLKREG_2 0x1e18 570 #define PCI_PHY_DBG_CLKREG_3 0x1e1c 571 572 #define PCI_TL_CTRL_0 0x800u 573 #define PCI_BEACON_DIS (1u << 20u) /* Disable Beacon Generation */ 574 575 /* Bit settings for PCIE_CFG_SUBSYSTEM_CONTROL register */ 576 #define PCIE_BAR1COHERENTACCEN_BIT 8 577 #define PCIE_BAR2COHERENTACCEN_BIT 9 578 #define PCIE_SSRESET_STATUS_BIT 13 579 #define PCIE_SSRESET_DISABLE_BIT 14 580 #define PCIE_SSRESET_DIS_ENUM_RST_BIT 15 581 582 #define PCIE_BARCOHERENTACCEN_MASK 0x300 583 584 /* Bit settings for PCI_UC_ERR_STATUS register */ 585 #define PCI_UC_ERR_URES (1 << 20) /* Unsupported Request Error Status */ 586 #define PCI_UC_ERR_ECRCS (1 << 19) /* ECRC Error Status */ 587 #define PCI_UC_ERR_MTLPS (1 << 18) /* Malformed TLP Status */ 588 #define PCI_UC_ERR_ROS (1 << 17) /* Receiver Overflow Status */ 589 #define PCI_UC_ERR_UCS (1 << 16) /* Unexpected Completion Status */ 590 #define PCI_UC_ERR_CAS (1 << 15) /* Completer Abort Status */ 591 #define PCI_UC_ERR_CTS (1 << 14) /* Completer Timeout Status */ 592 #define PCI_UC_ERR_FCPES (1 << 13) /* Flow Control Protocol Error Status */ 593 #define PCI_UC_ERR_PTLPS (1 << 12) /* Poisoned TLP Status */ 594 #define PCI_UC_ERR_DLPES (1 << 4) /* Data Link Protocol Error Status */ 595 596 #define PCI_DL_STATUS_PHY_LINKUP (1 << 13) /* Status of LINK */ 597 598 #define PCI_PMCR_REFUP 0x1814 /* Trefup time */ 599 #define PCI_PMCR_TREFUP_LO_MASK 0x3f 600 #define PCI_PMCR_TREFUP_LO_SHIFT 24 601 #define PCI_PMCR_TREFUP_LO_BITS 6 602 #define PCI_PMCR_TREFUP_HI_MASK 0xf 603 #define PCI_PMCR_TREFUP_HI_SHIFT 5 604 #define PCI_PMCR_TREFUP_HI_BITS 4 605 #define PCI_PMCR_TREFUP_MAX 0x400 606 #define PCI_PMCR_TREFUP_MAX_SCALE 0x2000 607 608 #define PCI_PMCR_REFUP_EXT 0x1818 /* Trefup extend Max */ 609 #define PCI_PMCR_TREFUP_EXT_SHIFT 22 610 #define PCI_PMCR_TREFUP_EXT_SCALE 3 611 #define PCI_PMCR_TREFUP_EXT_ON 1 612 #define PCI_PMCR_TREFUP_EXT_OFF 0 613 614 #define PCI_TPOWER_SCALE_MASK 0x3 615 #define PCI_TPOWER_SCALE_SHIFT 3 /* 0:1 is scale and 2 is rsvd */ 616 617 #define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */ 618 #define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */ 619 #define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */ 620 #define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the 621 * 8KB window, so their address is the "regular" 622 * address plus 4K 623 */ 624 /* 625 * PCIE GEN2 changed some of the above locations for 626 * Bar0WrapperBase, SecondaryBAR0Window and SecondaryBAR0WrapperBase 627 * BAR0 maps 32K of register space 628 */ 629 #define PCIE2_BAR0_WIN2 0x70 /* config register to map 2nd 4KB of BAR0 */ 630 #define PCIE2_BAR0_CORE2_WIN 0x74 /* config register to map 5th 4KB of BAR0 */ 631 #define PCIE2_BAR0_CORE2_WIN2 0x78 /* config register to map 6th 4KB of BAR0 */ 632 633 /* PCIE GEN2 BAR0 window size */ 634 #define PCIE2_BAR0_WINSZ 0x8000 635 636 #define PCI_BAR0_WIN2_OFFSET 0x1000u 637 #define PCI_CORE_ENUM_OFFSET 0x2000u 638 #define PCI_CC_CORE_ENUM_OFFSET 0x3000u 639 #define PCI_SEC_BAR0_WIN_OFFSET 0x4000u 640 #define PCI_SEC_BAR0_WRAP_OFFSET 0x5000u 641 #define PCI_CORE_ENUM2_OFFSET 0x6000u 642 #define PCI_CC_CORE_ENUM2_OFFSET 0x7000u 643 #define PCI_TER_BAR0_WIN_OFFSET 0x9000u 644 #define PCI_TER_BAR0_WRAP_OFFSET 0xa000u 645 646 #define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */ 647 /* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */ 648 #define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */ 649 #define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */ 650 #define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */ 651 #define PCI_SECOND_BAR0_OFFSET (16 * 1024) /* secondary bar 0 window */ 652 653 /* On AI chips we have a second window to map DMP regs are mapped: */ 654 #define PCI_16KB0_WIN2_OFFSET (4 * 1024) /* bar0 + 4K is "Window 2" */ 655 656 /* PCI_INT_STATUS */ 657 #define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */ 658 659 /* PCI_INT_MASK */ 660 #define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */ 661 #define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */ 662 #define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */ 663 #define PCI_CTO_INT_SHIFT 16 /* backplane SBErr interrupt mask */ 664 #define PCI_CTO_INT_MASK (1 << PCI_CTO_INT_SHIFT) /* backplane SBErr interrupt mask */ 665 666 /* PCI_SPROM_CONTROL */ 667 #define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */ 668 #define SPROM_LOCKED 0x08 /* SPROM Locked */ 669 #define SPROM_BLANK 0x04 /* indicating a blank SPROM */ 670 #define SPROM_WRITEEN 0x10 /* SPROM write enable */ 671 #define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */ 672 #define SPROM_BACKPLANE_EN 0x40 /* Enable indirect backplane access */ 673 #define SPROM_OTPIN_USE 0x80 /* device OTP In use */ 674 #define SPROM_BAR1_COHERENT_ACC_EN 0x100 /* PCIe acceeses through BAR1 are coherent */ 675 #define SPROM_BAR2_COHERENT_ACC_EN 0x200 /* PCIe acceeses through BAR2 are coherent */ 676 #define SPROM_CFG_TO_SB_RST 0x400 /* backplane reset */ 677 678 /* Bits in PCI command and status regs */ 679 #define PCI_CMD_IO 0x00000001 /* I/O enable */ 680 #define PCI_CMD_MEMORY 0x00000002 /* Memory enable */ 681 #define PCI_CMD_MASTER 0x00000004 /* Master enable */ 682 #define PCI_CMD_SPECIAL 0x00000008 /* Special cycles enable */ 683 #define PCI_CMD_INVALIDATE 0x00000010 /* Invalidate? */ 684 #define PCI_CMD_VGA_PAL 0x00000040 /* VGA Palate */ 685 #define PCI_STAT_TA 0x08000000 /* target abort status */ 686 687 /* Header types */ 688 #define PCI_HEADER_MULTI 0x80 689 #define PCI_HEADER_MASK 0x7f 690 typedef enum { 691 PCI_HEADER_NORMAL, 692 PCI_HEADER_BRIDGE, 693 PCI_HEADER_CARDBUS 694 } pci_header_types; 695 696 #define PCI_CONFIG_SPACE_SIZE 256 697 698 #define DWORD_ALIGN(x) ((x) & ~(0x03)) 699 #define BYTE_POS(x) ((x) & 0x3) 700 #define WORD_POS(x) ((x) & 0x1) 701 702 #define BYTE_SHIFT(x) (8 * BYTE_POS(x)) 703 #define WORD_SHIFT(x) (16 * WORD_POS(x)) 704 705 #define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF) 706 #define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF) 707 708 #define read_pci_cfg_byte(a) \ 709 BYTE_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) 710 711 #define read_pci_cfg_word(a) \ 712 WORD_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) 713 714 #define write_pci_cfg_byte(a, val) do { \ 715 uint32 tmpval; \ 716 tmpval = OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4); \ 717 tmpval &= ~(0xFF << BYTE_SHIFT(a)); \ 718 tmpval |= ((uint8)(val)) << BYTE_SHIFT(a); \ 719 OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \ 720 } while (0) 721 722 #define write_pci_cfg_word(a, val) do { \ 723 uint32 tmpval; \ 724 tmpval = OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4); \ 725 tmpval &= ~(0xFFFF << WORD_SHIFT(a))); \ 726 tmpval |= ((uint16)(val)) << WORD_SHIFT(a); \ 727 OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \ 728 } while (0) 729 730 #endif /* _h_pcicfg_ */ 731