1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_PIXELMUX_H 10 #define HPM_PIXELMUX_H 11 12 typedef struct { 13 __RW uint32_t PIXMUX; /* 0x0: pixel path mux register */ 14 __RW uint32_t DSI_SETTING[2]; /* 0x4 - 0x8: DSI0 config register */ 15 __RW uint32_t MISC; /* 0xC: common register */ 16 __RW uint32_t GPR_WR_D0; /* 0x10: gpr write-read register 0 */ 17 __RW uint32_t GPR_WR_D1; /* 0x14: gpr write-read register 1 */ 18 __RW uint32_t GPR_WR_D2; /* 0x18: gpr write-read register 2 */ 19 __RW uint32_t GPR_WR_D3; /* 0x1C: gpr write-read register 3 */ 20 __RW uint32_t GPR_WR_D4; /* 0x20: gpr write-read register 4 */ 21 __RW uint32_t GPR_WR_D5; /* 0x24: gpr write-read register 5 */ 22 __RW uint32_t GPR_WR_D6; /* 0x28: gpr write-read register 6 */ 23 __RW uint32_t GPR_WR_D7; /* 0x2C: gpr write-read register 7 */ 24 __RW uint32_t GPR_WR_D8; /* 0x30: gpr write-read register 8 */ 25 __RW uint32_t GPR_WR_D9; /* 0x34: gpr write-read register 9 */ 26 __R uint32_t GPR_RO_D0; /* 0x38: gpr read-only register 0 */ 27 __R uint32_t GPR_RO_D1; /* 0x3C: gpr read-only register 1 */ 28 __R uint32_t GPR_RO_D2; /* 0x40: gpr read-only register 2 */ 29 __R uint32_t GPR_RO_D3; /* 0x44: gpr read-only register 3 */ 30 __R uint32_t GPR_RO_D4; /* 0x48: gpr read-only register 4 */ 31 __R uint32_t GPR_RO_D5; /* 0x4C: gpr read-only register 5 */ 32 __R uint32_t GPR_RO_D6; /* 0x50: gpr read-only register 6 */ 33 __R uint32_t GPR_RO_D7; /* 0x54: gpr read-only register 7 */ 34 __R uint32_t GPR_RO_D8; /* 0x58: gpr read-only register 8 */ 35 __R uint32_t GPR_RO_D9; /* 0x5C: gpr read-only register 9 */ 36 __RW uint32_t GPR_WR1_CLR_D0; /* 0x60: gpr write1 set/no-write clr register */ 37 } PIXELMUX_Type; 38 39 40 /* Bitfield definition for register: PIXMUX */ 41 /* 42 * RGB_EN (RW) 43 * 44 * RGB pixel bus enable 45 */ 46 #define PIXELMUX_PIXMUX_RGB_EN_MASK (0x20000000UL) 47 #define PIXELMUX_PIXMUX_RGB_EN_SHIFT (29U) 48 #define PIXELMUX_PIXMUX_RGB_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_RGB_EN_SHIFT) & PIXELMUX_PIXMUX_RGB_EN_MASK) 49 #define PIXELMUX_PIXMUX_RGB_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_RGB_EN_MASK) >> PIXELMUX_PIXMUX_RGB_EN_SHIFT) 50 51 /* 52 * RGB_SEL (RW) 53 * 54 * RGB pixel bus selection 55 * 1: LCDC1 56 * 0: LCDC0 57 */ 58 #define PIXELMUX_PIXMUX_RGB_SEL_MASK (0x10000000UL) 59 #define PIXELMUX_PIXMUX_RGB_SEL_SHIFT (28U) 60 #define PIXELMUX_PIXMUX_RGB_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_RGB_SEL_SHIFT) & PIXELMUX_PIXMUX_RGB_SEL_MASK) 61 #define PIXELMUX_PIXMUX_RGB_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_RGB_SEL_MASK) >> PIXELMUX_PIXMUX_RGB_SEL_SHIFT) 62 63 /* 64 * GWC1_EN (RW) 65 * 66 * GWC1 pixel bus enable 67 */ 68 #define PIXELMUX_PIXMUX_GWC1_EN_MASK (0x8000000UL) 69 #define PIXELMUX_PIXMUX_GWC1_EN_SHIFT (27U) 70 #define PIXELMUX_PIXMUX_GWC1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC1_EN_SHIFT) & PIXELMUX_PIXMUX_GWC1_EN_MASK) 71 #define PIXELMUX_PIXMUX_GWC1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC1_EN_MASK) >> PIXELMUX_PIXMUX_GWC1_EN_SHIFT) 72 73 /* 74 * GWC1_SEL (RW) 75 * 76 * GWC1 pixel bus selection 77 * 1: LCDC1 78 * 0: LCDC0 79 */ 80 #define PIXELMUX_PIXMUX_GWC1_SEL_MASK (0x4000000UL) 81 #define PIXELMUX_PIXMUX_GWC1_SEL_SHIFT (26U) 82 #define PIXELMUX_PIXMUX_GWC1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC1_SEL_SHIFT) & PIXELMUX_PIXMUX_GWC1_SEL_MASK) 83 #define PIXELMUX_PIXMUX_GWC1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC1_SEL_MASK) >> PIXELMUX_PIXMUX_GWC1_SEL_SHIFT) 84 85 /* 86 * GWC0_EN (RW) 87 * 88 * GWC0 pixel bus enable 89 */ 90 #define PIXELMUX_PIXMUX_GWC0_EN_MASK (0x2000000UL) 91 #define PIXELMUX_PIXMUX_GWC0_EN_SHIFT (25U) 92 #define PIXELMUX_PIXMUX_GWC0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC0_EN_SHIFT) & PIXELMUX_PIXMUX_GWC0_EN_MASK) 93 #define PIXELMUX_PIXMUX_GWC0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC0_EN_MASK) >> PIXELMUX_PIXMUX_GWC0_EN_SHIFT) 94 95 /* 96 * GWC0_SEL (RW) 97 * 98 * GWC0 pixel bus selection 99 * 1: LCDC1 100 * 0: LCDC0 101 */ 102 #define PIXELMUX_PIXMUX_GWC0_SEL_MASK (0x1000000UL) 103 #define PIXELMUX_PIXMUX_GWC0_SEL_SHIFT (24U) 104 #define PIXELMUX_PIXMUX_GWC0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC0_SEL_SHIFT) & PIXELMUX_PIXMUX_GWC0_SEL_MASK) 105 #define PIXELMUX_PIXMUX_GWC0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC0_SEL_MASK) >> PIXELMUX_PIXMUX_GWC0_SEL_SHIFT) 106 107 /* 108 * LVB_DI1_EN (RW) 109 * 110 * LVB DI1 pixel bus enable 111 */ 112 #define PIXELMUX_PIXMUX_LVB_DI1_EN_MASK (0x800000UL) 113 #define PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT (23U) 114 #define PIXELMUX_PIXMUX_LVB_DI1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT) & PIXELMUX_PIXMUX_LVB_DI1_EN_MASK) 115 #define PIXELMUX_PIXMUX_LVB_DI1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI1_EN_MASK) >> PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT) 116 117 /* 118 * LVB_DI1_SEL (RW) 119 * 120 * LVB DI1 pixel bus selection 121 * 1: LCDC1 122 * 0: LCDC0 123 */ 124 #define PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK (0x400000UL) 125 #define PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT (22U) 126 #define PIXELMUX_PIXMUX_LVB_DI1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT) & PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK) 127 #define PIXELMUX_PIXMUX_LVB_DI1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK) >> PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT) 128 129 /* 130 * LVB_DI0_EN (RW) 131 * 132 * LVB DI0 pixel bus enable 133 */ 134 #define PIXELMUX_PIXMUX_LVB_DI0_EN_MASK (0x200000UL) 135 #define PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT (21U) 136 #define PIXELMUX_PIXMUX_LVB_DI0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT) & PIXELMUX_PIXMUX_LVB_DI0_EN_MASK) 137 #define PIXELMUX_PIXMUX_LVB_DI0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI0_EN_MASK) >> PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT) 138 139 /* 140 * LVB_DI0_SEL (RW) 141 * 142 * LVB DI0 pixel bus selection 143 * 1: LCDC1 144 * 0: LCDC0 145 */ 146 #define PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK (0x100000UL) 147 #define PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT (20U) 148 #define PIXELMUX_PIXMUX_LVB_DI0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT) & PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK) 149 #define PIXELMUX_PIXMUX_LVB_DI0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK) >> PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT) 150 151 /* 152 * DSI1_EN (RW) 153 * 154 * DSI0 pixel bus enable 155 */ 156 #define PIXELMUX_PIXMUX_DSI1_EN_MASK (0x80000UL) 157 #define PIXELMUX_PIXMUX_DSI1_EN_SHIFT (19U) 158 #define PIXELMUX_PIXMUX_DSI1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI1_EN_SHIFT) & PIXELMUX_PIXMUX_DSI1_EN_MASK) 159 #define PIXELMUX_PIXMUX_DSI1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI1_EN_MASK) >> PIXELMUX_PIXMUX_DSI1_EN_SHIFT) 160 161 /* 162 * DSI1_SEL (RW) 163 * 164 * DSI0 pixel bus selection 165 * 1: LCDC1 166 * 0: LCDC0 167 */ 168 #define PIXELMUX_PIXMUX_DSI1_SEL_MASK (0x40000UL) 169 #define PIXELMUX_PIXMUX_DSI1_SEL_SHIFT (18U) 170 #define PIXELMUX_PIXMUX_DSI1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI1_SEL_SHIFT) & PIXELMUX_PIXMUX_DSI1_SEL_MASK) 171 #define PIXELMUX_PIXMUX_DSI1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI1_SEL_MASK) >> PIXELMUX_PIXMUX_DSI1_SEL_SHIFT) 172 173 /* 174 * DSI0_EN (RW) 175 * 176 * DSI1 pixel bus enable 177 */ 178 #define PIXELMUX_PIXMUX_DSI0_EN_MASK (0x20000UL) 179 #define PIXELMUX_PIXMUX_DSI0_EN_SHIFT (17U) 180 #define PIXELMUX_PIXMUX_DSI0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI0_EN_SHIFT) & PIXELMUX_PIXMUX_DSI0_EN_MASK) 181 #define PIXELMUX_PIXMUX_DSI0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI0_EN_MASK) >> PIXELMUX_PIXMUX_DSI0_EN_SHIFT) 182 183 /* 184 * DSI0_SEL (RW) 185 * 186 * DSI1 pixel bus selection 187 * 1: LCDC1 188 * 0: LCDC0 189 */ 190 #define PIXELMUX_PIXMUX_DSI0_SEL_MASK (0x10000UL) 191 #define PIXELMUX_PIXMUX_DSI0_SEL_SHIFT (16U) 192 #define PIXELMUX_PIXMUX_DSI0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI0_SEL_SHIFT) & PIXELMUX_PIXMUX_DSI0_SEL_MASK) 193 #define PIXELMUX_PIXMUX_DSI0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI0_SEL_MASK) >> PIXELMUX_PIXMUX_DSI0_SEL_SHIFT) 194 195 /* 196 * CAM1_EN (RW) 197 * 198 * CAM1 pixel bus enable 199 */ 200 #define PIXELMUX_PIXMUX_CAM1_EN_MASK (0x80U) 201 #define PIXELMUX_PIXMUX_CAM1_EN_SHIFT (7U) 202 #define PIXELMUX_PIXMUX_CAM1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM1_EN_SHIFT) & PIXELMUX_PIXMUX_CAM1_EN_MASK) 203 #define PIXELMUX_PIXMUX_CAM1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM1_EN_MASK) >> PIXELMUX_PIXMUX_CAM1_EN_SHIFT) 204 205 /* 206 * CAM1_SEL (RW) 207 * 208 * CAM1 pixel bus selection 209 * 111: Reserved 210 * 110: LCB1 211 * 101: LCB0 212 * 100: LCDC1 213 * 011: LCDC0 214 * 010: CSI1 215 * 001: CSI0 216 * 000: DVP 217 */ 218 #define PIXELMUX_PIXMUX_CAM1_SEL_MASK (0x70U) 219 #define PIXELMUX_PIXMUX_CAM1_SEL_SHIFT (4U) 220 #define PIXELMUX_PIXMUX_CAM1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM1_SEL_SHIFT) & PIXELMUX_PIXMUX_CAM1_SEL_MASK) 221 #define PIXELMUX_PIXMUX_CAM1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM1_SEL_MASK) >> PIXELMUX_PIXMUX_CAM1_SEL_SHIFT) 222 223 /* 224 * CAM0_EN (RW) 225 * 226 * CAM0 pixel bus enable 227 */ 228 #define PIXELMUX_PIXMUX_CAM0_EN_MASK (0x8U) 229 #define PIXELMUX_PIXMUX_CAM0_EN_SHIFT (3U) 230 #define PIXELMUX_PIXMUX_CAM0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM0_EN_SHIFT) & PIXELMUX_PIXMUX_CAM0_EN_MASK) 231 #define PIXELMUX_PIXMUX_CAM0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM0_EN_MASK) >> PIXELMUX_PIXMUX_CAM0_EN_SHIFT) 232 233 /* 234 * CAM0_SEL (RW) 235 * 236 * CAM0 pixel bus selection 237 * 111: Reserved 238 * 110: LCB1 239 * 101: LCB0 240 * 100: LCDC1 241 * 011: LCDC0 242 * 010: CSI1 243 * 001: CSI0 244 * 000: DVP 245 */ 246 #define PIXELMUX_PIXMUX_CAM0_SEL_MASK (0x7U) 247 #define PIXELMUX_PIXMUX_CAM0_SEL_SHIFT (0U) 248 #define PIXELMUX_PIXMUX_CAM0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM0_SEL_SHIFT) & PIXELMUX_PIXMUX_CAM0_SEL_MASK) 249 #define PIXELMUX_PIXMUX_CAM0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM0_SEL_MASK) >> PIXELMUX_PIXMUX_CAM0_SEL_SHIFT) 250 251 /* Bitfield definition for register array: DSI_SETTING */ 252 /* 253 * DSI_DATA_ENABLE (RW) 254 * 255 * DSI pixel data type enable: 256 * Bit0: RGB565_CFG1 257 * Bit1: RGB565_CFG2 258 * Bit2: RGB565_CFG3 259 * Bit3: RGB666_CFG1 260 * Bit4: RGB666_CFG2 261 * Bit5: RGB888 262 * Bit6: RGB_10BIT 263 * Bit7: RGB_12BIT, no support 264 * Bit8: YUV422_12BIT, no support 265 * Bit9: YUV422_10BIT, no support 266 * Bit10: YUV422_8BIT, no support 267 * Bit11:YUV420_8BIT,no support 268 * others: Reserved 269 */ 270 #define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK (0xFFFF0000UL) 271 #define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT (16U) 272 #define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SET(x) (((uint32_t)(x) << PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT) & PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK) 273 #define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_GET(x) (((uint32_t)(x) & PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK) >> PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT) 274 275 /* 276 * DSI_DATA_TYPE (RW) 277 * 278 * DSI input pixel data type: 279 * ‘h0: RGB565_CFG1 280 * ‘h1: RGB565_CFG2 281 * ‘h2: RGB565_CFG3 282 * ‘h3: RGB666_CFG1 283 * ‘h4: RGB666_CFG2 284 * ‘h5: RGB888 285 * ‘h6: RGB_10BIT 286 * ‘h7: RGB_12BIT, no support 287 * ‘h8:YUV422_12BIT,no support 288 * ‘h9: YUV422_10BIT, no support 289 * ‘ha: YUV422_8BIT, no support 290 * ‘hb: YUV420_8BIT,no support 291 * ‘hc~’hf: Reserved 292 */ 293 #define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK (0xFU) 294 #define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT (0U) 295 #define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SET(x) (((uint32_t)(x) << PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT) & PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK) 296 #define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_GET(x) (((uint32_t)(x) & PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK) >> PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT) 297 298 /* Bitfield definition for register: MISC */ 299 /* 300 * LVB_DI1_CTL (RW) 301 * 302 * LVB DI1 optional general purpose control which is usually unused by display 303 */ 304 #define PIXELMUX_MISC_LVB_DI1_CTL_MASK (0x2U) 305 #define PIXELMUX_MISC_LVB_DI1_CTL_SHIFT (1U) 306 #define PIXELMUX_MISC_LVB_DI1_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_MISC_LVB_DI1_CTL_SHIFT) & PIXELMUX_MISC_LVB_DI1_CTL_MASK) 307 #define PIXELMUX_MISC_LVB_DI1_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_MISC_LVB_DI1_CTL_MASK) >> PIXELMUX_MISC_LVB_DI1_CTL_SHIFT) 308 309 /* 310 * LVB_DI0_CTL (RW) 311 * 312 * LVB DI0 optional general purpose control which is usually unused by display 313 */ 314 #define PIXELMUX_MISC_LVB_DI0_CTL_MASK (0x1U) 315 #define PIXELMUX_MISC_LVB_DI0_CTL_SHIFT (0U) 316 #define PIXELMUX_MISC_LVB_DI0_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_MISC_LVB_DI0_CTL_SHIFT) & PIXELMUX_MISC_LVB_DI0_CTL_MASK) 317 #define PIXELMUX_MISC_LVB_DI0_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_MISC_LVB_DI0_CTL_MASK) >> PIXELMUX_MISC_LVB_DI0_CTL_SHIFT) 318 319 /* Bitfield definition for register: GPR_WR_D0 */ 320 /* 321 * CSI1_CFG_AP_IF_CHECK_EN (RW) 322 * 323 * csi1 apb interface parity check enable 324 */ 325 #define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK (0x7C00000UL) 326 #define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT (22U) 327 #define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK) 328 #define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT) 329 330 /* 331 * CSI1_CFG_AP_IF_INT_EN (RW) 332 * 333 * csi1 apb interface error interrupt enable 334 */ 335 #define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK (0x200000UL) 336 #define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT (21U) 337 #define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK) 338 #define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT) 339 340 /* 341 * CSI1_CFG_APB_SLVERROR_EN (RW) 342 * 343 * csi1 apb interface error check enable 344 */ 345 #define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK (0x100000UL) 346 #define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT (20U) 347 #define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK) 348 #define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT) 349 350 /* 351 * CSI0_CFG_AP_IF_CHECK_EN (RW) 352 * 353 * csi0 apb interface parity check enable 354 */ 355 #define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK (0x7C000UL) 356 #define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT (14U) 357 #define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK) 358 #define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT) 359 360 /* 361 * CSI0_CFG_AP_IF_INT_EN (RW) 362 * 363 * csi0 apb interface error interrupt enable 364 */ 365 #define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK (0x2000U) 366 #define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT (13U) 367 #define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK) 368 #define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT) 369 370 /* 371 * CSI0_CFG_APB_SLVERROR_EN (RW) 372 * 373 * csi0 apb interface error check enable 374 */ 375 #define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK (0x1000U) 376 #define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT (12U) 377 #define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK) 378 #define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT) 379 380 /* 381 * DSI1_DPIUPDATECFG (RW) 382 * 383 * dsi1 dpi update configure 384 */ 385 #define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK (0x200U) 386 #define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT (9U) 387 #define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK) 388 #define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT) 389 390 /* 391 * DSI1_DPICOLORM (RW) 392 * 393 * dsi1 dpi cholor mode control 394 */ 395 #define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK (0x100U) 396 #define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT (8U) 397 #define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK) 398 #define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT) 399 400 /* 401 * DSI1_DPISHUTDN (RW) 402 * 403 * dsi1 dpi shuntdown control 404 */ 405 #define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK (0x80U) 406 #define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT (7U) 407 #define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK) 408 #define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT) 409 410 /* 411 * DSI0_DPIUPDATECFG (RW) 412 * 413 * dsi0 dpi update configure 414 */ 415 #define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK (0x40U) 416 #define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT (6U) 417 #define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK) 418 #define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT) 419 420 /* 421 * DSI0_DPICOLORM (RW) 422 * 423 * dsi0 dpi cholor mode control 424 */ 425 #define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK (0x20U) 426 #define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT (5U) 427 #define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK) 428 #define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT) 429 430 /* 431 * DSI0_DPISHUTDN (RW) 432 * 433 * dsi0 dpi shuntdown control 434 */ 435 #define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK (0x10U) 436 #define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT (4U) 437 #define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK) 438 #define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT) 439 440 /* 441 * CSI1_SOFT_RESET_N (RW) 442 * 443 * csi controller 1 reset, active low 444 */ 445 #define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK (0x8U) 446 #define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT (3U) 447 #define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK) 448 #define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT) 449 450 /* 451 * CSI0_SOFT_RESET_N (RW) 452 * 453 * csi controller 0 reset, active low 454 */ 455 #define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK (0x4U) 456 #define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT (2U) 457 #define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK) 458 #define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT) 459 460 /* 461 * DSI1_SOFT_RESET_N (RW) 462 * 463 * dsi controller 1 reset, active low 464 */ 465 #define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK (0x2U) 466 #define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT (1U) 467 #define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK) 468 #define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT) 469 470 /* 471 * DSI0_SOFT_RESET_N (RW) 472 * 473 * dsi controller 0 reset, active low 474 */ 475 #define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK (0x1U) 476 #define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT (0U) 477 #define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK) 478 #define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT) 479 480 /* Bitfield definition for register: GPR_WR_D1 */ 481 /* 482 * JPEG_CTRL (RW) 483 * 484 * bit0: select cam0; 485 * bit1: select cam1; 486 * bit2: select jpeg; 487 * bit3: select pdma 488 */ 489 #define PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK (0xF000000UL) 490 #define PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT (24U) 491 #define PIXELMUX_GPR_WR_D1_JPEG_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK) 492 #define PIXELMUX_GPR_WR_D1_JPEG_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT) 493 494 /* 495 * PDMA_P1_CTRL (RW) 496 * 497 * bit0: select cam0; 498 * bit1: select cam1; 499 * bit2: select jpeg; 500 * bit3: select pdma 501 */ 502 #define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK (0xF00000UL) 503 #define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT (20U) 504 #define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK) 505 #define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT) 506 507 /* 508 * PDMA_P0_CTRL (RW) 509 * 510 * bit0: select cam0; 511 * bit1: select cam1; 512 * bit2: select jpeg; 513 * bit3: select pdma 514 */ 515 #define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK (0xF0000UL) 516 #define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT (16U) 517 #define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK) 518 #define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT) 519 520 /* 521 * LCDC1_P1_CTRL (RW) 522 * 523 * bit0: select cam0; 524 * bit1: select cam1; 525 * bit2: select jpeg; 526 * bit3: select pdma 527 */ 528 #define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK (0xF000U) 529 #define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT (12U) 530 #define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK) 531 #define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT) 532 533 /* 534 * LCDC1_P0_CTRL (RW) 535 * 536 * bit0: select cam0; 537 * bit1: select cam1; 538 * bit2: select jpeg; 539 * bit3: select pdma 540 */ 541 #define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK (0xF00U) 542 #define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT (8U) 543 #define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK) 544 #define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT) 545 546 /* 547 * LCDC0_P1_CTRL (RW) 548 * 549 * bit0: select cam0; 550 * bit1: select cam1; 551 * bit2: select jpeg; 552 * bit3: select pdma 553 */ 554 #define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK (0xF0U) 555 #define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT (4U) 556 #define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK) 557 #define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT) 558 559 /* 560 * LCDC0_P0_CTRL (RW) 561 * 562 * bit0: select cam0; 563 * bit1: select cam1; 564 * bit2: select jpeg; 565 * bit3: select pdma 566 */ 567 #define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK (0xFU) 568 #define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT (0U) 569 #define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK) 570 #define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT) 571 572 /* Bitfield definition for register: GPR_WR_D2 */ 573 /* 574 * TX_PHY0_PORT_PLL_RDY_SEL (RW) 575 * 576 * tx phy0 port_pll_rdy_sel 577 */ 578 #define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK (0x20000000UL) 579 #define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT (29U) 580 #define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK) 581 #define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT) 582 583 /* 584 * TX_PHY0_RATE_LVDS (RW) 585 * 586 * tx phy0 rate_lvds 587 */ 588 #define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK (0x18000000UL) 589 #define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT (27U) 590 #define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK) 591 #define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT) 592 593 /* 594 * TX_PHY0_PHY_MODE (RW) 595 * 596 * tx phy0 phy_mode 597 */ 598 #define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK (0x6000000UL) 599 #define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT (25U) 600 #define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK) 601 #define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT) 602 603 /* 604 * TX_PHY0_REFCLK_DIV (RW) 605 * 606 * tx phy0 refclk_div 607 */ 608 #define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK (0xF00000UL) 609 #define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT (20U) 610 #define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK) 611 #define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT) 612 613 /* 614 * TX_PHY0_IDDQ_EN (RW) 615 * 616 * tx phy0 iddq_en 617 */ 618 #define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK (0x80000UL) 619 #define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT (19U) 620 #define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK) 621 #define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT) 622 623 /* 624 * TX_PHY0_RESET_N (RW) 625 * 626 * tx phy0 reset, active low 627 */ 628 #define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK (0x40000UL) 629 #define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT (18U) 630 #define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK) 631 #define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT) 632 633 /* 634 * TX_PHY0_SHUTDOWNZ (RW) 635 * 636 * tx phy0 shutdownz, active low 637 */ 638 #define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK (0x20000UL) 639 #define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT (17U) 640 #define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK) 641 #define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT) 642 643 /* 644 * TX_PHY0_BYPS_CKDET (RW) 645 * 646 * tx phy0 byps_ckdet 647 */ 648 #define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK (0x10000UL) 649 #define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT (16U) 650 #define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK) 651 #define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT) 652 653 /* 654 * TX_PHY0_PLL_DIV (RW) 655 * 656 * tx phy0 pll_div 657 */ 658 #define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK (0x7FFFU) 659 #define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT (0U) 660 #define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK) 661 #define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT) 662 663 /* Bitfield definition for register: GPR_WR_D3 */ 664 /* 665 * TX_PHY0_PLL_CTRL (RW) 666 * 667 * tx phy0 pll_ctrl 668 */ 669 #define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK (0xFFFFFFFFUL) 670 #define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT (0U) 671 #define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT) & PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK) 672 #define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK) >> PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT) 673 674 /* Bitfield definition for register: GPR_WR_D4 */ 675 /* 676 * TX_PHY0_TXCK_BIST_EN (RW) 677 * 678 * tx phy0 txck_bist_en 679 */ 680 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK (0x80000000UL) 681 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT (31U) 682 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK) 683 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT) 684 685 /* 686 * TX_PHY0_TX3_BIST_EN (RW) 687 * 688 * tx phy0 tx3_bist_en 689 */ 690 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK (0x40000000UL) 691 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT (30U) 692 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK) 693 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT) 694 695 /* 696 * TX_PHY0_TX2_BIST_EN (RW) 697 * 698 * tx phy0 tx2_bist_en 699 */ 700 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK (0x20000000UL) 701 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT (29U) 702 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK) 703 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT) 704 705 /* 706 * TX_PHY0_TX1_BIST_EN (RW) 707 * 708 * tx phy0 tx1_bist_en 709 */ 710 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK (0x10000000UL) 711 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT (28U) 712 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK) 713 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT) 714 715 /* 716 * TX_PHY0_TX0_BIST_EN (RW) 717 * 718 * tx phy0 tx0_bist_en 719 */ 720 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK (0x8000000UL) 721 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT (27U) 722 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK) 723 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT) 724 725 /* 726 * TX_PHY0_TXCK_LPBK_EN (RW) 727 * 728 * tx_phy0 txck_lpbk_en 729 */ 730 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK (0x4000000UL) 731 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT (26U) 732 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK) 733 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT) 734 735 /* 736 * TX_PHY0_TX3_LPBK_EN (RW) 737 * 738 * tx_phy0 tx3_lpbk_en 739 */ 740 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK (0x2000000UL) 741 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT (25U) 742 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK) 743 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT) 744 745 /* 746 * TX_PHY0_TX2_LPBK_EN (RW) 747 * 748 * tx_phy0 tx2_lpbk_en 749 */ 750 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK (0x1000000UL) 751 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT (24U) 752 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK) 753 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT) 754 755 /* 756 * TX_PHY0_TX1_LPBK_EN (RW) 757 * 758 * tx_phy0 tx1_lpbk_en 759 */ 760 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK (0x800000UL) 761 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT (23U) 762 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK) 763 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT) 764 765 /* 766 * TX_PHY0_TX0_LPBK_EN (RW) 767 * 768 * tx_phy0 tx0_lpbk_en 769 */ 770 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK (0x400000UL) 771 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT (22U) 772 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK) 773 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT) 774 775 /* 776 * TX_PHY0_TXCK_PAT_SEL (RW) 777 * 778 * tx phy0 txck_pat_sel 779 */ 780 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK (0x300000UL) 781 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT (20U) 782 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK) 783 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT) 784 785 /* 786 * TX_PHY0_TX3_PAT_SEL (RW) 787 * 788 * tx phy0 tx3_pat_sel 789 */ 790 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK (0xC0000UL) 791 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT (18U) 792 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK) 793 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT) 794 795 /* 796 * TX_PHY0_TX2_PAT_SEL (RW) 797 * 798 * tx phy0 tx2_pat_sel 799 */ 800 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK (0x30000UL) 801 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT (16U) 802 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK) 803 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT) 804 805 /* 806 * TX_PHY0_TX1_PAT_SEL (RW) 807 * 808 * tx phy0 tx1_pat_sel 809 */ 810 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK (0xC000U) 811 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT (14U) 812 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK) 813 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT) 814 815 /* 816 * TX_PHY0_TX0_PAT_SEL (RW) 817 * 818 * tx phy0 tx0_pat_sel 819 */ 820 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK (0x3000U) 821 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT (12U) 822 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK) 823 #define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT) 824 825 /* 826 * TX_PHY0_DSI0_PRBS_DISABLE (RW) 827 * 828 * tx phy0 dsi0_prbs_disable 829 */ 830 #define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK (0x800U) 831 #define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT (11U) 832 #define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK) 833 #define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT) 834 835 /* 836 * TX_PHY0_DSI0_PRBS_START (RW) 837 * 838 * tx phy0 dsi0_prbs_start 839 */ 840 #define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK (0x400U) 841 #define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT (10U) 842 #define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK) 843 #define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT) 844 845 /* 846 * TX_PHY0_CKPHY_CTL (RW) 847 * 848 * tx phy0 ckphy_ctl 849 */ 850 #define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK (0x1FFU) 851 #define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT (0U) 852 #define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK) 853 #define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT) 854 855 /* Bitfield definition for register: GPR_WR_D5 */ 856 /* 857 * TX_PHY1_PORT_PLL_RDY_SEL (RW) 858 * 859 * tx phy1 port_pll_rdy_sel 860 */ 861 #define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK (0x20000000UL) 862 #define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT (29U) 863 #define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK) 864 #define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT) 865 866 /* 867 * TX_PHY1_RATE_LVDS (RW) 868 * 869 * tx phy1 rate_lvds 870 */ 871 #define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK (0x18000000UL) 872 #define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT (27U) 873 #define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK) 874 #define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT) 875 876 /* 877 * TX_PHY1_PHY_MODE (RW) 878 * 879 * tx phy1 phy_mode 880 */ 881 #define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK (0x6000000UL) 882 #define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT (25U) 883 #define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK) 884 #define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT) 885 886 /* 887 * TX_PHY1_REFCLK_DIV (RW) 888 * 889 * tx phy1 refclk_div 890 */ 891 #define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK (0xF00000UL) 892 #define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT (20U) 893 #define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK) 894 #define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT) 895 896 /* 897 * TX_PHY1_IDDQ_EN (RW) 898 * 899 * tx phy1 iddq_en 900 */ 901 #define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK (0x80000UL) 902 #define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT (19U) 903 #define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK) 904 #define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT) 905 906 /* 907 * TX_PHY1_RESET_N (RW) 908 * 909 * tx phy1 reset, active low 910 */ 911 #define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK (0x40000UL) 912 #define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT (18U) 913 #define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK) 914 #define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT) 915 916 /* 917 * TX_PHY1_SHUTDOWNZ (RW) 918 * 919 * tx phy1 shutdownz, active low 920 */ 921 #define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK (0x20000UL) 922 #define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT (17U) 923 #define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK) 924 #define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT) 925 926 /* 927 * TX_PHY1_BYPS_CKDET (RW) 928 * 929 * tx phy1 byps_ckdet 930 */ 931 #define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK (0x10000UL) 932 #define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT (16U) 933 #define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK) 934 #define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT) 935 936 /* 937 * TX_PHY1_PLL_DIV (RW) 938 * 939 * tx phy1 pll_div 940 */ 941 #define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK (0x7FFFU) 942 #define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT (0U) 943 #define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK) 944 #define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT) 945 946 /* Bitfield definition for register: GPR_WR_D6 */ 947 /* 948 * TX_PHY1_PLL_CTRL (RW) 949 * 950 * tx phy1 pll_ctrl 951 */ 952 #define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK (0xFFFFFFFFUL) 953 #define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT (0U) 954 #define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT) & PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK) 955 #define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK) >> PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT) 956 957 /* Bitfield definition for register: GPR_WR_D7 */ 958 /* 959 * TX_PHY1_TXCK_BIST_EN (RW) 960 * 961 * tx phy1 txck_bist_en 962 */ 963 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK (0x80000000UL) 964 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT (31U) 965 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK) 966 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT) 967 968 /* 969 * TX_PHY1_TX3_BIST_EN (RW) 970 * 971 * tx phy1 tx3_bist_en 972 */ 973 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK (0x40000000UL) 974 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT (30U) 975 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK) 976 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT) 977 978 /* 979 * TX_PHY1_TX2_BIST_EN (RW) 980 * 981 * tx phy1 tx2_bist_en 982 */ 983 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK (0x20000000UL) 984 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT (29U) 985 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK) 986 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT) 987 988 /* 989 * TX_PHY1_TX1_BIST_EN (RW) 990 * 991 * tx phy1 tx1_bist_en 992 */ 993 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK (0x10000000UL) 994 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT (28U) 995 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK) 996 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT) 997 998 /* 999 * TX_PHY1_TX0_BIST_EN (RW) 1000 * 1001 * tx phy1 tx0_bist_en 1002 */ 1003 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK (0x8000000UL) 1004 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT (27U) 1005 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK) 1006 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT) 1007 1008 /* 1009 * TX_PHY1_TXCK_LPBK_EN (RW) 1010 * 1011 * tx_phy1 txck_lpbk_en 1012 */ 1013 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK (0x4000000UL) 1014 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT (26U) 1015 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK) 1016 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT) 1017 1018 /* 1019 * TX_PHY1_TX3_LPBK_EN (RW) 1020 * 1021 * tx_phy1 tx3_lpbk_en 1022 */ 1023 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK (0x2000000UL) 1024 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT (25U) 1025 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK) 1026 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT) 1027 1028 /* 1029 * TX_PHY1_TX2_LPBK_EN (RW) 1030 * 1031 * tx_phy1 tx2_lpbk_en 1032 */ 1033 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK (0x1000000UL) 1034 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT (24U) 1035 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK) 1036 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT) 1037 1038 /* 1039 * TX_PHY1_TX1_LPBK_EN (RW) 1040 * 1041 * tx_phy1 tx1_lpbk_en 1042 */ 1043 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK (0x800000UL) 1044 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT (23U) 1045 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK) 1046 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT) 1047 1048 /* 1049 * TX_PHY1_TX0_LPBK_EN (RW) 1050 * 1051 * tx_phy1 tx0_lpbk_en 1052 */ 1053 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK (0x400000UL) 1054 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT (22U) 1055 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK) 1056 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT) 1057 1058 /* 1059 * TX_PHY1_TXCK_PAT_SEL (RW) 1060 * 1061 * tx phy1 txck_pat_sel 1062 */ 1063 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK (0x300000UL) 1064 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT (20U) 1065 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK) 1066 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT) 1067 1068 /* 1069 * TX_PHY1_TX3_PAT_SEL (RW) 1070 * 1071 * tx phy1 tx3_pat_sel 1072 */ 1073 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK (0xC0000UL) 1074 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT (18U) 1075 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK) 1076 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT) 1077 1078 /* 1079 * TX_PHY1_TX2_PAT_SEL (RW) 1080 * 1081 * tx phy1 tx2_pat_sel 1082 */ 1083 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK (0x30000UL) 1084 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT (16U) 1085 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK) 1086 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT) 1087 1088 /* 1089 * TX_PHY1_TX1_PAT_SEL (RW) 1090 * 1091 * tx phy1 tx1_pat_sel 1092 */ 1093 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK (0xC000U) 1094 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT (14U) 1095 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK) 1096 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT) 1097 1098 /* 1099 * TX_PHY1_TX0_PAT_SEL (RW) 1100 * 1101 * tx phy1 tx0_pat_sel 1102 */ 1103 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK (0x3000U) 1104 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT (12U) 1105 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK) 1106 #define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT) 1107 1108 /* 1109 * TX_PHY1_DSI0_PRBS_DISABLE (RW) 1110 * 1111 * tx phy1 dsi0_prbs_disable 1112 */ 1113 #define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK (0x800U) 1114 #define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT (11U) 1115 #define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK) 1116 #define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT) 1117 1118 /* 1119 * TX_PHY1_DSI0_PRBS_START (RW) 1120 * 1121 * tx phy1 dsi0_prbs_start 1122 */ 1123 #define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK (0x400U) 1124 #define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT (10U) 1125 #define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK) 1126 #define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT) 1127 1128 /* 1129 * TX_PHY1_CKPHY_CTL (RW) 1130 * 1131 * tx phy1 ckphy_ctl 1132 */ 1133 #define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK (0x1FFU) 1134 #define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT (0U) 1135 #define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK) 1136 #define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT) 1137 1138 /* Bitfield definition for register: GPR_WR_D8 */ 1139 /* 1140 * RX_PHY0_BRUN_IN_MODE (RW) 1141 * 1142 * rx phy0 burn_in_mode 1143 */ 1144 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK (0x80000000UL) 1145 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT (31U) 1146 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK) 1147 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT) 1148 1149 /* 1150 * RX_PHY0_BURN_IN_EN_PAD (RW) 1151 * 1152 * rx phy0 burn_in_en_pad 1153 */ 1154 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK (0x40000000UL) 1155 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT (30U) 1156 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK) 1157 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT) 1158 1159 /* 1160 * RX_PHY0_LPBK_MODE (RW) 1161 * 1162 * rx phy0 lpbk_mode 1163 */ 1164 #define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK (0x30000000UL) 1165 #define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT (28U) 1166 #define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK) 1167 #define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT) 1168 1169 /* 1170 * RX_PHY0_BIST_FREQ_TRIM (RW) 1171 * 1172 * rx phy0 bist_freq_trim 1173 */ 1174 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK (0xF000000UL) 1175 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT (24U) 1176 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK) 1177 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT) 1178 1179 /* 1180 * RX_PHY0_RX0_BIST_EN (RW) 1181 * 1182 * rx phy0 rx0_bist_en rx1_bist_en 1183 */ 1184 #define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK (0x400000UL) 1185 #define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT (22U) 1186 #define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK) 1187 #define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT) 1188 1189 /* 1190 * RX_PHY0_BIST_MODE (RW) 1191 * 1192 * rx phy0 bist_mode 1193 */ 1194 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK (0x200000UL) 1195 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT (21U) 1196 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK) 1197 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT) 1198 1199 /* 1200 * RX_PHY0_BIST_EN_PAD (RW) 1201 * 1202 * rx phy0 bist_en_pad 1203 */ 1204 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK (0x100000UL) 1205 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT (20U) 1206 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK) 1207 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT) 1208 1209 /* 1210 * RX_PHY0_BIST_EN (RW) 1211 * 1212 * rx phy0 bist_en 1213 */ 1214 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK (0x80000UL) 1215 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT (19U) 1216 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK) 1217 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT) 1218 1219 /* 1220 * RX_PHY0_BIST_CKIN_SEL (RW) 1221 * 1222 * rx phy0 bist_ckin_sel 1223 */ 1224 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK (0x40000UL) 1225 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT (18U) 1226 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK) 1227 #define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT) 1228 1229 /* 1230 * RX_PHY0_PHY_MODE (RW) 1231 * 1232 * rx phy0 phy_mode 1233 */ 1234 #define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK (0x3U) 1235 #define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT (0U) 1236 #define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK) 1237 #define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT) 1238 1239 /* Bitfield definition for register: GPR_WR_D9 */ 1240 /* 1241 * RX_PHY1_BRUN_IN_MODE (RW) 1242 * 1243 * rx phy1 burn_in_mode 1244 */ 1245 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK (0x80000000UL) 1246 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT (31U) 1247 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK) 1248 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT) 1249 1250 /* 1251 * RX_PHY1_BURN_IN_EN_PAD (RW) 1252 * 1253 * rx phy1 burn_in_en_pad 1254 */ 1255 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK (0x40000000UL) 1256 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT (30U) 1257 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK) 1258 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT) 1259 1260 /* 1261 * RX_PHY1_LPBK_MODE (RW) 1262 * 1263 * rx phy1 lpbk_mode 1264 */ 1265 #define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK (0x30000000UL) 1266 #define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT (28U) 1267 #define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK) 1268 #define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT) 1269 1270 /* 1271 * RX_PHY1_BIST_FREQ_TRIM (RW) 1272 * 1273 * rx phy1 bist_freq_trim 1274 */ 1275 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK (0xF000000UL) 1276 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT (24U) 1277 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK) 1278 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT) 1279 1280 /* 1281 * RX_PHY1_RX0_BIST_EN (RW) 1282 * 1283 * rx phy1 rx0_bist_en rx1_bist_en 1284 */ 1285 #define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK (0x400000UL) 1286 #define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT (22U) 1287 #define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK) 1288 #define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT) 1289 1290 /* 1291 * RX_PHY1_BIST_MODE (RW) 1292 * 1293 * rx phy1 bist_mode 1294 */ 1295 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK (0x200000UL) 1296 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT (21U) 1297 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK) 1298 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT) 1299 1300 /* 1301 * RX_PHY1_BIST_EN_PAD (RW) 1302 * 1303 * rx phy1 bist_en_pad 1304 */ 1305 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK (0x100000UL) 1306 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT (20U) 1307 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK) 1308 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT) 1309 1310 /* 1311 * RX_PHY1_BIST_EN (RW) 1312 * 1313 * rx phy1 bist_en 1314 */ 1315 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK (0x80000UL) 1316 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT (19U) 1317 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK) 1318 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT) 1319 1320 /* 1321 * RX_PHY1_BIST_CKIN_SEL (RW) 1322 * 1323 * rx phy1 bist_ckin_sel 1324 */ 1325 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK (0x40000UL) 1326 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT (18U) 1327 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK) 1328 #define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT) 1329 1330 /* 1331 * RX_PHY1_PHY_MODE (RW) 1332 * 1333 * rx phy1 phy_mode 1334 */ 1335 #define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK (0x3U) 1336 #define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT (0U) 1337 #define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK) 1338 #define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT) 1339 1340 /* Bitfield definition for register: GPR_RO_D0 */ 1341 /* 1342 * TX_PHY1_CTL_O (RO) 1343 * 1344 * {2'b0, 1345 * tx_phy1_tx3_ctl_o,tx_phy1_tx2_ctl_o, 1346 * tx_phy1_tx1_ctl_o,tx_phy1_tx0_ctl_o, 1347 * tx_phy1_txck_ctl_o,tx_phy1_pll_dtest_o} 1348 */ 1349 #define PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_MASK (0xFF00U) 1350 #define PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_SHIFT (8U) 1351 #define PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_MASK) >> PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_SHIFT) 1352 1353 /* 1354 * TX_PHY0_CTL_O (RO) 1355 * 1356 * {2'b0, 1357 * tx_phy0_tx3_ctl_o,tx_phy0_tx2_ctl_o, 1358 * tx_phy0_tx1_ctl_o,tx_phy0_tx0_ctl_o, 1359 * tx_phy0_txck_ctl_o,tx_phy0_pll_dtest_o} 1360 */ 1361 #define PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_MASK (0xFFU) 1362 #define PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_SHIFT (0U) 1363 #define PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_MASK) >> PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_SHIFT) 1364 1365 /* Bitfield definition for register: GPR_RO_D1 */ 1366 /* 1367 * IRQ_CSI0_AP (RO) 1368 * 1369 * interrupt of csi0 ap 1370 */ 1371 #define PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_MASK (0x20000UL) 1372 #define PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_SHIFT (17U) 1373 #define PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_MASK) >> PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_SHIFT) 1374 1375 /* 1376 * CSI0_CFG_CSI_AP_DIAG_FAULTS (RO) 1377 * 1378 * csi0 ap diag faults 1379 */ 1380 #define PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_MASK (0x1FFE0UL) 1381 #define PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_SHIFT (5U) 1382 #define PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_MASK) >> PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_SHIFT) 1383 1384 /* 1385 * CSI0_STA_AP_IF_INT_STA (RO) 1386 * 1387 * csi0 apb parity check interrupt satus 1388 */ 1389 #define PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_MASK (0x1FU) 1390 #define PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_SHIFT (0U) 1391 #define PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_MASK) >> PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_SHIFT) 1392 1393 /* Bitfield definition for register: GPR_RO_D2 */ 1394 /* 1395 * IRQ_CSI1_AP (RO) 1396 * 1397 * interrupt of csi1 ap 1398 */ 1399 #define PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_MASK (0x20000UL) 1400 #define PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_SHIFT (17U) 1401 #define PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_MASK) >> PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_SHIFT) 1402 1403 /* 1404 * CSI1_CFG_CSI_AP_DIAG_FAULTS (RO) 1405 * 1406 * csi1 ap diag faults 1407 */ 1408 #define PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_MASK (0x1FFE0UL) 1409 #define PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_SHIFT (5U) 1410 #define PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_MASK) >> PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_SHIFT) 1411 1412 /* 1413 * CSI1_STA_AP_IF_INT_STA (RO) 1414 * 1415 * csi1 apb parity check interrupt satus 1416 */ 1417 #define PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_MASK (0x1FU) 1418 #define PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_SHIFT (0U) 1419 #define PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_MASK) >> PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_SHIFT) 1420 1421 /* Bitfield definition for register: GPR_RO_D3 */ 1422 /* 1423 * RX_PHY0_RXCK_CTLO (RO) 1424 * 1425 * rx phy0 rxck_ctlo 1426 */ 1427 #define PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_MASK (0xFF00U) 1428 #define PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_SHIFT (8U) 1429 #define PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_SHIFT) 1430 1431 /* 1432 * RX_PHY0_RX1_CTLO (RO) 1433 * 1434 * rx phy0 rx1_ctlo 1435 */ 1436 #define PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_MASK (0xF0U) 1437 #define PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_SHIFT (4U) 1438 #define PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_SHIFT) 1439 1440 /* 1441 * RX_PHY0_RX0_CTLO (RO) 1442 * 1443 * rx phy0 rx0_ctlo 1444 */ 1445 #define PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_MASK (0xFU) 1446 #define PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_SHIFT (0U) 1447 #define PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_SHIFT) 1448 1449 /* Bitfield definition for register: GPR_RO_D4 */ 1450 /* 1451 * RX_PHY1_RXCK_CTLO (RO) 1452 * 1453 * rx phy1 rxck_ctlo 1454 */ 1455 #define PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_MASK (0xFF00U) 1456 #define PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_SHIFT (8U) 1457 #define PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_SHIFT) 1458 1459 /* 1460 * RX_PHY1_RX1_CTLO (RO) 1461 * 1462 * rx phy1 rx1_ctlo 1463 */ 1464 #define PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_MASK (0xF0U) 1465 #define PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_SHIFT (4U) 1466 #define PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_SHIFT) 1467 1468 /* 1469 * RX_PHY1_RX0_CTLO (RO) 1470 * 1471 * rx phy1 rx0_ctlo 1472 */ 1473 #define PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_MASK (0xFU) 1474 #define PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_SHIFT (0U) 1475 #define PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_SHIFT) 1476 1477 /* Bitfield definition for register: GPR_RO_D5 */ 1478 /* 1479 * DSI0_PRBS_STATE (RO) 1480 * 1481 * dsi0_prbs_state for debug only 1482 */ 1483 #define PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_MASK (0xF000U) 1484 #define PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_SHIFT (12U) 1485 #define PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_MASK) >> PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_SHIFT) 1486 1487 /* 1488 * TX_PHY0_TXCK_BIST_DONE_PAD (RO) 1489 * 1490 * tx phy0 txck_done_pad 1491 */ 1492 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_MASK (0x800U) 1493 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_SHIFT (11U) 1494 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_SHIFT) 1495 1496 /* 1497 * TX_PHY0_TXCK_BIST_OK_PAD (RO) 1498 * 1499 * tx phy0 txck_ok_pad 1500 */ 1501 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_MASK (0x400U) 1502 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_SHIFT (10U) 1503 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_SHIFT) 1504 1505 /* 1506 * TX_PHY0_TXCK_BIST_DONE (RO) 1507 * 1508 * tx phy0 txck_bist_done 1509 */ 1510 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_MASK (0x200U) 1511 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_SHIFT (9U) 1512 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_SHIFT) 1513 1514 /* 1515 * TX_PHY0_TX3_BIST_DONE (RO) 1516 * 1517 * tx phy0 tx3_bist_done 1518 */ 1519 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_MASK (0x100U) 1520 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_SHIFT (8U) 1521 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_SHIFT) 1522 1523 /* 1524 * TX_PHY0_TX2_BIST_DONE (RO) 1525 * 1526 * tx phy0 tx2_bist_done 1527 */ 1528 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_MASK (0x80U) 1529 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_SHIFT (7U) 1530 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_SHIFT) 1531 1532 /* 1533 * TX_PHY0_TX1_BIST_DONE (RO) 1534 * 1535 * tx phy0 tx1_bist_done 1536 */ 1537 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_MASK (0x40U) 1538 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_SHIFT (6U) 1539 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_SHIFT) 1540 1541 /* 1542 * TX_PHY0_TX0_BIST_DONE (RO) 1543 * 1544 * tx phy0 tx0_bist_done 1545 */ 1546 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_MASK (0x20U) 1547 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_SHIFT (5U) 1548 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_SHIFT) 1549 1550 /* 1551 * TX_PHY0_TXCK_BIST_OUT (RO) 1552 * 1553 * tx phy0 txck_bist_out 1554 */ 1555 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_MASK (0x10U) 1556 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_SHIFT (4U) 1557 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_SHIFT) 1558 1559 /* 1560 * TX_PHY0_TX3_BIST_OUT (RO) 1561 * 1562 * tx phy0 tx3_bist_out 1563 */ 1564 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_MASK (0x8U) 1565 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_SHIFT (3U) 1566 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_SHIFT) 1567 1568 /* 1569 * TX_PHY0_TX2_BIST_OUT (RO) 1570 * 1571 * tx phy0 tx2_bist_out 1572 */ 1573 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_MASK (0x4U) 1574 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_SHIFT (2U) 1575 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_SHIFT) 1576 1577 /* 1578 * TX_PHY0_TX1_BIST_OUT (RO) 1579 * 1580 * tx phy0 tx1_bist_out 1581 */ 1582 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_MASK (0x2U) 1583 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_SHIFT (1U) 1584 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_SHIFT) 1585 1586 /* 1587 * TX_PHY0_TX0_BIST_OUT (RO) 1588 * 1589 * tx phy0 tx0_bist_out 1590 */ 1591 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_MASK (0x1U) 1592 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_SHIFT (0U) 1593 #define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_SHIFT) 1594 1595 /* Bitfield definition for register: GPR_RO_D6 */ 1596 /* 1597 * DSI1_PRBS_STATE (RO) 1598 * 1599 * dsi1_prbs_state for debug only 1600 */ 1601 #define PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_MASK (0xF000U) 1602 #define PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_SHIFT (12U) 1603 #define PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_MASK) >> PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_SHIFT) 1604 1605 /* 1606 * TX_PHY1_TXCK_BIST_DONE_PAD (RO) 1607 * 1608 * tx phy1 txck_done_pad 1609 */ 1610 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_MASK (0x800U) 1611 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_SHIFT (11U) 1612 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_SHIFT) 1613 1614 /* 1615 * TX_PHY1_TXCK_BIST_OK_PAD (RO) 1616 * 1617 * tx phy1 txck_ok_pad 1618 */ 1619 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_MASK (0x400U) 1620 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_SHIFT (10U) 1621 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_SHIFT) 1622 1623 /* 1624 * TX_PHY1_TXCK_BIST_DONE (RO) 1625 * 1626 * tx phy1 txck_bist_done 1627 */ 1628 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_MASK (0x200U) 1629 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_SHIFT (9U) 1630 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_SHIFT) 1631 1632 /* 1633 * TX_PHY1_TX3_BIST_DONE (RO) 1634 * 1635 * tx phy1 tx3_bist_done 1636 */ 1637 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_MASK (0x100U) 1638 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_SHIFT (8U) 1639 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_SHIFT) 1640 1641 /* 1642 * TX_PHY1_TX2_BIST_DONE (RO) 1643 * 1644 * tx phy1 tx2_bist_done 1645 */ 1646 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_MASK (0x80U) 1647 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_SHIFT (7U) 1648 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_SHIFT) 1649 1650 /* 1651 * TX_PHY1_TX1_BIST_DONE (RO) 1652 * 1653 * tx phy1 tx1_bist_done 1654 */ 1655 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_MASK (0x40U) 1656 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_SHIFT (6U) 1657 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_SHIFT) 1658 1659 /* 1660 * TX_PHY1_TX0_BIST_DONE (RO) 1661 * 1662 * tx phy1 tx0_bist_done 1663 */ 1664 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_MASK (0x20U) 1665 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_SHIFT (5U) 1666 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_SHIFT) 1667 1668 /* 1669 * TX_PHY1_TXCK_BIST_OUT (RO) 1670 * 1671 * tx phy1 txck_bist_out 1672 */ 1673 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_MASK (0x10U) 1674 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_SHIFT (4U) 1675 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_SHIFT) 1676 1677 /* 1678 * TX_PHY1_TX3_BIST_OUT (RO) 1679 * 1680 * tx phy1 tx3_bist_out 1681 */ 1682 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_MASK (0x8U) 1683 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_SHIFT (3U) 1684 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_SHIFT) 1685 1686 /* 1687 * TX_PHY1_TX2_BIST_OUT (RO) 1688 * 1689 * tx phy1 tx2_bist_out 1690 */ 1691 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_MASK (0x4U) 1692 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_SHIFT (2U) 1693 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_SHIFT) 1694 1695 /* 1696 * TX_PHY1_TX1_BIST_OUT (RO) 1697 * 1698 * tx phy1 tx1_bist_out 1699 */ 1700 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_MASK (0x2U) 1701 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_SHIFT (1U) 1702 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_SHIFT) 1703 1704 /* 1705 * TX_PHY1_TX0_BIST_OUT (RO) 1706 * 1707 * tx phy1 tx0_bist_out 1708 */ 1709 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_MASK (0x1U) 1710 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_SHIFT (0U) 1711 #define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_SHIFT) 1712 1713 /* Bitfield definition for register: GPR_RO_D7 */ 1714 /* 1715 * RX_PHY0_BURN_IN_OK_PAD (RO) 1716 * 1717 * rx_phy0_burn_in_ok_pad 1718 */ 1719 #define PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_MASK (0x40U) 1720 #define PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_SHIFT (6U) 1721 #define PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_SHIFT) 1722 1723 /* 1724 * RX_PHY0_RX1_BIST_DONE (RO) 1725 * 1726 * rx phy0 rx1_bist_done 1727 */ 1728 #define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_MASK (0x20U) 1729 #define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_SHIFT (5U) 1730 #define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_SHIFT) 1731 1732 /* 1733 * RX_PHY0_RX0_BIST_DONE (RO) 1734 * 1735 * rx phy0 rx0_bist_done 1736 */ 1737 #define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_MASK (0x10U) 1738 #define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_SHIFT (4U) 1739 #define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_SHIFT) 1740 1741 /* 1742 * RX_PHY0_RX1_BIST_OUT (RO) 1743 * 1744 * rx phy0 rx1_bist_out 1745 */ 1746 #define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_MASK (0x8U) 1747 #define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_SHIFT (3U) 1748 #define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_SHIFT) 1749 1750 /* 1751 * RX_PHY0_RX0_BIST_OUT (RO) 1752 * 1753 * rx phy0 rx0_bist_out 1754 */ 1755 #define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_MASK (0x4U) 1756 #define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_SHIFT (2U) 1757 #define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_SHIFT) 1758 1759 /* 1760 * RX_PHY0_BIST_OK_PAD (RO) 1761 * 1762 * rx phy0 bist_ok_pad 1763 */ 1764 #define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_MASK (0x2U) 1765 #define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_SHIFT (1U) 1766 #define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_SHIFT) 1767 1768 /* 1769 * RX_PHY0_BIST_DONE_PAD (RO) 1770 * 1771 * rx phy0 bist_done_pad 1772 */ 1773 #define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_MASK (0x1U) 1774 #define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_SHIFT (0U) 1775 #define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_SHIFT) 1776 1777 /* Bitfield definition for register: GPR_RO_D8 */ 1778 /* 1779 * RX_PHY1_BURN_IN_OK_PAD (RO) 1780 * 1781 * rx_phy1_burn_in_ok_pad 1782 */ 1783 #define PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_MASK (0x40U) 1784 #define PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_SHIFT (6U) 1785 #define PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_SHIFT) 1786 1787 /* 1788 * RX_PHY1_RX1_BIST_DONE (RO) 1789 * 1790 * rx phy1 rx1_bist_done 1791 */ 1792 #define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_MASK (0x20U) 1793 #define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_SHIFT (5U) 1794 #define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_SHIFT) 1795 1796 /* 1797 * RX_PHY1_RX0_BIST_DONE (RO) 1798 * 1799 * rx phy1 rx0_bist_done 1800 */ 1801 #define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_MASK (0x10U) 1802 #define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_SHIFT (4U) 1803 #define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_SHIFT) 1804 1805 /* 1806 * RX_PHY1_RX1_BIST_OUT (RO) 1807 * 1808 * rx phy1 rx1_bist_out 1809 */ 1810 #define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_MASK (0x8U) 1811 #define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_SHIFT (3U) 1812 #define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_SHIFT) 1813 1814 /* 1815 * RX_PHY1_RX0_BIST_OUT (RO) 1816 * 1817 * rx phy1 rx0_bist_out 1818 */ 1819 #define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_MASK (0x4U) 1820 #define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_SHIFT (2U) 1821 #define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_SHIFT) 1822 1823 /* 1824 * RX_PHY1_BIST_OK_PAD (RO) 1825 * 1826 * rx phy1 bist_ok_pad 1827 */ 1828 #define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_MASK (0x2U) 1829 #define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_SHIFT (1U) 1830 #define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_SHIFT) 1831 1832 /* 1833 * RX_PHY1_BIST_DONE_PAD (RO) 1834 * 1835 * rx phy1 bist_done_pad 1836 */ 1837 #define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_MASK (0x1U) 1838 #define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_SHIFT (0U) 1839 #define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_SHIFT) 1840 1841 /* Bitfield definition for register: GPR_RO_D9 */ 1842 /* Bitfield definition for register: GPR_WR1_CLR_D0 */ 1843 /* 1844 * GPR_WR1_CLR_DATA (RW) 1845 * 1846 * gpr register, write 1 /no-write set/clr matching bit 1847 */ 1848 #define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK (0xFFFFFFFFUL) 1849 #define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT (0U) 1850 #define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT) & PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK) 1851 #define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK) >> PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT) 1852 1853 1854 1855 /* DSI_SETTING register group index macro definition */ 1856 #define PIXELMUX_DSI_SETTING_DSI0_CFG (0UL) 1857 #define PIXELMUX_DSI_SETTING_DSI1_CFG (1UL) 1858 1859 1860 #endif /* HPM_PIXELMUX_H */ 1861