1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32F4xx_HAL_RCC_EX_H 22 #define __STM32F4xx_HAL_RCC_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f4xx_hal_def.h" 30 31 /** @addtogroup STM32F4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCCEx 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief RCC PLL configuration structure definition 46 */ 47 typedef struct 48 { 49 uint32_t PLLState; /*!< The new state of the PLL. 50 This parameter can be a value of @ref RCC_PLL_Config */ 51 52 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 53 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 54 55 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 56 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ 57 58 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 59 This parameter must be a number between Min_Data = 50 and Max_Data = 432 60 except for STM32F411xE devices where the Min_Data = 192 */ 61 62 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). 63 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 64 65 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks. 66 This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ 67 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 68 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 69 defined(STM32F413xx) || defined(STM32F423xx) 70 uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. 71 This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx 72 and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. 73 This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ 74 #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 75 }RCC_PLLInitTypeDef; 76 77 #if defined(STM32F446xx) 78 /** 79 * @brief PLLI2S Clock structure definition 80 */ 81 typedef struct 82 { 83 uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. 84 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ 85 86 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 87 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ 88 89 uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock. 90 This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */ 91 92 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. 93 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 94 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 95 96 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 97 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 98 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 99 }RCC_PLLI2SInitTypeDef; 100 101 /** 102 * @brief PLLSAI Clock structure definition 103 */ 104 typedef struct 105 { 106 uint32_t PLLSAIM; /*!< Specifies division factor for PLL VCO input clock. 107 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ 108 109 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 110 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ 111 112 uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks. 113 This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ 114 115 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock. 116 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 117 This parameter will be used only when PLLSAI is selected as Clock Source SAI */ 118 }RCC_PLLSAIInitTypeDef; 119 120 /** 121 * @brief RCC extended clocks structure definition 122 */ 123 typedef struct 124 { 125 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 126 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 127 128 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 129 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 130 131 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. 132 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ 133 134 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 135 This parameter must be a number between Min_Data = 1 and Max_Data = 32 136 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 137 138 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 139 This parameter must be a number between Min_Data = 1 and Max_Data = 32 140 This parameter will be used only when PLLSAI is selected as Clock Source SAI */ 141 142 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection. 143 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 144 145 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection. 146 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 147 148 uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. 149 This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ 150 151 uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. 152 This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ 153 154 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. 155 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 156 157 uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. 158 This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ 159 160 uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection. 161 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 162 163 uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. 164 This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ 165 166 uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection. 167 This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */ 168 169 uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 170 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 171 172 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 173 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 174 }RCC_PeriphCLKInitTypeDef; 175 #endif /* STM32F446xx */ 176 177 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 178 /** 179 * @brief RCC extended clocks structure definition 180 */ 181 typedef struct 182 { 183 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 184 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 185 186 uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection. 187 This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */ 188 189 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. 190 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 191 192 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. 193 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 194 195 uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. 196 This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ 197 198 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 199 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 200 }RCC_PeriphCLKInitTypeDef; 201 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 202 203 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 204 /** 205 * @brief PLLI2S Clock structure definition 206 */ 207 typedef struct 208 { 209 uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. 210 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ 211 212 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 213 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ 214 215 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. 216 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 217 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 218 219 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 220 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 221 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 222 }RCC_PLLI2SInitTypeDef; 223 224 /** 225 * @brief RCC extended clocks structure definition 226 */ 227 typedef struct 228 { 229 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 230 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 231 232 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 233 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 234 235 #if defined(STM32F413xx) || defined(STM32F423xx) 236 uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock. 237 This parameter must be a number between Min_Data = 1 and Max_Data = 32 238 This parameter will be used only when PLL is selected as Clock Source SAI */ 239 240 uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock. 241 This parameter must be a number between Min_Data = 1 and Max_Data = 32 242 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 243 #endif /* STM32F413xx || STM32F423xx */ 244 245 uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. 246 This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ 247 248 uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. 249 This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ 250 251 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. 252 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 253 254 uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. 255 This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ 256 257 uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. 258 This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ 259 260 uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 261 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 262 263 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection. 264 This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ 265 266 uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection. 267 This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ 268 269 #if defined(STM32F413xx) || defined(STM32F423xx) 270 uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection. 271 This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */ 272 273 uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection. 274 This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */ 275 276 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. 277 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 278 279 uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection 280 This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */ 281 282 uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection 283 This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */ 284 #endif /* STM32F413xx || STM32F423xx */ 285 286 uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection. 287 This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */ 288 289 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 290 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 291 }RCC_PeriphCLKInitTypeDef; 292 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 293 294 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 295 296 /** 297 * @brief PLLI2S Clock structure definition 298 */ 299 typedef struct 300 { 301 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 302 This parameter must be a number between Min_Data = 50 and Max_Data = 432. 303 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 304 305 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 306 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 307 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 308 309 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. 310 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 311 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 312 }RCC_PLLI2SInitTypeDef; 313 314 /** 315 * @brief PLLSAI Clock structure definition 316 */ 317 typedef struct 318 { 319 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 320 This parameter must be a number between Min_Data = 50 and Max_Data = 432. 321 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 322 #if defined(STM32F469xx) || defined(STM32F479xx) 323 uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks. 324 This parameter is only available in STM32F469xx/STM32F479xx devices. 325 This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ 326 #endif /* STM32F469xx || STM32F479xx */ 327 328 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. 329 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 330 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 331 332 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock 333 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 334 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ 335 336 }RCC_PLLSAIInitTypeDef; 337 338 /** 339 * @brief RCC extended clocks structure definition 340 */ 341 typedef struct 342 { 343 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 344 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 345 346 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 347 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 348 349 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. 350 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ 351 352 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 353 This parameter must be a number between Min_Data = 1 and Max_Data = 32 354 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 355 356 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 357 This parameter must be a number between Min_Data = 1 and Max_Data = 32 358 This parameter will be used only when PLLSAI is selected as Clock Source SAI */ 359 360 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. 361 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ 362 363 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. 364 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 365 366 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. 367 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 368 #if defined(STM32F469xx) || defined(STM32F479xx) 369 uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 370 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 371 372 uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. 373 This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ 374 #endif /* STM32F469xx || STM32F479xx */ 375 }RCC_PeriphCLKInitTypeDef; 376 377 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 378 379 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ 380 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 381 /** 382 * @brief PLLI2S Clock structure definition 383 */ 384 typedef struct 385 { 386 #if defined(STM32F411xE) 387 uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock. 388 This parameter must be a number between Min_Data = 2 and Max_Data = 62 */ 389 #endif /* STM32F411xE */ 390 391 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 392 This parameter must be a number between Min_Data = 50 and Max_Data = 432 393 Except for STM32F411xE devices where the Min_Data = 192. 394 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 395 396 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 397 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 398 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 399 400 }RCC_PLLI2SInitTypeDef; 401 402 /** 403 * @brief RCC extended clocks structure definition 404 */ 405 typedef struct 406 { 407 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 408 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 409 410 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 411 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 412 413 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. 414 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 415 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 416 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 417 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 418 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ 419 }RCC_PeriphCLKInitTypeDef; 420 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ 421 /** 422 * @} 423 */ 424 425 /* Exported constants --------------------------------------------------------*/ 426 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 427 * @{ 428 */ 429 430 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection 431 * @{ 432 */ 433 /* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */ 434 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 435 defined(STM32F413xx) || defined(STM32F423xx) 436 #define RCC_PERIPHCLK_I2S_APB1 0x00000001U 437 #define RCC_PERIPHCLK_I2S_APB2 0x00000002U 438 #define RCC_PERIPHCLK_TIM 0x00000004U 439 #define RCC_PERIPHCLK_RTC 0x00000008U 440 #define RCC_PERIPHCLK_FMPI2C1 0x00000010U 441 #define RCC_PERIPHCLK_CLK48 0x00000020U 442 #define RCC_PERIPHCLK_SDIO 0x00000040U 443 #define RCC_PERIPHCLK_PLLI2S 0x00000080U 444 #define RCC_PERIPHCLK_DFSDM1 0x00000100U 445 #define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U 446 #endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */ 447 #if defined(STM32F413xx) || defined(STM32F423xx) 448 #define RCC_PERIPHCLK_DFSDM2 0x00000400U 449 #define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U 450 #define RCC_PERIPHCLK_LPTIM1 0x00001000U 451 #define RCC_PERIPHCLK_SAIA 0x00002000U 452 #define RCC_PERIPHCLK_SAIB 0x00004000U 453 #endif /* STM32F413xx || STM32F423xx */ 454 /*----------------------------------------------------------------------------*/ 455 456 /*------------------- Peripheral Clock source for STM32F410xx ----------------*/ 457 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 458 #define RCC_PERIPHCLK_I2S 0x00000001U 459 #define RCC_PERIPHCLK_TIM 0x00000002U 460 #define RCC_PERIPHCLK_RTC 0x00000004U 461 #define RCC_PERIPHCLK_FMPI2C1 0x00000008U 462 #define RCC_PERIPHCLK_LPTIM1 0x00000010U 463 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 464 /*----------------------------------------------------------------------------*/ 465 466 /*------------------- Peripheral Clock source for STM32F446xx ----------------*/ 467 #if defined(STM32F446xx) 468 #define RCC_PERIPHCLK_I2S_APB1 0x00000001U 469 #define RCC_PERIPHCLK_I2S_APB2 0x00000002U 470 #define RCC_PERIPHCLK_SAI1 0x00000004U 471 #define RCC_PERIPHCLK_SAI2 0x00000008U 472 #define RCC_PERIPHCLK_TIM 0x00000010U 473 #define RCC_PERIPHCLK_RTC 0x00000020U 474 #define RCC_PERIPHCLK_CEC 0x00000040U 475 #define RCC_PERIPHCLK_FMPI2C1 0x00000080U 476 #define RCC_PERIPHCLK_CLK48 0x00000100U 477 #define RCC_PERIPHCLK_SDIO 0x00000200U 478 #define RCC_PERIPHCLK_SPDIFRX 0x00000400U 479 #define RCC_PERIPHCLK_PLLI2S 0x00000800U 480 #endif /* STM32F446xx */ 481 /*-----------------------------------------------------------------------------*/ 482 483 /*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/ 484 #if defined(STM32F469xx) || defined(STM32F479xx) 485 #define RCC_PERIPHCLK_I2S 0x00000001U 486 #define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U 487 #define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U 488 #define RCC_PERIPHCLK_LTDC 0x00000008U 489 #define RCC_PERIPHCLK_TIM 0x00000010U 490 #define RCC_PERIPHCLK_RTC 0x00000020U 491 #define RCC_PERIPHCLK_PLLI2S 0x00000040U 492 #define RCC_PERIPHCLK_CLK48 0x00000080U 493 #define RCC_PERIPHCLK_SDIO 0x00000100U 494 #endif /* STM32F469xx || STM32F479xx */ 495 /*----------------------------------------------------------------------------*/ 496 497 /*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/ 498 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 499 #define RCC_PERIPHCLK_I2S 0x00000001U 500 #define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U 501 #define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U 502 #define RCC_PERIPHCLK_LTDC 0x00000008U 503 #define RCC_PERIPHCLK_TIM 0x00000010U 504 #define RCC_PERIPHCLK_RTC 0x00000020U 505 #define RCC_PERIPHCLK_PLLI2S 0x00000040U 506 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 507 /*----------------------------------------------------------------------------*/ 508 509 /*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/ 510 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ 511 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 512 #define RCC_PERIPHCLK_I2S 0x00000001U 513 #define RCC_PERIPHCLK_RTC 0x00000002U 514 #define RCC_PERIPHCLK_PLLI2S 0x00000004U 515 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ 516 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 517 #define RCC_PERIPHCLK_TIM 0x00000008U 518 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ 519 /*----------------------------------------------------------------------------*/ 520 /** 521 * @} 522 */ 523 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 524 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 525 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \ 526 defined(STM32F479xx) 527 /** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source 528 * @{ 529 */ 530 #define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U 531 #define RCC_I2SCLKSOURCE_EXT 0x00000001U 532 /** 533 * @} 534 */ 535 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 536 STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ 537 538 /** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR 539 * @{ 540 */ 541 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ 542 defined(STM32F469xx) || defined(STM32F479xx) 543 #define RCC_PLLSAIDIVR_2 0x00000000U 544 #define RCC_PLLSAIDIVR_4 0x00010000U 545 #define RCC_PLLSAIDIVR_8 0x00020000U 546 #define RCC_PLLSAIDIVR_16 0x00030000U 547 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 548 /** 549 * @} 550 */ 551 552 /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider 553 * @{ 554 */ 555 #if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 556 defined(STM32F412Rx) || defined(STM32F412Cx) 557 #define RCC_PLLI2SP_DIV2 0x00000002U 558 #define RCC_PLLI2SP_DIV4 0x00000004U 559 #define RCC_PLLI2SP_DIV6 0x00000006U 560 #define RCC_PLLI2SP_DIV8 0x00000008U 561 #endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 562 /** 563 * @} 564 */ 565 566 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider 567 * @{ 568 */ 569 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 570 #define RCC_PLLSAIP_DIV2 0x00000002U 571 #define RCC_PLLSAIP_DIV4 0x00000004U 572 #define RCC_PLLSAIP_DIV6 0x00000006U 573 #define RCC_PLLSAIP_DIV8 0x00000008U 574 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */ 575 /** 576 * @} 577 */ 578 579 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 580 /** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source 581 * @{ 582 */ 583 #define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U 584 #define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U 585 #define RCC_SAIACLKSOURCE_EXT 0x00200000U 586 /** 587 * @} 588 */ 589 590 /** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source 591 * @{ 592 */ 593 #define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U 594 #define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U 595 #define RCC_SAIBCLKSOURCE_EXT 0x00800000U 596 /** 597 * @} 598 */ 599 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 600 601 #if defined(STM32F469xx) || defined(STM32F479xx) 602 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source 603 * @{ 604 */ 605 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U 606 #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL) 607 /** 608 * @} 609 */ 610 611 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source 612 * @{ 613 */ 614 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U 615 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL) 616 /** 617 * @} 618 */ 619 620 /** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source 621 * @{ 622 */ 623 #define RCC_DSICLKSOURCE_DSIPHY 0x00000000U 624 #define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL) 625 /** 626 * @} 627 */ 628 #endif /* STM32F469xx || STM32F479xx */ 629 630 #if defined(STM32F446xx) 631 /** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source 632 * @{ 633 */ 634 #define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U 635 #define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0) 636 #define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1) 637 #define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC) 638 /** 639 * @} 640 */ 641 642 /** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source 643 * @{ 644 */ 645 #define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U 646 #define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0) 647 #define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1) 648 #define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC) 649 /** 650 * @} 651 */ 652 653 /** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source 654 * @{ 655 */ 656 #define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U 657 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) 658 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) 659 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) 660 /** 661 * @} 662 */ 663 664 /** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source 665 * @{ 666 */ 667 #define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U 668 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) 669 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) 670 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) 671 /** 672 * @} 673 */ 674 675 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source 676 * @{ 677 */ 678 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U 679 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 680 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 681 /** 682 * @} 683 */ 684 685 /** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source 686 * @{ 687 */ 688 #define RCC_CECCLKSOURCE_HSI 0x00000000U 689 #define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL) 690 /** 691 * @} 692 */ 693 694 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source 695 * @{ 696 */ 697 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U 698 #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL) 699 /** 700 * @} 701 */ 702 703 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source 704 * @{ 705 */ 706 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U 707 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) 708 /** 709 * @} 710 */ 711 712 /** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source 713 * @{ 714 */ 715 #define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U 716 #define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL) 717 /** 718 * @} 719 */ 720 721 #endif /* STM32F446xx */ 722 723 #if defined(STM32F413xx) || defined(STM32F423xx) 724 /** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source 725 * @{ 726 */ 727 #define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U 728 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0) 729 #define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1) 730 #define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1) 731 /** 732 * @} 733 */ 734 735 /** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source 736 * @{ 737 */ 738 #define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U 739 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0) 740 #define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1) 741 #define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1) 742 /** 743 * @} 744 */ 745 746 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source 747 * @{ 748 */ 749 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 750 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) 751 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) 752 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) 753 /** 754 * @} 755 */ 756 757 758 /** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source 759 * @{ 760 */ 761 #define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U 762 #define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL) 763 /** 764 * @} 765 */ 766 767 /** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source 768 * @{ 769 */ 770 #define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U 771 #define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) 772 /** 773 * @} 774 */ 775 776 #endif /* STM32F413xx || STM32F423xx */ 777 778 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 779 /** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source 780 * @{ 781 */ 782 #define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U 783 #define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC) 784 /** 785 * @} 786 */ 787 788 /** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source 789 * @{ 790 */ 791 #define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U 792 #define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL) 793 /** 794 * @} 795 */ 796 797 /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source 798 * @{ 799 */ 800 #define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U 801 #define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) 802 /** 803 * @} 804 */ 805 806 /** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source 807 * @{ 808 */ 809 #define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U 810 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) 811 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) 812 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) 813 /** 814 * @} 815 */ 816 817 /** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source 818 * @{ 819 */ 820 #define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U 821 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) 822 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) 823 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) 824 /** 825 * @} 826 */ 827 828 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source 829 * @{ 830 */ 831 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U 832 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 833 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 834 /** 835 * @} 836 */ 837 838 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source 839 * @{ 840 */ 841 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U 842 #define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL) 843 /** 844 * @} 845 */ 846 847 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source 848 * @{ 849 */ 850 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U 851 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) 852 /** 853 * @} 854 */ 855 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 856 857 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 858 859 /** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source 860 * @{ 861 */ 862 #define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U 863 #define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) 864 #define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) 865 /** 866 * @} 867 */ 868 869 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source 870 * @{ 871 */ 872 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U 873 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 874 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 875 /** 876 * @} 877 */ 878 879 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source 880 * @{ 881 */ 882 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 883 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) 884 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) 885 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) 886 /** 887 * @} 888 */ 889 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 890 891 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 892 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ 893 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 894 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ 895 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 896 /** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection 897 * @{ 898 */ 899 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) 900 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) 901 /** 902 * @} 903 */ 904 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ 905 STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ 906 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 907 908 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ 909 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ 910 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ 911 defined(STM32F423xx) 912 /** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection 913 * @{ 914 */ 915 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) 916 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) 917 /** 918 * @} 919 */ 920 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\ 921 STM32F412Rx || STM32F412Cx */ 922 923 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 924 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 925 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 926 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 927 defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 928 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 929 * @{ 930 */ 931 #define RCC_MCO2SOURCE_SYSCLK 0x00000000U 932 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 933 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 934 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 935 /** 936 * @} 937 */ 938 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 939 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 940 STM32F412Rx || STM32F413xx | STM32F423xx */ 941 942 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 943 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 944 * @{ 945 */ 946 #define RCC_MCO2SOURCE_SYSCLK 0x00000000U 947 #define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0 948 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 949 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 950 /** 951 * @} 952 */ 953 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 954 955 /** 956 * @} 957 */ 958 959 /* Exported macro ------------------------------------------------------------*/ 960 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 961 * @{ 962 */ 963 /*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/ 964 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 965 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 966 * @brief Enables or disables the AHB1 peripheral clock. 967 * @note After reset, the peripheral clock (used for registers read/write access) 968 * is disabled and the application software has to enable this clock before 969 * using it. 970 * @{ 971 */ 972 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 973 __IO uint32_t tmpreg = 0x00U; \ 974 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 975 /* Delay after an RCC peripheral clock enabling */ \ 976 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 977 UNUSED(tmpreg); \ 978 } while(0U) 979 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 980 __IO uint32_t tmpreg = 0x00U; \ 981 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 982 /* Delay after an RCC peripheral clock enabling */ \ 983 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 984 UNUSED(tmpreg); \ 985 } while(0U) 986 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 987 __IO uint32_t tmpreg = 0x00U; \ 988 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 989 /* Delay after an RCC peripheral clock enabling */ \ 990 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 991 UNUSED(tmpreg); \ 992 } while(0U) 993 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 994 __IO uint32_t tmpreg = 0x00U; \ 995 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 996 /* Delay after an RCC peripheral clock enabling */ \ 997 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 998 UNUSED(tmpreg); \ 999 } while(0U) 1000 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 1001 __IO uint32_t tmpreg = 0x00U; \ 1002 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 1003 /* Delay after an RCC peripheral clock enabling */ \ 1004 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 1005 UNUSED(tmpreg); \ 1006 } while(0U) 1007 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 1008 __IO uint32_t tmpreg = 0x00U; \ 1009 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 1010 /* Delay after an RCC peripheral clock enabling */ \ 1011 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 1012 UNUSED(tmpreg); \ 1013 } while(0U) 1014 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 1015 __IO uint32_t tmpreg = 0x00U; \ 1016 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 1017 /* Delay after an RCC peripheral clock enabling */ \ 1018 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 1019 UNUSED(tmpreg); \ 1020 } while(0U) 1021 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 1022 __IO uint32_t tmpreg = 0x00U; \ 1023 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 1024 /* Delay after an RCC peripheral clock enabling */ \ 1025 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 1026 UNUSED(tmpreg); \ 1027 } while(0U) 1028 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ 1029 __IO uint32_t tmpreg = 0x00U; \ 1030 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ 1031 /* Delay after an RCC peripheral clock enabling */ \ 1032 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ 1033 UNUSED(tmpreg); \ 1034 } while(0U) 1035 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ 1036 __IO uint32_t tmpreg = 0x00U; \ 1037 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ 1038 /* Delay after an RCC peripheral clock enabling */ \ 1039 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ 1040 UNUSED(tmpreg); \ 1041 } while(0U) 1042 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 1043 __IO uint32_t tmpreg = 0x00U; \ 1044 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ 1045 /* Delay after an RCC peripheral clock enabling */ \ 1046 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ 1047 UNUSED(tmpreg); \ 1048 } while(0U) 1049 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ 1050 __IO uint32_t tmpreg = 0x00U; \ 1051 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 1052 /* Delay after an RCC peripheral clock enabling */ \ 1053 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 1054 UNUSED(tmpreg); \ 1055 } while(0U) 1056 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ 1057 __IO uint32_t tmpreg = 0x00U; \ 1058 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 1059 /* Delay after an RCC peripheral clock enabling */ \ 1060 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 1061 UNUSED(tmpreg); \ 1062 } while(0U) 1063 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ 1064 __IO uint32_t tmpreg = 0x00U; \ 1065 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 1066 /* Delay after an RCC peripheral clock enabling */ \ 1067 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 1068 UNUSED(tmpreg); \ 1069 } while(0U) 1070 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ 1071 __IO uint32_t tmpreg = 0x00U; \ 1072 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 1073 /* Delay after an RCC peripheral clock enabling */ \ 1074 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 1075 UNUSED(tmpreg); \ 1076 } while(0U) 1077 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 1078 __IO uint32_t tmpreg = 0x00U; \ 1079 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 1080 /* Delay after an RCC peripheral clock enabling */ \ 1081 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 1082 UNUSED(tmpreg); \ 1083 } while(0U) 1084 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 1085 __IO uint32_t tmpreg = 0x00U; \ 1086 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 1087 /* Delay after an RCC peripheral clock enabling */ \ 1088 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 1089 UNUSED(tmpreg); \ 1090 } while(0U) 1091 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 1092 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 1093 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 1094 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 1095 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) 1096 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) 1097 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) 1098 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) 1099 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) 1100 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) 1101 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) 1102 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) 1103 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 1104 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 1105 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 1106 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 1107 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 1108 1109 /** 1110 * @brief Enable ETHERNET clock. 1111 */ 1112 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 1113 __HAL_RCC_ETHMAC_CLK_ENABLE(); \ 1114 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ 1115 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ 1116 } while(0U) 1117 /** 1118 * @brief Disable ETHERNET clock. 1119 */ 1120 #define __HAL_RCC_ETH_CLK_DISABLE() do { \ 1121 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ 1122 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ 1123 __HAL_RCC_ETHMAC_CLK_DISABLE(); \ 1124 } while(0U) 1125 /** 1126 * @} 1127 */ 1128 1129 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 1130 * @brief Get the enable or disable status of the AHB1 peripheral clock. 1131 * @note After reset, the peripheral clock (used for registers read/write access) 1132 * is disabled and the application software has to enable this clock before 1133 * using it. 1134 * @{ 1135 */ 1136 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 1137 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 1138 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 1139 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 1140 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) 1141 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) 1142 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) 1143 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) 1144 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) 1145 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) 1146 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) 1147 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) 1148 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 1149 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 1150 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 1151 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 1152 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 1153 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ 1154 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ 1155 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 1156 1157 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 1158 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 1159 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 1160 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 1161 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) 1162 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) 1163 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) 1164 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) 1165 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) 1166 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) 1167 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) 1168 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) 1169 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 1170 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 1171 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 1172 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 1173 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 1174 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ 1175 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ 1176 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) 1177 /** 1178 * @} 1179 */ 1180 1181 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 1182 * @brief Enable or disable the AHB2 peripheral clock. 1183 * @note After reset, the peripheral clock (used for registers read/write access) 1184 * is disabled and the application software has to enable this clock before 1185 * using it. 1186 * @{ 1187 */ 1188 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 1189 __IO uint32_t tmpreg = 0x00U; \ 1190 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 1191 /* Delay after an RCC peripheral clock enabling */ \ 1192 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 1193 UNUSED(tmpreg); \ 1194 } while(0U) 1195 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 1196 1197 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 1198 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ 1199 __IO uint32_t tmpreg = 0x00U; \ 1200 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 1201 /* Delay after an RCC peripheral clock enabling */ \ 1202 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 1203 UNUSED(tmpreg); \ 1204 } while(0U) 1205 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 1206 __IO uint32_t tmpreg = 0x00U; \ 1207 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 1208 /* Delay after an RCC peripheral clock enabling */ \ 1209 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 1210 UNUSED(tmpreg); \ 1211 } while(0U) 1212 1213 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) 1214 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) 1215 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 1216 1217 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 1218 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 1219 }while(0U) 1220 1221 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 1222 1223 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 1224 __IO uint32_t tmpreg = 0x00U; \ 1225 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 1226 /* Delay after an RCC peripheral clock enabling */ \ 1227 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 1228 UNUSED(tmpreg); \ 1229 } while(0U) 1230 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 1231 /** 1232 * @} 1233 */ 1234 1235 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 1236 * @brief Get the enable or disable status of the AHB1 peripheral clock. 1237 * @note After reset, the peripheral clock (used for registers read/write access) 1238 * is disabled and the application software has to enable this clock before 1239 * using it. 1240 * @{ 1241 */ 1242 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 1243 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 1244 1245 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 1246 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) 1247 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) 1248 1249 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) 1250 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) 1251 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 1252 1253 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 1254 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 1255 1256 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 1257 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 1258 /** 1259 * @} 1260 */ 1261 1262 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 1263 * @brief Enables or disables the AHB3 peripheral clock. 1264 * @note After reset, the peripheral clock (used for registers read/write access) 1265 * is disabled and the application software has to enable this clock before 1266 * using it. 1267 * @{ 1268 */ 1269 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 1270 __IO uint32_t tmpreg = 0x00U; \ 1271 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 1272 /* Delay after an RCC peripheral clock enabling */ \ 1273 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 1274 UNUSED(tmpreg); \ 1275 } while(0U) 1276 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) 1277 #if defined(STM32F469xx) || defined(STM32F479xx) 1278 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 1279 __IO uint32_t tmpreg = 0x00U; \ 1280 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 1281 /* Delay after an RCC peripheral clock enabling */ \ 1282 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 1283 UNUSED(tmpreg); \ 1284 } while(0U) 1285 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 1286 #endif /* STM32F469xx || STM32F479xx */ 1287 /** 1288 * @} 1289 */ 1290 1291 1292 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 1293 * @brief Get the enable or disable status of the AHB3 peripheral clock. 1294 * @note After reset, the peripheral clock (used for registers read/write access) 1295 * is disabled and the application software has to enable this clock before 1296 * using it. 1297 * @{ 1298 */ 1299 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) 1300 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) 1301 #if defined(STM32F469xx) || defined(STM32F479xx) 1302 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 1303 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 1304 #endif /* STM32F469xx || STM32F479xx */ 1305 /** 1306 * @} 1307 */ 1308 1309 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1310 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 1311 * @note After reset, the peripheral clock (used for registers read/write access) 1312 * is disabled and the application software has to enable this clock before 1313 * using it. 1314 * @{ 1315 */ 1316 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1317 __IO uint32_t tmpreg = 0x00U; \ 1318 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 1319 /* Delay after an RCC peripheral clock enabling */ \ 1320 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 1321 UNUSED(tmpreg); \ 1322 } while(0U) 1323 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1324 __IO uint32_t tmpreg = 0x00U; \ 1325 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 1326 /* Delay after an RCC peripheral clock enabling */ \ 1327 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 1328 UNUSED(tmpreg); \ 1329 } while(0U) 1330 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 1331 __IO uint32_t tmpreg = 0x00U; \ 1332 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 1333 /* Delay after an RCC peripheral clock enabling */ \ 1334 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 1335 UNUSED(tmpreg); \ 1336 } while(0U) 1337 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 1338 __IO uint32_t tmpreg = 0x00U; \ 1339 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 1340 /* Delay after an RCC peripheral clock enabling */ \ 1341 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 1342 UNUSED(tmpreg); \ 1343 } while(0U) 1344 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 1345 __IO uint32_t tmpreg = 0x00U; \ 1346 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 1347 /* Delay after an RCC peripheral clock enabling */ \ 1348 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 1349 UNUSED(tmpreg); \ 1350 } while(0U) 1351 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 1352 __IO uint32_t tmpreg = 0x00U; \ 1353 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 1354 /* Delay after an RCC peripheral clock enabling */ \ 1355 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 1356 UNUSED(tmpreg); \ 1357 } while(0U) 1358 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1359 __IO uint32_t tmpreg = 0x00U; \ 1360 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 1361 /* Delay after an RCC peripheral clock enabling */ \ 1362 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 1363 UNUSED(tmpreg); \ 1364 } while(0U) 1365 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1366 __IO uint32_t tmpreg = 0x00U; \ 1367 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 1368 /* Delay after an RCC peripheral clock enabling */ \ 1369 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 1370 UNUSED(tmpreg); \ 1371 } while(0U) 1372 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1373 __IO uint32_t tmpreg = 0x00U; \ 1374 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 1375 /* Delay after an RCC peripheral clock enabling */ \ 1376 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 1377 UNUSED(tmpreg); \ 1378 } while(0U) 1379 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 1380 __IO uint32_t tmpreg = 0x00U; \ 1381 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 1382 /* Delay after an RCC peripheral clock enabling */ \ 1383 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 1384 UNUSED(tmpreg); \ 1385 } while(0U) 1386 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 1387 __IO uint32_t tmpreg = 0x00U; \ 1388 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 1389 /* Delay after an RCC peripheral clock enabling */ \ 1390 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 1391 UNUSED(tmpreg); \ 1392 } while(0U) 1393 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 1394 __IO uint32_t tmpreg = 0x00U; \ 1395 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 1396 /* Delay after an RCC peripheral clock enabling */ \ 1397 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 1398 UNUSED(tmpreg); \ 1399 } while(0U) 1400 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 1401 __IO uint32_t tmpreg = 0x00U; \ 1402 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 1403 /* Delay after an RCC peripheral clock enabling */ \ 1404 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 1405 UNUSED(tmpreg); \ 1406 } while(0U) 1407 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 1408 __IO uint32_t tmpreg = 0x00U; \ 1409 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 1410 /* Delay after an RCC peripheral clock enabling */ \ 1411 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 1412 UNUSED(tmpreg); \ 1413 } while(0U) 1414 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 1415 __IO uint32_t tmpreg = 0x00U; \ 1416 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 1417 /* Delay after an RCC peripheral clock enabling */ \ 1418 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 1419 UNUSED(tmpreg); \ 1420 } while(0U) 1421 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 1422 __IO uint32_t tmpreg = 0x00U; \ 1423 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 1424 /* Delay after an RCC peripheral clock enabling */ \ 1425 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 1426 UNUSED(tmpreg); \ 1427 } while(0U) 1428 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 1429 __IO uint32_t tmpreg = 0x00U; \ 1430 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 1431 /* Delay after an RCC peripheral clock enabling */ \ 1432 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 1433 UNUSED(tmpreg); \ 1434 } while(0U) 1435 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1436 __IO uint32_t tmpreg = 0x00U; \ 1437 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 1438 /* Delay after an RCC peripheral clock enabling */ \ 1439 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 1440 UNUSED(tmpreg); \ 1441 } while(0U) 1442 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1443 __IO uint32_t tmpreg = 0x00U; \ 1444 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 1445 /* Delay after an RCC peripheral clock enabling */ \ 1446 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 1447 UNUSED(tmpreg); \ 1448 } while(0U) 1449 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 1450 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 1451 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 1452 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 1453 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 1454 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 1455 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 1456 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 1457 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 1458 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 1459 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 1460 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 1461 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 1462 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 1463 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 1464 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 1465 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) 1466 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) 1467 /** 1468 * @} 1469 */ 1470 1471 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 1472 * @brief Get the enable or disable status of the APB1 peripheral clock. 1473 * @note After reset, the peripheral clock (used for registers read/write access) 1474 * is disabled and the application software has to enable this clock before 1475 * using it. 1476 * @{ 1477 */ 1478 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 1479 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 1480 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 1481 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 1482 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 1483 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 1484 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 1485 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 1486 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 1487 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 1488 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 1489 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 1490 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 1491 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 1492 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 1493 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 1494 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) 1495 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 1496 1497 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 1498 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 1499 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 1500 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 1501 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 1502 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 1503 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 1504 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 1505 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 1506 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 1507 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 1508 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 1509 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 1510 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 1511 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 1512 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 1513 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) 1514 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) 1515 /** 1516 * @} 1517 */ 1518 1519 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1520 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 1521 * @note After reset, the peripheral clock (used for registers read/write access) 1522 * is disabled and the application software has to enable this clock before 1523 * using it. 1524 * @{ 1525 */ 1526 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1527 __IO uint32_t tmpreg = 0x00U; \ 1528 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 1529 /* Delay after an RCC peripheral clock enabling */ \ 1530 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 1531 UNUSED(tmpreg); \ 1532 } while(0U) 1533 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 1534 __IO uint32_t tmpreg = 0x00U; \ 1535 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 1536 /* Delay after an RCC peripheral clock enabling */ \ 1537 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 1538 UNUSED(tmpreg); \ 1539 } while(0U) 1540 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 1541 __IO uint32_t tmpreg = 0x00U; \ 1542 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 1543 /* Delay after an RCC peripheral clock enabling */ \ 1544 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 1545 UNUSED(tmpreg); \ 1546 } while(0U) 1547 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 1548 __IO uint32_t tmpreg = 0x00U; \ 1549 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 1550 /* Delay after an RCC peripheral clock enabling */ \ 1551 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 1552 UNUSED(tmpreg); \ 1553 } while(0U) 1554 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ 1555 __IO uint32_t tmpreg = 0x00U; \ 1556 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ 1557 /* Delay after an RCC peripheral clock enabling */ \ 1558 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ 1559 UNUSED(tmpreg); \ 1560 } while(0U) 1561 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1562 __IO uint32_t tmpreg = 0x00U; \ 1563 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 1564 /* Delay after an RCC peripheral clock enabling */ \ 1565 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 1566 UNUSED(tmpreg); \ 1567 } while(0U) 1568 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 1569 __IO uint32_t tmpreg = 0x00U; \ 1570 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 1571 /* Delay after an RCC peripheral clock enabling */ \ 1572 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 1573 UNUSED(tmpreg); \ 1574 } while(0U) 1575 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 1576 __IO uint32_t tmpreg = 0x00U; \ 1577 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 1578 /* Delay after an RCC peripheral clock enabling */ \ 1579 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 1580 UNUSED(tmpreg); \ 1581 } while(0U) 1582 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 1583 __IO uint32_t tmpreg = 0x00U; \ 1584 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 1585 /* Delay after an RCC peripheral clock enabling */ \ 1586 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 1587 UNUSED(tmpreg); \ 1588 } while(0U) 1589 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 1590 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 1591 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 1592 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 1593 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 1594 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 1595 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 1596 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) 1597 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 1598 1599 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 1600 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ 1601 __IO uint32_t tmpreg = 0x00U; \ 1602 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ 1603 /* Delay after an RCC peripheral clock enabling */ \ 1604 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ 1605 UNUSED(tmpreg); \ 1606 } while(0U) 1607 1608 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) 1609 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 1610 1611 #if defined(STM32F469xx) || defined(STM32F479xx) 1612 #define __HAL_RCC_DSI_CLK_ENABLE() do { \ 1613 __IO uint32_t tmpreg = 0x00U; \ 1614 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ 1615 /* Delay after an RCC peripheral clock enabling */ \ 1616 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ 1617 UNUSED(tmpreg); \ 1618 } while(0U) 1619 1620 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) 1621 #endif /* STM32F469xx || STM32F479xx */ 1622 /** 1623 * @} 1624 */ 1625 1626 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 1627 * @brief Get the enable or disable status of the APB2 peripheral clock. 1628 * @note After reset, the peripheral clock (used for registers read/write access) 1629 * is disabled and the application software has to enable this clock before 1630 * using it. 1631 * @{ 1632 */ 1633 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 1634 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 1635 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 1636 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 1637 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) 1638 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 1639 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 1640 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 1641 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET) 1642 1643 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 1644 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 1645 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET) 1646 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 1647 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 1648 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 1649 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 1650 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) 1651 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 1652 1653 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 1654 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) 1655 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) 1656 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 1657 1658 #if defined(STM32F469xx) || defined(STM32F479xx) 1659 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) 1660 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) 1661 #endif /* STM32F469xx || STM32F479xx */ 1662 /** 1663 * @} 1664 */ 1665 1666 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 1667 * @brief Force or release AHB1 peripheral reset. 1668 * @{ 1669 */ 1670 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 1671 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 1672 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 1673 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 1674 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) 1675 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) 1676 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 1677 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) 1678 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) 1679 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) 1680 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 1681 1682 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 1683 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 1684 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 1685 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 1686 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) 1687 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) 1688 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 1689 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) 1690 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) 1691 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) 1692 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 1693 /** 1694 * @} 1695 */ 1696 1697 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 1698 * @brief Force or release AHB2 peripheral reset. 1699 * @{ 1700 */ 1701 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 1702 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 1703 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 1704 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 1705 1706 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 1707 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 1708 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 1709 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 1710 1711 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 1712 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) 1713 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) 1714 1715 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) 1716 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) 1717 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 1718 /** 1719 * @} 1720 */ 1721 1722 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 1723 * @brief Force or release AHB3 peripheral reset. 1724 * @{ 1725 */ 1726 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 1727 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 1728 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) 1729 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) 1730 1731 #if defined(STM32F469xx) || defined(STM32F479xx) 1732 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 1733 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 1734 #endif /* STM32F469xx || STM32F479xx */ 1735 /** 1736 * @} 1737 */ 1738 1739 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 1740 * @brief Force or release APB1 peripheral reset. 1741 * @{ 1742 */ 1743 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 1744 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 1745 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 1746 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 1747 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 1748 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 1749 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 1750 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 1751 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 1752 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 1753 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 1754 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) 1755 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) 1756 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 1757 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 1758 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 1759 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 1760 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 1761 1762 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 1763 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 1764 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 1765 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 1766 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 1767 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 1768 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 1769 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 1770 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 1771 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 1772 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 1773 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 1774 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 1775 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 1776 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 1777 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 1778 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) 1779 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) 1780 /** 1781 * @} 1782 */ 1783 1784 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 1785 * @brief Force or release APB2 peripheral reset. 1786 * @{ 1787 */ 1788 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 1789 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 1790 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) 1791 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 1792 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 1793 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 1794 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 1795 1796 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 1797 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 1798 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 1799 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 1800 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 1801 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) 1802 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 1803 1804 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 1805 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) 1806 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) 1807 #endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ 1808 1809 #if defined(STM32F469xx) || defined(STM32F479xx) 1810 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) 1811 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) 1812 #endif /* STM32F469xx || STM32F479xx */ 1813 /** 1814 * @} 1815 */ 1816 1817 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 1818 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 1819 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1820 * power consumption. 1821 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1822 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1823 * @{ 1824 */ 1825 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 1826 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 1827 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 1828 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 1829 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) 1830 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 1831 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) 1832 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) 1833 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) 1834 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) 1835 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 1836 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 1837 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) 1838 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) 1839 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN)) 1840 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) 1841 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 1842 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 1843 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 1844 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 1845 1846 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 1847 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 1848 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 1849 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 1850 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) 1851 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 1852 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) 1853 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) 1854 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) 1855 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) 1856 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 1857 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 1858 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) 1859 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) 1860 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) 1861 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 1862 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 1863 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 1864 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 1865 /** 1866 * @} 1867 */ 1868 1869 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 1870 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 1871 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1872 * power consumption. 1873 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 1874 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1875 * @{ 1876 */ 1877 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 1878 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 1879 1880 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 1881 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 1882 1883 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 1884 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 1885 1886 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 1887 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 1888 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 1889 1890 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) 1891 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) 1892 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 1893 /** 1894 * @} 1895 */ 1896 1897 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 1898 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 1899 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1900 * power consumption. 1901 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1902 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1903 * @{ 1904 */ 1905 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 1906 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) 1907 1908 #if defined(STM32F469xx) || defined(STM32F479xx) 1909 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 1910 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 1911 #endif /* STM32F469xx || STM32F479xx */ 1912 /** 1913 * @} 1914 */ 1915 1916 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 1917 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 1918 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1919 * power consumption. 1920 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1921 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1922 * @{ 1923 */ 1924 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 1925 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 1926 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 1927 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 1928 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 1929 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 1930 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 1931 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 1932 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 1933 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 1934 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 1935 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) 1936 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) 1937 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 1938 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 1939 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 1940 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 1941 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 1942 1943 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 1944 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 1945 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 1946 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 1947 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 1948 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 1949 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 1950 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 1951 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 1952 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 1953 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 1954 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 1955 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 1956 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 1957 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 1958 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 1959 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) 1960 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) 1961 /** 1962 * @} 1963 */ 1964 1965 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 1966 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 1967 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1968 * power consumption. 1969 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1970 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1971 * @{ 1972 */ 1973 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 1974 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 1975 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 1976 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 1977 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) 1978 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 1979 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 1980 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 1981 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 1982 1983 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 1984 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 1985 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 1986 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 1987 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 1988 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 1989 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 1990 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) 1991 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 1992 1993 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 1994 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) 1995 1996 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) 1997 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 1998 1999 #if defined(STM32F469xx) || defined(STM32F479xx) 2000 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) 2001 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) 2002 #endif /* STM32F469xx || STM32F479xx */ 2003 /** 2004 * @} 2005 */ 2006 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ 2007 /*----------------------------------------------------------------------------*/ 2008 2009 /*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/ 2010 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) 2011 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 2012 * @brief Enables or disables the AHB1 peripheral clock. 2013 * @note After reset, the peripheral clock (used for registers read/write access) 2014 * is disabled and the application software has to enable this clock before 2015 * using it. 2016 * @{ 2017 */ 2018 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 2019 __IO uint32_t tmpreg = 0x00U; \ 2020 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 2021 /* Delay after an RCC peripheral clock enabling */ \ 2022 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 2023 UNUSED(tmpreg); \ 2024 } while(0U) 2025 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 2026 __IO uint32_t tmpreg = 0x00U; \ 2027 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 2028 /* Delay after an RCC peripheral clock enabling */ \ 2029 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 2030 UNUSED(tmpreg); \ 2031 } while(0U) 2032 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 2033 __IO uint32_t tmpreg = 0x00U; \ 2034 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 2035 /* Delay after an RCC peripheral clock enabling */ \ 2036 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 2037 UNUSED(tmpreg); \ 2038 } while(0U) 2039 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 2040 __IO uint32_t tmpreg = 0x00U; \ 2041 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 2042 /* Delay after an RCC peripheral clock enabling */ \ 2043 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 2044 UNUSED(tmpreg); \ 2045 } while(0U) 2046 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 2047 __IO uint32_t tmpreg = 0x00U; \ 2048 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 2049 /* Delay after an RCC peripheral clock enabling */ \ 2050 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 2051 UNUSED(tmpreg); \ 2052 } while(0U) 2053 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 2054 __IO uint32_t tmpreg = 0x00U; \ 2055 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 2056 /* Delay after an RCC peripheral clock enabling */ \ 2057 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 2058 UNUSED(tmpreg); \ 2059 } while(0U) 2060 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 2061 __IO uint32_t tmpreg = 0x00U; \ 2062 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 2063 /* Delay after an RCC peripheral clock enabling */ \ 2064 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 2065 UNUSED(tmpreg); \ 2066 } while(0U) 2067 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 2068 __IO uint32_t tmpreg = 0x00U; \ 2069 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 2070 /* Delay after an RCC peripheral clock enabling */ \ 2071 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 2072 UNUSED(tmpreg); \ 2073 } while(0U) 2074 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 2075 __IO uint32_t tmpreg = 0x00U; \ 2076 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 2077 /* Delay after an RCC peripheral clock enabling */ \ 2078 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 2079 UNUSED(tmpreg); \ 2080 } while(0U) 2081 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 2082 __IO uint32_t tmpreg = 0x00U; \ 2083 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 2084 /* Delay after an RCC peripheral clock enabling */ \ 2085 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 2086 UNUSED(tmpreg); \ 2087 } while(0U) 2088 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 2089 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 2090 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 2091 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 2092 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) 2093 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 2094 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 2095 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 2096 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 2097 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 2098 #if defined(STM32F407xx)|| defined(STM32F417xx) 2099 /** 2100 * @brief Enable ETHERNET clock. 2101 */ 2102 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ 2103 __IO uint32_t tmpreg = 0x00U; \ 2104 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 2105 /* Delay after an RCC peripheral clock enabling */ \ 2106 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 2107 UNUSED(tmpreg); \ 2108 } while(0U) 2109 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ 2110 __IO uint32_t tmpreg = 0x00U; \ 2111 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 2112 /* Delay after an RCC peripheral clock enabling */ \ 2113 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 2114 UNUSED(tmpreg); \ 2115 } while(0U) 2116 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ 2117 __IO uint32_t tmpreg = 0x00U; \ 2118 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 2119 /* Delay after an RCC peripheral clock enabling */ \ 2120 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 2121 UNUSED(tmpreg); \ 2122 } while(0U) 2123 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ 2124 __IO uint32_t tmpreg = 0x00U; \ 2125 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 2126 /* Delay after an RCC peripheral clock enabling */ \ 2127 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 2128 UNUSED(tmpreg); \ 2129 } while(0U) 2130 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 2131 __HAL_RCC_ETHMAC_CLK_ENABLE(); \ 2132 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ 2133 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ 2134 } while(0U) 2135 2136 /** 2137 * @brief Disable ETHERNET clock. 2138 */ 2139 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) 2140 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) 2141 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) 2142 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) 2143 #define __HAL_RCC_ETH_CLK_DISABLE() do { \ 2144 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ 2145 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ 2146 __HAL_RCC_ETHMAC_CLK_DISABLE(); \ 2147 } while(0U) 2148 #endif /* STM32F407xx || STM32F417xx */ 2149 /** 2150 * @} 2151 */ 2152 2153 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 2154 * @brief Get the enable or disable status of the AHB1 peripheral clock. 2155 * @note After reset, the peripheral clock (used for registers read/write access) 2156 * is disabled and the application software has to enable this clock before 2157 * using it. 2158 * @{ 2159 */ 2160 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 2161 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 2162 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 2163 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 2164 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 2165 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) 2166 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 2167 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 2168 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 2169 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 2170 2171 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 2172 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 2173 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 2174 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 2175 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) 2176 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 2177 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET) 2178 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 2179 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 2180 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 2181 #if defined(STM32F407xx)|| defined(STM32F417xx) 2182 /** 2183 * @brief Enable ETHERNET clock. 2184 */ 2185 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) 2186 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) 2187 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) 2188 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) 2189 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ 2190 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ 2191 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 2192 /** 2193 * @brief Disable ETHERNET clock. 2194 */ 2195 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) 2196 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) 2197 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) 2198 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) 2199 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ 2200 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ 2201 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) 2202 #endif /* STM32F407xx || STM32F417xx */ 2203 /** 2204 * @} 2205 */ 2206 2207 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 2208 * @brief Enable or disable the AHB2 peripheral clock. 2209 * @note After reset, the peripheral clock (used for registers read/write access) 2210 * is disabled and the application software has to enable this clock before 2211 * using it. 2212 * @{ 2213 */ 2214 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 2215 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 2216 }while(0U) 2217 2218 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 2219 2220 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 2221 __IO uint32_t tmpreg = 0x00U; \ 2222 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 2223 /* Delay after an RCC peripheral clock enabling */ \ 2224 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 2225 UNUSED(tmpreg); \ 2226 } while(0U) 2227 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 2228 2229 #if defined(STM32F407xx)|| defined(STM32F417xx) 2230 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 2231 __IO uint32_t tmpreg = 0x00U; \ 2232 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 2233 /* Delay after an RCC peripheral clock enabling */ \ 2234 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 2235 UNUSED(tmpreg); \ 2236 } while(0U) 2237 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 2238 #endif /* STM32F407xx || STM32F417xx */ 2239 2240 #if defined(STM32F415xx) || defined(STM32F417xx) 2241 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ 2242 __IO uint32_t tmpreg = 0x00U; \ 2243 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 2244 /* Delay after an RCC peripheral clock enabling */ \ 2245 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 2246 UNUSED(tmpreg); \ 2247 } while(0U) 2248 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 2249 __IO uint32_t tmpreg = 0x00U; \ 2250 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 2251 /* Delay after an RCC peripheral clock enabling */ \ 2252 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 2253 UNUSED(tmpreg); \ 2254 } while(0U) 2255 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) 2256 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) 2257 #endif /* STM32F415xx || STM32F417xx */ 2258 /** 2259 * @} 2260 */ 2261 2262 2263 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 2264 * @brief Get the enable or disable status of the AHB2 peripheral clock. 2265 * @note After reset, the peripheral clock (used for registers read/write access) 2266 * is disabled and the application software has to enable this clock before 2267 * using it. 2268 * @{ 2269 */ 2270 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 2271 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 2272 2273 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 2274 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 2275 2276 #if defined(STM32F407xx)|| defined(STM32F417xx) 2277 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 2278 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 2279 #endif /* STM32F407xx || STM32F417xx */ 2280 2281 #if defined(STM32F415xx) || defined(STM32F417xx) 2282 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) 2283 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) 2284 2285 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) 2286 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) 2287 #endif /* STM32F415xx || STM32F417xx */ 2288 /** 2289 * @} 2290 */ 2291 2292 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 2293 * @brief Enables or disables the AHB3 peripheral clock. 2294 * @note After reset, the peripheral clock (used for registers read/write access) 2295 * is disabled and the application software has to enable this clock before 2296 * using it. 2297 * @{ 2298 */ 2299 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ 2300 __IO uint32_t tmpreg = 0x00U; \ 2301 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 2302 /* Delay after an RCC peripheral clock enabling */ \ 2303 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 2304 UNUSED(tmpreg); \ 2305 } while(0U) 2306 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) 2307 /** 2308 * @} 2309 */ 2310 2311 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 2312 * @brief Get the enable or disable status of the AHB3 peripheral clock. 2313 * @note After reset, the peripheral clock (used for registers read/write access) 2314 * is disabled and the application software has to enable this clock before 2315 * using it. 2316 * @{ 2317 */ 2318 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 2319 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) 2320 /** 2321 * @} 2322 */ 2323 2324 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 2325 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 2326 * @note After reset, the peripheral clock (used for registers read/write access) 2327 * is disabled and the application software has to enable this clock before 2328 * using it. 2329 * @{ 2330 */ 2331 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 2332 __IO uint32_t tmpreg = 0x00U; \ 2333 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 2334 /* Delay after an RCC peripheral clock enabling */ \ 2335 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 2336 UNUSED(tmpreg); \ 2337 } while(0U) 2338 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 2339 __IO uint32_t tmpreg = 0x00U; \ 2340 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 2341 /* Delay after an RCC peripheral clock enabling */ \ 2342 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 2343 UNUSED(tmpreg); \ 2344 } while(0U) 2345 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 2346 __IO uint32_t tmpreg = 0x00U; \ 2347 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 2348 /* Delay after an RCC peripheral clock enabling */ \ 2349 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 2350 UNUSED(tmpreg); \ 2351 } while(0U) 2352 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 2353 __IO uint32_t tmpreg = 0x00U; \ 2354 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 2355 /* Delay after an RCC peripheral clock enabling */ \ 2356 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 2357 UNUSED(tmpreg); \ 2358 } while(0U) 2359 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 2360 __IO uint32_t tmpreg = 0x00U; \ 2361 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 2362 /* Delay after an RCC peripheral clock enabling */ \ 2363 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 2364 UNUSED(tmpreg); \ 2365 } while(0U) 2366 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 2367 __IO uint32_t tmpreg = 0x00U; \ 2368 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 2369 /* Delay after an RCC peripheral clock enabling */ \ 2370 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 2371 UNUSED(tmpreg); \ 2372 } while(0U) 2373 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 2374 __IO uint32_t tmpreg = 0x00U; \ 2375 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 2376 /* Delay after an RCC peripheral clock enabling */ \ 2377 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 2378 UNUSED(tmpreg); \ 2379 } while(0U) 2380 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 2381 __IO uint32_t tmpreg = 0x00U; \ 2382 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 2383 /* Delay after an RCC peripheral clock enabling */ \ 2384 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 2385 UNUSED(tmpreg); \ 2386 } while(0U) 2387 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 2388 __IO uint32_t tmpreg = 0x00U; \ 2389 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 2390 /* Delay after an RCC peripheral clock enabling */ \ 2391 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 2392 UNUSED(tmpreg); \ 2393 } while(0U) 2394 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 2395 __IO uint32_t tmpreg = 0x00U; \ 2396 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 2397 /* Delay after an RCC peripheral clock enabling */ \ 2398 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 2399 UNUSED(tmpreg); \ 2400 } while(0U) 2401 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 2402 __IO uint32_t tmpreg = 0x00U; \ 2403 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 2404 /* Delay after an RCC peripheral clock enabling */ \ 2405 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 2406 UNUSED(tmpreg); \ 2407 } while(0U) 2408 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 2409 __IO uint32_t tmpreg = 0x00U; \ 2410 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 2411 /* Delay after an RCC peripheral clock enabling */ \ 2412 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 2413 UNUSED(tmpreg); \ 2414 } while(0U) 2415 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 2416 __IO uint32_t tmpreg = 0x00U; \ 2417 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 2418 /* Delay after an RCC peripheral clock enabling */ \ 2419 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 2420 UNUSED(tmpreg); \ 2421 } while(0U) 2422 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 2423 __IO uint32_t tmpreg = 0x00U; \ 2424 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 2425 /* Delay after an RCC peripheral clock enabling */ \ 2426 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 2427 UNUSED(tmpreg); \ 2428 } while(0U) 2429 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 2430 __IO uint32_t tmpreg = 0x00U; \ 2431 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 2432 /* Delay after an RCC peripheral clock enabling */ \ 2433 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 2434 UNUSED(tmpreg); \ 2435 } while(0U) 2436 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 2437 __IO uint32_t tmpreg = 0x00U; \ 2438 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 2439 /* Delay after an RCC peripheral clock enabling */ \ 2440 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 2441 UNUSED(tmpreg); \ 2442 } while(0U) 2443 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 2444 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 2445 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 2446 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 2447 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 2448 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 2449 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 2450 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 2451 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 2452 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 2453 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 2454 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 2455 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 2456 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 2457 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 2458 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 2459 /** 2460 * @} 2461 */ 2462 2463 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 2464 * @brief Get the enable or disable status of the APB1 peripheral clock. 2465 * @note After reset, the peripheral clock (used for registers read/write access) 2466 * is disabled and the application software has to enable this clock before 2467 * using it. 2468 * @{ 2469 */ 2470 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 2471 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 2472 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 2473 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 2474 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 2475 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 2476 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 2477 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 2478 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 2479 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 2480 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 2481 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 2482 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 2483 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 2484 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 2485 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 2486 2487 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 2488 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 2489 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 2490 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 2491 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 2492 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 2493 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 2494 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 2495 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 2496 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 2497 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 2498 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 2499 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 2500 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 2501 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 2502 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 2503 /** 2504 * @} 2505 */ 2506 2507 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 2508 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 2509 * @note After reset, the peripheral clock (used for registers read/write access) 2510 * is disabled and the application software has to enable this clock before 2511 * using it. 2512 * @{ 2513 */ 2514 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 2515 __IO uint32_t tmpreg = 0x00U; \ 2516 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 2517 /* Delay after an RCC peripheral clock enabling */ \ 2518 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 2519 UNUSED(tmpreg); \ 2520 } while(0U) 2521 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 2522 __IO uint32_t tmpreg = 0x00U; \ 2523 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 2524 /* Delay after an RCC peripheral clock enabling */ \ 2525 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 2526 UNUSED(tmpreg); \ 2527 } while(0U) 2528 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 2529 __IO uint32_t tmpreg = 0x00U; \ 2530 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 2531 /* Delay after an RCC peripheral clock enabling */ \ 2532 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 2533 UNUSED(tmpreg); \ 2534 } while(0U) 2535 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 2536 __IO uint32_t tmpreg = 0x00U; \ 2537 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 2538 /* Delay after an RCC peripheral clock enabling */ \ 2539 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 2540 UNUSED(tmpreg); \ 2541 } while(0U) 2542 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 2543 __IO uint32_t tmpreg = 0x00U; \ 2544 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 2545 /* Delay after an RCC peripheral clock enabling */ \ 2546 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 2547 UNUSED(tmpreg); \ 2548 } while(0U) 2549 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 2550 __IO uint32_t tmpreg = 0x00U; \ 2551 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 2552 /* Delay after an RCC peripheral clock enabling */ \ 2553 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 2554 UNUSED(tmpreg); \ 2555 } while(0U) 2556 2557 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 2558 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 2559 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 2560 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 2561 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 2562 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 2563 /** 2564 * @} 2565 */ 2566 2567 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 2568 * @brief Get the enable or disable status of the APB2 peripheral clock. 2569 * @note After reset, the peripheral clock (used for registers read/write access) 2570 * is disabled and the application software has to enable this clock before 2571 * using it. 2572 * @{ 2573 */ 2574 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 2575 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 2576 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 2577 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 2578 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 2579 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 2580 2581 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 2582 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 2583 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 2584 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 2585 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 2586 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 2587 /** 2588 * @} 2589 */ 2590 2591 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 2592 * @brief Force or release AHB1 peripheral reset. 2593 * @{ 2594 */ 2595 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 2596 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 2597 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 2598 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 2599 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) 2600 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) 2601 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 2602 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 2603 2604 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 2605 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 2606 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 2607 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 2608 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) 2609 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) 2610 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 2611 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 2612 /** 2613 * @} 2614 */ 2615 2616 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 2617 * @brief Force or release AHB2 peripheral reset. 2618 * @{ 2619 */ 2620 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 2621 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 2622 2623 #if defined(STM32F407xx)|| defined(STM32F417xx) 2624 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 2625 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 2626 #endif /* STM32F407xx || STM32F417xx */ 2627 2628 #if defined(STM32F415xx) || defined(STM32F417xx) 2629 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) 2630 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) 2631 2632 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) 2633 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) 2634 #endif /* STM32F415xx || STM32F417xx */ 2635 2636 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 2637 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 2638 2639 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 2640 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 2641 /** 2642 * @} 2643 */ 2644 2645 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 2646 * @brief Force or release AHB3 peripheral reset. 2647 * @{ 2648 */ 2649 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 2650 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 2651 2652 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) 2653 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) 2654 /** 2655 * @} 2656 */ 2657 2658 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 2659 * @brief Force or release APB1 peripheral reset. 2660 * @{ 2661 */ 2662 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 2663 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 2664 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 2665 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 2666 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 2667 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 2668 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 2669 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 2670 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 2671 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 2672 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 2673 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 2674 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 2675 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 2676 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 2677 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 2678 2679 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 2680 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 2681 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 2682 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 2683 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 2684 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 2685 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 2686 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 2687 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 2688 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 2689 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 2690 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 2691 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 2692 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 2693 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 2694 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 2695 /** 2696 * @} 2697 */ 2698 2699 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 2700 * @brief Force or release APB2 peripheral reset. 2701 * @{ 2702 */ 2703 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 2704 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 2705 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 2706 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 2707 2708 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 2709 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 2710 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 2711 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 2712 /** 2713 * @} 2714 */ 2715 2716 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 2717 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 2718 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2719 * power consumption. 2720 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2721 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2722 * @{ 2723 */ 2724 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 2725 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 2726 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 2727 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 2728 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) 2729 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 2730 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) 2731 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) 2732 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) 2733 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) 2734 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 2735 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 2736 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 2737 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 2738 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 2739 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 2740 2741 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 2742 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 2743 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 2744 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 2745 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) 2746 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 2747 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) 2748 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) 2749 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) 2750 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) 2751 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 2752 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 2753 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 2754 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 2755 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 2756 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 2757 /** 2758 * @} 2759 */ 2760 2761 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 2762 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 2763 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2764 * power consumption. 2765 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 2766 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2767 * @{ 2768 */ 2769 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 2770 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 2771 2772 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 2773 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 2774 2775 #if defined(STM32F407xx)|| defined(STM32F417xx) 2776 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 2777 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 2778 #endif /* STM32F407xx || STM32F417xx */ 2779 2780 #if defined(STM32F415xx) || defined(STM32F417xx) 2781 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 2782 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 2783 2784 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) 2785 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) 2786 #endif /* STM32F415xx || STM32F417xx */ 2787 /** 2788 * @} 2789 */ 2790 2791 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 2792 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 2793 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2794 * power consumption. 2795 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2796 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2797 * @{ 2798 */ 2799 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) 2800 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) 2801 /** 2802 * @} 2803 */ 2804 2805 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 2806 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 2807 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2808 * power consumption. 2809 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2810 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2811 * @{ 2812 */ 2813 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 2814 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 2815 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 2816 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 2817 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 2818 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 2819 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 2820 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 2821 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 2822 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 2823 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 2824 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 2825 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 2826 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 2827 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 2828 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 2829 2830 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 2831 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 2832 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 2833 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 2834 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 2835 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 2836 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 2837 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 2838 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 2839 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 2840 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 2841 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 2842 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 2843 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 2844 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 2845 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 2846 /** 2847 * @} 2848 */ 2849 2850 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 2851 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 2852 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2853 * power consumption. 2854 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2855 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2856 * @{ 2857 */ 2858 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 2859 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 2860 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 2861 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 2862 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 2863 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 2864 2865 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 2866 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 2867 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 2868 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 2869 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 2870 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 2871 /** 2872 * @} 2873 */ 2874 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ 2875 /*----------------------------------------------------------------------------*/ 2876 2877 /*------------------------- STM32F401xE/STM32F401xC --------------------------*/ 2878 #if defined(STM32F401xC) || defined(STM32F401xE) 2879 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 2880 * @brief Enable or disable the AHB1 peripheral clock. 2881 * @note After reset, the peripheral clock (used for registers read/write access) 2882 * is disabled and the application software has to enable this clock before 2883 * using it. 2884 * @{ 2885 */ 2886 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 2887 __IO uint32_t tmpreg = 0x00U; \ 2888 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 2889 /* Delay after an RCC peripheral clock enabling */ \ 2890 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 2891 UNUSED(tmpreg); \ 2892 } while(0U) 2893 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 2894 __IO uint32_t tmpreg = 0x00U; \ 2895 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 2896 /* Delay after an RCC peripheral clock enabling */ \ 2897 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 2898 UNUSED(tmpreg); \ 2899 } while(0U) 2900 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 2901 __IO uint32_t tmpreg = 0x00U; \ 2902 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 2903 /* Delay after an RCC peripheral clock enabling */ \ 2904 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 2905 UNUSED(tmpreg); \ 2906 } while(0U) 2907 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 2908 __IO uint32_t tmpreg = 0x00U; \ 2909 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 2910 /* Delay after an RCC peripheral clock enabling */ \ 2911 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 2912 UNUSED(tmpreg); \ 2913 } while(0U) 2914 2915 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 2916 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 2917 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 2918 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 2919 /** 2920 * @} 2921 */ 2922 2923 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 2924 * @brief Get the enable or disable status of the AHB1 peripheral clock. 2925 * @note After reset, the peripheral clock (used for registers read/write access) 2926 * is disabled and the application software has to enable this clock before 2927 * using it. 2928 * @{ 2929 */ 2930 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 2931 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 2932 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 2933 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 2934 2935 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 2936 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 2937 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 2938 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 2939 /** 2940 * @} 2941 */ 2942 2943 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 2944 * @brief Enable or disable the AHB2 peripheral clock. 2945 * @note After reset, the peripheral clock (used for registers read/write access) 2946 * is disabled and the application software has to enable this clock before 2947 * using it. 2948 * @{ 2949 */ 2950 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 2951 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 2952 }while(0U) 2953 2954 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 2955 /** 2956 * @} 2957 */ 2958 2959 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 2960 * @brief Get the enable or disable status of the AHB2 peripheral clock. 2961 * @note After reset, the peripheral clock (used for registers read/write access) 2962 * is disabled and the application software has to enable this clock before 2963 * using it. 2964 * @{ 2965 */ 2966 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 2967 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 2968 /** 2969 * @} 2970 */ 2971 2972 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 2973 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 2974 * @note After reset, the peripheral clock (used for registers read/write access) 2975 * is disabled and the application software has to enable this clock before 2976 * using it. 2977 * @{ 2978 */ 2979 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 2980 __IO uint32_t tmpreg = 0x00U; \ 2981 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 2982 /* Delay after an RCC peripheral clock enabling */ \ 2983 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 2984 UNUSED(tmpreg); \ 2985 } while(0U) 2986 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 2987 __IO uint32_t tmpreg = 0x00U; \ 2988 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 2989 /* Delay after an RCC peripheral clock enabling */ \ 2990 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 2991 UNUSED(tmpreg); \ 2992 } while(0U) 2993 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 2994 __IO uint32_t tmpreg = 0x00U; \ 2995 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 2996 /* Delay after an RCC peripheral clock enabling */ \ 2997 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 2998 UNUSED(tmpreg); \ 2999 } while(0U) 3000 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 3001 __IO uint32_t tmpreg = 0x00U; \ 3002 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 3003 /* Delay after an RCC peripheral clock enabling */ \ 3004 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 3005 UNUSED(tmpreg); \ 3006 } while(0U) 3007 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 3008 __IO uint32_t tmpreg = 0x00U; \ 3009 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 3010 /* Delay after an RCC peripheral clock enabling */ \ 3011 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 3012 UNUSED(tmpreg); \ 3013 } while(0U) 3014 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 3015 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 3016 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 3017 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 3018 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 3019 /** 3020 * @} 3021 */ 3022 3023 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 3024 * @brief Get the enable or disable status of the APB1 peripheral clock. 3025 * @note After reset, the peripheral clock (used for registers read/write access) 3026 * is disabled and the application software has to enable this clock before 3027 * using it. 3028 * @{ 3029 */ 3030 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 3031 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 3032 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 3033 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 3034 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 3035 3036 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 3037 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 3038 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 3039 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 3040 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 3041 /** 3042 * @} 3043 */ 3044 3045 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 3046 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 3047 * @note After reset, the peripheral clock (used for registers read/write access) 3048 * is disabled and the application software has to enable this clock before 3049 * using it. 3050 * @{ 3051 */ 3052 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 3053 __IO uint32_t tmpreg = 0x00U; \ 3054 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 3055 /* Delay after an RCC peripheral clock enabling */ \ 3056 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 3057 UNUSED(tmpreg); \ 3058 } while(0U) 3059 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 3060 __IO uint32_t tmpreg = 0x00U; \ 3061 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 3062 /* Delay after an RCC peripheral clock enabling */ \ 3063 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 3064 UNUSED(tmpreg); \ 3065 } while(0U) 3066 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 3067 __IO uint32_t tmpreg = 0x00U; \ 3068 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 3069 /* Delay after an RCC peripheral clock enabling */ \ 3070 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 3071 UNUSED(tmpreg); \ 3072 } while(0U) 3073 3074 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 3075 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 3076 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 3077 /** 3078 * @} 3079 */ 3080 3081 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 3082 * @brief Get the enable or disable status of the APB2 peripheral clock. 3083 * @note After reset, the peripheral clock (used for registers read/write access) 3084 * is disabled and the application software has to enable this clock before 3085 * using it. 3086 * @{ 3087 */ 3088 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 3089 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 3090 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 3091 3092 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 3093 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 3094 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 3095 /** 3096 * @} 3097 */ 3098 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 3099 * @brief Force or release AHB1 peripheral reset. 3100 * @{ 3101 */ 3102 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) 3103 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 3104 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 3105 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 3106 3107 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) 3108 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 3109 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 3110 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 3111 /** 3112 * @} 3113 */ 3114 3115 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 3116 * @brief Force or release AHB2 peripheral reset. 3117 * @{ 3118 */ 3119 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 3120 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 3121 3122 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 3123 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 3124 /** 3125 * @} 3126 */ 3127 3128 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 3129 * @brief Force or release APB1 peripheral reset. 3130 * @{ 3131 */ 3132 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) 3133 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 3134 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 3135 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 3136 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 3137 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 3138 3139 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) 3140 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 3141 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 3142 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 3143 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 3144 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 3145 /** 3146 * @} 3147 */ 3148 3149 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 3150 * @brief Force or release APB2 peripheral reset. 3151 * @{ 3152 */ 3153 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 3154 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 3155 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 3156 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 3157 3158 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) 3159 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 3160 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 3161 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 3162 /** 3163 * @} 3164 */ 3165 3166 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 3167 * @brief Force or release AHB3 peripheral reset. 3168 * @{ 3169 */ 3170 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 3171 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 3172 /** 3173 * @} 3174 */ 3175 3176 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 3177 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 3178 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3179 * power consumption. 3180 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 3181 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3182 * @{ 3183 */ 3184 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 3185 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 3186 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 3187 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 3188 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 3189 3190 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 3191 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 3192 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 3193 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 3194 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 3195 /** 3196 * @} 3197 */ 3198 3199 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 3200 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 3201 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3202 * power consumption. 3203 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 3204 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3205 * @{ 3206 */ 3207 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 3208 3209 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 3210 /** 3211 * @} 3212 */ 3213 3214 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 3215 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 3216 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3217 * power consumption. 3218 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 3219 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3220 * @{ 3221 */ 3222 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 3223 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 3224 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 3225 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 3226 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 3227 3228 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 3229 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 3230 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 3231 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 3232 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 3233 /** 3234 * @} 3235 */ 3236 3237 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 3238 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 3239 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3240 * power consumption. 3241 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 3242 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3243 * @{ 3244 */ 3245 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 3246 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 3247 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 3248 3249 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 3250 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 3251 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 3252 /** 3253 * @} 3254 */ 3255 #endif /* STM32F401xC || STM32F401xE*/ 3256 /*----------------------------------------------------------------------------*/ 3257 3258 /*-------------------------------- STM32F410xx -------------------------------*/ 3259 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 3260 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 3261 * @brief Enables or disables the AHB1 peripheral clock. 3262 * @note After reset, the peripheral clock (used for registers read/write access) 3263 * is disabled and the application software has to enable this clock before 3264 * using it. 3265 * @{ 3266 */ 3267 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 3268 __IO uint32_t tmpreg = 0x00U; \ 3269 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3270 /* Delay after an RCC peripheral clock enabling */ \ 3271 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3272 UNUSED(tmpreg); \ 3273 } while(0U) 3274 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 3275 __IO uint32_t tmpreg = 0x00U; \ 3276 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ 3277 /* Delay after an RCC peripheral clock enabling */ \ 3278 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ 3279 UNUSED(tmpreg); \ 3280 } while(0U) 3281 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 3282 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN)) 3283 /** 3284 * @} 3285 */ 3286 3287 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 3288 * @brief Get the enable or disable status of the AHB1 peripheral clock. 3289 * @note After reset, the peripheral clock (used for registers read/write access) 3290 * is disabled and the application software has to enable this clock before 3291 * using it. 3292 * @{ 3293 */ 3294 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 3295 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET) 3296 3297 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 3298 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET) 3299 /** 3300 * @} 3301 */ 3302 3303 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 3304 * @brief Enable or disable the High Speed APB (APB1) peripheral clock. 3305 * @{ 3306 */ 3307 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 3308 __IO uint32_t tmpreg = 0x00U; \ 3309 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 3310 /* Delay after an RCC peripheral clock enabling */ \ 3311 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 3312 UNUSED(tmpreg); \ 3313 } while(0U) 3314 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 3315 __IO uint32_t tmpreg = 0x00U; \ 3316 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 3317 /* Delay after an RCC peripheral clock enabling */ \ 3318 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 3319 UNUSED(tmpreg); \ 3320 } while(0U) 3321 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 3322 __IO uint32_t tmpreg = 0x00U; \ 3323 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 3324 /* Delay after an RCC peripheral clock enabling */ \ 3325 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 3326 UNUSED(tmpreg); \ 3327 } while(0U) 3328 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ 3329 __IO uint32_t tmpreg = 0x00U; \ 3330 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 3331 /* Delay after an RCC peripheral clock enabling */ \ 3332 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 3333 UNUSED(tmpreg); \ 3334 } while(0U) 3335 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 3336 __IO uint32_t tmpreg = 0x00U; \ 3337 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 3338 /* Delay after an RCC peripheral clock enabling */ \ 3339 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 3340 UNUSED(tmpreg); \ 3341 } while(0U) 3342 3343 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 3344 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) 3345 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) 3346 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) 3347 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 3348 /** 3349 * @} 3350 */ 3351 3352 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 3353 * @brief Get the enable or disable status of the APB1 peripheral clock. 3354 * @note After reset, the peripheral clock (used for registers read/write access) 3355 * is disabled and the application software has to enable this clock before 3356 * using it. 3357 * @{ 3358 */ 3359 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 3360 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) 3361 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 3362 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) 3363 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 3364 3365 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 3366 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) 3367 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 3368 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) 3369 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 3370 /** 3371 * @} 3372 */ 3373 3374 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 3375 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 3376 * @{ 3377 */ 3378 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 3379 __IO uint32_t tmpreg = 0x00U; \ 3380 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 3381 /* Delay after an RCC peripheral clock enabling */ \ 3382 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 3383 UNUSED(tmpreg); \ 3384 } while(0U) 3385 #define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ 3386 __IO uint32_t tmpreg = 0x00U; \ 3387 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 3388 /* Delay after an RCC peripheral clock enabling */ \ 3389 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 3390 UNUSED(tmpreg); \ 3391 } while(0U) 3392 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 3393 #define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) 3394 /** 3395 * @} 3396 */ 3397 3398 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 3399 * @brief Get the enable or disable status of the APB2 peripheral clock. 3400 * @note After reset, the peripheral clock (used for registers read/write access) 3401 * is disabled and the application software has to enable this clock before 3402 * using it. 3403 * @{ 3404 */ 3405 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 3406 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) 3407 3408 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 3409 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) 3410 /** 3411 * @} 3412 */ 3413 3414 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 3415 * @brief Force or release AHB1 peripheral reset. 3416 * @{ 3417 */ 3418 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 3419 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST)) 3420 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 3421 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST)) 3422 /** 3423 * @} 3424 */ 3425 3426 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 3427 * @brief Force or release AHB2 peripheral reset. 3428 * @{ 3429 */ 3430 #define __HAL_RCC_AHB2_FORCE_RESET() 3431 #define __HAL_RCC_AHB2_RELEASE_RESET() 3432 /** 3433 * @} 3434 */ 3435 3436 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 3437 * @brief Force or release AHB3 peripheral reset. 3438 * @{ 3439 */ 3440 #define __HAL_RCC_AHB3_FORCE_RESET() 3441 #define __HAL_RCC_AHB3_RELEASE_RESET() 3442 /** 3443 * @} 3444 */ 3445 3446 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 3447 * @brief Force or release APB1 peripheral reset. 3448 * @{ 3449 */ 3450 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 3451 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) 3452 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) 3453 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 3454 3455 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 3456 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) 3457 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) 3458 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 3459 /** 3460 * @} 3461 */ 3462 3463 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 3464 * @brief Force or release APB2 peripheral reset. 3465 * @{ 3466 */ 3467 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 3468 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 3469 /** 3470 * @} 3471 */ 3472 3473 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 3474 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 3475 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3476 * power consumption. 3477 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3478 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3479 * @{ 3480 */ 3481 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN)) 3482 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 3483 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 3484 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 3485 3486 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN)) 3487 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 3488 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 3489 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 3490 /** 3491 * @} 3492 */ 3493 3494 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 3495 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 3496 * @{ 3497 */ 3498 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 3499 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) 3500 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) 3501 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) 3502 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 3503 3504 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 3505 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) 3506 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) 3507 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) 3508 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 3509 /** 3510 * @} 3511 */ 3512 3513 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 3514 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 3515 * @{ 3516 */ 3517 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 3518 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) 3519 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 3520 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) 3521 /** 3522 * @} 3523 */ 3524 3525 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 3526 /*----------------------------------------------------------------------------*/ 3527 3528 /*-------------------------------- STM32F411xx -------------------------------*/ 3529 #if defined(STM32F411xE) 3530 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 3531 * @brief Enables or disables the AHB1 peripheral clock. 3532 * @note After reset, the peripheral clock (used for registers read/write access) 3533 * is disabled and the application software has to enable this clock before 3534 * using it. 3535 * @{ 3536 */ 3537 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 3538 __IO uint32_t tmpreg = 0x00U; \ 3539 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 3540 /* Delay after an RCC peripheral clock enabling */ \ 3541 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 3542 UNUSED(tmpreg); \ 3543 } while(0U) 3544 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 3545 __IO uint32_t tmpreg = 0x00U; \ 3546 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 3547 /* Delay after an RCC peripheral clock enabling */ \ 3548 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 3549 UNUSED(tmpreg); \ 3550 } while(0U) 3551 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 3552 __IO uint32_t tmpreg = 0x00U; \ 3553 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 3554 /* Delay after an RCC peripheral clock enabling */ \ 3555 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 3556 UNUSED(tmpreg); \ 3557 } while(0U) 3558 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 3559 __IO uint32_t tmpreg = 0x00U; \ 3560 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3561 /* Delay after an RCC peripheral clock enabling */ \ 3562 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3563 UNUSED(tmpreg); \ 3564 } while(0U) 3565 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 3566 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 3567 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 3568 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 3569 /** 3570 * @} 3571 */ 3572 3573 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 3574 * @brief Get the enable or disable status of the AHB1 peripheral clock. 3575 * @note After reset, the peripheral clock (used for registers read/write access) 3576 * is disabled and the application software has to enable this clock before 3577 * using it. 3578 * @{ 3579 */ 3580 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 3581 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 3582 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 3583 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 3584 3585 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 3586 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 3587 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 3588 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 3589 /** 3590 * @} 3591 */ 3592 3593 /** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 3594 * @brief Enable or disable the AHB2 peripheral clock. 3595 * @note After reset, the peripheral clock (used for registers read/write access) 3596 * is disabled and the application software has to enable this clock before 3597 * using it. 3598 * @{ 3599 */ 3600 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 3601 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 3602 }while(0U) 3603 3604 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 3605 /** 3606 * @} 3607 */ 3608 3609 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 3610 * @brief Get the enable or disable status of the AHB2 peripheral clock. 3611 * @note After reset, the peripheral clock (used for registers read/write access) 3612 * is disabled and the application software has to enable this clock before 3613 * using it. 3614 * @{ 3615 */ 3616 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 3617 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 3618 /** 3619 * @} 3620 */ 3621 3622 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 3623 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 3624 * @note After reset, the peripheral clock (used for registers read/write access) 3625 * is disabled and the application software has to enable this clock before 3626 * using it. 3627 * @{ 3628 */ 3629 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 3630 __IO uint32_t tmpreg = 0x00U; \ 3631 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 3632 /* Delay after an RCC peripheral clock enabling */ \ 3633 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 3634 UNUSED(tmpreg); \ 3635 } while(0U) 3636 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 3637 __IO uint32_t tmpreg = 0x00U; \ 3638 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 3639 /* Delay after an RCC peripheral clock enabling */ \ 3640 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 3641 UNUSED(tmpreg); \ 3642 } while(0U) 3643 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 3644 __IO uint32_t tmpreg = 0x00U; \ 3645 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 3646 /* Delay after an RCC peripheral clock enabling */ \ 3647 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 3648 UNUSED(tmpreg); \ 3649 } while(0U) 3650 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 3651 __IO uint32_t tmpreg = 0x00U; \ 3652 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 3653 /* Delay after an RCC peripheral clock enabling */ \ 3654 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 3655 UNUSED(tmpreg); \ 3656 } while(0U) 3657 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 3658 __IO uint32_t tmpreg = 0x00U; \ 3659 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 3660 /* Delay after an RCC peripheral clock enabling */ \ 3661 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 3662 UNUSED(tmpreg); \ 3663 } while(0U) 3664 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 3665 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 3666 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 3667 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 3668 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 3669 /** 3670 * @} 3671 */ 3672 3673 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 3674 * @brief Get the enable or disable status of the APB1 peripheral clock. 3675 * @note After reset, the peripheral clock (used for registers read/write access) 3676 * is disabled and the application software has to enable this clock before 3677 * using it. 3678 * @{ 3679 */ 3680 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 3681 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 3682 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 3683 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 3684 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 3685 3686 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 3687 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 3688 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 3689 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 3690 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 3691 /** 3692 * @} 3693 */ 3694 3695 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 3696 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 3697 * @{ 3698 */ 3699 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 3700 __IO uint32_t tmpreg = 0x00U; \ 3701 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 3702 /* Delay after an RCC peripheral clock enabling */ \ 3703 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 3704 UNUSED(tmpreg); \ 3705 } while(0U) 3706 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 3707 __IO uint32_t tmpreg = 0x00U; \ 3708 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 3709 /* Delay after an RCC peripheral clock enabling */ \ 3710 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 3711 UNUSED(tmpreg); \ 3712 } while(0U) 3713 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 3714 __IO uint32_t tmpreg = 0x00U; \ 3715 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 3716 /* Delay after an RCC peripheral clock enabling */ \ 3717 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 3718 UNUSED(tmpreg); \ 3719 } while(0U) 3720 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 3721 __IO uint32_t tmpreg = 0x00U; \ 3722 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 3723 /* Delay after an RCC peripheral clock enabling */ \ 3724 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 3725 UNUSED(tmpreg); \ 3726 } while(0U) 3727 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 3728 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 3729 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 3730 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 3731 /** 3732 * @} 3733 */ 3734 3735 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 3736 * @brief Get the enable or disable status of the APB2 peripheral clock. 3737 * @note After reset, the peripheral clock (used for registers read/write access) 3738 * is disabled and the application software has to enable this clock before 3739 * using it. 3740 * @{ 3741 */ 3742 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 3743 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 3744 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 3745 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 3746 3747 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 3748 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 3749 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 3750 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 3751 /** 3752 * @} 3753 */ 3754 3755 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 3756 * @brief Force or release AHB1 peripheral reset. 3757 * @{ 3758 */ 3759 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 3760 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 3761 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 3762 3763 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 3764 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 3765 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 3766 /** 3767 * @} 3768 */ 3769 3770 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 3771 * @brief Force or release AHB2 peripheral reset. 3772 * @{ 3773 */ 3774 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 3775 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 3776 3777 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 3778 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 3779 /** 3780 * @} 3781 */ 3782 3783 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 3784 * @brief Force or release AHB3 peripheral reset. 3785 * @{ 3786 */ 3787 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 3788 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 3789 /** 3790 * @} 3791 */ 3792 3793 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 3794 * @brief Force or release APB1 peripheral reset. 3795 * @{ 3796 */ 3797 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 3798 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 3799 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 3800 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 3801 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 3802 3803 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 3804 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 3805 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 3806 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 3807 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 3808 /** 3809 * @} 3810 */ 3811 3812 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 3813 * @brief Force or release APB2 peripheral reset. 3814 * @{ 3815 */ 3816 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 3817 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 3818 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 3819 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 3820 3821 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 3822 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 3823 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 3824 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 3825 /** 3826 * @} 3827 */ 3828 3829 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 3830 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 3831 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3832 * power consumption. 3833 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3834 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3835 * @{ 3836 */ 3837 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 3838 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 3839 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 3840 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 3841 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 3842 3843 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 3844 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 3845 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 3846 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 3847 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 3848 /** 3849 * @} 3850 */ 3851 3852 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 3853 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 3854 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3855 * power consumption. 3856 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 3857 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3858 * @{ 3859 */ 3860 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 3861 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 3862 /** 3863 * @} 3864 */ 3865 3866 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 3867 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 3868 * @{ 3869 */ 3870 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 3871 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 3872 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 3873 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 3874 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 3875 3876 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 3877 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 3878 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 3879 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 3880 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 3881 /** 3882 * @} 3883 */ 3884 3885 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 3886 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 3887 * @{ 3888 */ 3889 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 3890 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 3891 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 3892 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 3893 3894 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 3895 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 3896 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 3897 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 3898 /** 3899 * @} 3900 */ 3901 #endif /* STM32F411xE */ 3902 /*----------------------------------------------------------------------------*/ 3903 3904 /*---------------------------------- STM32F446xx -----------------------------*/ 3905 #if defined(STM32F446xx) 3906 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 3907 * @brief Enables or disables the AHB1 peripheral clock. 3908 * @note After reset, the peripheral clock (used for registers read/write access) 3909 * is disabled and the application software has to enable this clock before 3910 * using it. 3911 * @{ 3912 */ 3913 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 3914 __IO uint32_t tmpreg = 0x00U; \ 3915 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 3916 /* Delay after an RCC peripheral clock enabling */ \ 3917 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 3918 UNUSED(tmpreg); \ 3919 } while(0U) 3920 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 3921 __IO uint32_t tmpreg = 0x00U; \ 3922 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 3923 /* Delay after an RCC peripheral clock enabling */ \ 3924 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 3925 UNUSED(tmpreg); \ 3926 } while(0U) 3927 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 3928 __IO uint32_t tmpreg = 0x00U; \ 3929 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3930 /* Delay after an RCC peripheral clock enabling */ \ 3931 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3932 UNUSED(tmpreg); \ 3933 } while(0U) 3934 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 3935 __IO uint32_t tmpreg = 0x00U; \ 3936 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 3937 /* Delay after an RCC peripheral clock enabling */ \ 3938 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 3939 UNUSED(tmpreg); \ 3940 } while(0U) 3941 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 3942 __IO uint32_t tmpreg = 0x00U; \ 3943 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 3944 /* Delay after an RCC peripheral clock enabling */ \ 3945 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 3946 UNUSED(tmpreg); \ 3947 } while(0U) 3948 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 3949 __IO uint32_t tmpreg = 0x00U; \ 3950 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 3951 /* Delay after an RCC peripheral clock enabling */ \ 3952 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 3953 UNUSED(tmpreg); \ 3954 } while(0U) 3955 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 3956 __IO uint32_t tmpreg = 0x00U; \ 3957 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 3958 /* Delay after an RCC peripheral clock enabling */ \ 3959 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 3960 UNUSED(tmpreg); \ 3961 } while(0U) 3962 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 3963 __IO uint32_t tmpreg = 0x00U; \ 3964 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 3965 /* Delay after an RCC peripheral clock enabling */ \ 3966 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 3967 UNUSED(tmpreg); \ 3968 } while(0U) 3969 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 3970 __IO uint32_t tmpreg = 0x00U; \ 3971 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 3972 /* Delay after an RCC peripheral clock enabling */ \ 3973 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 3974 UNUSED(tmpreg); \ 3975 } while(0U) 3976 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 3977 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 3978 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 3979 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 3980 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 3981 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 3982 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 3983 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 3984 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 3985 /** 3986 * @} 3987 */ 3988 3989 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 3990 * @brief Get the enable or disable status of the AHB1 peripheral clock. 3991 * @note After reset, the peripheral clock (used for registers read/write access) 3992 * is disabled and the application software has to enable this clock before 3993 * using it. 3994 * @{ 3995 */ 3996 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 3997 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 3998 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 3999 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 4000 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 4001 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 4002 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 4003 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET) 4004 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 4005 4006 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 4007 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 4008 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 4009 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 4010 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 4011 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 4012 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 4013 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 4014 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 4015 /** 4016 * @} 4017 */ 4018 4019 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 4020 * @brief Enable or disable the AHB2 peripheral clock. 4021 * @note After reset, the peripheral clock (used for registers read/write access) 4022 * is disabled and the application software has to enable this clock before 4023 * using it. 4024 * @{ 4025 */ 4026 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 4027 __IO uint32_t tmpreg = 0x00U; \ 4028 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 4029 /* Delay after an RCC peripheral clock enabling */ \ 4030 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 4031 UNUSED(tmpreg); \ 4032 } while(0U) 4033 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 4034 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 4035 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 4036 }while(0U) 4037 4038 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 4039 4040 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 4041 __IO uint32_t tmpreg = 0x00U; \ 4042 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 4043 /* Delay after an RCC peripheral clock enabling */ \ 4044 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 4045 UNUSED(tmpreg); \ 4046 } while(0U) 4047 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 4048 /** 4049 * @} 4050 */ 4051 4052 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 4053 * @brief Get the enable or disable status of the AHB2 peripheral clock. 4054 * @note After reset, the peripheral clock (used for registers read/write access) 4055 * is disabled and the application software has to enable this clock before 4056 * using it. 4057 * @{ 4058 */ 4059 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 4060 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 4061 4062 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 4063 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 4064 4065 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 4066 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 4067 /** 4068 * @} 4069 */ 4070 4071 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 4072 * @brief Enables or disables the AHB3 peripheral clock. 4073 * @note After reset, the peripheral clock (used for registers read/write access) 4074 * is disabled and the application software has to enable this clock before 4075 * using it. 4076 * @{ 4077 */ 4078 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 4079 __IO uint32_t tmpreg = 0x00U; \ 4080 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 4081 /* Delay after an RCC peripheral clock enabling */ \ 4082 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 4083 UNUSED(tmpreg); \ 4084 } while(0U) 4085 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 4086 __IO uint32_t tmpreg = 0x00U; \ 4087 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 4088 /* Delay after an RCC peripheral clock enabling */ \ 4089 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 4090 UNUSED(tmpreg); \ 4091 } while(0U) 4092 4093 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) 4094 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 4095 /** 4096 * @} 4097 */ 4098 4099 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 4100 * @brief Get the enable or disable status of the AHB3 peripheral clock. 4101 * @note After reset, the peripheral clock (used for registers read/write access) 4102 * is disabled and the application software has to enable this clock before 4103 * using it. 4104 * @{ 4105 */ 4106 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) 4107 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 4108 4109 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) 4110 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 4111 /** 4112 * @} 4113 */ 4114 4115 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 4116 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 4117 * @note After reset, the peripheral clock (used for registers read/write access) 4118 * is disabled and the application software has to enable this clock before 4119 * using it. 4120 * @{ 4121 */ 4122 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 4123 __IO uint32_t tmpreg = 0x00U; \ 4124 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 4125 /* Delay after an RCC peripheral clock enabling */ \ 4126 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 4127 UNUSED(tmpreg); \ 4128 } while(0U) 4129 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 4130 __IO uint32_t tmpreg = 0x00U; \ 4131 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 4132 /* Delay after an RCC peripheral clock enabling */ \ 4133 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 4134 UNUSED(tmpreg); \ 4135 } while(0U) 4136 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 4137 __IO uint32_t tmpreg = 0x00U; \ 4138 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 4139 /* Delay after an RCC peripheral clock enabling */ \ 4140 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 4141 UNUSED(tmpreg); \ 4142 } while(0U) 4143 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 4144 __IO uint32_t tmpreg = 0x00U; \ 4145 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 4146 /* Delay after an RCC peripheral clock enabling */ \ 4147 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 4148 UNUSED(tmpreg); \ 4149 } while(0U) 4150 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 4151 __IO uint32_t tmpreg = 0x00U; \ 4152 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 4153 /* Delay after an RCC peripheral clock enabling */ \ 4154 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 4155 UNUSED(tmpreg); \ 4156 } while(0U) 4157 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ 4158 __IO uint32_t tmpreg = 0x00U; \ 4159 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ 4160 /* Delay after an RCC peripheral clock enabling */ \ 4161 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ 4162 UNUSED(tmpreg); \ 4163 } while(0U) 4164 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 4165 __IO uint32_t tmpreg = 0x00U; \ 4166 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 4167 /* Delay after an RCC peripheral clock enabling */ \ 4168 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 4169 UNUSED(tmpreg); \ 4170 } while(0U) 4171 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 4172 __IO uint32_t tmpreg = 0x00U; \ 4173 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 4174 /* Delay after an RCC peripheral clock enabling */ \ 4175 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 4176 UNUSED(tmpreg); \ 4177 } while(0U) 4178 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 4179 __IO uint32_t tmpreg = 0x00U; \ 4180 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 4181 /* Delay after an RCC peripheral clock enabling */ \ 4182 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 4183 UNUSED(tmpreg); \ 4184 } while(0U) 4185 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ 4186 __IO uint32_t tmpreg = 0x00U; \ 4187 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 4188 /* Delay after an RCC peripheral clock enabling */ \ 4189 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 4190 UNUSED(tmpreg); \ 4191 } while(0U) 4192 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 4193 __IO uint32_t tmpreg = 0x00U; \ 4194 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 4195 /* Delay after an RCC peripheral clock enabling */ \ 4196 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 4197 UNUSED(tmpreg); \ 4198 } while(0U) 4199 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 4200 __IO uint32_t tmpreg = 0x00U; \ 4201 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 4202 /* Delay after an RCC peripheral clock enabling */ \ 4203 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 4204 UNUSED(tmpreg); \ 4205 } while(0U) 4206 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 4207 __IO uint32_t tmpreg = 0x00U; \ 4208 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 4209 /* Delay after an RCC peripheral clock enabling */ \ 4210 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 4211 UNUSED(tmpreg); \ 4212 } while(0U) 4213 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 4214 __IO uint32_t tmpreg = 0x00U; \ 4215 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 4216 /* Delay after an RCC peripheral clock enabling */ \ 4217 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 4218 UNUSED(tmpreg); \ 4219 } while(0U) 4220 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 4221 __IO uint32_t tmpreg = 0x00U; \ 4222 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 4223 /* Delay after an RCC peripheral clock enabling */ \ 4224 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 4225 UNUSED(tmpreg); \ 4226 } while(0U) 4227 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 4228 __IO uint32_t tmpreg = 0x00U; \ 4229 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 4230 /* Delay after an RCC peripheral clock enabling */ \ 4231 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 4232 UNUSED(tmpreg); \ 4233 } while(0U) 4234 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 4235 __IO uint32_t tmpreg = 0x00U; \ 4236 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 4237 /* Delay after an RCC peripheral clock enabling */ \ 4238 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 4239 UNUSED(tmpreg); \ 4240 } while(0U) 4241 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 4242 __IO uint32_t tmpreg = 0x00U; \ 4243 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 4244 /* Delay after an RCC peripheral clock enabling */ \ 4245 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 4246 UNUSED(tmpreg); \ 4247 } while(0U) 4248 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 4249 __IO uint32_t tmpreg = 0x00U; \ 4250 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 4251 /* Delay after an RCC peripheral clock enabling */ \ 4252 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 4253 UNUSED(tmpreg); \ 4254 } while(0U) 4255 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 4256 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 4257 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 4258 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 4259 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 4260 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 4261 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 4262 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 4263 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 4264 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 4265 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) 4266 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 4267 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 4268 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 4269 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) 4270 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 4271 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 4272 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) 4273 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 4274 /** 4275 * @} 4276 */ 4277 4278 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 4279 * @brief Get the enable or disable status of the APB1 peripheral clock. 4280 * @note After reset, the peripheral clock (used for registers read/write access) 4281 * is disabled and the application software has to enable this clock before 4282 * using it. 4283 * @{ 4284 */ 4285 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 4286 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 4287 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 4288 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 4289 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 4290 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 4291 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 4292 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 4293 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 4294 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 4295 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) 4296 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 4297 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 4298 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 4299 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) 4300 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 4301 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 4302 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) 4303 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 4304 4305 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 4306 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 4307 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 4308 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 4309 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 4310 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 4311 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 4312 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 4313 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 4314 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 4315 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) 4316 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 4317 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 4318 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 4319 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) 4320 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 4321 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 4322 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) 4323 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 4324 /** 4325 * @} 4326 */ 4327 4328 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 4329 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 4330 * @note After reset, the peripheral clock (used for registers read/write access) 4331 * is disabled and the application software has to enable this clock before 4332 * using it. 4333 * @{ 4334 */ 4335 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 4336 __IO uint32_t tmpreg = 0x00U; \ 4337 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 4338 /* Delay after an RCC peripheral clock enabling */ \ 4339 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 4340 UNUSED(tmpreg); \ 4341 } while(0U) 4342 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 4343 __IO uint32_t tmpreg = 0x00U; \ 4344 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 4345 /* Delay after an RCC peripheral clock enabling */ \ 4346 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 4347 UNUSED(tmpreg); \ 4348 } while(0U) 4349 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 4350 __IO uint32_t tmpreg = 0x00U; \ 4351 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 4352 /* Delay after an RCC peripheral clock enabling */ \ 4353 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 4354 UNUSED(tmpreg); \ 4355 } while(0U) 4356 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 4357 __IO uint32_t tmpreg = 0x00U; \ 4358 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 4359 /* Delay after an RCC peripheral clock enabling */ \ 4360 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 4361 UNUSED(tmpreg); \ 4362 } while(0U) 4363 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 4364 __IO uint32_t tmpreg = 0x00U; \ 4365 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 4366 /* Delay after an RCC peripheral clock enabling */ \ 4367 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 4368 UNUSED(tmpreg); \ 4369 } while(0U) 4370 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 4371 __IO uint32_t tmpreg = 0x00U; \ 4372 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 4373 /* Delay after an RCC peripheral clock enabling */ \ 4374 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 4375 UNUSED(tmpreg); \ 4376 } while(0U) 4377 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 4378 __IO uint32_t tmpreg = 0x00U; \ 4379 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 4380 /* Delay after an RCC peripheral clock enabling */ \ 4381 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 4382 UNUSED(tmpreg); \ 4383 } while(0U) 4384 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 4385 __IO uint32_t tmpreg = 0x00U; \ 4386 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 4387 /* Delay after an RCC peripheral clock enabling */ \ 4388 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 4389 UNUSED(tmpreg); \ 4390 } while(0U) 4391 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 4392 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 4393 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 4394 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 4395 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 4396 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 4397 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 4398 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) 4399 /** 4400 * @} 4401 */ 4402 4403 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 4404 * @brief Get the enable or disable status of the APB2 peripheral clock. 4405 * @note After reset, the peripheral clock (used for registers read/write access) 4406 * is disabled and the application software has to enable this clock before 4407 * using it. 4408 * @{ 4409 */ 4410 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 4411 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 4412 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 4413 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 4414 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 4415 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 4416 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 4417 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) 4418 4419 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 4420 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 4421 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 4422 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 4423 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 4424 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 4425 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 4426 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) 4427 /** 4428 * @} 4429 */ 4430 4431 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 4432 * @brief Force or release AHB1 peripheral reset. 4433 * @{ 4434 */ 4435 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 4436 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 4437 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 4438 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 4439 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 4440 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 4441 4442 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 4443 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 4444 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 4445 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 4446 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 4447 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 4448 /** 4449 * @} 4450 */ 4451 4452 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 4453 * @brief Force or release AHB2 peripheral reset. 4454 * @{ 4455 */ 4456 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 4457 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 4458 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 4459 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 4460 4461 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 4462 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 4463 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 4464 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 4465 /** 4466 * @} 4467 */ 4468 4469 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 4470 * @brief Force or release AHB3 peripheral reset. 4471 * @{ 4472 */ 4473 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 4474 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 4475 4476 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) 4477 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 4478 4479 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) 4480 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 4481 /** 4482 * @} 4483 */ 4484 4485 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 4486 * @brief Force or release APB1 peripheral reset. 4487 * @{ 4488 */ 4489 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 4490 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 4491 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 4492 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 4493 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 4494 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) 4495 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 4496 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 4497 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 4498 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) 4499 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 4500 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 4501 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) 4502 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 4503 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 4504 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 4505 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 4506 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 4507 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 4508 4509 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 4510 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 4511 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 4512 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 4513 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 4514 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 4515 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 4516 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 4517 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 4518 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 4519 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) 4520 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 4521 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 4522 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 4523 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) 4524 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 4525 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 4526 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) 4527 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 4528 /** 4529 * @} 4530 */ 4531 4532 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 4533 * @brief Force or release APB2 peripheral reset. 4534 * @{ 4535 */ 4536 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 4537 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 4538 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) 4539 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 4540 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 4541 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 4542 4543 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 4544 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 4545 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 4546 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 4547 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 4548 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) 4549 /** 4550 * @} 4551 */ 4552 4553 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 4554 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 4555 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 4556 * power consumption. 4557 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 4558 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4559 * @{ 4560 */ 4561 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 4562 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 4563 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 4564 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 4565 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 4566 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 4567 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 4568 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 4569 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 4570 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 4571 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 4572 4573 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 4574 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 4575 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 4576 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 4577 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 4578 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 4579 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 4580 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 4581 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 4582 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 4583 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 4584 /** 4585 * @} 4586 */ 4587 4588 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 4589 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 4590 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 4591 * power consumption. 4592 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 4593 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4594 * @{ 4595 */ 4596 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 4597 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 4598 4599 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 4600 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 4601 4602 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 4603 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 4604 /** 4605 * @} 4606 */ 4607 4608 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 4609 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 4610 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 4611 * power consumption. 4612 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 4613 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4614 * @{ 4615 */ 4616 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 4617 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 4618 4619 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) 4620 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 4621 /** 4622 * @} 4623 */ 4624 4625 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 4626 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 4627 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 4628 * power consumption. 4629 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 4630 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4631 * @{ 4632 */ 4633 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 4634 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 4635 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 4636 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 4637 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 4638 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) 4639 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 4640 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 4641 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 4642 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) 4643 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 4644 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 4645 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) 4646 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 4647 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 4648 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 4649 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 4650 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 4651 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 4652 4653 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 4654 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 4655 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 4656 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 4657 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 4658 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 4659 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 4660 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 4661 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 4662 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 4663 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) 4664 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 4665 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 4666 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 4667 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) 4668 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 4669 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 4670 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) 4671 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 4672 /** 4673 * @} 4674 */ 4675 4676 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 4677 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 4678 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 4679 * power consumption. 4680 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 4681 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4682 * @{ 4683 */ 4684 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 4685 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 4686 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 4687 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 4688 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) 4689 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 4690 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 4691 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 4692 4693 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 4694 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 4695 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 4696 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 4697 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 4698 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 4699 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 4700 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) 4701 /** 4702 * @} 4703 */ 4704 4705 #endif /* STM32F446xx */ 4706 /*----------------------------------------------------------------------------*/ 4707 4708 /*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/ 4709 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 4710 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 4711 * @brief Enables or disables the AHB1 peripheral clock. 4712 * @note After reset, the peripheral clock (used for registers read/write access) 4713 * is disabled and the application software has to enable this clock before 4714 * using it. 4715 * @{ 4716 */ 4717 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4718 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 4719 __IO uint32_t tmpreg = 0x00U; \ 4720 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 4721 /* Delay after an RCC peripheral clock enabling */ \ 4722 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 4723 UNUSED(tmpreg); \ 4724 } while(0U) 4725 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4726 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4727 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 4728 __IO uint32_t tmpreg = 0x00U; \ 4729 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 4730 /* Delay after an RCC peripheral clock enabling */ \ 4731 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 4732 UNUSED(tmpreg); \ 4733 } while(0U) 4734 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4735 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4736 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 4737 __IO uint32_t tmpreg = 0x00U; \ 4738 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 4739 /* Delay after an RCC peripheral clock enabling */ \ 4740 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 4741 UNUSED(tmpreg); \ 4742 } while(0U) 4743 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 4744 __IO uint32_t tmpreg = 0x00U; \ 4745 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 4746 /* Delay after an RCC peripheral clock enabling */ \ 4747 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 4748 UNUSED(tmpreg); \ 4749 } while(0U) 4750 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 4751 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 4752 __IO uint32_t tmpreg = 0x00U; \ 4753 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 4754 /* Delay after an RCC peripheral clock enabling */ \ 4755 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 4756 UNUSED(tmpreg); \ 4757 } while(0U) 4758 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4759 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 4760 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4761 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4762 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 4763 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4764 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4765 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 4766 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 4767 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 4768 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 4769 /** 4770 * @} 4771 */ 4772 4773 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 4774 * @brief Get the enable or disable status of the AHB1 peripheral clock. 4775 * @note After reset, the peripheral clock (used for registers read/write access) 4776 * is disabled and the application software has to enable this clock before 4777 * using it. 4778 * @{ 4779 */ 4780 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4781 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 4782 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4783 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4784 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 4785 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4786 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4787 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 4788 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 4789 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 4790 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 4791 4792 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4793 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 4794 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4795 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4796 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 4797 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4798 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4799 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 4800 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 4801 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 4802 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 4803 /** 4804 * @} 4805 */ 4806 4807 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 4808 * @brief Enable or disable the AHB2 peripheral clock. 4809 * @note After reset, the peripheral clock (used for registers read/write access) 4810 * is disabled and the application software has to enable this clock before 4811 * using it. 4812 * @{ 4813 */ 4814 #if defined(STM32F423xx) 4815 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 4816 __IO uint32_t tmpreg = 0x00U; \ 4817 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ 4818 /* Delay after an RCC peripheral clock enabling */ \ 4819 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ 4820 UNUSED(tmpreg); \ 4821 } while(0U) 4822 4823 #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) 4824 #endif /* STM32F423xx */ 4825 4826 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 4827 __IO uint32_t tmpreg = 0x00U; \ 4828 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 4829 /* Delay after an RCC peripheral clock enabling */ \ 4830 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 4831 UNUSED(tmpreg); \ 4832 } while(0U) 4833 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 4834 4835 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 4836 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 4837 }while(0U) 4838 4839 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 4840 /** 4841 * @} 4842 */ 4843 4844 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 4845 * @brief Get the enable or disable status of the AHB2 peripheral clock. 4846 * @note After reset, the peripheral clock (used for registers read/write access) 4847 * is disabled and the application software has to enable this clock before 4848 * using it. 4849 * @{ 4850 */ 4851 #if defined(STM32F423xx) 4852 #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) 4853 #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) 4854 #endif /* STM32F423xx */ 4855 4856 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 4857 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 4858 4859 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 4860 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 4861 /** 4862 * @} 4863 */ 4864 4865 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 4866 * @brief Enables or disables the AHB3 peripheral clock. 4867 * @note After reset, the peripheral clock (used for registers read/write access) 4868 * is disabled and the application software has to enable this clock before 4869 * using it. 4870 * @{ 4871 */ 4872 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 4873 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ 4874 __IO uint32_t tmpreg = 0x00U; \ 4875 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 4876 /* Delay after an RCC peripheral clock enabling */ \ 4877 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 4878 UNUSED(tmpreg); \ 4879 } while(0U) 4880 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 4881 __IO uint32_t tmpreg = 0x00U; \ 4882 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 4883 /* Delay after an RCC peripheral clock enabling */ \ 4884 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 4885 UNUSED(tmpreg); \ 4886 } while(0U) 4887 4888 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) 4889 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 4890 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 4891 /** 4892 * @} 4893 */ 4894 4895 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 4896 * @brief Get the enable or disable status of the AHB3 peripheral clock. 4897 * @note After reset, the peripheral clock (used for registers read/write access) 4898 * is disabled and the application software has to enable this clock before 4899 * using it. 4900 * @{ 4901 */ 4902 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 4903 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 4904 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 4905 4906 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) 4907 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 4908 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 4909 4910 /** 4911 * @} 4912 */ 4913 4914 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 4915 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 4916 * @note After reset, the peripheral clock (used for registers read/write access) 4917 * is disabled and the application software has to enable this clock before 4918 * using it. 4919 * @{ 4920 */ 4921 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 4922 __IO uint32_t tmpreg = 0x00U; \ 4923 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 4924 /* Delay after an RCC peripheral clock enabling */ \ 4925 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 4926 UNUSED(tmpreg); \ 4927 } while(0U) 4928 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 4929 __IO uint32_t tmpreg = 0x00U; \ 4930 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 4931 /* Delay after an RCC peripheral clock enabling */ \ 4932 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 4933 UNUSED(tmpreg); \ 4934 } while(0U) 4935 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 4936 __IO uint32_t tmpreg = 0x00U; \ 4937 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 4938 /* Delay after an RCC peripheral clock enabling */ \ 4939 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 4940 UNUSED(tmpreg); \ 4941 } while(0U) 4942 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 4943 __IO uint32_t tmpreg = 0x00U; \ 4944 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 4945 /* Delay after an RCC peripheral clock enabling */ \ 4946 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 4947 UNUSED(tmpreg); \ 4948 } while(0U) 4949 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 4950 __IO uint32_t tmpreg = 0x00U; \ 4951 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 4952 /* Delay after an RCC peripheral clock enabling */ \ 4953 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 4954 UNUSED(tmpreg); \ 4955 } while(0U) 4956 #if defined(STM32F413xx) || defined(STM32F423xx) 4957 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 4958 __IO uint32_t tmpreg = 0x00U; \ 4959 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 4960 /* Delay after an RCC peripheral clock enabling */ \ 4961 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 4962 UNUSED(tmpreg); \ 4963 } while(0U) 4964 #endif /* STM32F413xx || STM32F423xx */ 4965 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 4966 __IO uint32_t tmpreg = 0x00U; \ 4967 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 4968 /* Delay after an RCC peripheral clock enabling */ \ 4969 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 4970 UNUSED(tmpreg); \ 4971 } while(0U) 4972 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 4973 __IO uint32_t tmpreg = 0x00U; \ 4974 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 4975 /* Delay after an RCC peripheral clock enabling */ \ 4976 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 4977 UNUSED(tmpreg); \ 4978 } while(0U) 4979 4980 #if defined(STM32F413xx) || defined(STM32F423xx) 4981 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 4982 __IO uint32_t tmpreg = 0x00U; \ 4983 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 4984 /* Delay after an RCC peripheral clock enabling */ \ 4985 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 4986 UNUSED(tmpreg); \ 4987 } while(0U) 4988 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 4989 __IO uint32_t tmpreg = 0x00U; \ 4990 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 4991 /* Delay after an RCC peripheral clock enabling */ \ 4992 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 4993 UNUSED(tmpreg); \ 4994 } while(0U) 4995 #endif /* STM32F413xx || STM32F423xx */ 4996 4997 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ 4998 __IO uint32_t tmpreg = 0x00U; \ 4999 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 5000 /* Delay after an RCC peripheral clock enabling */ \ 5001 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 5002 UNUSED(tmpreg); \ 5003 } while(0U) 5004 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 5005 __IO uint32_t tmpreg = 0x00U; \ 5006 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 5007 /* Delay after an RCC peripheral clock enabling */ \ 5008 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 5009 UNUSED(tmpreg); \ 5010 } while(0U) 5011 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 5012 __IO uint32_t tmpreg = 0x00U; \ 5013 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 5014 /* Delay after an RCC peripheral clock enabling */ \ 5015 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 5016 UNUSED(tmpreg); \ 5017 } while(0U) 5018 #if defined(STM32F413xx) || defined(STM32F423xx) 5019 #define __HAL_RCC_CAN3_CLK_ENABLE() do { \ 5020 __IO uint32_t tmpreg = 0x00U; \ 5021 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ 5022 /* Delay after an RCC peripheral clock enabling */ \ 5023 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ 5024 UNUSED(tmpreg); \ 5025 } while(0U) 5026 #endif /* STM32F413xx || STM32F423xx */ 5027 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 5028 __IO uint32_t tmpreg = 0x00U; \ 5029 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 5030 /* Delay after an RCC peripheral clock enabling */ \ 5031 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 5032 UNUSED(tmpreg); \ 5033 } while(0U) 5034 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 5035 __IO uint32_t tmpreg = 0x00U; \ 5036 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 5037 /* Delay after an RCC peripheral clock enabling */ \ 5038 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 5039 UNUSED(tmpreg); \ 5040 } while(0U) 5041 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 5042 __IO uint32_t tmpreg = 0x00U; \ 5043 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 5044 /* Delay after an RCC peripheral clock enabling */ \ 5045 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 5046 UNUSED(tmpreg); \ 5047 } while(0U) 5048 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 5049 __IO uint32_t tmpreg = 0x00U; \ 5050 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 5051 /* Delay after an RCC peripheral clock enabling */ \ 5052 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 5053 UNUSED(tmpreg); \ 5054 } while(0U) 5055 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 5056 __IO uint32_t tmpreg = 0x00U; \ 5057 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 5058 /* Delay after an RCC peripheral clock enabling */ \ 5059 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 5060 UNUSED(tmpreg); \ 5061 } while(0U) 5062 #if defined(STM32F413xx) || defined(STM32F423xx) 5063 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 5064 __IO uint32_t tmpreg = 0x00U; \ 5065 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 5066 /* Delay after an RCC peripheral clock enabling */ \ 5067 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 5068 UNUSED(tmpreg); \ 5069 } while(0U) 5070 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 5071 __IO uint32_t tmpreg = 0x00U; \ 5072 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 5073 /* Delay after an RCC peripheral clock enabling */ \ 5074 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 5075 UNUSED(tmpreg); \ 5076 } while(0U) 5077 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 5078 __IO uint32_t tmpreg = 0x00U; \ 5079 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 5080 /* Delay after an RCC peripheral clock enabling */ \ 5081 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 5082 UNUSED(tmpreg); \ 5083 } while(0U) 5084 #endif /* STM32F413xx || STM32F423xx */ 5085 5086 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 5087 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 5088 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 5089 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 5090 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 5091 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 5092 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 5093 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 5094 #if defined(STM32F413xx) || defined(STM32F423xx) 5095 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) 5096 #endif /* STM32F413xx || STM32F423xx */ 5097 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) 5098 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 5099 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 5100 #if defined(STM32F413xx) || defined(STM32F423xx) 5101 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 5102 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 5103 #endif /* STM32F413xx || STM32F423xx */ 5104 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 5105 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) 5106 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 5107 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 5108 #if defined(STM32F413xx) || defined(STM32F423xx) 5109 #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) 5110 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 5111 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) 5112 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) 5113 #endif /* STM32F413xx || STM32F423xx */ 5114 5115 /** 5116 * @} 5117 */ 5118 5119 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 5120 * @brief Get the enable or disable status of the APB1 peripheral clock. 5121 * @note After reset, the peripheral clock (used for registers read/write access) 5122 * is disabled and the application software has to enable this clock before 5123 * using it. 5124 * @{ 5125 */ 5126 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 5127 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 5128 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 5129 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 5130 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 5131 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 5132 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 5133 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 5134 #if defined(STM32F413xx) || defined(STM32F423xx) 5135 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 5136 #endif /* STM32F413xx || STM32F423xx */ 5137 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) 5138 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 5139 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 5140 #if defined(STM32F413xx) || defined(STM32F423xx) 5141 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 5142 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 5143 #endif /* STM32F413xx || STM32F423xx */ 5144 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 5145 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) 5146 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET) 5147 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 5148 #if defined(STM32F413xx) || defined(STM32F423xx) 5149 #define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) 5150 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 5151 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) 5152 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 5153 #endif /* STM32F413xx || STM32F423xx */ 5154 5155 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 5156 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 5157 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 5158 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 5159 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 5160 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 5161 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 5162 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 5163 #if defined(STM32F413xx) || defined(STM32F423xx) 5164 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 5165 #endif /* STM32F413xx || STM32F423xx */ 5166 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) 5167 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 5168 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 5169 #if defined(STM32F413xx) || defined(STM32F423xx) 5170 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 5171 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 5172 #endif /* STM32F413xx || STM32F423xx */ 5173 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 5174 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) 5175 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 5176 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 5177 #if defined(STM32F413xx) || defined(STM32F423xx) 5178 #define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) 5179 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 5180 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) 5181 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) 5182 #endif /* STM32F413xx || STM32F423xx */ 5183 /** 5184 * @} 5185 */ 5186 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 5187 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 5188 * @note After reset, the peripheral clock (used for registers read/write access) 5189 * is disabled and the application software has to enable this clock before 5190 * using it. 5191 * @{ 5192 */ 5193 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 5194 __IO uint32_t tmpreg = 0x00U; \ 5195 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 5196 /* Delay after an RCC peripheral clock enabling */ \ 5197 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 5198 UNUSED(tmpreg); \ 5199 } while(0U) 5200 #if defined(STM32F413xx) || defined(STM32F423xx) 5201 #define __HAL_RCC_UART9_CLK_ENABLE() do { \ 5202 __IO uint32_t tmpreg = 0x00U; \ 5203 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ 5204 /* Delay after an RCC peripheral clock enabling */ \ 5205 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ 5206 UNUSED(tmpreg); \ 5207 } while(0U) 5208 #define __HAL_RCC_UART10_CLK_ENABLE() do { \ 5209 __IO uint32_t tmpreg = 0x00U; \ 5210 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ 5211 /* Delay after an RCC peripheral clock enabling */ \ 5212 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ 5213 UNUSED(tmpreg); \ 5214 } while(0U) 5215 #endif /* STM32F413xx || STM32F423xx */ 5216 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 5217 __IO uint32_t tmpreg = 0x00U; \ 5218 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 5219 /* Delay after an RCC peripheral clock enabling */ \ 5220 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 5221 UNUSED(tmpreg); \ 5222 } while(0U) 5223 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 5224 __IO uint32_t tmpreg = 0x00U; \ 5225 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 5226 /* Delay after an RCC peripheral clock enabling */ \ 5227 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 5228 UNUSED(tmpreg); \ 5229 } while(0U) 5230 #define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ 5231 __IO uint32_t tmpreg = 0x00U; \ 5232 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 5233 /* Delay after an RCC peripheral clock enabling */ \ 5234 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 5235 UNUSED(tmpreg); \ 5236 } while(0U) 5237 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 5238 __IO uint32_t tmpreg = 0x00U; \ 5239 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 5240 /* Delay after an RCC peripheral clock enabling */ \ 5241 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 5242 UNUSED(tmpreg); \ 5243 } while(0U) 5244 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 5245 __IO uint32_t tmpreg = 0x00U; \ 5246 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 5247 /* Delay after an RCC peripheral clock enabling */ \ 5248 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 5249 UNUSED(tmpreg); \ 5250 } while(0U) 5251 #if defined(STM32F413xx) || defined(STM32F423xx) 5252 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 5253 __IO uint32_t tmpreg = 0x00U; \ 5254 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 5255 /* Delay after an RCC peripheral clock enabling */ \ 5256 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 5257 UNUSED(tmpreg); \ 5258 } while(0U) 5259 #endif /* STM32F413xx || STM32F423xx */ 5260 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ 5261 __IO uint32_t tmpreg = 0x00U; \ 5262 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 5263 /* Delay after an RCC peripheral clock enabling */ \ 5264 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 5265 UNUSED(tmpreg); \ 5266 } while(0U) 5267 #if defined(STM32F413xx) || defined(STM32F423xx) 5268 #define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \ 5269 __IO uint32_t tmpreg = 0x00U; \ 5270 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ 5271 /* Delay after an RCC peripheral clock enabling */ \ 5272 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ 5273 UNUSED(tmpreg); \ 5274 } while(0U) 5275 #endif /* STM32F413xx || STM32F423xx */ 5276 5277 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 5278 #if defined(STM32F413xx) || defined(STM32F423xx) 5279 #define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN)) 5280 #define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN)) 5281 #endif /* STM32F413xx || STM32F423xx */ 5282 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 5283 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 5284 #define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) 5285 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 5286 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 5287 #if defined(STM32F413xx) || defined(STM32F423xx) 5288 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 5289 #endif /* STM32F413xx || STM32F423xx */ 5290 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) 5291 #if defined(STM32F413xx) || defined(STM32F423xx) 5292 #define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN)) 5293 #endif /* STM32F413xx || STM32F423xx */ 5294 /** 5295 * @} 5296 */ 5297 5298 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 5299 * @brief Get the enable or disable status of the APB2 peripheral clock. 5300 * @note After reset, the peripheral clock (used for registers read/write access) 5301 * is disabled and the application software has to enable this clock before 5302 * using it. 5303 * @{ 5304 */ 5305 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 5306 #if defined(STM32F413xx) || defined(STM32F423xx) 5307 #define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET) 5308 #define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET) 5309 #endif /* STM32F413xx || STM32F423xx */ 5310 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 5311 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 5312 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) 5313 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 5314 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 5315 #if defined(STM32F413xx) || defined(STM32F423xx) 5316 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 5317 #endif /* STM32F413xx || STM32F423xx */ 5318 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) 5319 #if defined(STM32F413xx) || defined(STM32F423xx) 5320 #define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET) 5321 #endif /* STM32F413xx || STM32F423xx */ 5322 5323 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 5324 #if defined(STM32F413xx) || defined(STM32F423xx) 5325 #define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET) 5326 #define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET) 5327 #endif /* STM32F413xx || STM32F423xx */ 5328 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 5329 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 5330 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) 5331 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 5332 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 5333 #if defined(STM32F413xx) || defined(STM32F423xx) 5334 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 5335 #endif /* STM32F413xx || STM32F423xx */ 5336 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) 5337 #if defined(STM32F413xx) || defined(STM32F423xx) 5338 #define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET) 5339 #endif /* STM32F413xx || STM32F423xx */ 5340 /** 5341 * @} 5342 */ 5343 5344 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 5345 * @brief Force or release AHB1 peripheral reset. 5346 * @{ 5347 */ 5348 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5349 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 5350 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 5351 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5352 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 5353 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 5354 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5355 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 5356 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 5357 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 5358 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 5359 5360 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5361 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 5362 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 5363 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5364 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 5365 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 5366 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5367 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 5368 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 5369 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 5370 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 5371 /** 5372 * @} 5373 */ 5374 5375 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 5376 * @brief Force or release AHB2 peripheral reset. 5377 * @{ 5378 */ 5379 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 5380 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 5381 5382 #if defined(STM32F423xx) 5383 #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) 5384 #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) 5385 #endif /* STM32F423xx */ 5386 5387 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 5388 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 5389 5390 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 5391 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 5392 /** 5393 * @} 5394 */ 5395 5396 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 5397 * @brief Force or release AHB3 peripheral reset. 5398 * @{ 5399 */ 5400 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 5401 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 5402 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 5403 5404 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) 5405 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 5406 5407 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) 5408 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 5409 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 5410 #if defined(STM32F412Cx) 5411 #define __HAL_RCC_AHB3_FORCE_RESET() 5412 #define __HAL_RCC_AHB3_RELEASE_RESET() 5413 5414 #define __HAL_RCC_FSMC_FORCE_RESET() 5415 #define __HAL_RCC_QSPI_FORCE_RESET() 5416 5417 #define __HAL_RCC_FSMC_RELEASE_RESET() 5418 #define __HAL_RCC_QSPI_RELEASE_RESET() 5419 #endif /* STM32F412Cx */ 5420 /** 5421 * @} 5422 */ 5423 5424 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 5425 * @brief Force or release APB1 peripheral reset. 5426 * @{ 5427 */ 5428 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 5429 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 5430 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 5431 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 5432 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 5433 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 5434 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 5435 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 5436 #if defined(STM32F413xx) || defined(STM32F423xx) 5437 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) 5438 #endif /* STM32F413xx || STM32F423xx */ 5439 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 5440 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 5441 #if defined(STM32F413xx) || defined(STM32F423xx) 5442 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 5443 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 5444 #endif /* STM32F413xx || STM32F423xx */ 5445 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 5446 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) 5447 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 5448 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 5449 #if defined(STM32F413xx) || defined(STM32F423xx) 5450 #define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) 5451 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 5452 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) 5453 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) 5454 #endif /* STM32F413xx || STM32F423xx */ 5455 5456 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 5457 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 5458 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 5459 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 5460 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 5461 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 5462 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 5463 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 5464 #if defined(STM32F413xx) || defined(STM32F423xx) 5465 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) 5466 #endif /* STM32F413xx || STM32F423xx */ 5467 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 5468 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 5469 #if defined(STM32F413xx) || defined(STM32F423xx) 5470 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 5471 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 5472 #endif /* STM32F413xx || STM32F423xx */ 5473 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 5474 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) 5475 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 5476 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 5477 #if defined(STM32F413xx) || defined(STM32F423xx) 5478 #define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) 5479 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 5480 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) 5481 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) 5482 #endif /* STM32F413xx || STM32F423xx */ 5483 /** 5484 * @} 5485 */ 5486 5487 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 5488 * @brief Force or release APB2 peripheral reset. 5489 * @{ 5490 */ 5491 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 5492 #if defined(STM32F413xx) || defined(STM32F423xx) 5493 #define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST)) 5494 #define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART10RST)) 5495 #endif /* STM32F413xx || STM32F423xx */ 5496 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 5497 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 5498 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 5499 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 5500 #if defined(STM32F413xx) || defined(STM32F423xx) 5501 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 5502 #endif /* STM32F413xx || STM32F423xx */ 5503 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) 5504 #if defined(STM32F413xx) || defined(STM32F423xx) 5505 #define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM2RST)) 5506 #endif /* STM32F413xx || STM32F423xx */ 5507 5508 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 5509 #if defined(STM32F413xx) || defined(STM32F423xx) 5510 #define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST)) 5511 #define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST)) 5512 #endif /* STM32F413xx || STM32F423xx */ 5513 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 5514 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 5515 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 5516 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 5517 #if defined(STM32F413xx) || defined(STM32F423xx) 5518 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 5519 #endif /* STM32F413xx || STM32F423xx */ 5520 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) 5521 #if defined(STM32F413xx) || defined(STM32F423xx) 5522 #define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST)) 5523 #endif /* STM32F413xx || STM32F423xx */ 5524 /** 5525 * @} 5526 */ 5527 5528 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 5529 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 5530 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5531 * power consumption. 5532 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5533 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5534 * @{ 5535 */ 5536 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 5537 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 5538 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 5539 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 5540 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 5541 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 5542 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 5543 #if defined(STM32F413xx) || defined(STM32F423xx) 5544 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 5545 #endif /* STM32F413xx || STM32F423xx */ 5546 5547 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 5548 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 5549 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 5550 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 5551 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 5552 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 5553 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 5554 #if defined(STM32F413xx) || defined(STM32F423xx) 5555 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 5556 #endif /* STM32F413xx || STM32F423xx */ 5557 /** 5558 * @} 5559 */ 5560 5561 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 5562 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 5563 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5564 * power consumption. 5565 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 5566 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5567 * @{ 5568 */ 5569 #if defined(STM32F423xx) 5570 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) 5571 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) 5572 #endif /* STM32F423xx */ 5573 5574 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 5575 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 5576 5577 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 5578 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 5579 /** 5580 * @} 5581 */ 5582 5583 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 5584 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 5585 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5586 * power consumption. 5587 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5588 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5589 * @{ 5590 */ 5591 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 5592 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) 5593 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 5594 5595 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) 5596 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 5597 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 5598 5599 /** 5600 * @} 5601 */ 5602 5603 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 5604 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 5605 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5606 * power consumption. 5607 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5608 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5609 * @{ 5610 */ 5611 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 5612 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 5613 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 5614 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 5615 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 5616 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 5617 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 5618 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 5619 #if defined(STM32F413xx) || defined(STM32F423xx) 5620 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) 5621 #endif /* STM32F413xx || STM32F423xx */ 5622 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) 5623 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 5624 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 5625 #if defined(STM32F413xx) || defined(STM32F423xx) 5626 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 5627 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 5628 #endif /* STM32F413xx || STM32F423xx */ 5629 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 5630 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) 5631 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 5632 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 5633 #if defined(STM32F413xx) || defined(STM32F423xx) 5634 #define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) 5635 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 5636 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) 5637 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) 5638 #endif /* STM32F413xx || STM32F423xx */ 5639 5640 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 5641 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 5642 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 5643 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 5644 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 5645 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 5646 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 5647 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 5648 #if defined(STM32F413xx) || defined(STM32F423xx) 5649 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) 5650 #endif /* STM32F413xx || STM32F423xx */ 5651 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) 5652 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 5653 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 5654 #if defined(STM32F413xx) || defined(STM32F423xx) 5655 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 5656 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 5657 #endif /* STM32F413xx || STM32F423xx */ 5658 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 5659 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) 5660 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 5661 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 5662 #if defined(STM32F413xx) || defined(STM32F423xx) 5663 #define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) 5664 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 5665 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) 5666 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) 5667 #endif /* STM32F413xx || STM32F423xx */ 5668 /** 5669 * @} 5670 */ 5671 5672 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 5673 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 5674 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5675 * power consumption. 5676 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5677 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5678 * @{ 5679 */ 5680 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 5681 #if defined(STM32F413xx) || defined(STM32F423xx) 5682 #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART9LPEN)) 5683 #define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART10LPEN)) 5684 #endif /* STM32F413xx || STM32F423xx */ 5685 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 5686 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 5687 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) 5688 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 5689 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 5690 #if defined(STM32F413xx) || defined(STM32F423xx) 5691 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 5692 #endif /* STM32F413xx || STM32F423xx */ 5693 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) 5694 #if defined(STM32F413xx) || defined(STM32F423xx) 5695 #define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM2LPEN)) 5696 #endif /* STM32F413xx || STM32F423xx */ 5697 5698 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 5699 #if defined(STM32F413xx) || defined(STM32F423xx) 5700 #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN)) 5701 #define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN)) 5702 #endif /* STM32F413xx || STM32F423xx */ 5703 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 5704 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 5705 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) 5706 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 5707 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 5708 #if defined(STM32F413xx) || defined(STM32F423xx) 5709 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 5710 #endif /* STM32F413xx || STM32F423xx */ 5711 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) 5712 #if defined(STM32F413xx) || defined(STM32F423xx) 5713 #define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN)) 5714 #endif /* STM32F413xx || STM32F423xx */ 5715 /** 5716 * @} 5717 */ 5718 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 5719 /*----------------------------------------------------------------------------*/ 5720 5721 /*------------------------------- PLL Configuration --------------------------*/ 5722 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\ 5723 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 5724 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 5725 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. 5726 * @note This function must be used only when the main PLL is disabled. 5727 * @param __RCC_PLLSource__ specifies the PLL entry clock source. 5728 * This parameter can be one of the following values: 5729 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 5730 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 5731 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. 5732 * @param __PLLM__ specifies the division factor for PLL VCO input clock 5733 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5734 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 5735 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5736 * of 2 MHz to limit PLL jitter. 5737 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock 5738 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5739 * @note You have to set the PLLN parameter correctly to ensure that the VCO 5740 * output frequency is between 100 and 432 MHz. 5741 * 5742 * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) 5743 * This parameter must be a number in the range {2, 4, 6, or 8}. 5744 * 5745 * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks 5746 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 5747 * @note If the USB OTG FS is used in your application, you have to set the 5748 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 5749 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work 5750 * correctly. 5751 * 5752 * @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. 5753 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5754 * @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/ 5755 STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. 5756 * 5757 */ 5758 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ 5759 (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ 5760 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 5761 ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ 5762 ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ 5763 ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) 5764 #else 5765 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. 5766 * @note This function must be used only when the main PLL is disabled. 5767 * @param __RCC_PLLSource__ specifies the PLL entry clock source. 5768 * This parameter can be one of the following values: 5769 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 5770 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 5771 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. 5772 * @param __PLLM__ specifies the division factor for PLL VCO input clock 5773 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5774 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 5775 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5776 * of 2 MHz to limit PLL jitter. 5777 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock 5778 * This parameter must be a number between Min_Data = 50 and Max_Data = 432 5779 * Except for STM32F411xE devices where Min_Data = 192. 5780 * @note You have to set the PLLN parameter correctly to ensure that the VCO 5781 * output frequency is between 100 and 432 MHz, Except for STM32F411xE devices 5782 * where frequency is between 192 and 432 MHz. 5783 * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) 5784 * This parameter must be a number in the range {2, 4, 6, or 8}. 5785 * 5786 * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks 5787 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 5788 * @note If the USB OTG FS is used in your application, you have to set the 5789 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 5790 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work 5791 * correctly. 5792 * 5793 */ 5794 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ 5795 (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \ 5796 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 5797 ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ 5798 ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) 5799 #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 5800 /*----------------------------------------------------------------------------*/ 5801 5802 /*----------------------------PLLI2S Configuration ---------------------------*/ 5803 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 5804 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 5805 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 5806 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 5807 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 5808 5809 /** @brief Macros to enable or disable the PLLI2S. 5810 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. 5811 */ 5812 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) 5813 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) 5814 5815 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 5816 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 5817 STM32F412Rx || STM32F412Cx */ 5818 #if defined(STM32F446xx) 5819 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 5820 * @note This macro must be used only when the PLLI2S is disabled. 5821 * @note PLLI2S clock source is common with the main PLL (configured in 5822 * HAL_RCC_ClockConfig() API). 5823 * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock 5824 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5825 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input 5826 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5827 * of 1 MHz to limit PLLI2S jitter. 5828 * 5829 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 5830 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5831 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 5832 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 5833 * 5834 * @param __PLLI2SP__ specifies division factor for SPDIFRX Clock. 5835 * This parameter must be a number in the range {2, 4, 6, or 8}. 5836 * @note the PLLI2SP parameter is only available with STM32F446xx Devices 5837 * 5838 * @param __PLLI2SR__ specifies the division factor for I2S clock 5839 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5840 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 5841 * on the I2S clock frequency. 5842 * 5843 * @param __PLLI2SQ__ specifies the division factor for SAI clock 5844 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 5845 */ 5846 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ 5847 (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ 5848 ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 5849 ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ 5850 ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ 5851 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 5852 #elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 5853 defined(STM32F413xx) || defined(STM32F423xx) 5854 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 5855 * @note This macro must be used only when the PLLI2S is disabled. 5856 * @note PLLI2S clock source is common with the main PLL (configured in 5857 * HAL_RCC_ClockConfig() API). 5858 * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock 5859 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5860 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input 5861 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5862 * of 1 MHz to limit PLLI2S jitter. 5863 * 5864 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 5865 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5866 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 5867 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 5868 * 5869 * @param __PLLI2SR__ specifies the division factor for I2S clock 5870 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5871 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 5872 * on the I2S clock frequency. 5873 * 5874 * @param __PLLI2SQ__ specifies the division factor for SAI clock 5875 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 5876 */ 5877 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ 5878 (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ 5879 ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 5880 ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ 5881 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 5882 #else 5883 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 5884 * @note This macro must be used only when the PLLI2S is disabled. 5885 * @note PLLI2S clock source is common with the main PLL (configured in 5886 * HAL_RCC_ClockConfig() API). 5887 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 5888 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5889 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 5890 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 5891 * 5892 * @param __PLLI2SR__ specifies the division factor for I2S clock 5893 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5894 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 5895 * on the I2S clock frequency. 5896 * 5897 */ 5898 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \ 5899 (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 5900 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 5901 #endif /* STM32F446xx */ 5902 5903 #if defined(STM32F411xE) 5904 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 5905 * @note This macro must be used only when the PLLI2S is disabled. 5906 * @note This macro must be used only when the PLLI2S is disabled. 5907 * @note PLLI2S clock source is common with the main PLL (configured in 5908 * HAL_RCC_ClockConfig() API). 5909 * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock 5910 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5911 * @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices 5912 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input 5913 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5914 * of 2 MHz to limit PLLI2S jitter. 5915 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 5916 * This parameter must be a number between Min_Data = 192 and Max_Data = 432. 5917 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 5918 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. 5919 * @param __PLLI2SR__ specifies the division factor for I2S clock 5920 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5921 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 5922 * on the I2S clock frequency. 5923 */ 5924 #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ 5925 ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 5926 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 5927 #endif /* STM32F411xE */ 5928 5929 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 5930 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors. 5931 * @note This macro must be used only when the PLLI2S is disabled. 5932 * @note PLLI2S clock source is common with the main PLL (configured in 5933 * HAL_RCC_ClockConfig() API) 5934 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. 5935 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5936 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 5937 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 5938 * @param __PLLI2SQ__ specifies the division factor for SAI1 clock. 5939 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 5940 * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx 5941 * Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro 5942 * @param __PLLI2SR__ specifies the division factor for I2S clock 5943 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5944 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 5945 * on the I2S clock frequency. 5946 */ 5947 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) |\ 5948 ((__PLLI2SQ__) << 24U) |\ 5949 ((__PLLI2SR__) << 28U)) 5950 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 5951 /*----------------------------------------------------------------------------*/ 5952 5953 /*------------------------------ PLLSAI Configuration ------------------------*/ 5954 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 5955 /** @brief Macros to Enable or Disable the PLLISAI. 5956 * @note The PLLSAI is only available with STM32F429x/439x Devices. 5957 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. 5958 */ 5959 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE) 5960 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE) 5961 5962 #if defined(STM32F446xx) 5963 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 5964 * 5965 * @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock 5966 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5967 * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input 5968 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5969 * of 1 MHz to limit PLLI2S jitter. 5970 * @note The PLLSAIM parameter is only used with STM32F446xx Devices 5971 * 5972 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 5973 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5974 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 5975 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 5976 * 5977 * @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks. 5978 * This parameter must be a number in the range {2, 4, 6, or 8}. 5979 * @note the PLLSAIP parameter is only available with STM32F446xx Devices 5980 * 5981 * @param __PLLSAIQ__ specifies the division factor for SAI clock 5982 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 5983 * 5984 * @param __PLLSAIR__ specifies the division factor for LTDC clock 5985 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5986 * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices 5987 */ 5988 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ 5989 (RCC->PLLSAICFGR = ((__PLLSAIM__) | \ 5990 ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ 5991 ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \ 5992 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))) 5993 #endif /* STM32F446xx */ 5994 5995 #if defined(STM32F469xx) || defined(STM32F479xx) 5996 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 5997 * 5998 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 5999 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 6000 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 6001 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 6002 * 6003 * @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks. 6004 * This parameter must be a number in the range {2, 4, 6, or 8}. 6005 * 6006 * @param __PLLSAIQ__ specifies the division factor for SAI clock 6007 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 6008 * 6009 * @param __PLLSAIR__ specifies the division factor for LTDC clock 6010 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 6011 */ 6012 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ 6013 (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ 6014 ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ 6015 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ 6016 ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) 6017 #endif /* STM32F469xx || STM32F479xx */ 6018 6019 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 6020 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 6021 * 6022 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 6023 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 6024 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 6025 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 6026 * 6027 * @param __PLLSAIQ__ specifies the division factor for SAI clock 6028 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 6029 * 6030 * @param __PLLSAIR__ specifies the division factor for LTDC clock 6031 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 6032 * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices 6033 */ 6034 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \ 6035 (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ 6036 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) | \ 6037 ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) 6038 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 6039 6040 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 6041 /*----------------------------------------------------------------------------*/ 6042 6043 /*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/ 6044 #if defined(STM32F413xx) || defined(STM32F423xx) 6045 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. 6046 * @note This function must be called before enabling the PLLI2S. 6047 * @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock. 6048 * This parameter must be a number between 1 and 32. 6049 * SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__ 6050 */ 6051 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U)) 6052 6053 /** @brief Macro to configure the SAI clock Divider coming from PLL. 6054 * @param __PLLDivR__ specifies the PLL division factor for SAI1 clock. 6055 * This parameter must be a number between 1 and 32. 6056 * SAI1 clock frequency = f(PLLR) / __PLLDivR__ 6057 */ 6058 #define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U)) 6059 #endif /* STM32F413xx || STM32F423xx */ 6060 6061 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ 6062 defined(STM32F469xx) || defined(STM32F479xx) 6063 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. 6064 * @note This function must be called before enabling the PLLI2S. 6065 * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock. 6066 * This parameter must be a number between 1 and 32. 6067 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ 6068 */ 6069 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U)) 6070 6071 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI. 6072 * @note This function must be called before enabling the PLLSAI. 6073 * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . 6074 * This parameter must be a number between Min_Data = 1 and Max_Data = 32. 6075 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ 6076 */ 6077 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U)) 6078 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 6079 6080 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 6081 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. 6082 * 6083 * @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices. 6084 * @note This function must be called before enabling the PLLSAI. 6085 * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . 6086 * This parameter must be a number between Min_Data = 2 and Max_Data = 16. 6087 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ 6088 */ 6089 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__))) 6090 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 6091 /*----------------------------------------------------------------------------*/ 6092 6093 /*------------------------- Peripheral Clock selection -----------------------*/ 6094 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ 6095 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 6096 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\ 6097 defined(STM32F479xx) 6098 /** @brief Macro to configure the I2S clock source (I2SCLK). 6099 * @note This function must be called before enabling the I2S APB clock. 6100 * @param __SOURCE__ specifies the I2S clock source. 6101 * This parameter can be one of the following values: 6102 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. 6103 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin 6104 * used as I2S clock source. 6105 */ 6106 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__)) 6107 6108 6109 /** @brief Macro to get the I2S clock source (I2SCLK). 6110 * @retval The clock source can be one of the following values: 6111 * @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. 6112 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin 6113 * used as I2S clock source 6114 */ 6115 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) 6116 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */ 6117 6118 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 6119 6120 /** @brief Macro to configure SAI1BlockA clock source selection. 6121 * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. 6122 * @note This function must be called before enabling PLLSAI, PLLI2S and 6123 * the SAI clock. 6124 * @param __SOURCE__ specifies the SAI Block A clock source. 6125 * This parameter can be one of the following values: 6126 * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 6127 * as SAI1 Block A clock. 6128 * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 6129 * as SAI1 Block A clock. 6130 * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin 6131 * used as SAI1 Block A clock. 6132 */ 6133 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) 6134 6135 /** @brief Macro to configure SAI1BlockB clock source selection. 6136 * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. 6137 * @note This function must be called before enabling PLLSAI, PLLI2S and 6138 * the SAI clock. 6139 * @param __SOURCE__ specifies the SAI Block B clock source. 6140 * This parameter can be one of the following values: 6141 * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 6142 * as SAI1 Block B clock. 6143 * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 6144 * as SAI1 Block B clock. 6145 * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin 6146 * used as SAI1 Block B clock. 6147 */ 6148 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) 6149 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 6150 6151 #if defined(STM32F446xx) 6152 /** @brief Macro to configure SAI1 clock source selection. 6153 * @note This configuration is only available with STM32F446xx Devices. 6154 * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and 6155 * the SAI clock. 6156 * @param __SOURCE__ specifies the SAI1 clock source. 6157 * This parameter can be one of the following values: 6158 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 6159 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. 6160 * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. 6161 * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. 6162 */ 6163 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__))) 6164 6165 /** @brief Macro to Get SAI1 clock source selection. 6166 * @note This configuration is only available with STM32F446xx Devices. 6167 * @retval The clock source can be one of the following values: 6168 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 6169 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. 6170 * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. 6171 * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. 6172 */ 6173 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC)) 6174 6175 /** @brief Macro to configure SAI2 clock source selection. 6176 * @note This configuration is only available with STM32F446xx Devices. 6177 * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and 6178 * the SAI clock. 6179 * @param __SOURCE__ specifies the SAI2 clock source. 6180 * This parameter can be one of the following values: 6181 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 6182 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. 6183 * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. 6184 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. 6185 */ 6186 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__))) 6187 6188 /** @brief Macro to Get SAI2 clock source selection. 6189 * @note This configuration is only available with STM32F446xx Devices. 6190 * @retval The clock source can be one of the following values: 6191 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 6192 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. 6193 * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. 6194 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. 6195 */ 6196 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC)) 6197 6198 /** @brief Macro to configure I2S APB1 clock source selection. 6199 * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. 6200 * @param __SOURCE__ specifies the I2S APB1 clock source. 6201 * This parameter can be one of the following values: 6202 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 6203 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. 6204 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. 6205 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6206 */ 6207 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) 6208 6209 /** @brief Macro to Get I2S APB1 clock source selection. 6210 * @retval The clock source can be one of the following values: 6211 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 6212 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. 6213 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. 6214 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6215 */ 6216 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) 6217 6218 /** @brief Macro to configure I2S APB2 clock source selection. 6219 * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. 6220 * @param __SOURCE__ specifies the SAI Block A clock source. 6221 * This parameter can be one of the following values: 6222 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 6223 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. 6224 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. 6225 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6226 */ 6227 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) 6228 6229 /** @brief Macro to Get I2S APB2 clock source selection. 6230 * @retval The clock source can be one of the following values: 6231 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 6232 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. 6233 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. 6234 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6235 */ 6236 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) 6237 6238 /** @brief Macro to configure the CEC clock. 6239 * @param __SOURCE__ specifies the CEC clock source. 6240 * This parameter can be one of the following values: 6241 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock 6242 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 6243 */ 6244 #define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__))) 6245 6246 /** @brief Macro to Get the CEC clock. 6247 * @retval The clock source can be one of the following values: 6248 * @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock 6249 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 6250 */ 6251 #define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)) 6252 6253 /** @brief Macro to configure the FMPI2C1 clock. 6254 * @param __SOURCE__ specifies the FMPI2C1 clock source. 6255 * This parameter can be one of the following values: 6256 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6257 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6258 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6259 */ 6260 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) 6261 6262 /** @brief Macro to Get the FMPI2C1 clock. 6263 * @retval The clock source can be one of the following values: 6264 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6265 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6266 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6267 */ 6268 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) 6269 6270 /** @brief Macro to configure the CLK48 clock. 6271 * @param __SOURCE__ specifies the CLK48 clock source. 6272 * This parameter can be one of the following values: 6273 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6274 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 6275 */ 6276 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) 6277 6278 /** @brief Macro to Get the CLK48 clock. 6279 * @retval The clock source can be one of the following values: 6280 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6281 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 6282 */ 6283 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) 6284 6285 /** @brief Macro to configure the SDIO clock. 6286 * @param __SOURCE__ specifies the SDIO clock source. 6287 * This parameter can be one of the following values: 6288 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6289 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6290 */ 6291 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) 6292 6293 /** @brief Macro to Get the SDIO clock. 6294 * @retval The clock source can be one of the following values: 6295 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6296 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6297 */ 6298 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) 6299 6300 /** @brief Macro to configure the SPDIFRX clock. 6301 * @param __SOURCE__ specifies the SPDIFRX clock source. 6302 * This parameter can be one of the following values: 6303 * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. 6304 * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 6305 */ 6306 #define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__))) 6307 6308 /** @brief Macro to Get the SPDIFRX clock. 6309 * @retval The clock source can be one of the following values: 6310 * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. 6311 * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 6312 */ 6313 #define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL)) 6314 #endif /* STM32F446xx */ 6315 6316 #if defined(STM32F469xx) || defined(STM32F479xx) 6317 6318 /** @brief Macro to configure the CLK48 clock. 6319 * @param __SOURCE__ specifies the CLK48 clock source. 6320 * This parameter can be one of the following values: 6321 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6322 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 6323 */ 6324 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__))) 6325 6326 /** @brief Macro to Get the CLK48 clock. 6327 * @retval The clock source can be one of the following values: 6328 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6329 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 6330 */ 6331 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL)) 6332 6333 /** @brief Macro to configure the SDIO clock. 6334 * @param __SOURCE__ specifies the SDIO clock source. 6335 * This parameter can be one of the following values: 6336 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6337 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6338 */ 6339 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__))) 6340 6341 /** @brief Macro to Get the SDIO clock. 6342 * @retval The clock source can be one of the following values: 6343 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6344 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6345 */ 6346 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL)) 6347 6348 /** @brief Macro to configure the DSI clock. 6349 * @param __SOURCE__ specifies the DSI clock source. 6350 * This parameter can be one of the following values: 6351 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 6352 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 6353 */ 6354 #define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__))) 6355 6356 /** @brief Macro to Get the DSI clock. 6357 * @retval The clock source can be one of the following values: 6358 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 6359 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 6360 */ 6361 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL)) 6362 6363 #endif /* STM32F469xx || STM32F479xx */ 6364 6365 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 6366 defined(STM32F413xx) || defined(STM32F423xx) 6367 /** @brief Macro to configure the DFSDM1 clock. 6368 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. 6369 * This parameter can be one of the following values: 6370 * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 6371 * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock. 6372 * @retval None 6373 */ 6374 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__)) 6375 6376 /** @brief Macro to get the DFSDM1 clock source. 6377 * @retval The clock source can be one of the following values: 6378 * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 6379 * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock. 6380 */ 6381 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) 6382 6383 /** @brief Macro to configure DFSDM1 Audio clock source selection. 6384 * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ 6385 STM32F413xx/STM32F423xx Devices. 6386 * @param __SOURCE__ specifies the DFSDM1 Audio clock source. 6387 * This parameter can be one of the following values: 6388 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 6389 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 6390 */ 6391 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__))) 6392 6393 /** @brief Macro to Get DFSDM1 Audio clock source selection. 6394 * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ 6395 STM32F413xx/STM32F423xx Devices. 6396 * @retval The clock source can be one of the following values: 6397 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 6398 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 6399 */ 6400 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL)) 6401 6402 #if defined(STM32F413xx) || defined(STM32F423xx) 6403 /** @brief Macro to configure the DFSDM2 clock. 6404 * @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source. 6405 * This parameter can be one of the following values: 6406 * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 6407 * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock. 6408 * @retval None 6409 */ 6410 #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__)) 6411 6412 /** @brief Macro to get the DFSDM2 clock source. 6413 * @retval The clock source can be one of the following values: 6414 * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 6415 * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock. 6416 */ 6417 #define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) 6418 6419 /** @brief Macro to configure DFSDM1 Audio clock source selection. 6420 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 6421 * @param __SOURCE__ specifies the DFSDM2 Audio clock source. 6422 * This parameter can be one of the following values: 6423 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 6424 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 6425 */ 6426 #define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__))) 6427 6428 /** @brief Macro to Get DFSDM2 Audio clock source selection. 6429 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 6430 * @retval The clock source can be one of the following values: 6431 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 6432 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 6433 */ 6434 #define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL)) 6435 6436 /** @brief Macro to configure SAI1BlockA clock source selection. 6437 * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. 6438 * @note This function must be called before enabling PLLSAI, PLLI2S and 6439 * the SAI clock. 6440 * @param __SOURCE__ specifies the SAI Block A clock source. 6441 * This parameter can be one of the following values: 6442 * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 6443 * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. 6444 * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 6445 * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6446 */ 6447 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) 6448 6449 /** @brief Macro to Get SAI1 BlockA clock source selection. 6450 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 6451 * @retval The clock source can be one of the following values: 6452 * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 6453 * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. 6454 * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 6455 * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6456 */ 6457 #define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC)) 6458 6459 /** @brief Macro to configure SAI1 BlockB clock source selection. 6460 * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. 6461 * @note This function must be called before enabling PLLSAI, PLLI2S and 6462 * the SAI clock. 6463 * @param __SOURCE__ specifies the SAI Block B clock source. 6464 * This parameter can be one of the following values: 6465 * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 6466 * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. 6467 * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 6468 * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6469 */ 6470 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) 6471 6472 /** @brief Macro to Get SAI1 BlockB clock source selection. 6473 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 6474 * @retval The clock source can be one of the following values: 6475 * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 6476 * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. 6477 * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 6478 * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6479 */ 6480 #define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC)) 6481 6482 /** @brief Macro to configure the LPTIM1 clock. 6483 * @param __SOURCE__ specifies the LPTIM1 clock source. 6484 * This parameter can be one of the following values: 6485 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock 6486 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 6487 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 6488 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 6489 */ 6490 #define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) 6491 6492 /** @brief Macro to Get the LPTIM1 clock. 6493 * @retval The clock source can be one of the following values: 6494 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock 6495 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 6496 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 6497 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 6498 */ 6499 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) 6500 #endif /* STM32F413xx || STM32F423xx */ 6501 6502 /** @brief Macro to configure I2S APB1 clock source selection. 6503 * @param __SOURCE__ specifies the I2S APB1 clock source. 6504 * This parameter can be one of the following values: 6505 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 6506 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6507 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 6508 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6509 */ 6510 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) 6511 6512 /** @brief Macro to Get I2S APB1 clock source selection. 6513 * @retval The clock source can be one of the following values: 6514 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 6515 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6516 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 6517 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6518 */ 6519 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) 6520 6521 /** @brief Macro to configure I2S APB2 clock source selection. 6522 * @param __SOURCE__ specifies the I2S APB2 clock source. 6523 * This parameter can be one of the following values: 6524 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 6525 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6526 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 6527 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6528 */ 6529 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) 6530 6531 /** @brief Macro to Get I2S APB2 clock source selection. 6532 * @retval The clock source can be one of the following values: 6533 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 6534 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6535 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 6536 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6537 */ 6538 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) 6539 6540 /** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK). 6541 * @note This macro must be called before enabling the I2S APB clock. 6542 * @param __SOURCE__ specifies the I2S clock source. 6543 * This parameter can be one of the following values: 6544 * @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6545 * @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin 6546 * used as I2S clock source. 6547 */ 6548 #define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__)) 6549 6550 /** @brief Macro to configure the FMPI2C1 clock. 6551 * @param __SOURCE__ specifies the FMPI2C1 clock source. 6552 * This parameter can be one of the following values: 6553 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6554 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6555 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6556 */ 6557 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) 6558 6559 /** @brief Macro to Get the FMPI2C1 clock. 6560 * @retval The clock source can be one of the following values: 6561 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6562 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6563 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6564 */ 6565 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) 6566 6567 /** @brief Macro to configure the CLK48 clock. 6568 * @param __SOURCE__ specifies the CLK48 clock source. 6569 * This parameter can be one of the following values: 6570 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6571 * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock. 6572 */ 6573 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) 6574 6575 /** @brief Macro to Get the CLK48 clock. 6576 * @retval The clock source can be one of the following values: 6577 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6578 * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock 6579 */ 6580 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) 6581 6582 /** @brief Macro to configure the SDIO clock. 6583 * @param __SOURCE__ specifies the SDIO clock source. 6584 * This parameter can be one of the following values: 6585 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6586 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6587 */ 6588 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) 6589 6590 /** @brief Macro to Get the SDIO clock. 6591 * @retval The clock source can be one of the following values: 6592 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6593 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6594 */ 6595 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) 6596 6597 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 6598 6599 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 6600 /** @brief Macro to configure I2S clock source selection. 6601 * @param __SOURCE__ specifies the I2S clock source. 6602 * This parameter can be one of the following values: 6603 * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. 6604 * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6605 * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. 6606 */ 6607 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__))) 6608 6609 /** @brief Macro to Get I2S clock source selection. 6610 * @retval The clock source can be one of the following values: 6611 * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. 6612 * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6613 * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. 6614 */ 6615 #define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC)) 6616 6617 /** @brief Macro to configure the FMPI2C1 clock. 6618 * @param __SOURCE__ specifies the FMPI2C1 clock source. 6619 * This parameter can be one of the following values: 6620 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6621 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6622 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6623 */ 6624 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) 6625 6626 /** @brief Macro to Get the FMPI2C1 clock. 6627 * @retval The clock source can be one of the following values: 6628 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6629 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6630 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6631 */ 6632 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) 6633 6634 /** @brief Macro to configure the LPTIM1 clock. 6635 * @param __SOURCE__ specifies the LPTIM1 clock source. 6636 * This parameter can be one of the following values: 6637 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock 6638 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 6639 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 6640 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 6641 */ 6642 #define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) 6643 6644 /** @brief Macro to Get the LPTIM1 clock. 6645 * @retval The clock source can be one of the following values: 6646 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock 6647 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 6648 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 6649 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 6650 */ 6651 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) 6652 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 6653 6654 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 6655 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ 6656 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 6657 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ 6658 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 6659 /** @brief Macro to configure the Timers clocks prescalers 6660 * @note This feature is only available with STM32F429x/439x Devices. 6661 * @param __PRESC__ specifies the Timers clocks prescalers selection 6662 * This parameter can be one of the following values: 6663 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is 6664 * equal to HPRE if PPREx is corresponding to division by 1 or 2, 6665 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to 6666 * division by 4 or more. 6667 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 6668 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, 6669 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding 6670 * to division by 8 or more. 6671 */ 6672 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__)) 6673 6674 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\ 6675 STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx ||\ 6676 STM32F423xx */ 6677 6678 /*----------------------------------------------------------------------------*/ 6679 6680 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 6681 /** @brief Enable PLLSAI_RDY interrupt. 6682 */ 6683 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) 6684 6685 /** @brief Disable PLLSAI_RDY interrupt. 6686 */ 6687 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) 6688 6689 /** @brief Clear the PLLSAI RDY interrupt pending bits. 6690 */ 6691 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) 6692 6693 /** @brief Check the PLLSAI RDY interrupt has occurred or not. 6694 * @retval The new state (TRUE or FALSE). 6695 */ 6696 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) 6697 6698 /** @brief Check PLLSAI RDY flag is set or not. 6699 * @retval The new state (TRUE or FALSE). 6700 */ 6701 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) 6702 6703 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 6704 6705 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 6706 /** @brief Macros to enable or disable the RCC MCO1 feature. 6707 */ 6708 #define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE) 6709 #define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE) 6710 6711 /** @brief Macros to enable or disable the RCC MCO2 feature. 6712 */ 6713 #define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE) 6714 #define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE) 6715 6716 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 6717 6718 /** 6719 * @} 6720 */ 6721 6722 /* Exported functions --------------------------------------------------------*/ 6723 /** @addtogroup RCCEx_Exported_Functions 6724 * @{ 6725 */ 6726 6727 /** @addtogroup RCCEx_Exported_Functions_Group1 6728 * @{ 6729 */ 6730 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 6731 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 6732 6733 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 6734 6735 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ 6736 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ 6737 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ 6738 defined(STM32F423xx) 6739 void HAL_RCCEx_SelectLSEMode(uint8_t Mode); 6740 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 6741 #if defined(RCC_PLLI2S_SUPPORT) 6742 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); 6743 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); 6744 #endif /* RCC_PLLI2S_SUPPORT */ 6745 #if defined(RCC_PLLSAI_SUPPORT) 6746 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); 6747 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); 6748 #endif /* RCC_PLLSAI_SUPPORT */ 6749 /** 6750 * @} 6751 */ 6752 6753 /** 6754 * @} 6755 */ 6756 /* Private types -------------------------------------------------------------*/ 6757 /* Private variables ---------------------------------------------------------*/ 6758 /* Private constants ---------------------------------------------------------*/ 6759 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants 6760 * @{ 6761 */ 6762 6763 /** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion 6764 * @brief RCC registers bit address in the alias region 6765 * @{ 6766 */ 6767 /* --- CR Register ---*/ 6768 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 6769 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 6770 /* Alias word address of PLLSAION bit */ 6771 #define RCC_PLLSAION_BIT_NUMBER 0x1CU 6772 #define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U)) 6773 6774 #define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ 6775 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 6776 6777 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 6778 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 6779 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 6780 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 6781 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 6782 /* Alias word address of PLLI2SON bit */ 6783 #define RCC_PLLI2SON_BIT_NUMBER 0x1AU 6784 #define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U)) 6785 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 6786 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 6787 STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 6788 6789 /* --- DCKCFGR Register ---*/ 6790 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 6791 defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\ 6792 defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 6793 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ 6794 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 6795 /* Alias word address of TIMPRE bit */ 6796 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU) 6797 #define RCC_TIMPRE_BIT_NUMBER 0x18U 6798 #define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U)) 6799 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\ 6800 STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ 6801 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 6802 6803 /* --- CFGR Register ---*/ 6804 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U) 6805 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 6806 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 6807 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 6808 defined(STM32F469xx) || defined(STM32F479xx) 6809 /* Alias word address of I2SSRC bit */ 6810 #define RCC_I2SSRC_BIT_NUMBER 0x17U 6811 #define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U)) 6812 6813 #define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ 6814 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 6815 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ 6816 6817 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 6818 defined(STM32F413xx) || defined(STM32F423xx) 6819 /* --- PLLI2SCFGR Register ---*/ 6820 #define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U) 6821 /* Alias word address of PLLI2SSRC bit */ 6822 #define RCC_PLLI2SSRC_BIT_NUMBER 0x16U 6823 #define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U)) 6824 6825 #define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ 6826 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx | STM32F423xx */ 6827 6828 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 6829 /* Alias word address of MCO1EN bit */ 6830 #define RCC_MCO1EN_BIT_NUMBER 0x8U 6831 #define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U)) 6832 6833 /* Alias word address of MCO2EN bit */ 6834 #define RCC_MCO2EN_BIT_NUMBER 0x9U 6835 #define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U)) 6836 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 6837 6838 #define PLL_TIMEOUT_VALUE 2U /* 2 ms */ 6839 /** 6840 * @} 6841 */ 6842 6843 /** 6844 * @} 6845 */ 6846 6847 /* Private macros ------------------------------------------------------------*/ 6848 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros 6849 * @{ 6850 */ 6851 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters 6852 * @{ 6853 */ 6854 #define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) 6855 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) 6856 6857 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 6858 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU)) 6859 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 6860 6861 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) 6862 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U)) 6863 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ 6864 6865 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 6866 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU)) 6867 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ 6868 6869 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 6870 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU)) 6871 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 6872 6873 #if defined(STM32F446xx) 6874 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU)) 6875 #endif /* STM32F446xx */ 6876 6877 #if defined(STM32F469xx) || defined(STM32F479xx) 6878 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU)) 6879 #endif /* STM32F469xx || STM32F479xx */ 6880 6881 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) 6882 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU)) 6883 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 6884 6885 #if defined(STM32F413xx) || defined(STM32F423xx) 6886 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU)) 6887 #endif /* STM32F413xx || STM32F423xx */ 6888 6889 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 6890 6891 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ 6892 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 6893 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 6894 6895 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) 6896 6897 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 6898 6899 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 6900 6901 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 6902 6903 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 6904 6905 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ 6906 ((VALUE) == RCC_PLLSAIDIVR_4) ||\ 6907 ((VALUE) == RCC_PLLSAIDIVR_8) ||\ 6908 ((VALUE) == RCC_PLLSAIDIVR_16)) 6909 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 6910 6911 #if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 6912 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 6913 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U)) 6914 6915 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ 6916 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 6917 #endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 6918 6919 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 6920 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 6921 6922 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ 6923 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 6924 6925 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ 6926 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ 6927 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) 6928 6929 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ 6930 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ 6931 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ 6932 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) 6933 6934 #define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) ||\ 6935 ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) ||\ 6936 ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) 6937 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 6938 6939 #if defined(STM32F446xx) 6940 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 6941 6942 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ 6943 ((VALUE) == RCC_PLLI2SP_DIV4) ||\ 6944 ((VALUE) == RCC_PLLI2SP_DIV6) ||\ 6945 ((VALUE) == RCC_PLLI2SP_DIV8)) 6946 6947 #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U) 6948 6949 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ 6950 ((VALUE) == RCC_PLLSAIP_DIV4) ||\ 6951 ((VALUE) == RCC_PLLSAIP_DIV6) ||\ 6952 ((VALUE) == RCC_PLLSAIP_DIV8)) 6953 6954 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\ 6955 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\ 6956 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) ||\ 6957 ((SOURCE) == RCC_SAI1CLKSOURCE_EXT)) 6958 6959 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\ 6960 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\ 6961 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) ||\ 6962 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) 6963 6964 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ 6965 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ 6966 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ 6967 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) 6968 6969 #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ 6970 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ 6971 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ 6972 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) 6973 6974 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ 6975 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ 6976 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) 6977 6978 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) ||\ 6979 ((SOURCE) == RCC_CECCLKSOURCE_LSE)) 6980 6981 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ 6982 ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) 6983 6984 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ 6985 ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) 6986 6987 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\ 6988 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) 6989 #endif /* STM32F446xx */ 6990 6991 #if defined(STM32F469xx) || defined(STM32F479xx) 6992 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 6993 6994 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ 6995 ((VALUE) == RCC_PLLSAIP_DIV4) ||\ 6996 ((VALUE) == RCC_PLLSAIP_DIV6) ||\ 6997 ((VALUE) == RCC_PLLSAIP_DIV8)) 6998 6999 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ 7000 ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) 7001 7002 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ 7003 ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) 7004 7005 #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ 7006 ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) 7007 7008 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ 7009 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 7010 #endif /* STM32F469xx || STM32F479xx */ 7011 7012 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 7013 defined(STM32F413xx) || defined(STM32F423xx) 7014 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 7015 7016 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 7017 7018 #define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \ 7019 ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT)) 7020 7021 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ 7022 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ 7023 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ 7024 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) 7025 7026 #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ 7027 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ 7028 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ 7029 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) 7030 7031 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ 7032 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ 7033 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) 7034 7035 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ 7036 ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ)) 7037 7038 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ 7039 ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) 7040 7041 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ 7042 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) 7043 7044 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) || \ 7045 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2)) 7046 7047 #if defined(STM32F413xx) || defined(STM32F423xx) 7048 #define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) || \ 7049 ((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK)) 7050 7051 #define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) || \ 7052 ((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2)) 7053 7054 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ 7055 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ 7056 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ 7057 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) 7058 7059 #define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) ||\ 7060 ((SOURCE) == RCC_SAIACLKSOURCE_EXT) ||\ 7061 ((SOURCE) == RCC_SAIACLKSOURCE_PLLR) ||\ 7062 ((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC)) 7063 7064 #define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) ||\ 7065 ((SOURCE) == RCC_SAIBCLKSOURCE_EXT) ||\ 7066 ((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) ||\ 7067 ((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC)) 7068 7069 #define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 7070 7071 #define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 7072 7073 #endif /* STM32F413xx || STM32F423xx */ 7074 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 7075 7076 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 7077 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 7078 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 7079 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 7080 defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 7081 7082 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ 7083 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) 7084 7085 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 7086 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \ 7087 STM32F412Rx */ 7088 7089 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 7090 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \ 7091 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) 7092 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 7093 /** 7094 * @} 7095 */ 7096 7097 /** 7098 * @} 7099 */ 7100 7101 /** 7102 * @} 7103 */ 7104 7105 /** 7106 * @} 7107 */ 7108 #ifdef __cplusplus 7109 } 7110 #endif 7111 7112 #endif /* __STM32F4xx_HAL_RCC_EX_H */ 7113 7114 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 7115