1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_PWM_H 10 #define HPM_PWM_H 11 12 typedef struct { 13 __RW uint32_t UNLK; /* 0x0: Shadow registers unlock register */ 14 union { 15 __RW uint32_t STA; /* 0x4: Counter start register */ 16 __RW uint32_t STA_HRPWM; /* 0x4: Counter start register */ 17 }; 18 union { 19 __RW uint32_t RLD; /* 0x8: Counter reload register */ 20 __RW uint32_t RLD_HRPWM; /* 0x8: Counter reload register */ 21 }; 22 union { 23 __RW uint32_t CMP[24]; /* 0xC - 0x68: Comparator register */ 24 __RW uint32_t CMP_HRPWM[24]; /* 0xC - 0x68: Comparator register */ 25 }; 26 __R uint8_t RESERVED0[12]; /* 0x6C - 0x77: Reserved */ 27 __RW uint32_t FRCMD; /* 0x78: Force output mode register */ 28 __RW uint32_t SHLK; /* 0x7C: Shadow registers lock register */ 29 __RW uint32_t CHCFG[24]; /* 0x80 - 0xDC: Output channel configure register */ 30 __R uint8_t RESERVED1[16]; /* 0xE0 - 0xEF: Reserved */ 31 __RW uint32_t GCR; /* 0xF0: Global control register */ 32 __RW uint32_t SHCR; /* 0xF4: Shadow register control register */ 33 __R uint8_t RESERVED2[8]; /* 0xF8 - 0xFF: Reserved */ 34 __R uint32_t CAPPOS[24]; /* 0x100 - 0x15C: Capture rising edge register */ 35 __R uint8_t RESERVED3[16]; /* 0x160 - 0x16F: Reserved */ 36 __R uint32_t CNT; /* 0x170: Counter */ 37 __R uint8_t RESERVED4[12]; /* 0x174 - 0x17F: Reserved */ 38 __R uint32_t CAPNEG[24]; /* 0x180 - 0x1DC: Capture falling edge register */ 39 __R uint8_t RESERVED5[16]; /* 0x1E0 - 0x1EF: Reserved */ 40 __R uint32_t CNTCOPY; /* 0x1F0: Counter copy */ 41 __R uint8_t RESERVED6[12]; /* 0x1F4 - 0x1FF: Reserved */ 42 __RW uint32_t PWMCFG[8]; /* 0x200 - 0x21C: PWM channel configure register */ 43 __W uint32_t SR; /* 0x220: Status register */ 44 __RW uint32_t IRQEN; /* 0x224: Interrupt request enable register */ 45 __R uint8_t RESERVED7[4]; /* 0x228 - 0x22B: Reserved */ 46 __RW uint32_t DMAEN; /* 0x22C: DMA request enable register */ 47 __RW uint32_t CMPCFG[24]; /* 0x230 - 0x28C: Comparator configure register */ 48 __R uint8_t RESERVED8[368]; /* 0x290 - 0x3FF: Reserved */ 49 __R uint32_t ANASTS[8]; /* 0x400 - 0x41C: analog status register */ 50 __W uint32_t HRPWM_CFG; /* 0x420: hrpwm config register */ 51 } PWM_Type; 52 53 54 /* Bitfield definition for register: UNLK */ 55 /* 56 * SHUNLK (RW) 57 * 58 * write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, 59 * otherwise the shadow registers can not be written. 60 */ 61 #define PWM_UNLK_SHUNLK_MASK (0xFFFFFFFFUL) 62 #define PWM_UNLK_SHUNLK_SHIFT (0U) 63 #define PWM_UNLK_SHUNLK_SET(x) (((uint32_t)(x) << PWM_UNLK_SHUNLK_SHIFT) & PWM_UNLK_SHUNLK_MASK) 64 #define PWM_UNLK_SHUNLK_GET(x) (((uint32_t)(x) & PWM_UNLK_SHUNLK_MASK) >> PWM_UNLK_SHUNLK_SHIFT) 65 66 /* Bitfield definition for register: STA */ 67 /* 68 * XSTA (RW) 69 * 70 * pwm timer counter extended start point, should back to this value after reach xrld 71 */ 72 #define PWM_STA_XSTA_MASK (0xF0000000UL) 73 #define PWM_STA_XSTA_SHIFT (28U) 74 #define PWM_STA_XSTA_SET(x) (((uint32_t)(x) << PWM_STA_XSTA_SHIFT) & PWM_STA_XSTA_MASK) 75 #define PWM_STA_XSTA_GET(x) (((uint32_t)(x) & PWM_STA_XSTA_MASK) >> PWM_STA_XSTA_SHIFT) 76 77 /* 78 * STA (RW) 79 * 80 * pwm timer counter start value 81 * sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk 82 */ 83 #define PWM_STA_STA_MASK (0xFFFFFF0UL) 84 #define PWM_STA_STA_SHIFT (4U) 85 #define PWM_STA_STA_SET(x) (((uint32_t)(x) << PWM_STA_STA_SHIFT) & PWM_STA_STA_MASK) 86 #define PWM_STA_STA_GET(x) (((uint32_t)(x) & PWM_STA_STA_MASK) >> PWM_STA_STA_SHIFT) 87 88 /* Bitfield definition for register: STA_HRPWM */ 89 /* 90 * STA (RW) 91 * 92 */ 93 #define PWM_STA_HRPWM_STA_MASK (0xFFFFFF00UL) 94 #define PWM_STA_HRPWM_STA_SHIFT (8U) 95 #define PWM_STA_HRPWM_STA_SET(x) (((uint32_t)(x) << PWM_STA_HRPWM_STA_SHIFT) & PWM_STA_HRPWM_STA_MASK) 96 #define PWM_STA_HRPWM_STA_GET(x) (((uint32_t)(x) & PWM_STA_HRPWM_STA_MASK) >> PWM_STA_HRPWM_STA_SHIFT) 97 98 /* Bitfield definition for register: RLD */ 99 /* 100 * XRLD (RW) 101 * 102 * timeout counter extended reload point, counter will reload to xsta after reach this point 103 */ 104 #define PWM_RLD_XRLD_MASK (0xF0000000UL) 105 #define PWM_RLD_XRLD_SHIFT (28U) 106 #define PWM_RLD_XRLD_SET(x) (((uint32_t)(x) << PWM_RLD_XRLD_SHIFT) & PWM_RLD_XRLD_MASK) 107 #define PWM_RLD_XRLD_GET(x) (((uint32_t)(x) & PWM_RLD_XRLD_MASK) >> PWM_RLD_XRLD_SHIFT) 108 109 /* 110 * RLD (RW) 111 * 112 * pwm timer counter reload value 113 */ 114 #define PWM_RLD_RLD_MASK (0xFFFFFF0UL) 115 #define PWM_RLD_RLD_SHIFT (4U) 116 #define PWM_RLD_RLD_SET(x) (((uint32_t)(x) << PWM_RLD_RLD_SHIFT) & PWM_RLD_RLD_MASK) 117 #define PWM_RLD_RLD_GET(x) (((uint32_t)(x) & PWM_RLD_RLD_MASK) >> PWM_RLD_RLD_SHIFT) 118 119 /* Bitfield definition for register: RLD_HRPWM */ 120 /* 121 * RLD (RW) 122 * 123 */ 124 #define PWM_RLD_HRPWM_RLD_MASK (0xFFFFFF00UL) 125 #define PWM_RLD_HRPWM_RLD_SHIFT (8U) 126 #define PWM_RLD_HRPWM_RLD_SET(x) (((uint32_t)(x) << PWM_RLD_HRPWM_RLD_SHIFT) & PWM_RLD_HRPWM_RLD_MASK) 127 #define PWM_RLD_HRPWM_RLD_GET(x) (((uint32_t)(x) & PWM_RLD_HRPWM_RLD_MASK) >> PWM_RLD_HRPWM_RLD_SHIFT) 128 129 /* 130 * RLD_HR (RW) 131 * 132 * pwm timer counter reload value at high resolution, only exist if hwpwm is enabled. 133 */ 134 #define PWM_RLD_HRPWM_RLD_HR_MASK (0xFFU) 135 #define PWM_RLD_HRPWM_RLD_HR_SHIFT (0U) 136 #define PWM_RLD_HRPWM_RLD_HR_SET(x) (((uint32_t)(x) << PWM_RLD_HRPWM_RLD_HR_SHIFT) & PWM_RLD_HRPWM_RLD_HR_MASK) 137 #define PWM_RLD_HRPWM_RLD_HR_GET(x) (((uint32_t)(x) & PWM_RLD_HRPWM_RLD_HR_MASK) >> PWM_RLD_HRPWM_RLD_HR_SHIFT) 138 139 /* Bitfield definition for register: 0 */ 140 /* 141 * XCMP (RW) 142 * 143 * extended counter compare value 144 */ 145 #define PWM_CMP_XCMP_MASK (0xF0000000UL) 146 #define PWM_CMP_XCMP_SHIFT (28U) 147 #define PWM_CMP_XCMP_SET(x) (((uint32_t)(x) << PWM_CMP_XCMP_SHIFT) & PWM_CMP_XCMP_MASK) 148 #define PWM_CMP_XCMP_GET(x) (((uint32_t)(x) & PWM_CMP_XCMP_MASK) >> PWM_CMP_XCMP_SHIFT) 149 150 /* 151 * CMP (RW) 152 * 153 * clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, 154 * and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. 155 */ 156 #define PWM_CMP_CMP_MASK (0xFFFFFF0UL) 157 #define PWM_CMP_CMP_SHIFT (4U) 158 #define PWM_CMP_CMP_SET(x) (((uint32_t)(x) << PWM_CMP_CMP_SHIFT) & PWM_CMP_CMP_MASK) 159 #define PWM_CMP_CMP_GET(x) (((uint32_t)(x) & PWM_CMP_CMP_MASK) >> PWM_CMP_CMP_SHIFT) 160 161 /* 162 * CMPHLF (RW) 163 * 164 * half clock counter compare value 165 */ 166 #define PWM_CMP_CMPHLF_MASK (0x8U) 167 #define PWM_CMP_CMPHLF_SHIFT (3U) 168 #define PWM_CMP_CMPHLF_SET(x) (((uint32_t)(x) << PWM_CMP_CMPHLF_SHIFT) & PWM_CMP_CMPHLF_MASK) 169 #define PWM_CMP_CMPHLF_GET(x) (((uint32_t)(x) & PWM_CMP_CMPHLF_MASK) >> PWM_CMP_CMPHLF_SHIFT) 170 171 /* 172 * CMPJIT (RW) 173 * 174 * jitter counter compare value 175 */ 176 #define PWM_CMP_CMPJIT_MASK (0x7U) 177 #define PWM_CMP_CMPJIT_SHIFT (0U) 178 #define PWM_CMP_CMPJIT_SET(x) (((uint32_t)(x) << PWM_CMP_CMPJIT_SHIFT) & PWM_CMP_CMPJIT_MASK) 179 #define PWM_CMP_CMPJIT_GET(x) (((uint32_t)(x) & PWM_CMP_CMPJIT_MASK) >> PWM_CMP_CMPJIT_SHIFT) 180 181 /* Bitfield definition for register: 0 */ 182 /* 183 * CMP (RW) 184 * 185 */ 186 #define PWM_CMP_HRPWM_CMP_MASK (0xFFFFFF00UL) 187 #define PWM_CMP_HRPWM_CMP_SHIFT (8U) 188 #define PWM_CMP_HRPWM_CMP_SET(x) (((uint32_t)(x) << PWM_CMP_HRPWM_CMP_SHIFT) & PWM_CMP_HRPWM_CMP_MASK) 189 #define PWM_CMP_HRPWM_CMP_GET(x) (((uint32_t)(x) & PWM_CMP_HRPWM_CMP_MASK) >> PWM_CMP_HRPWM_CMP_SHIFT) 190 191 /* 192 * CMP_HR (RW) 193 * 194 * high resolution compare value 195 */ 196 #define PWM_CMP_HRPWM_CMP_HR_MASK (0xFFU) 197 #define PWM_CMP_HRPWM_CMP_HR_SHIFT (0U) 198 #define PWM_CMP_HRPWM_CMP_HR_SET(x) (((uint32_t)(x) << PWM_CMP_HRPWM_CMP_HR_SHIFT) & PWM_CMP_HRPWM_CMP_HR_MASK) 199 #define PWM_CMP_HRPWM_CMP_HR_GET(x) (((uint32_t)(x) & PWM_CMP_HRPWM_CMP_HR_MASK) >> PWM_CMP_HRPWM_CMP_HR_SHIFT) 200 201 /* Bitfield definition for register: FRCMD */ 202 /* 203 * FRCMD (RW) 204 * 205 * 2bit for each PWM output channel (0-7); 206 * 00: force output 0 207 * 01: force output 1 208 * 10: output highz 209 * 11: no force 210 */ 211 #define PWM_FRCMD_FRCMD_MASK (0xFFFFU) 212 #define PWM_FRCMD_FRCMD_SHIFT (0U) 213 #define PWM_FRCMD_FRCMD_SET(x) (((uint32_t)(x) << PWM_FRCMD_FRCMD_SHIFT) & PWM_FRCMD_FRCMD_MASK) 214 #define PWM_FRCMD_FRCMD_GET(x) (((uint32_t)(x) & PWM_FRCMD_FRCMD_MASK) >> PWM_FRCMD_FRCMD_SHIFT) 215 216 /* Bitfield definition for register: SHLK */ 217 /* 218 * SHLK (RW) 219 * 220 * write 1 to lock all shawdow register, wirte access is not permitted 221 */ 222 #define PWM_SHLK_SHLK_MASK (0x80000000UL) 223 #define PWM_SHLK_SHLK_SHIFT (31U) 224 #define PWM_SHLK_SHLK_SET(x) (((uint32_t)(x) << PWM_SHLK_SHLK_SHIFT) & PWM_SHLK_SHLK_MASK) 225 #define PWM_SHLK_SHLK_GET(x) (((uint32_t)(x) & PWM_SHLK_SHLK_MASK) >> PWM_SHLK_SHLK_SHIFT) 226 227 /* Bitfield definition for register array: CHCFG */ 228 /* 229 * CMPSELEND (RW) 230 * 231 * assign the last comparator for this output channel 232 */ 233 #define PWM_CHCFG_CMPSELEND_MASK (0x1F000000UL) 234 #define PWM_CHCFG_CMPSELEND_SHIFT (24U) 235 #define PWM_CHCFG_CMPSELEND_SET(x) (((uint32_t)(x) << PWM_CHCFG_CMPSELEND_SHIFT) & PWM_CHCFG_CMPSELEND_MASK) 236 #define PWM_CHCFG_CMPSELEND_GET(x) (((uint32_t)(x) & PWM_CHCFG_CMPSELEND_MASK) >> PWM_CHCFG_CMPSELEND_SHIFT) 237 238 /* 239 * CMPSELBEG (RW) 240 * 241 * assign the first comparator for this output channel 242 */ 243 #define PWM_CHCFG_CMPSELBEG_MASK (0x1F0000UL) 244 #define PWM_CHCFG_CMPSELBEG_SHIFT (16U) 245 #define PWM_CHCFG_CMPSELBEG_SET(x) (((uint32_t)(x) << PWM_CHCFG_CMPSELBEG_SHIFT) & PWM_CHCFG_CMPSELBEG_MASK) 246 #define PWM_CHCFG_CMPSELBEG_GET(x) (((uint32_t)(x) & PWM_CHCFG_CMPSELBEG_MASK) >> PWM_CHCFG_CMPSELBEG_SHIFT) 247 248 /* 249 * OUTPOL (RW) 250 * 251 * output polarity, set to 1 will invert the output 252 */ 253 #define PWM_CHCFG_OUTPOL_MASK (0x2U) 254 #define PWM_CHCFG_OUTPOL_SHIFT (1U) 255 #define PWM_CHCFG_OUTPOL_SET(x) (((uint32_t)(x) << PWM_CHCFG_OUTPOL_SHIFT) & PWM_CHCFG_OUTPOL_MASK) 256 #define PWM_CHCFG_OUTPOL_GET(x) (((uint32_t)(x) & PWM_CHCFG_OUTPOL_MASK) >> PWM_CHCFG_OUTPOL_SHIFT) 257 258 /* Bitfield definition for register: GCR */ 259 /* 260 * FAULTI3EN (RW) 261 * 262 * 1- enable the internal fault input 3 263 */ 264 #define PWM_GCR_FAULTI3EN_MASK (0x80000000UL) 265 #define PWM_GCR_FAULTI3EN_SHIFT (31U) 266 #define PWM_GCR_FAULTI3EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI3EN_SHIFT) & PWM_GCR_FAULTI3EN_MASK) 267 #define PWM_GCR_FAULTI3EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI3EN_MASK) >> PWM_GCR_FAULTI3EN_SHIFT) 268 269 /* 270 * FAULTI2EN (RW) 271 * 272 * 1- enable the internal fault input 2 273 */ 274 #define PWM_GCR_FAULTI2EN_MASK (0x40000000UL) 275 #define PWM_GCR_FAULTI2EN_SHIFT (30U) 276 #define PWM_GCR_FAULTI2EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI2EN_SHIFT) & PWM_GCR_FAULTI2EN_MASK) 277 #define PWM_GCR_FAULTI2EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI2EN_MASK) >> PWM_GCR_FAULTI2EN_SHIFT) 278 279 /* 280 * FAULTI1EN (RW) 281 * 282 * 1- enable the internal fault input 1 283 */ 284 #define PWM_GCR_FAULTI1EN_MASK (0x20000000UL) 285 #define PWM_GCR_FAULTI1EN_SHIFT (29U) 286 #define PWM_GCR_FAULTI1EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI1EN_SHIFT) & PWM_GCR_FAULTI1EN_MASK) 287 #define PWM_GCR_FAULTI1EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI1EN_MASK) >> PWM_GCR_FAULTI1EN_SHIFT) 288 289 /* 290 * FAULTI0EN (RW) 291 * 292 * 1- enable the internal fault input 0 293 */ 294 #define PWM_GCR_FAULTI0EN_MASK (0x10000000UL) 295 #define PWM_GCR_FAULTI0EN_SHIFT (28U) 296 #define PWM_GCR_FAULTI0EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI0EN_SHIFT) & PWM_GCR_FAULTI0EN_MASK) 297 #define PWM_GCR_FAULTI0EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI0EN_MASK) >> PWM_GCR_FAULTI0EN_SHIFT) 298 299 /* 300 * DEBUGFAULT (RW) 301 * 302 * 1- enable debug mode output protection 303 */ 304 #define PWM_GCR_DEBUGFAULT_MASK (0x8000000UL) 305 #define PWM_GCR_DEBUGFAULT_SHIFT (27U) 306 #define PWM_GCR_DEBUGFAULT_SET(x) (((uint32_t)(x) << PWM_GCR_DEBUGFAULT_SHIFT) & PWM_GCR_DEBUGFAULT_MASK) 307 #define PWM_GCR_DEBUGFAULT_GET(x) (((uint32_t)(x) & PWM_GCR_DEBUGFAULT_MASK) >> PWM_GCR_DEBUGFAULT_SHIFT) 308 309 /* 310 * FRCPOL (RW) 311 * 312 * polarity of input pwm_force, 313 * 1- active low 314 * 0- active high 315 */ 316 #define PWM_GCR_FRCPOL_MASK (0x4000000UL) 317 #define PWM_GCR_FRCPOL_SHIFT (26U) 318 #define PWM_GCR_FRCPOL_SET(x) (((uint32_t)(x) << PWM_GCR_FRCPOL_SHIFT) & PWM_GCR_FRCPOL_MASK) 319 #define PWM_GCR_FRCPOL_GET(x) (((uint32_t)(x) & PWM_GCR_FRCPOL_MASK) >> PWM_GCR_FRCPOL_SHIFT) 320 321 /* 322 * HWSHDWEDG (RW) 323 * 324 * When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. 325 * This bit assign its which edge is used as compare shadow register hardware load event. 326 * 1- Falling edge 327 * 0- Rising edge 328 */ 329 #define PWM_GCR_HWSHDWEDG_MASK (0x1000000UL) 330 #define PWM_GCR_HWSHDWEDG_SHIFT (24U) 331 #define PWM_GCR_HWSHDWEDG_SET(x) (((uint32_t)(x) << PWM_GCR_HWSHDWEDG_SHIFT) & PWM_GCR_HWSHDWEDG_MASK) 332 #define PWM_GCR_HWSHDWEDG_GET(x) (((uint32_t)(x) & PWM_GCR_HWSHDWEDG_MASK) >> PWM_GCR_HWSHDWEDG_SHIFT) 333 334 /* 335 * CMPSHDWSEL (RW) 336 * 337 * This bitfield select one of the comparators as hardware event time to load comparator shadow registers 338 */ 339 #define PWM_GCR_CMPSHDWSEL_MASK (0xF80000UL) 340 #define PWM_GCR_CMPSHDWSEL_SHIFT (19U) 341 #define PWM_GCR_CMPSHDWSEL_SET(x) (((uint32_t)(x) << PWM_GCR_CMPSHDWSEL_SHIFT) & PWM_GCR_CMPSHDWSEL_MASK) 342 #define PWM_GCR_CMPSHDWSEL_GET(x) (((uint32_t)(x) & PWM_GCR_CMPSHDWSEL_MASK) >> PWM_GCR_CMPSHDWSEL_SHIFT) 343 344 /* 345 * FAULTRECEDG (RW) 346 * 347 * When hardware load is selected as output fault recover trigger and the selected channel is capture mode. 348 * This bit assign its effective edge of fault recover trigger. 349 * 1- Falling edge 350 * 0- Rising edge 351 */ 352 #define PWM_GCR_FAULTRECEDG_MASK (0x40000UL) 353 #define PWM_GCR_FAULTRECEDG_SHIFT (18U) 354 #define PWM_GCR_FAULTRECEDG_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTRECEDG_SHIFT) & PWM_GCR_FAULTRECEDG_MASK) 355 #define PWM_GCR_FAULTRECEDG_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTRECEDG_MASK) >> PWM_GCR_FAULTRECEDG_SHIFT) 356 357 /* 358 * FAULTRECHWSEL (RW) 359 * 360 * Selec one of the 24 comparators as fault output recover trigger. 361 */ 362 #define PWM_GCR_FAULTRECHWSEL_MASK (0x3E000UL) 363 #define PWM_GCR_FAULTRECHWSEL_SHIFT (13U) 364 #define PWM_GCR_FAULTRECHWSEL_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTRECHWSEL_SHIFT) & PWM_GCR_FAULTRECHWSEL_MASK) 365 #define PWM_GCR_FAULTRECHWSEL_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTRECHWSEL_MASK) >> PWM_GCR_FAULTRECHWSEL_SHIFT) 366 367 /* 368 * FAULTE1EN (RW) 369 * 370 * 1- enable the external fault input 1 371 */ 372 #define PWM_GCR_FAULTE1EN_MASK (0x1000U) 373 #define PWM_GCR_FAULTE1EN_SHIFT (12U) 374 #define PWM_GCR_FAULTE1EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTE1EN_SHIFT) & PWM_GCR_FAULTE1EN_MASK) 375 #define PWM_GCR_FAULTE1EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTE1EN_MASK) >> PWM_GCR_FAULTE1EN_SHIFT) 376 377 /* 378 * FAULTE0EN (RW) 379 * 380 * 1- enable the external fault input 0 381 */ 382 #define PWM_GCR_FAULTE0EN_MASK (0x800U) 383 #define PWM_GCR_FAULTE0EN_SHIFT (11U) 384 #define PWM_GCR_FAULTE0EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTE0EN_SHIFT) & PWM_GCR_FAULTE0EN_MASK) 385 #define PWM_GCR_FAULTE0EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTE0EN_MASK) >> PWM_GCR_FAULTE0EN_SHIFT) 386 387 /* 388 * FAULTEXPOL (RW) 389 * 390 * external fault polarity 391 * 1-active low 392 * 0-active high 393 */ 394 #define PWM_GCR_FAULTEXPOL_MASK (0x600U) 395 #define PWM_GCR_FAULTEXPOL_SHIFT (9U) 396 #define PWM_GCR_FAULTEXPOL_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTEXPOL_SHIFT) & PWM_GCR_FAULTEXPOL_MASK) 397 #define PWM_GCR_FAULTEXPOL_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTEXPOL_MASK) >> PWM_GCR_FAULTEXPOL_SHIFT) 398 399 /* 400 * RLDSYNCEN (RW) 401 * 402 * 1- pwm timer counter reset to reload value (rld) by synci is enabled 403 */ 404 #define PWM_GCR_RLDSYNCEN_MASK (0x100U) 405 #define PWM_GCR_RLDSYNCEN_SHIFT (8U) 406 #define PWM_GCR_RLDSYNCEN_SET(x) (((uint32_t)(x) << PWM_GCR_RLDSYNCEN_SHIFT) & PWM_GCR_RLDSYNCEN_MASK) 407 #define PWM_GCR_RLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_RLDSYNCEN_MASK) >> PWM_GCR_RLDSYNCEN_SHIFT) 408 409 /* 410 * CEN (RW) 411 * 412 * 1- enable the pwm timer counter 413 * 0- stop the pwm timer counter 414 */ 415 #define PWM_GCR_CEN_MASK (0x80U) 416 #define PWM_GCR_CEN_SHIFT (7U) 417 #define PWM_GCR_CEN_SET(x) (((uint32_t)(x) << PWM_GCR_CEN_SHIFT) & PWM_GCR_CEN_MASK) 418 #define PWM_GCR_CEN_GET(x) (((uint32_t)(x) & PWM_GCR_CEN_MASK) >> PWM_GCR_CEN_SHIFT) 419 420 /* 421 * FAULTCLR (RW) 422 * 423 * 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. 424 * User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. 425 */ 426 #define PWM_GCR_FAULTCLR_MASK (0x40U) 427 #define PWM_GCR_FAULTCLR_SHIFT (6U) 428 #define PWM_GCR_FAULTCLR_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTCLR_SHIFT) & PWM_GCR_FAULTCLR_MASK) 429 #define PWM_GCR_FAULTCLR_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTCLR_MASK) >> PWM_GCR_FAULTCLR_SHIFT) 430 431 /* 432 * XRLDSYNCEN (RW) 433 * 434 * 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled 435 */ 436 #define PWM_GCR_XRLDSYNCEN_MASK (0x20U) 437 #define PWM_GCR_XRLDSYNCEN_SHIFT (5U) 438 #define PWM_GCR_XRLDSYNCEN_SET(x) (((uint32_t)(x) << PWM_GCR_XRLDSYNCEN_SHIFT) & PWM_GCR_XRLDSYNCEN_MASK) 439 #define PWM_GCR_XRLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_XRLDSYNCEN_MASK) >> PWM_GCR_XRLDSYNCEN_SHIFT) 440 441 /* 442 * HR_PWM_EN (RW) 443 * 444 * set to enable high resolution pwm, trig_cmp, start/reload register will have different definition. 445 */ 446 #define PWM_GCR_HR_PWM_EN_MASK (0x10U) 447 #define PWM_GCR_HR_PWM_EN_SHIFT (4U) 448 #define PWM_GCR_HR_PWM_EN_SET(x) (((uint32_t)(x) << PWM_GCR_HR_PWM_EN_SHIFT) & PWM_GCR_HR_PWM_EN_MASK) 449 #define PWM_GCR_HR_PWM_EN_GET(x) (((uint32_t)(x) & PWM_GCR_HR_PWM_EN_MASK) >> PWM_GCR_HR_PWM_EN_SHIFT) 450 451 /* 452 * TIMERRESET (RW) 453 * 454 * set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear 455 */ 456 #define PWM_GCR_TIMERRESET_MASK (0x8U) 457 #define PWM_GCR_TIMERRESET_SHIFT (3U) 458 #define PWM_GCR_TIMERRESET_SET(x) (((uint32_t)(x) << PWM_GCR_TIMERRESET_SHIFT) & PWM_GCR_TIMERRESET_MASK) 459 #define PWM_GCR_TIMERRESET_GET(x) (((uint32_t)(x) & PWM_GCR_TIMERRESET_MASK) >> PWM_GCR_TIMERRESET_SHIFT) 460 461 /* 462 * FRCTIME (WO) 463 * 464 * This bit field select the force effective time 465 * 00: force immediately 466 * 01: force at main counter reload time 467 * 10: force at FRCSYNCI 468 * 11: no force 469 */ 470 #define PWM_GCR_FRCTIME_MASK (0x6U) 471 #define PWM_GCR_FRCTIME_SHIFT (1U) 472 #define PWM_GCR_FRCTIME_SET(x) (((uint32_t)(x) << PWM_GCR_FRCTIME_SHIFT) & PWM_GCR_FRCTIME_MASK) 473 #define PWM_GCR_FRCTIME_GET(x) (((uint32_t)(x) & PWM_GCR_FRCTIME_MASK) >> PWM_GCR_FRCTIME_SHIFT) 474 475 /* 476 * SWFRC (RW) 477 * 478 * 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect 479 */ 480 #define PWM_GCR_SWFRC_MASK (0x1U) 481 #define PWM_GCR_SWFRC_SHIFT (0U) 482 #define PWM_GCR_SWFRC_SET(x) (((uint32_t)(x) << PWM_GCR_SWFRC_SHIFT) & PWM_GCR_SWFRC_MASK) 483 #define PWM_GCR_SWFRC_GET(x) (((uint32_t)(x) & PWM_GCR_SWFRC_MASK) >> PWM_GCR_SWFRC_SHIFT) 484 485 /* Bitfield definition for register: SHCR */ 486 /* 487 * CNT_UPDATE_RELOAD (RW) 488 * 489 * set to update counter working register at reload point, clear to use cnt_update_time as old version. 490 */ 491 #define PWM_SHCR_CNT_UPDATE_RELOAD_MASK (0x8000U) 492 #define PWM_SHCR_CNT_UPDATE_RELOAD_SHIFT (15U) 493 #define PWM_SHCR_CNT_UPDATE_RELOAD_SET(x) (((uint32_t)(x) << PWM_SHCR_CNT_UPDATE_RELOAD_SHIFT) & PWM_SHCR_CNT_UPDATE_RELOAD_MASK) 494 #define PWM_SHCR_CNT_UPDATE_RELOAD_GET(x) (((uint32_t)(x) & PWM_SHCR_CNT_UPDATE_RELOAD_MASK) >> PWM_SHCR_CNT_UPDATE_RELOAD_SHIFT) 495 496 /* 497 * CNT_UPDATE_EDGE (RW) 498 * 499 * 0 for posedge; 1 for negedge if hardware trigger time is selected for update_time, and selected channel is capture mode, for counter shadow registers 500 */ 501 #define PWM_SHCR_CNT_UPDATE_EDGE_MASK (0x4000U) 502 #define PWM_SHCR_CNT_UPDATE_EDGE_SHIFT (14U) 503 #define PWM_SHCR_CNT_UPDATE_EDGE_SET(x) (((uint32_t)(x) << PWM_SHCR_CNT_UPDATE_EDGE_SHIFT) & PWM_SHCR_CNT_UPDATE_EDGE_MASK) 504 #define PWM_SHCR_CNT_UPDATE_EDGE_GET(x) (((uint32_t)(x) & PWM_SHCR_CNT_UPDATE_EDGE_MASK) >> PWM_SHCR_CNT_UPDATE_EDGE_SHIFT) 505 506 /* 507 * FORCE_UPDATE_EDGE (RW) 508 * 509 * 0 for posedge; 1 for negedge if hardware trigger time is selected for update_time, and selected channel is capture mode, for FRCMD shadow registers 510 */ 511 #define PWM_SHCR_FORCE_UPDATE_EDGE_MASK (0x2000U) 512 #define PWM_SHCR_FORCE_UPDATE_EDGE_SHIFT (13U) 513 #define PWM_SHCR_FORCE_UPDATE_EDGE_SET(x) (((uint32_t)(x) << PWM_SHCR_FORCE_UPDATE_EDGE_SHIFT) & PWM_SHCR_FORCE_UPDATE_EDGE_MASK) 514 #define PWM_SHCR_FORCE_UPDATE_EDGE_GET(x) (((uint32_t)(x) & PWM_SHCR_FORCE_UPDATE_EDGE_MASK) >> PWM_SHCR_FORCE_UPDATE_EDGE_SHIFT) 515 516 /* 517 * FRCSHDWSEL (RW) 518 * 519 * This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers 520 */ 521 #define PWM_SHCR_FRCSHDWSEL_MASK (0x1F00U) 522 #define PWM_SHCR_FRCSHDWSEL_SHIFT (8U) 523 #define PWM_SHCR_FRCSHDWSEL_SET(x) (((uint32_t)(x) << PWM_SHCR_FRCSHDWSEL_SHIFT) & PWM_SHCR_FRCSHDWSEL_MASK) 524 #define PWM_SHCR_FRCSHDWSEL_GET(x) (((uint32_t)(x) & PWM_SHCR_FRCSHDWSEL_MASK) >> PWM_SHCR_FRCSHDWSEL_SHIFT) 525 526 /* 527 * CNTSHDWSEL (RW) 528 * 529 * This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) 530 */ 531 #define PWM_SHCR_CNTSHDWSEL_MASK (0xF8U) 532 #define PWM_SHCR_CNTSHDWSEL_SHIFT (3U) 533 #define PWM_SHCR_CNTSHDWSEL_SET(x) (((uint32_t)(x) << PWM_SHCR_CNTSHDWSEL_SHIFT) & PWM_SHCR_CNTSHDWSEL_MASK) 534 #define PWM_SHCR_CNTSHDWSEL_GET(x) (((uint32_t)(x) & PWM_SHCR_CNTSHDWSEL_MASK) >> PWM_SHCR_CNTSHDWSEL_SHIFT) 535 536 /* 537 * CNTSHDWUPT (RW) 538 * 539 * This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register 540 * 00: after software set shlk bit of shlk register 541 * 01: immediately after the register being modified 542 * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. 543 * The comparator can be either output compare mode or input capture mode. 544 * 11: after SHSYNCI assert 545 */ 546 #define PWM_SHCR_CNTSHDWUPT_MASK (0x6U) 547 #define PWM_SHCR_CNTSHDWUPT_SHIFT (1U) 548 #define PWM_SHCR_CNTSHDWUPT_SET(x) (((uint32_t)(x) << PWM_SHCR_CNTSHDWUPT_SHIFT) & PWM_SHCR_CNTSHDWUPT_MASK) 549 #define PWM_SHCR_CNTSHDWUPT_GET(x) (((uint32_t)(x) & PWM_SHCR_CNTSHDWUPT_MASK) >> PWM_SHCR_CNTSHDWUPT_SHIFT) 550 551 /* 552 * SHLKEN (RW) 553 * 554 * 1- enable shadow registers lock feature, 555 * 0- disable shadow registers lock, shlk bit will always be 0 556 */ 557 #define PWM_SHCR_SHLKEN_MASK (0x1U) 558 #define PWM_SHCR_SHLKEN_SHIFT (0U) 559 #define PWM_SHCR_SHLKEN_SET(x) (((uint32_t)(x) << PWM_SHCR_SHLKEN_SHIFT) & PWM_SHCR_SHLKEN_MASK) 560 #define PWM_SHCR_SHLKEN_GET(x) (((uint32_t)(x) & PWM_SHCR_SHLKEN_MASK) >> PWM_SHCR_SHLKEN_SHIFT) 561 562 /* Bitfield definition for register array: CAPPOS */ 563 /* 564 * CAPPOS (RO) 565 * 566 * counter value captured at input posedge 567 */ 568 #define PWM_CAPPOS_CAPPOS_MASK (0xFFFFFFF0UL) 569 #define PWM_CAPPOS_CAPPOS_SHIFT (4U) 570 #define PWM_CAPPOS_CAPPOS_GET(x) (((uint32_t)(x) & PWM_CAPPOS_CAPPOS_MASK) >> PWM_CAPPOS_CAPPOS_SHIFT) 571 572 /* Bitfield definition for register: CNT */ 573 /* 574 * XCNT (RO) 575 * 576 * current extended counter value 577 */ 578 #define PWM_CNT_XCNT_MASK (0xF0000000UL) 579 #define PWM_CNT_XCNT_SHIFT (28U) 580 #define PWM_CNT_XCNT_GET(x) (((uint32_t)(x) & PWM_CNT_XCNT_MASK) >> PWM_CNT_XCNT_SHIFT) 581 582 /* 583 * CNT (RO) 584 * 585 * current clock counter value 586 */ 587 #define PWM_CNT_CNT_MASK (0xFFFFFF0UL) 588 #define PWM_CNT_CNT_SHIFT (4U) 589 #define PWM_CNT_CNT_GET(x) (((uint32_t)(x) & PWM_CNT_CNT_MASK) >> PWM_CNT_CNT_SHIFT) 590 591 /* Bitfield definition for register array: CAPNEG */ 592 /* 593 * CAPNEG (RO) 594 * 595 * counter value captured at input signal falling edge 596 */ 597 #define PWM_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) 598 #define PWM_CAPNEG_CAPNEG_SHIFT (0U) 599 #define PWM_CAPNEG_CAPNEG_GET(x) (((uint32_t)(x) & PWM_CAPNEG_CAPNEG_MASK) >> PWM_CAPNEG_CAPNEG_SHIFT) 600 601 /* Bitfield definition for register: CNTCOPY */ 602 /* 603 * XCNT (RO) 604 * 605 * current extended counter value 606 */ 607 #define PWM_CNTCOPY_XCNT_MASK (0xF0000000UL) 608 #define PWM_CNTCOPY_XCNT_SHIFT (28U) 609 #define PWM_CNTCOPY_XCNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_XCNT_MASK) >> PWM_CNTCOPY_XCNT_SHIFT) 610 611 /* 612 * CNT (RO) 613 * 614 * current clock counter value 615 */ 616 #define PWM_CNTCOPY_CNT_MASK (0xFFFFFF0UL) 617 #define PWM_CNTCOPY_CNT_SHIFT (4U) 618 #define PWM_CNTCOPY_CNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_CNT_MASK) >> PWM_CNTCOPY_CNT_SHIFT) 619 620 /* Bitfield definition for register array: PWMCFG */ 621 /* 622 * HR_UPDATE_MODE (RW) 623 * 624 * 0: update the hr value for the first edge at reload point; 625 * 1: update the hr value for the first edge at the last edge; 626 * all others will be updated at previous edge 627 * for pair mode, only pwm_cfg 0/2/4/6 are used 628 */ 629 #define PWM_PWMCFG_HR_UPDATE_MODE_MASK (0x20000000UL) 630 #define PWM_PWMCFG_HR_UPDATE_MODE_SHIFT (29U) 631 #define PWM_PWMCFG_HR_UPDATE_MODE_SET(x) (((uint32_t)(x) << PWM_PWMCFG_HR_UPDATE_MODE_SHIFT) & PWM_PWMCFG_HR_UPDATE_MODE_MASK) 632 #define PWM_PWMCFG_HR_UPDATE_MODE_GET(x) (((uint32_t)(x) & PWM_PWMCFG_HR_UPDATE_MODE_MASK) >> PWM_PWMCFG_HR_UPDATE_MODE_SHIFT) 633 634 /* 635 * OEN (RW) 636 * 637 * PWM output enable 638 * 1- output is enabled 639 * 0- output is disabled 640 */ 641 #define PWM_PWMCFG_OEN_MASK (0x10000000UL) 642 #define PWM_PWMCFG_OEN_SHIFT (28U) 643 #define PWM_PWMCFG_OEN_SET(x) (((uint32_t)(x) << PWM_PWMCFG_OEN_SHIFT) & PWM_PWMCFG_OEN_MASK) 644 #define PWM_PWMCFG_OEN_GET(x) (((uint32_t)(x) & PWM_PWMCFG_OEN_MASK) >> PWM_PWMCFG_OEN_SHIFT) 645 646 /* 647 * FRCSHDWUPT (RW) 648 * 649 * This bitfield select when the FRCMD shadow register will be loaded to its work register 650 * 00: after software set shlk bit of shlk register 651 * 01: immediately after the register being modified 652 * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. 653 * The comparator can be either output compare mode or input capture mode. 654 * 11: after SHSYNCI assert 655 */ 656 #define PWM_PWMCFG_FRCSHDWUPT_MASK (0xC000000UL) 657 #define PWM_PWMCFG_FRCSHDWUPT_SHIFT (26U) 658 #define PWM_PWMCFG_FRCSHDWUPT_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FRCSHDWUPT_SHIFT) & PWM_PWMCFG_FRCSHDWUPT_MASK) 659 #define PWM_PWMCFG_FRCSHDWUPT_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FRCSHDWUPT_MASK) >> PWM_PWMCFG_FRCSHDWUPT_SHIFT) 660 661 /* 662 * FAULTMODE (RW) 663 * 664 * This bitfield defines the PWM output status when fault condition happen 665 * 00: force output 0 666 * 01: force output 1 667 * 1x: output highz 668 */ 669 #define PWM_PWMCFG_FAULTMODE_MASK (0x3000000UL) 670 #define PWM_PWMCFG_FAULTMODE_SHIFT (24U) 671 #define PWM_PWMCFG_FAULTMODE_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FAULTMODE_SHIFT) & PWM_PWMCFG_FAULTMODE_MASK) 672 #define PWM_PWMCFG_FAULTMODE_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FAULTMODE_MASK) >> PWM_PWMCFG_FAULTMODE_SHIFT) 673 674 /* 675 * FAULTRECTIME (RW) 676 * 677 * This bitfield select when to recover PWM output after fault condition removed. 678 * 00: immediately 679 * 01: after pwm timer counter reload time 680 * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. 681 * The comparator can be either output compare mode or input capture mode. 682 * 11: after software write faultclr bit in GCR register 683 */ 684 #define PWM_PWMCFG_FAULTRECTIME_MASK (0xC00000UL) 685 #define PWM_PWMCFG_FAULTRECTIME_SHIFT (22U) 686 #define PWM_PWMCFG_FAULTRECTIME_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FAULTRECTIME_SHIFT) & PWM_PWMCFG_FAULTRECTIME_MASK) 687 #define PWM_PWMCFG_FAULTRECTIME_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FAULTRECTIME_MASK) >> PWM_PWMCFG_FAULTRECTIME_SHIFT) 688 689 /* 690 * FRCSRCSEL (RW) 691 * 692 * Select sources for force output 693 * 0- force output is enabled when FRCI assert 694 * 1- force output is enabled by software write swfrc to 1 695 */ 696 #define PWM_PWMCFG_FRCSRCSEL_MASK (0x200000UL) 697 #define PWM_PWMCFG_FRCSRCSEL_SHIFT (21U) 698 #define PWM_PWMCFG_FRCSRCSEL_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FRCSRCSEL_SHIFT) & PWM_PWMCFG_FRCSRCSEL_MASK) 699 #define PWM_PWMCFG_FRCSRCSEL_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FRCSRCSEL_MASK) >> PWM_PWMCFG_FRCSRCSEL_SHIFT) 700 701 /* 702 * PAIR (RW) 703 * 704 * 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. 705 * 0- PWM output is in indepandent mode. 706 */ 707 #define PWM_PWMCFG_PAIR_MASK (0x100000UL) 708 #define PWM_PWMCFG_PAIR_SHIFT (20U) 709 #define PWM_PWMCFG_PAIR_SET(x) (((uint32_t)(x) << PWM_PWMCFG_PAIR_SHIFT) & PWM_PWMCFG_PAIR_MASK) 710 #define PWM_PWMCFG_PAIR_GET(x) (((uint32_t)(x) & PWM_PWMCFG_PAIR_MASK) >> PWM_PWMCFG_PAIR_SHIFT) 711 712 /* 713 * DEADAREA (RW) 714 * 715 * This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. 716 * Note: user should configure pair bit and this bitfield before PWM output is enabled. 717 */ 718 #define PWM_PWMCFG_DEADAREA_MASK (0xFFFFFUL) 719 #define PWM_PWMCFG_DEADAREA_SHIFT (0U) 720 #define PWM_PWMCFG_DEADAREA_SET(x) (((uint32_t)(x) << PWM_PWMCFG_DEADAREA_SHIFT) & PWM_PWMCFG_DEADAREA_MASK) 721 #define PWM_PWMCFG_DEADAREA_GET(x) (((uint32_t)(x) & PWM_PWMCFG_DEADAREA_MASK) >> PWM_PWMCFG_DEADAREA_SHIFT) 722 723 /* Bitfield definition for register: SR */ 724 /* 725 * FAULTF (W1C) 726 * 727 * fault condition flag 728 */ 729 #define PWM_SR_FAULTF_MASK (0x8000000UL) 730 #define PWM_SR_FAULTF_SHIFT (27U) 731 #define PWM_SR_FAULTF_SET(x) (((uint32_t)(x) << PWM_SR_FAULTF_SHIFT) & PWM_SR_FAULTF_MASK) 732 #define PWM_SR_FAULTF_GET(x) (((uint32_t)(x) & PWM_SR_FAULTF_MASK) >> PWM_SR_FAULTF_SHIFT) 733 734 /* 735 * XRLDF (W1C) 736 * 737 * extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert 738 */ 739 #define PWM_SR_XRLDF_MASK (0x4000000UL) 740 #define PWM_SR_XRLDF_SHIFT (26U) 741 #define PWM_SR_XRLDF_SET(x) (((uint32_t)(x) << PWM_SR_XRLDF_SHIFT) & PWM_SR_XRLDF_MASK) 742 #define PWM_SR_XRLDF_GET(x) (((uint32_t)(x) & PWM_SR_XRLDF_MASK) >> PWM_SR_XRLDF_SHIFT) 743 744 /* 745 * HALFRLDF (W1C) 746 * 747 * half reload flag, this flag set when cnt count to rld/2 748 */ 749 #define PWM_SR_HALFRLDF_MASK (0x2000000UL) 750 #define PWM_SR_HALFRLDF_SHIFT (25U) 751 #define PWM_SR_HALFRLDF_SET(x) (((uint32_t)(x) << PWM_SR_HALFRLDF_SHIFT) & PWM_SR_HALFRLDF_MASK) 752 #define PWM_SR_HALFRLDF_GET(x) (((uint32_t)(x) & PWM_SR_HALFRLDF_MASK) >> PWM_SR_HALFRLDF_SHIFT) 753 754 /* 755 * RLDF (W1C) 756 * 757 * reload flag, this flag set when cnt count to rld value or when SYNCI assert 758 */ 759 #define PWM_SR_RLDF_MASK (0x1000000UL) 760 #define PWM_SR_RLDF_SHIFT (24U) 761 #define PWM_SR_RLDF_SET(x) (((uint32_t)(x) << PWM_SR_RLDF_SHIFT) & PWM_SR_RLDF_MASK) 762 #define PWM_SR_RLDF_GET(x) (((uint32_t)(x) & PWM_SR_RLDF_MASK) >> PWM_SR_RLDF_SHIFT) 763 764 /* 765 * CMPFX (W1C) 766 * 767 * comparator output compare or input capture flag 768 */ 769 #define PWM_SR_CMPFX_MASK (0xFFFFFFUL) 770 #define PWM_SR_CMPFX_SHIFT (0U) 771 #define PWM_SR_CMPFX_SET(x) (((uint32_t)(x) << PWM_SR_CMPFX_SHIFT) & PWM_SR_CMPFX_MASK) 772 #define PWM_SR_CMPFX_GET(x) (((uint32_t)(x) & PWM_SR_CMPFX_MASK) >> PWM_SR_CMPFX_SHIFT) 773 774 /* Bitfield definition for register: IRQEN */ 775 /* 776 * FAULTIRQE (RW) 777 * 778 * fault condition interrupt enable 779 */ 780 #define PWM_IRQEN_FAULTIRQE_MASK (0x8000000UL) 781 #define PWM_IRQEN_FAULTIRQE_SHIFT (27U) 782 #define PWM_IRQEN_FAULTIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_FAULTIRQE_SHIFT) & PWM_IRQEN_FAULTIRQE_MASK) 783 #define PWM_IRQEN_FAULTIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_FAULTIRQE_MASK) >> PWM_IRQEN_FAULTIRQE_SHIFT) 784 785 /* 786 * XRLDIRQE (RW) 787 * 788 * extended reload flag interrupt enable 789 */ 790 #define PWM_IRQEN_XRLDIRQE_MASK (0x4000000UL) 791 #define PWM_IRQEN_XRLDIRQE_SHIFT (26U) 792 #define PWM_IRQEN_XRLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_XRLDIRQE_SHIFT) & PWM_IRQEN_XRLDIRQE_MASK) 793 #define PWM_IRQEN_XRLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_XRLDIRQE_MASK) >> PWM_IRQEN_XRLDIRQE_SHIFT) 794 795 /* 796 * HALFRLDIRQE (RW) 797 * 798 * half reload flag interrupt enable 799 */ 800 #define PWM_IRQEN_HALFRLDIRQE_MASK (0x2000000UL) 801 #define PWM_IRQEN_HALFRLDIRQE_SHIFT (25U) 802 #define PWM_IRQEN_HALFRLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_HALFRLDIRQE_SHIFT) & PWM_IRQEN_HALFRLDIRQE_MASK) 803 #define PWM_IRQEN_HALFRLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_HALFRLDIRQE_MASK) >> PWM_IRQEN_HALFRLDIRQE_SHIFT) 804 805 /* 806 * RLDIRQE (RW) 807 * 808 * reload flag interrupt enable 809 */ 810 #define PWM_IRQEN_RLDIRQE_MASK (0x1000000UL) 811 #define PWM_IRQEN_RLDIRQE_SHIFT (24U) 812 #define PWM_IRQEN_RLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_RLDIRQE_SHIFT) & PWM_IRQEN_RLDIRQE_MASK) 813 #define PWM_IRQEN_RLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_RLDIRQE_MASK) >> PWM_IRQEN_RLDIRQE_SHIFT) 814 815 /* 816 * CMPIRQEX (RW) 817 * 818 * comparator output compare or input capture flag interrupt enable 819 */ 820 #define PWM_IRQEN_CMPIRQEX_MASK (0xFFFFFFUL) 821 #define PWM_IRQEN_CMPIRQEX_SHIFT (0U) 822 #define PWM_IRQEN_CMPIRQEX_SET(x) (((uint32_t)(x) << PWM_IRQEN_CMPIRQEX_SHIFT) & PWM_IRQEN_CMPIRQEX_MASK) 823 #define PWM_IRQEN_CMPIRQEX_GET(x) (((uint32_t)(x) & PWM_IRQEN_CMPIRQEX_MASK) >> PWM_IRQEN_CMPIRQEX_SHIFT) 824 825 /* Bitfield definition for register: DMAEN */ 826 /* 827 * FAULTEN (RW) 828 * 829 * fault condition DMA request enable 830 */ 831 #define PWM_DMAEN_FAULTEN_MASK (0x8000000UL) 832 #define PWM_DMAEN_FAULTEN_SHIFT (27U) 833 #define PWM_DMAEN_FAULTEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_FAULTEN_SHIFT) & PWM_DMAEN_FAULTEN_MASK) 834 #define PWM_DMAEN_FAULTEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_FAULTEN_MASK) >> PWM_DMAEN_FAULTEN_SHIFT) 835 836 /* 837 * XRLDEN (RW) 838 * 839 * extended reload flag DMA request enable 840 */ 841 #define PWM_DMAEN_XRLDEN_MASK (0x4000000UL) 842 #define PWM_DMAEN_XRLDEN_SHIFT (26U) 843 #define PWM_DMAEN_XRLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_XRLDEN_SHIFT) & PWM_DMAEN_XRLDEN_MASK) 844 #define PWM_DMAEN_XRLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_XRLDEN_MASK) >> PWM_DMAEN_XRLDEN_SHIFT) 845 846 /* 847 * HALFRLDEN (RW) 848 * 849 * half reload flag DMA request enable 850 */ 851 #define PWM_DMAEN_HALFRLDEN_MASK (0x2000000UL) 852 #define PWM_DMAEN_HALFRLDEN_SHIFT (25U) 853 #define PWM_DMAEN_HALFRLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_HALFRLDEN_SHIFT) & PWM_DMAEN_HALFRLDEN_MASK) 854 #define PWM_DMAEN_HALFRLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_HALFRLDEN_MASK) >> PWM_DMAEN_HALFRLDEN_SHIFT) 855 856 /* 857 * RLDEN (RW) 858 * 859 * reload flag DMA request enable 860 */ 861 #define PWM_DMAEN_RLDEN_MASK (0x1000000UL) 862 #define PWM_DMAEN_RLDEN_SHIFT (24U) 863 #define PWM_DMAEN_RLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_RLDEN_SHIFT) & PWM_DMAEN_RLDEN_MASK) 864 #define PWM_DMAEN_RLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_RLDEN_MASK) >> PWM_DMAEN_RLDEN_SHIFT) 865 866 /* 867 * CMPENX (RW) 868 * 869 * comparator output compare or input capture flag DMA request enable 870 */ 871 #define PWM_DMAEN_CMPENX_MASK (0xFFFFFFUL) 872 #define PWM_DMAEN_CMPENX_SHIFT (0U) 873 #define PWM_DMAEN_CMPENX_SET(x) (((uint32_t)(x) << PWM_DMAEN_CMPENX_SHIFT) & PWM_DMAEN_CMPENX_MASK) 874 #define PWM_DMAEN_CMPENX_GET(x) (((uint32_t)(x) & PWM_DMAEN_CMPENX_MASK) >> PWM_DMAEN_CMPENX_SHIFT) 875 876 /* Bitfield definition for register array: CMPCFG */ 877 /* 878 * XCNTCMPEN (RW) 879 * 880 * This bitfield enable the comparator to compare xcmp with xcnt. 881 */ 882 #define PWM_CMPCFG_XCNTCMPEN_MASK (0xF0U) 883 #define PWM_CMPCFG_XCNTCMPEN_SHIFT (4U) 884 #define PWM_CMPCFG_XCNTCMPEN_SET(x) (((uint32_t)(x) << PWM_CMPCFG_XCNTCMPEN_SHIFT) & PWM_CMPCFG_XCNTCMPEN_MASK) 885 #define PWM_CMPCFG_XCNTCMPEN_GET(x) (((uint32_t)(x) & PWM_CMPCFG_XCNTCMPEN_MASK) >> PWM_CMPCFG_XCNTCMPEN_SHIFT) 886 887 /* 888 * CMPSHDWUPT (RW) 889 * 890 * This bitfield select when the comparator shadow register will be loaded to its work register 891 * 00: after software set shlk bit of shlk register 892 * 01: immediately after the register being modified 893 * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. 894 * The comparator can be either output compare mode or input capture mode. 895 * 11: after SHSYNCI assert 896 */ 897 #define PWM_CMPCFG_CMPSHDWUPT_MASK (0xCU) 898 #define PWM_CMPCFG_CMPSHDWUPT_SHIFT (2U) 899 #define PWM_CMPCFG_CMPSHDWUPT_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPSHDWUPT_SHIFT) & PWM_CMPCFG_CMPSHDWUPT_MASK) 900 #define PWM_CMPCFG_CMPSHDWUPT_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPSHDWUPT_MASK) >> PWM_CMPCFG_CMPSHDWUPT_SHIFT) 901 902 /* 903 * CMPMODE (RW) 904 * 905 * comparator mode 906 * 0- output compare mode 907 * 1- input capture mode 908 */ 909 #define PWM_CMPCFG_CMPMODE_MASK (0x2U) 910 #define PWM_CMPCFG_CMPMODE_SHIFT (1U) 911 #define PWM_CMPCFG_CMPMODE_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPMODE_SHIFT) & PWM_CMPCFG_CMPMODE_MASK) 912 #define PWM_CMPCFG_CMPMODE_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPMODE_MASK) >> PWM_CMPCFG_CMPMODE_SHIFT) 913 914 /* Bitfield definition for register array: ANASTS */ 915 /* 916 * CALON (RO) 917 * 918 * calibration status. 919 * will be set by hardware after setting cal_start. 920 * cleared after calibration finished 921 */ 922 #define PWM_ANASTS_CALON_MASK (0x80000000UL) 923 #define PWM_ANASTS_CALON_SHIFT (31U) 924 #define PWM_ANASTS_CALON_GET(x) (((uint32_t)(x) & PWM_ANASTS_CALON_MASK) >> PWM_ANASTS_CALON_SHIFT) 925 926 /* Bitfield definition for register: HRPWM_CFG */ 927 /* 928 * CAL_START (WO) 929 * 930 * calibration start. 931 * software setting this bit to start calibration process. 932 * each bit for one channel. 933 */ 934 #define PWM_HRPWM_CFG_CAL_START_MASK (0xFFU) 935 #define PWM_HRPWM_CFG_CAL_START_SHIFT (0U) 936 #define PWM_HRPWM_CFG_CAL_START_SET(x) (((uint32_t)(x) << PWM_HRPWM_CFG_CAL_START_SHIFT) & PWM_HRPWM_CFG_CAL_START_MASK) 937 #define PWM_HRPWM_CFG_CAL_START_GET(x) (((uint32_t)(x) & PWM_HRPWM_CFG_CAL_START_MASK) >> PWM_HRPWM_CFG_CAL_START_SHIFT) 938 939 940 941 /* CMP register group index macro definition */ 942 #define PWM_CMP_0 (0UL) 943 #define PWM_CMP_1 (1UL) 944 #define PWM_CMP_2 (2UL) 945 #define PWM_CMP_3 (3UL) 946 #define PWM_CMP_4 (4UL) 947 #define PWM_CMP_5 (5UL) 948 #define PWM_CMP_6 (6UL) 949 #define PWM_CMP_7 (7UL) 950 #define PWM_CMP_8 (8UL) 951 #define PWM_CMP_9 (9UL) 952 #define PWM_CMP_10 (10UL) 953 #define PWM_CMP_11 (11UL) 954 #define PWM_CMP_12 (12UL) 955 #define PWM_CMP_13 (13UL) 956 #define PWM_CMP_14 (14UL) 957 #define PWM_CMP_15 (15UL) 958 #define PWM_CMP_16 (16UL) 959 #define PWM_CMP_17 (17UL) 960 #define PWM_CMP_18 (18UL) 961 #define PWM_CMP_19 (19UL) 962 #define PWM_CMP_20 (20UL) 963 #define PWM_CMP_21 (21UL) 964 #define PWM_CMP_22 (22UL) 965 #define PWM_CMP_23 (23UL) 966 967 /* CMP_HRPWM register group index macro definition */ 968 #define PWM_CMP_HRPWM_0 (0UL) 969 #define PWM_CMP_HRPWM_1 (1UL) 970 #define PWM_CMP_HRPWM_2 (2UL) 971 #define PWM_CMP_HRPWM_3 (3UL) 972 #define PWM_CMP_HRPWM_4 (4UL) 973 #define PWM_CMP_HRPWM_5 (5UL) 974 #define PWM_CMP_HRPWM_6 (6UL) 975 #define PWM_CMP_HRPWM_7 (7UL) 976 #define PWM_CMP_HRPWM_8 (8UL) 977 #define PWM_CMP_HRPWM_9 (9UL) 978 #define PWM_CMP_HRPWM_10 (10UL) 979 #define PWM_CMP_HRPWM_11 (11UL) 980 #define PWM_CMP_HRPWM_12 (12UL) 981 #define PWM_CMP_HRPWM_13 (13UL) 982 #define PWM_CMP_HRPWM_14 (14UL) 983 #define PWM_CMP_HRPWM_15 (15UL) 984 #define PWM_CMP_HRPWM_16 (16UL) 985 #define PWM_CMP_HRPWM_17 (17UL) 986 #define PWM_CMP_HRPWM_18 (18UL) 987 #define PWM_CMP_HRPWM_19 (19UL) 988 #define PWM_CMP_HRPWM_20 (20UL) 989 #define PWM_CMP_HRPWM_21 (21UL) 990 #define PWM_CMP_HRPWM_22 (22UL) 991 #define PWM_CMP_HRPWM_23 (23UL) 992 993 /* CHCFG register group index macro definition */ 994 #define PWM_CHCFG_0 (0UL) 995 #define PWM_CHCFG_1 (1UL) 996 #define PWM_CHCFG_2 (2UL) 997 #define PWM_CHCFG_3 (3UL) 998 #define PWM_CHCFG_4 (4UL) 999 #define PWM_CHCFG_5 (5UL) 1000 #define PWM_CHCFG_6 (6UL) 1001 #define PWM_CHCFG_7 (7UL) 1002 #define PWM_CHCFG_8 (8UL) 1003 #define PWM_CHCFG_9 (9UL) 1004 #define PWM_CHCFG_10 (10UL) 1005 #define PWM_CHCFG_11 (11UL) 1006 #define PWM_CHCFG_12 (12UL) 1007 #define PWM_CHCFG_13 (13UL) 1008 #define PWM_CHCFG_14 (14UL) 1009 #define PWM_CHCFG_15 (15UL) 1010 #define PWM_CHCFG_16 (16UL) 1011 #define PWM_CHCFG_17 (17UL) 1012 #define PWM_CHCFG_18 (18UL) 1013 #define PWM_CHCFG_19 (19UL) 1014 #define PWM_CHCFG_20 (20UL) 1015 #define PWM_CHCFG_21 (21UL) 1016 #define PWM_CHCFG_22 (22UL) 1017 #define PWM_CHCFG_23 (23UL) 1018 1019 /* CAPPOS register group index macro definition */ 1020 #define PWM_CAPPOS_0 (0UL) 1021 #define PWM_CAPPOS_1 (1UL) 1022 #define PWM_CAPPOS_2 (2UL) 1023 #define PWM_CAPPOS_3 (3UL) 1024 #define PWM_CAPPOS_4 (4UL) 1025 #define PWM_CAPPOS_5 (5UL) 1026 #define PWM_CAPPOS_6 (6UL) 1027 #define PWM_CAPPOS_7 (7UL) 1028 #define PWM_CAPPOS_8 (8UL) 1029 #define PWM_CAPPOS_9 (9UL) 1030 #define PWM_CAPPOS_10 (10UL) 1031 #define PWM_CAPPOS_11 (11UL) 1032 #define PWM_CAPPOS_12 (12UL) 1033 #define PWM_CAPPOS_13 (13UL) 1034 #define PWM_CAPPOS_14 (14UL) 1035 #define PWM_CAPPOS_15 (15UL) 1036 #define PWM_CAPPOS_16 (16UL) 1037 #define PWM_CAPPOS_17 (17UL) 1038 #define PWM_CAPPOS_18 (18UL) 1039 #define PWM_CAPPOS_19 (19UL) 1040 #define PWM_CAPPOS_20 (20UL) 1041 #define PWM_CAPPOS_21 (21UL) 1042 #define PWM_CAPPOS_22 (22UL) 1043 #define PWM_CAPPOS_23 (23UL) 1044 1045 /* CAPNEG register group index macro definition */ 1046 #define PWM_CAPNEG_0 (0UL) 1047 #define PWM_CAPNEG_1 (1UL) 1048 #define PWM_CAPNEG_2 (2UL) 1049 #define PWM_CAPNEG_3 (3UL) 1050 #define PWM_CAPNEG_4 (4UL) 1051 #define PWM_CAPNEG_5 (5UL) 1052 #define PWM_CAPNEG_6 (6UL) 1053 #define PWM_CAPNEG_7 (7UL) 1054 #define PWM_CAPNEG_8 (8UL) 1055 #define PWM_CAPNEG_9 (9UL) 1056 #define PWM_CAPNEG_10 (10UL) 1057 #define PWM_CAPNEG_11 (11UL) 1058 #define PWM_CAPNEG_12 (12UL) 1059 #define PWM_CAPNEG_13 (13UL) 1060 #define PWM_CAPNEG_14 (14UL) 1061 #define PWM_CAPNEG_15 (15UL) 1062 #define PWM_CAPNEG_16 (16UL) 1063 #define PWM_CAPNEG_17 (17UL) 1064 #define PWM_CAPNEG_18 (18UL) 1065 #define PWM_CAPNEG_19 (19UL) 1066 #define PWM_CAPNEG_20 (20UL) 1067 #define PWM_CAPNEG_21 (21UL) 1068 #define PWM_CAPNEG_22 (22UL) 1069 #define PWM_CAPNEG_23 (23UL) 1070 1071 /* PWMCFG register group index macro definition */ 1072 #define PWM_PWMCFG_0 (0UL) 1073 #define PWM_PWMCFG_1 (1UL) 1074 #define PWM_PWMCFG_2 (2UL) 1075 #define PWM_PWMCFG_3 (3UL) 1076 #define PWM_PWMCFG_4 (4UL) 1077 #define PWM_PWMCFG_5 (5UL) 1078 #define PWM_PWMCFG_6 (6UL) 1079 #define PWM_PWMCFG_7 (7UL) 1080 1081 /* CMPCFG register group index macro definition */ 1082 #define PWM_CMPCFG_CMPCFG0 (0UL) 1083 #define PWM_CMPCFG_1 (1UL) 1084 #define PWM_CMPCFG_2 (2UL) 1085 #define PWM_CMPCFG_3 (3UL) 1086 #define PWM_CMPCFG_4 (4UL) 1087 #define PWM_CMPCFG_5 (5UL) 1088 #define PWM_CMPCFG_6 (6UL) 1089 #define PWM_CMPCFG_7 (7UL) 1090 #define PWM_CMPCFG_8 (8UL) 1091 #define PWM_CMPCFG_9 (9UL) 1092 #define PWM_CMPCFG_10 (10UL) 1093 #define PWM_CMPCFG_11 (11UL) 1094 #define PWM_CMPCFG_12 (12UL) 1095 #define PWM_CMPCFG_13 (13UL) 1096 #define PWM_CMPCFG_14 (14UL) 1097 #define PWM_CMPCFG_15 (15UL) 1098 #define PWM_CMPCFG_16 (16UL) 1099 #define PWM_CMPCFG_17 (17UL) 1100 #define PWM_CMPCFG_18 (18UL) 1101 #define PWM_CMPCFG_19 (19UL) 1102 #define PWM_CMPCFG_20 (20UL) 1103 #define PWM_CMPCFG_21 (21UL) 1104 #define PWM_CMPCFG_22 (22UL) 1105 #define PWM_CMPCFG_23 (23UL) 1106 1107 /* ANASTS register group index macro definition */ 1108 #define PWM_ANASTS_0 (0UL) 1109 #define PWM_ANASTS_1 (1UL) 1110 #define PWM_ANASTS_2 (2UL) 1111 #define PWM_ANASTS_3 (3UL) 1112 #define PWM_ANASTS_4 (4UL) 1113 #define PWM_ANASTS_5 (5UL) 1114 #define PWM_ANASTS_6 (6UL) 1115 #define PWM_ANASTS_7 (7UL) 1116 1117 1118 #endif /* HPM_PWM_H */ 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