1 /**
2 ******************************************************************************
3 * @file stm32f4xx_pwr.c
4 * @author MCD Application Team
5 * @version V1.4.0
6 * @date 04-August-2014
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the Power Controller (PWR) peripheral:
9 * + Backup Domain Access
10 * + PVD configuration
11 * + WakeUp pin configuration
12 * + Main and Backup Regulators configuration
13 * + FLASH Power Down configuration
14 * + Low Power modes configuration
15 * + Flags management
16 *
17 ******************************************************************************
18 * @attention
19 *
20 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
21 *
22 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
23 * You may not use this file except in compliance with the License.
24 * You may obtain a copy of the License at:
25 *
26 * http://www.st.com/software_license_agreement_liberty_v2
27 *
28 * Unless required by applicable law or agreed to in writing, software
29 * distributed under the License is distributed on an "AS IS" BASIS,
30 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
31 * See the License for the specific language governing permissions and
32 * limitations under the License.
33 *
34 ******************************************************************************
35 */
36
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f4xx_pwr.h"
39 #include "stm32f4xx_rcc.h"
40
41 /** @addtogroup STM32F4xx_StdPeriph_Driver
42 * @{
43 */
44
45 /** @defgroup PWR
46 * @brief PWR driver modules
47 * @{
48 */
49
50 /* Private typedef -----------------------------------------------------------*/
51 /* Private define ------------------------------------------------------------*/
52 /* --------- PWR registers bit address in the alias region ---------- */
53 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
54
55 /* --- CR Register ---*/
56
57 /* Alias word address of DBP bit */
58 #define CR_OFFSET (PWR_OFFSET + 0x00)
59 #define DBP_BitNumber 0x08
60 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
61
62 /* Alias word address of PVDE bit */
63 #define PVDE_BitNumber 0x04
64 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
65
66 /* Alias word address of FPDS bit */
67 #define FPDS_BitNumber 0x09
68 #define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
69
70 /* Alias word address of PMODE bit */
71 #define PMODE_BitNumber 0x0E
72 #define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
73
74 /* Alias word address of ODEN bit */
75 #define ODEN_BitNumber 0x10
76 #define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4))
77
78 /* Alias word address of ODSWEN bit */
79 #define ODSWEN_BitNumber 0x11
80 #define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4))
81
82 /* Alias word address of MRLVDS bit */
83 #define MRLVDS_BitNumber 0x0B
84 #define CR_MRLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4))
85
86 /* Alias word address of LPLVDS bit */
87 #define LPLVDS_BitNumber 0x0A
88 #define CR_LPLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPLVDS_BitNumber * 4))
89
90 /* --- CSR Register ---*/
91
92 /* Alias word address of EWUP bit */
93 #define CSR_OFFSET (PWR_OFFSET + 0x04)
94 #define EWUP_BitNumber 0x08
95 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
96
97 /* Alias word address of BRE bit */
98 #define BRE_BitNumber 0x09
99 #define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
100
101 /* ------------------ PWR registers bit mask ------------------------ */
102
103 /* CR register bit mask */
104 #define CR_DS_MASK ((uint32_t)0xFFFFF3FC)
105 #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
106 #define CR_VOS_MASK ((uint32_t)0xFFFF3FFF)
107
108 /* Private macro -------------------------------------------------------------*/
109 /* Private variables ---------------------------------------------------------*/
110 /* Private function prototypes -----------------------------------------------*/
111 /* Private functions ---------------------------------------------------------*/
112
113 /** @defgroup PWR_Private_Functions
114 * @{
115 */
116
117 /** @defgroup PWR_Group1 Backup Domain Access function
118 * @brief Backup Domain Access function
119 *
120 @verbatim
121 ===============================================================================
122 ##### Backup Domain Access function #####
123 ===============================================================================
124 [..]
125 After reset, the backup domain (RTC registers, RTC backup data
126 registers and backup SRAM) is protected against possible unwanted
127 write accesses.
128 To enable access to the RTC Domain and RTC registers, proceed as follows:
129 (+) Enable the Power Controller (PWR) APB1 interface clock using the
130 RCC_APB1PeriphClockCmd() function.
131 (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function.
132
133 @endverbatim
134 * @{
135 */
136
137 /**
138 * @brief Deinitializes the PWR peripheral registers to their default reset values.
139 * @param None
140 * @retval None
141 */
PWR_DeInit(void)142 void PWR_DeInit(void)
143 {
144 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
145 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
146 }
147
148 /**
149 * @brief Enables or disables access to the backup domain (RTC registers, RTC
150 * backup data registers and backup SRAM).
151 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
152 * Backup Domain Access should be kept enabled.
153 * @param NewState: new state of the access to the backup domain.
154 * This parameter can be: ENABLE or DISABLE.
155 * @retval None
156 */
PWR_BackupAccessCmd(FunctionalState NewState)157 void PWR_BackupAccessCmd(FunctionalState NewState)
158 {
159 /* Check the parameters */
160 assert_param(IS_FUNCTIONAL_STATE(NewState));
161
162 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
163 }
164
165 /**
166 * @}
167 */
168
169 /** @defgroup PWR_Group2 PVD configuration functions
170 * @brief PVD configuration functions
171 *
172 @verbatim
173 ===============================================================================
174 ##### PVD configuration functions #####
175 ===============================================================================
176 [..]
177 (+) The PVD is used to monitor the VDD power supply by comparing it to a
178 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
179 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
180 than the PVD threshold. This event is internally connected to the EXTI
181 line16 and can generate an interrupt if enabled through the EXTI registers.
182 (+) The PVD is stopped in Standby mode.
183
184 @endverbatim
185 * @{
186 */
187
188 /**
189 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
190 * @param PWR_PVDLevel: specifies the PVD detection level
191 * This parameter can be one of the following values:
192 * @arg PWR_PVDLevel_0
193 * @arg PWR_PVDLevel_1
194 * @arg PWR_PVDLevel_2
195 * @arg PWR_PVDLevel_3
196 * @arg PWR_PVDLevel_4
197 * @arg PWR_PVDLevel_5
198 * @arg PWR_PVDLevel_6
199 * @arg PWR_PVDLevel_7
200 * @note Refer to the electrical characteristics of your device datasheet for
201 * more details about the voltage threshold corresponding to each
202 * detection level.
203 * @retval None
204 */
PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)205 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
206 {
207 uint32_t tmpreg = 0;
208
209 /* Check the parameters */
210 assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
211
212 tmpreg = PWR->CR;
213
214 /* Clear PLS[7:5] bits */
215 tmpreg &= CR_PLS_MASK;
216
217 /* Set PLS[7:5] bits according to PWR_PVDLevel value */
218 tmpreg |= PWR_PVDLevel;
219
220 /* Store the new value */
221 PWR->CR = tmpreg;
222 }
223
224 /**
225 * @brief Enables or disables the Power Voltage Detector(PVD).
226 * @param NewState: new state of the PVD.
227 * This parameter can be: ENABLE or DISABLE.
228 * @retval None
229 */
PWR_PVDCmd(FunctionalState NewState)230 void PWR_PVDCmd(FunctionalState NewState)
231 {
232 /* Check the parameters */
233 assert_param(IS_FUNCTIONAL_STATE(NewState));
234
235 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
236 }
237
238 /**
239 * @}
240 */
241
242 /** @defgroup PWR_Group3 WakeUp pin configuration functions
243 * @brief WakeUp pin configuration functions
244 *
245 @verbatim
246 ===============================================================================
247 ##### WakeUp pin configuration functions #####
248 ===============================================================================
249 [..]
250 (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
251 forced in input pull down configuration and is active on rising edges.
252 (+) There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
253
254 @endverbatim
255 * @{
256 */
257
258 /**
259 * @brief Enables or disables the WakeUp Pin functionality.
260 * @param NewState: new state of the WakeUp Pin functionality.
261 * This parameter can be: ENABLE or DISABLE.
262 * @retval None
263 */
PWR_WakeUpPinCmd(FunctionalState NewState)264 void PWR_WakeUpPinCmd(FunctionalState NewState)
265 {
266 /* Check the parameters */
267 assert_param(IS_FUNCTIONAL_STATE(NewState));
268
269 *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
270 }
271
272 /**
273 * @}
274 */
275
276 /** @defgroup PWR_Group4 Main and Backup Regulators configuration functions
277 * @brief Main and Backup Regulators configuration functions
278 *
279 @verbatim
280 ===============================================================================
281 ##### Main and Backup Regulators configuration functions #####
282 ===============================================================================
283 [..]
284 (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
285 the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
286 retained even in Standby or VBAT mode when the low power backup regulator
287 is enabled. It can be considered as an internal EEPROM when VBAT is
288 always present. You can use the PWR_BackupRegulatorCmd() function to
289 enable the low power backup regulator and use the PWR_GetFlagStatus
290 (PWR_FLAG_BRR) to check if it is ready or not.
291
292 (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
293 the backup SRAM is powered from VDD which replaces the VBAT power supply to
294 save battery life.
295
296 (+) The backup SRAM is not mass erased by an tamper event. It is read
297 protected to prevent confidential data, such as cryptographic private
298 key, from being accessed. The backup SRAM can be erased only through
299 the Flash interface when a protection level change from level 1 to
300 level 0 is requested.
301 -@- Refer to the description of Read protection (RDP) in the reference manual.
302
303 (+) The main internal regulator can be configured to have a tradeoff between
304 performance and power consumption when the device does not operate at
305 the maximum frequency.
306 (+) For STM32F405xx/407xx and STM32F415xx/417xx Devices, the regulator can be
307 configured on the fly through PWR_MainRegulatorModeConfig() function which
308 configure VOS bit in PWR_CR register:
309 (++) When this bit is set (Regulator voltage output Scale 1 mode selected)
310 the System frequency can go up to 168 MHz.
311 (++) When this bit is reset (Regulator voltage output Scale 2 mode selected)
312 the System frequency can go up to 144 MHz.
313
314 (+) For STM32F42xxx/43xxx Devices, the regulator can be configured through
315 PWR_MainRegulatorModeConfig() function which configure VOS[1:0] bits in
316 PWR_CR register:
317 which configure VOS[1:0] bits in PWR_CR register:
318 (++) When VOS[1:0] = 11 (Regulator voltage output Scale 1 mode selected)
319 the System frequency can go up to 168 MHz.
320 (++) When VOS[1:0] = 10 (Regulator voltage output Scale 2 mode selected)
321 the System frequency can go up to 144 MHz.
322 (++) When VOS[1:0] = 01 (Regulator voltage output Scale 3 mode selected)
323 the System frequency can go up to 120 MHz.
324
325 (+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL
326 is OFF and the HSI or HSE clock source is selected as system clock.
327 The new value programmed is active only when the PLL is ON.
328 When the PLL is OFF, the voltage scale 3 is automatically selected.
329 Refer to the datasheets for more details.
330
331 (+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has
332 2 operating modes available:
333 (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
334 voltage scaling (scale 1, scale 2 or scale 3)
335 (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
336 higher frequency than the normal mode for a given voltage scaling (scale 1,
337 scale 2 or scale 3). This mode is enabled through PWR_OverDriveCmd() function and
338 PWR_OverDriveSWCmd() function, to enter or exit from Over-drive mode please follow
339 the sequence described in Reference manual.
340
341 (+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator
342 supplies a low power voltage to the 1.2V domain, thus preserving the content of registers
343 and internal SRAM. 2 operating modes are available:
344 (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
345 available when the main regulator or the low power regulator is used in Scale 3 or
346 low voltage mode.
347 (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
348 available when the main regulator or the low power regulator is in low voltage mode.
349 This mode is enabled through PWR_UnderDriveCmd() function.
350
351 @endverbatim
352 * @{
353 */
354
355 /**
356 * @brief Enables or disables the Backup Regulator.
357 * @param NewState: new state of the Backup Regulator.
358 * This parameter can be: ENABLE or DISABLE.
359 * @retval None
360 */
PWR_BackupRegulatorCmd(FunctionalState NewState)361 void PWR_BackupRegulatorCmd(FunctionalState NewState)
362 {
363 /* Check the parameters */
364 assert_param(IS_FUNCTIONAL_STATE(NewState));
365
366 *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
367 }
368
369 /**
370 * @brief Configures the main internal regulator output voltage.
371 * @param PWR_Regulator_Voltage: specifies the regulator output voltage to achieve
372 * a tradeoff between performance and power consumption when the device does
373 * not operate at the maximum frequency (refer to the datasheets for more details).
374 * This parameter can be one of the following values:
375 * @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode,
376 * System frequency up to 168 MHz.
377 * @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode,
378 * System frequency up to 144 MHz.
379 * @arg PWR_Regulator_Voltage_Scale3: Regulator voltage output Scale 3 mode,
380 * System frequency up to 120 MHz (only for STM32F42xxx/43xxx devices)
381 * @retval None
382 */
PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)383 void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
384 {
385 uint32_t tmpreg = 0;
386
387 /* Check the parameters */
388 assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
389
390 tmpreg = PWR->CR;
391
392 /* Clear VOS[15:14] bits */
393 tmpreg &= CR_VOS_MASK;
394
395 /* Set VOS[15:14] bits according to PWR_Regulator_Voltage value */
396 tmpreg |= PWR_Regulator_Voltage;
397
398 /* Store the new value */
399 PWR->CR = tmpreg;
400 }
401
402 /**
403 * @brief Enables or disables the Over-Drive.
404 *
405 * @note This function can be used only for STM32F42xxx/STM3243xxx devices.
406 * This mode allows the CPU and the core logic to operate at a higher frequency
407 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
408 *
409 * @note It is recommended to enter or exit Over-drive mode when the application is not running
410 * critical tasks and when the system clock source is either HSI or HSE.
411 * During the Over-drive switch activation, no peripheral clocks should be enabled.
412 * The peripheral clocks must be enabled once the Over-drive mode is activated.
413 *
414 * @param NewState: new state of the Over Drive mode.
415 * This parameter can be: ENABLE or DISABLE.
416 * @retval None
417 */
PWR_OverDriveCmd(FunctionalState NewState)418 void PWR_OverDriveCmd(FunctionalState NewState)
419 {
420 /* Check the parameters */
421 assert_param(IS_FUNCTIONAL_STATE(NewState));
422
423 /* Set/Reset the ODEN bit to enable/disable the Over Drive mode */
424 *(__IO uint32_t *) CR_ODEN_BB = (uint32_t)NewState;
425 }
426
427 /**
428 * @brief Enables or disables the Over-Drive switching.
429 *
430 * @note This function can be used only for STM32F42xxx/STM3243xxx devices.
431 *
432 * @param NewState: new state of the Over Drive switching mode.
433 * This parameter can be: ENABLE or DISABLE.
434 * @retval None
435 */
PWR_OverDriveSWCmd(FunctionalState NewState)436 void PWR_OverDriveSWCmd(FunctionalState NewState)
437 {
438 /* Check the parameters */
439 assert_param(IS_FUNCTIONAL_STATE(NewState));
440
441 /* Set/Reset the ODSWEN bit to enable/disable the Over Drive switching mode */
442 *(__IO uint32_t *) CR_ODSWEN_BB = (uint32_t)NewState;
443 }
444
445 /**
446 * @brief Enables or disables the Under-Drive mode.
447 *
448 * @note This function can be used only for STM32F42xxx/STM3243xxx devices.
449 * @note This mode is enabled only with STOP low power mode.
450 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
451 * mode is only available when the main regulator or the low power regulator
452 * is in low voltage mode
453 *
454 * @note If the Under-drive mode was enabled, it is automatically disabled after
455 * exiting Stop mode.
456 * When the voltage regulator operates in Under-drive mode, an additional
457 * startup delay is induced when waking up from Stop mode.
458 *
459 * @param NewState: new state of the Under Drive mode.
460 * This parameter can be: ENABLE or DISABLE.
461 * @retval None
462 */
PWR_UnderDriveCmd(FunctionalState NewState)463 void PWR_UnderDriveCmd(FunctionalState NewState)
464 {
465 /* Check the parameters */
466 assert_param(IS_FUNCTIONAL_STATE(NewState));
467
468 if (NewState != DISABLE)
469 {
470 /* Set the UDEN[1:0] bits to enable the Under Drive mode */
471 PWR->CR |= (uint32_t)PWR_CR_UDEN;
472 }
473 else
474 {
475 /* Reset the UDEN[1:0] bits to disable the Under Drive mode */
476 PWR->CR &= (uint32_t)(~PWR_CR_UDEN);
477 }
478 }
479
480 /**
481 * @brief Enables or disables the Main Regulator low voltage mode.
482 *
483 * @note This mode is only available for STM32F401xx/STM32F411xx devices.
484 *
485 * @param NewState: new state of the Under Drive mode.
486 * This parameter can be: ENABLE or DISABLE.
487 * @retval None
488 */
PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState)489 void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState)
490 {
491 /* Check the parameters */
492 assert_param(IS_FUNCTIONAL_STATE(NewState));
493
494 if (NewState != DISABLE)
495 {
496 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;
497 }
498 else
499 {
500 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;
501 }
502 }
503
504 /**
505 * @brief Enables or disables the Low Power Regulator low voltage mode.
506 *
507 * @note This mode is only available for STM32F401xx/STM32F411xx devices.
508 *
509 * @param NewState: new state of the Under Drive mode.
510 * This parameter can be: ENABLE or DISABLE.
511 * @retval None
512 */
PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState)513 void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState)
514 {
515 /* Check the parameters */
516 assert_param(IS_FUNCTIONAL_STATE(NewState));
517
518 if (NewState != DISABLE)
519 {
520 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;
521 }
522 else
523 {
524 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
525 }
526 }
527
528 /**
529 * @}
530 */
531
532 /** @defgroup PWR_Group5 FLASH Power Down configuration functions
533 * @brief FLASH Power Down configuration functions
534 *
535 @verbatim
536 ===============================================================================
537 ##### FLASH Power Down configuration functions #####
538 ===============================================================================
539 [..]
540 (+) By setting the FPDS bit in the PWR_CR register by using the
541 PWR_FlashPowerDownCmd() function, the Flash memory also enters power
542 down mode when the device enters Stop mode. When the Flash memory
543 is in power down mode, an additional startup delay is incurred when
544 waking up from Stop mode.
545 @endverbatim
546 * @{
547 */
548
549 /**
550 * @brief Enables or disables the Flash Power Down in STOP mode.
551 * @param NewState: new state of the Flash power mode.
552 * This parameter can be: ENABLE or DISABLE.
553 * @retval None
554 */
PWR_FlashPowerDownCmd(FunctionalState NewState)555 void PWR_FlashPowerDownCmd(FunctionalState NewState)
556 {
557 /* Check the parameters */
558 assert_param(IS_FUNCTIONAL_STATE(NewState));
559
560 *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
561 }
562
563 /**
564 * @}
565 */
566
567 /** @defgroup PWR_Group6 Low Power modes configuration functions
568 * @brief Low Power modes configuration functions
569 *
570 @verbatim
571 ===============================================================================
572 ##### Low Power modes configuration functions #####
573 ===============================================================================
574 [..]
575 The devices feature 3 low-power modes:
576 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
577 (+) Stop mode: all clocks are stopped, regulator running, regulator
578 in low power mode
579 (+) Standby mode: 1.2V domain powered off.
580
581 *** Sleep mode ***
582 ==================
583 [..]
584 (+) Entry:
585 (++) The Sleep mode is entered by using the __WFI() or __WFE() functions.
586 (+) Exit:
587 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
588 controller (NVIC) can wake up the device from Sleep mode.
589
590 *** Stop mode ***
591 =================
592 [..]
593 In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
594 and the HSE RC oscillators are disabled. Internal SRAM and register contents
595 are preserved.
596 The voltage regulator can be configured either in normal or low-power mode.
597 To minimize the consumption In Stop mode, FLASH can be powered off before
598 entering the Stop mode. It can be switched on again by software after exiting
599 the Stop mode using the PWR_FlashPowerDownCmd() function.
600
601 (+) Entry:
602 (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_MainRegulator_ON)
603 function with:
604 (+++) Main regulator ON.
605 (+++) Low Power regulator ON.
606 (+) Exit:
607 (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
608
609 *** Standby mode ***
610 ====================
611 [..]
612 The Standby mode allows to achieve the lowest power consumption. It is based
613 on the Cortex-M4 deepsleep mode, with the voltage regulator disabled.
614 The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
615 the HSE oscillator are also switched off. SRAM and register contents are lost
616 except for the RTC registers, RTC backup registers, backup SRAM and Standby
617 circuitry.
618
619 The voltage regulator is OFF.
620
621 (+) Entry:
622 (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
623 (+) Exit:
624 (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
625 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
626
627 *** Auto-wakeup (AWU) from low-power mode ***
628 =============================================
629 [..]
630 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
631 Wakeup event, a tamper event, a time-stamp event, or a comparator event,
632 without depending on an external interrupt (Auto-wakeup mode).
633
634 (#) RTC auto-wakeup (AWU) from the Stop mode
635
636 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
637 (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
638 or Event modes) using the EXTI_Init() function.
639 (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
640 (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
641 and RTC_AlarmCmd() functions.
642 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
643 is necessary to:
644 (+++) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt
645 or Event modes) using the EXTI_Init() function.
646 (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
647 function
648 (+++) Configure the RTC to detect the tamper or time stamp event using the
649 RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
650 functions.
651 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
652 (+++) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt
653 or Event modes) using the EXTI_Init() function.
654 (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
655 (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
656 RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
657
658 (#) RTC auto-wakeup (AWU) from the Standby mode
659
660 (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
661 (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
662 (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
663 and RTC_AlarmCmd() functions.
664 (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
665 is necessary to:
666 (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
667 function
668 (+++) Configure the RTC to detect the tamper or time stamp event using the
669 RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
670 functions.
671 (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
672 (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
673 (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
674 RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
675
676 @endverbatim
677 * @{
678 */
679
680 /**
681 * @brief Enters STOP mode.
682 *
683 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
684 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
685 * the HSI RC oscillator is selected as system clock.
686 * @note When the voltage regulator operates in low power mode, an additional
687 * startup delay is incurred when waking up from Stop mode.
688 * By keeping the internal regulator ON during Stop mode, the consumption
689 * is higher although the startup time is reduced.
690 *
691 * @param PWR_Regulator: specifies the regulator state in STOP mode.
692 * This parameter can be one of the following values:
693 * @arg PWR_MainRegulator_ON: STOP mode with regulator ON
694 * @arg PWR_LowPowerRegulator_ON: STOP mode with low power regulator ON
695 * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
696 * This parameter can be one of the following values:
697 * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
698 * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
699 * @retval None
700 */
PWR_EnterSTOPMode(uint32_t PWR_Regulator,uint8_t PWR_STOPEntry)701 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
702 {
703 uint32_t tmpreg = 0;
704
705 /* Check the parameters */
706 assert_param(IS_PWR_REGULATOR(PWR_Regulator));
707 assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
708
709 /* Select the regulator state in STOP mode ---------------------------------*/
710 tmpreg = PWR->CR;
711 /* Clear PDDS and LPDS bits */
712 tmpreg &= CR_DS_MASK;
713
714 /* Set LPDS, MRLVDS and LPLVDS bits according to PWR_Regulator value */
715 tmpreg |= PWR_Regulator;
716
717 /* Store the new value */
718 PWR->CR = tmpreg;
719
720 /* Set SLEEPDEEP bit of Cortex System Control Register */
721 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
722
723 /* Select STOP mode entry --------------------------------------------------*/
724 if(PWR_STOPEntry == PWR_STOPEntry_WFI)
725 {
726 /* Request Wait For Interrupt */
727 __WFI();
728 }
729 else
730 {
731 /* Request Wait For Event */
732 __WFE();
733 }
734 /* Reset SLEEPDEEP bit of Cortex System Control Register */
735 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
736 }
737
738 /**
739 * @brief Enters in Under-Drive STOP mode.
740 *
741 * @note This mode is only available for STM32F42xxx/STM3243xxx devices.
742 *
743 * @note This mode can be selected only when the Under-Drive is already active
744 *
745 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
746 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
747 * the HSI RC oscillator is selected as system clock.
748 * @note When the voltage regulator operates in low power mode, an additional
749 * startup delay is incurred when waking up from Stop mode.
750 * By keeping the internal regulator ON during Stop mode, the consumption
751 * is higher although the startup time is reduced.
752 *
753 * @param PWR_Regulator: specifies the regulator state in STOP mode.
754 * This parameter can be one of the following values:
755 * @arg PWR_MainRegulator_UnderDrive_ON: Main Regulator in under-drive mode
756 * and Flash memory in power-down when the device is in Stop under-drive mode
757 * @arg PWR_LowPowerRegulator_UnderDrive_ON: Low Power Regulator in under-drive mode
758 * and Flash memory in power-down when the device is in Stop under-drive mode
759 * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
760 * This parameter can be one of the following values:
761 * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
762 * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
763 * @retval None
764 */
PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator,uint8_t PWR_STOPEntry)765 void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
766 {
767 uint32_t tmpreg = 0;
768
769 /* Check the parameters */
770 assert_param(IS_PWR_REGULATOR_UNDERDRIVE(PWR_Regulator));
771 assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
772
773 /* Select the regulator state in STOP mode ---------------------------------*/
774 tmpreg = PWR->CR;
775 /* Clear PDDS and LPDS bits */
776 tmpreg &= CR_DS_MASK;
777
778 /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
779 tmpreg |= PWR_Regulator;
780
781 /* Store the new value */
782 PWR->CR = tmpreg;
783
784 /* Set SLEEPDEEP bit of Cortex System Control Register */
785 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
786
787 /* Select STOP mode entry --------------------------------------------------*/
788 if(PWR_STOPEntry == PWR_STOPEntry_WFI)
789 {
790 /* Request Wait For Interrupt */
791 __WFI();
792 }
793 else
794 {
795 /* Request Wait For Event */
796 __WFE();
797 }
798 /* Reset SLEEPDEEP bit of Cortex System Control Register */
799 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
800 }
801
802 /**
803 * @brief Enters STANDBY mode.
804 * @note In Standby mode, all I/O pins are high impedance except for:
805 * - Reset pad (still available)
806 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
807 * Alarm out, or RTC clock calibration out.
808 * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
809 * - WKUP pin 1 (PA0) if enabled.
810 * @note The Wakeup flag (WUF) need to be cleared at application level before to call this function
811 * @param None
812 * @retval None
813 */
PWR_EnterSTANDBYMode(void)814 void PWR_EnterSTANDBYMode(void)
815 {
816 /* Select STANDBY mode */
817 PWR->CR |= PWR_CR_PDDS;
818
819 /* Set SLEEPDEEP bit of Cortex System Control Register */
820 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
821
822 /* This option is used to ensure that store operations are completed */
823 #if defined ( __CC_ARM )
824 __force_stores();
825 #endif
826 /* Request Wait For Interrupt */
827 __WFI();
828 }
829
830 /**
831 * @}
832 */
833
834 /** @defgroup PWR_Group7 Flags management functions
835 * @brief Flags management functions
836 *
837 @verbatim
838 ===============================================================================
839 ##### Flags management functions #####
840 ===============================================================================
841
842 @endverbatim
843 * @{
844 */
845
846 /**
847 * @brief Checks whether the specified PWR flag is set or not.
848 * @param PWR_FLAG: specifies the flag to check.
849 * This parameter can be one of the following values:
850 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
851 * was received from the WKUP pin or from the RTC alarm (Alarm A
852 * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
853 * An additional wakeup event is detected if the WKUP pin is enabled
854 * (by setting the EWUP bit) when the WKUP pin level is already high.
855 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
856 * resumed from StandBy mode.
857 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
858 * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode
859 * For this reason, this bit is equal to 0 after Standby or reset
860 * until the PVDE bit is set.
861 * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
862 * when the device wakes up from Standby mode or by a system reset
863 * or power reset.
864 * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
865 * scaling output selection is ready.
866 * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
867 * is ready (STM32F42xxx/43xxx devices)
868 * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
869 * switcching is ready (STM32F42xxx/43xxx devices)
870 * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
871 * is enabled in Stop mode (STM32F42xxx/43xxx devices)
872 * @retval The new state of PWR_FLAG (SET or RESET).
873 */
PWR_GetFlagStatus(uint32_t PWR_FLAG)874 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
875 {
876 FlagStatus bitstatus = RESET;
877
878 /* Check the parameters */
879 assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
880
881 if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
882 {
883 bitstatus = SET;
884 }
885 else
886 {
887 bitstatus = RESET;
888 }
889 /* Return the flag status */
890 return bitstatus;
891 }
892
893 /**
894 * @brief Clears the PWR's pending flags.
895 * @param PWR_FLAG: specifies the flag to clear.
896 * This parameter can be one of the following values:
897 * @arg PWR_FLAG_WU: Wake Up flag
898 * @arg PWR_FLAG_SB: StandBy flag
899 * @arg PWR_FLAG_UDRDY: Under-drive ready flag (STM32F42xxx/43xxx devices)
900 * @retval None
901 */
PWR_ClearFlag(uint32_t PWR_FLAG)902 void PWR_ClearFlag(uint32_t PWR_FLAG)
903 {
904 /* Check the parameters */
905 assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
906
907 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
908 if (PWR_FLAG != PWR_FLAG_UDRDY)
909 {
910 PWR->CR |= PWR_FLAG << 2;
911 }
912 else
913 {
914 PWR->CSR |= PWR_FLAG_UDRDY;
915 }
916 #endif /* STM32F427_437xx || STM32F429_439xx */
917
918 #if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F411xE)
919 PWR->CR |= PWR_FLAG << 2;
920 #endif /* STM32F40_41xxx || STM32F401xx || STM32F411xE */
921 }
922
923 /**
924 * @}
925 */
926
927 /**
928 * @}
929 */
930
931 /**
932 * @}
933 */
934
935 /**
936 * @}
937 */
938
939 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
940