1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __PLAT_ADDR_MAP_BEST2003_H__ 16 #define __PLAT_ADDR_MAP_BEST2003_H__ 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 #define ROM_BASE 0x00020000 23 #define ROMD_BASE 0x24020000 24 25 #ifndef ROM_SIZE 26 #ifdef FPGA 27 #define ROM_SIZE 0x00020000 28 #else 29 #define ROM_SIZE 0x00010000 30 #endif 31 #endif 32 33 #define RAM0_BASE 0x20000000 34 #define RAMX0_BASE 0x00200000 35 #define RAM1_BASE 0x20040000 36 #define RAMX1_BASE 0x00240000 37 #define RAM2_BASE 0x20080000 38 #define RAMX2_BASE 0x00280000 39 #define RAM3_BASE 0x20100000 40 #define RAMX3_BASE 0x00300000 41 #define RAM4_BASE 0x20180000 42 #define RAMX4_BASE 0x00380000 43 #define RAM5_BASE 0x201C0000 44 #define RAMX5_BASE 0x003C0000 45 #define RAM_BASE RAM0_BASE 46 #define RAMX_BASE RAMX0_BASE 47 48 #define RAM5_SIZE 0x00040000 49 50 /* total ramv size is 0x30000 */ 51 #define RAMV_BASE 0x20200000 52 #ifndef RAMV_SIZE 53 #define RAMV_SIZE 0x00000000 54 #endif 55 56 #ifdef __BT_RAMRUN__ 57 #define BT_RAMRUN_BASE RAM3_BASE 58 #define BT_RAMRUNX_BASE RAMX3_BASE 59 #endif 60 61 #ifndef CP_FLASH_SIZE 62 #define CP_FLASH_SIZE 0 63 #endif 64 65 #ifdef CHIP_HAS_CP 66 #if (CP_FLASH_SIZE > 0) 67 #define CP_FLASH_BASE (FLASH_BASE + FLASH_SIZE - CP_FLASH_SIZE) 68 #define CP_FLASHX_BASE (FLASHX_BASE + FLASH_SIZE - CP_FLASH_SIZE) 69 #endif 70 71 #ifdef LARGE_RAM 72 /*MCU use RAM0/1/2/3, CPX use RAM4, and CP use RAM5*/ 73 #define RAMCP_TOP (RAM5_BASE + RAM5_SIZE) 74 75 #ifndef RAMCP_SIZE 76 #define RAMCP_SIZE RAM5_SIZE 77 #endif 78 79 #ifndef RAMCP_BASE 80 #define RAMCP_BASE (RAMCP_TOP - RAMCP_SIZE) 81 #endif 82 83 #ifndef RAMCPX_SIZE 84 #define RAMCPX_SIZE (RAM5_BASE - RAM4_BASE) 85 #endif 86 87 #ifndef RAMCPX_BASE 88 #define RAMCPX_BASE (RAM_TO_RAMX(RAMCP_BASE) - RAMCPX_SIZE) 89 #endif 90 91 #else /*LARGE_RAM*/ 92 /*MCU use RAM0, CP and CPX use RAM1*/ 93 #define RAMCP_TOP RAM2_BASE 94 95 #ifndef RAMCP_SIZE 96 #define RAMCP_SIZE 0x20000 97 #endif 98 99 #ifndef RAMCP_BASE 100 #define RAMCP_BASE (RAMCP_TOP - RAMCP_SIZE) 101 #endif 102 103 #ifndef RAMCPX_SIZE 104 #define RAMCPX_SIZE (RAMX2_BASE - RAMX1_BASE - RAMCP_SIZE) 105 #endif 106 107 #ifndef RAMCPX_BASE 108 #define RAMCPX_BASE (RAM_TO_RAMX(RAMCP_BASE) - RAMCPX_SIZE) 109 #endif 110 111 #endif /*LARGE_RAM*/ 112 #endif 113 114 #define RAM_TOTAL_SIZE (RAM5_BASE + RAM5_SIZE - RAM0_BASE) // 0x00200000 115 116 #if defined(ARM_CMSE) || defined(ARM_CMNS) 117 #undef RAM_BASE 118 #undef RAMX_BASE 119 120 /*MPC: SRAM block size: 0x8000, FLASH block size 0x40000*/ 121 #ifndef RAM_S_SIZE 122 #define RAM_S_SIZE 0x00020000 123 #endif 124 #define RAM_NSC_SIZE 0 125 #ifndef FLASH_S_SIZE 126 #define FLASH_S_SIZE 0x00040000 127 #endif 128 129 #define RAM_NS_BASE (RAM0_BASE + RAM_S_SIZE) 130 #define RAMX_NS_BASE (RAMX0_BASE + RAM_S_SIZE) 131 132 #if defined(ARM_CMNS) 133 #define RAM_BASE RAM_NS_BASE 134 #define RAMX_BASE RAMX_NS_BASE 135 #else 136 #if ((RAM_S_SIZE) & (0x8000-1)) 137 #error "RAM_S_SIZE should be 0x8000 aligned" 138 #endif 139 #if (FLASH_S_SIZE & (0x40000-1)) 140 #error "FLASH_S_SIZE should be 0x40000 aligned" 141 #endif 142 #define RAM_BASE RAM0_BASE 143 #define RAMX_BASE RAMX0_BASE 144 #define RAM_SIZE RAM_S_SIZE 145 #ifndef NS_APP_START_OFFSET 146 #define NS_APP_START_OFFSET (FLASH_S_SIZE) 147 #endif 148 #ifndef FLASH_REGION_SIZE 149 #define FLASH_REGION_SIZE FLASH_S_SIZE 150 #endif 151 #endif 152 #endif /* defined(ARM_CMSE) || defined(ARM_CMNS) */ 153 154 #ifndef RAM_MCU_SIZE 155 /* secure and non-secure ram size */ 156 #ifdef LARGE_RAM 157 #ifdef CHIP_HAS_CP 158 #define RAM_MCU_SIZE (RAMCPX_BASE - RAMX_BASE) 159 #else 160 #define RAM_MCU_SIZE (RAM5_BASE + RAM5_SIZE - RAM_BASE) 161 #endif 162 #else 163 #ifdef CHIP_HAS_CP 164 #define RAM_MCU_SIZE (RAMCPX_BASE - RAMX_BASE) 165 #else 166 #define RAM_MCU_SIZE (RAM2_BASE - RAM_BASE) // 0x00080000 167 #endif 168 #endif 169 #endif /*RAM_MCU_SIZE*/ 170 171 #if defined(ARM_CMSE) 172 #ifndef RAM_NS_SIZE 173 #define RAM_NS_SIZE (RAM_BASE + RAM_MCU_SIZE - RAM_NS_BASE) 174 #endif /*RAM_NS_SIZE*/ 175 #endif 176 177 #ifndef RAM_SIZE 178 #define RAM_SIZE RAM_MCU_SIZE 179 #endif 180 181 #define FLASH_BASE 0x2C000000 182 #define FLASH_NC_BASE 0x28000000 183 #define FLASHX_BASE 0x0C000000 184 #define FLASHX_NC_BASE 0x08000000 185 #ifndef FLASH1_BASE 186 #define FLASH1_BASE 0x2D000000 187 #define FLASH1_NC_BASE 0x29000000 188 #define FLASH1X_BASE 0x0D000000 189 #define FLASH1X_NC_BASE 0x09000000 190 #endif 191 192 #ifndef PSRAM_BASE 193 #define PSRAM_BASE 0x34000000 194 #endif 195 #define PSRAM_NC_BASE 0x30000000 196 #define PSRAMX_BASE 0x14000000 197 #define PSRAMX_NC_BASE 0x10000000 198 199 #define PSRAMUHS_BASE 0x3C000000 200 #define PSRAMUHS_NC_BASE 0x38000000 201 #define PSRAMUHSX_BASE 0x1C000000 202 #define PSRAMUHSX_NC_BASE 0x18000000 203 204 #define DCACHE_CTRL_BASE 0x27FFA000 205 #define ICACHE_CTRL_BASE 0x27FFC000 206 207 #define CMU_BASE 0x40000000 208 #define MCU_WDT_BASE 0x40001000 209 #define MCU_TIMER0_BASE 0x40002000 210 #define MCU_TIMER1_BASE 0x40003000 211 #define MCU_TIMER2_BASE 0x40004000 212 #define I2C0_BASE 0x40005000 213 #define I2C1_BASE 0x40006000 214 #define SPI_BASE 0x40007000 215 #define SPILCD_BASE 0x40008000 216 #define ISPI_BASE 0x40009000 217 #define SPIPHY_BASE 0x4000A000 218 #define UART0_BASE 0x4000B000 219 #define UART1_BASE 0x4000C000 220 #define UART2_BASE 0x4000D000 221 #define BTPCM_BASE 0x4000E000 222 #define I2S0_BASE 0x4000F000 223 #define SPDIF0_BASE 0x40010000 224 #define TRANSQW_BASE 0x40011000 225 #define TRANSQD_BASE 0x40012000 226 #define TRNG_BASE 0x40013000 227 #define IRDA_BASE 0x40014000 228 #define I2C2_BASE 0x40015000 229 #define UART3_BASE 0x40016000 230 #define I2S1_BASE 0x40017000 231 #define SEC_ENG_BASE 0x40020000 232 #define TRUST_ZONE_BASE 0X40030000 233 #define MPC_PSRAMUHS_BASE 0x40040000 234 #define SPY_PSRAMUHS_BASE 0x40041000 235 #define MPC_IMEM_LO_A7_BASE 0x40042000 236 #define SPY_IMEM_LO_A7_BASE 0x40043000 237 #define MPC_IMEM_HI_A7_BASE 0x40044000 238 #define SPY_IMEM_HI_A7_BASE 0x40045000 239 #define MPC_PSRAM0_BASE 0x40046000 240 #define SPY_PSRAM0_BASE 0x40047000 241 #define MPC_PSRAM1_BASE 0x40048000 242 #define SPY_PSRAM1_BASE 0x40049000 243 #define MPC_PSRAM_A7_BASE 0x4004A000 244 #define SPY_PSRAM_A7_BASE 0x4004B000 245 #define MPC_FLASH0_BASE 0x4004C000 246 #define SPY_FLASH0_BASE 0x4004D000 247 #define MPC_FLASH1_BASE 0x4004E000 248 #define SPY_FLASH1_BASE 0x4004F000 249 #define MPC_ROM0_BASE 0x40050000 250 #define SPY_ROM0_BASE 0x40051000 251 #define MPC_SRAM0_BASE 0x40052000 252 #define SPY_SRAM0_BASE 0x40053000 253 #define MPC_SRAM1_BASE 0x40054000 254 #define SPY_SRAM1_BASE 0x40055000 255 #define MPC_SRAM2_BASE 0x40056000 256 #define SPY_SRAM2_BASE 0x40057000 257 #define MPC_SRAM3_BASE 0x40058000 258 #define SPY_SRAM3_BASE 0x40059000 259 #define MPC_SRAM4_BASE 0x4005A000 260 #define SPY_SRAM4_BASE 0x4005B000 261 #define MPC_SRAM5_BASE 0x4005C000 262 #define SPY_SRAM5_BASE 0x4005D000 263 264 #define AON_CMU_BASE 0x40080000 265 #define AON_GPIO_BASE 0x40081000 266 #define AON_WDT_BASE 0x40082000 267 #define AON_PWM0_BASE 0x40083000 268 #define AON_TIMER_BASE 0x40084000 269 #define AON_IOMUX_BASE 0x40086000 270 #define AON_PSC_BASE 0x40088000 271 #define AON_PWM1_BASE 0x40089000 272 273 #define CHECKSUM_BASE 0x40100000 274 #define CRC_BASE 0x40108000 275 #define SDMMC_BASE 0x40110000 276 #define BES2003_AUDMA_BASE 0x40120000 277 #define BES2003_GPDMA_BASE 0x40130000 278 #define FLASH_CTRL_BASE 0x40140000 279 #define FLASH1_CTRL_BASE 0x40148000 280 #define PSRAM_CTRL_BASE 0x40150000 281 #define I2C_SLAVE_BASE 0x40160000 282 #define WFDUMP_BASE 0x40170000 283 #define USB_BASE 0x40180000 284 #define SEDMA_BASE 0x401D0000 285 #define BTDUMP_BASE 0x401E0000 286 #define PSRAMUHS_CTRL_BASE 0x401F0000 287 288 #define CODEC_BASE 0x40380000 289 290 #define PATCH_ENTRY_NUM 8 291 #define PATCH_CTRL_BASE 0x000FFE00 292 #define PATCH_DATA_BASE 0x000FFF00 293 #define WIFI_PATCH_CTRL_BASE 0x60040000 294 #define WIFI_PATCH_DATA_BASE 0x60040200 295 296 #define BT_SUBSYS_BASE 0xA0000000 297 #define BT_RAM_BASE 0xC0000000 298 #define BT_RAM_SIZE 0x00008000 299 #define BT_UART_BASE 0xD0300000 300 #define BT_CMU_BASE 0xD0330000 301 302 #define WIFI_SUBSYS_BASE 0x60000000 303 #define WIFI_RAM_BASE 0x80000000 304 #define WIFI_PAS_BASE 0x82000000 305 #define WIFI_TRANSQM_BASE 0x9000A000 306 #define WIFI_CMU_BASE 0x90000000 307 308 #define DSP_SUBSYS_BASE 0x50000000 309 310 #define DSP_BOOT_BASE 0x00000000 311 #define DSP_BOOT_SIZE (24 * 4) 312 313 #define DSP_RAM0_BASE 0x50000000 314 #define DSP_RAM1_BASE 0x50040000 315 #define DSP_RAM2_BASE 0x50080000 316 #define DSP_RAM3_BASE 0x50100000 317 #define DSP_RAM4_BASE 0x50180000 318 #define DSP_RAM5_BASE 0x501C0000 319 #define DSP_RAM_BASE DSP_RAM0_BASE 320 321 #define DSP_RAM5_SIZE 0x00040000 322 323 #define MAX_DSP_RAM_SIZE (DSP_RAM5_BASE + DSP_RAM5_SIZE - DSP_RAM1_BASE) 324 325 #ifndef DSP_RAM_SIZE 326 #ifdef LARGE_DSP_RAM 327 #define DSP_RAM_SIZE MAX_DSP_RAM_SIZE 328 #else /*LARGE_DSP_RAM*/ 329 #ifdef FPGA 330 #define DSP_RAM_SIZE (DSP_RAM1_BASE - DSP_RAM0_BASE) 331 #else /*FPGA*/ 332 #define DSP_RAM_SIZE (DSP_RAM3_BASE - DSP_RAM0_BASE) 333 #endif /*FPGA*/ 334 #endif /*LARGE_DSP_RAM*/ 335 #endif 336 337 #define GPV_MAIN_BASE 0x50300000 338 #define GPV_PSRAM1G_BASE 0x50400000 339 340 #define DSP_BOOT_REG 0x58000000 341 #define DSP_WDT_BASE 0x58001000 342 #define DSP_TIMER0_BASE 0x58002000 343 #define DSP_TIMER1_BASE 0x58003000 344 #define DSP_TRANSQM_BASE 0x58004000 345 #define DSP_TIMESTAMP_GEN_BASE 0x58020000 346 347 #define DSI_BASE 0x58005000 348 #define CSI_BASE 0x58006000 349 #define LCDC_BASE 0x58100000 350 351 #define DSP_DEBUGSYS_APB_BASE 0x58040000 352 353 #define DSP_XDMA_BASE 0x58200000 354 355 #define GIC_DISTRIBUTOR_BASE 0x58301000 356 #define GIC_INTERFACE_BASE 0x58302000 357 358 #define IOMUX_BASE AON_IOMUX_BASE 359 #define GPIO_BASE AON_GPIO_BASE 360 #define PWM_BASE AON_PWM0_BASE 361 #define PWM1_BASE AON_PWM1_BASE 362 363 #ifdef CHIP_BEST2003_DSP 364 #define TIMER0_BASE DSP_TIMER0_BASE 365 #define TIMER1_BASE DSP_TIMER1_BASE 366 #define TRANSQ0_BASE TRANSQW_BASE 367 #define TRANSQ0_PEER_BASE WIFI_TRANSQM_BASE 368 #define TRANSQ1_BASE DSP_TRANSQM_BASE 369 #define TRANSQ1_PEER_BASE TRANSQD_BASE 370 #define WDT_BASE DSP_WDT_BASE 371 #else 372 #define TIMER0_BASE MCU_TIMER0_BASE 373 #define TIMER1_BASE MCU_TIMER1_BASE 374 #define TIMER2_BASE MCU_TIMER2_BASE 375 #define TRANSQ0_BASE TRANSQW_BASE 376 #define TRANSQ0_PEER_BASE WIFI_TRANSQM_BASE 377 #define TRANSQ1_BASE TRANSQD_BASE 378 #define TRANSQ1_PEER_BASE DSP_TRANSQM_BASE 379 #define WDT_BASE AON_WDT_BASE 380 #endif 381 382 #ifndef DSP_USE_GPDMA 383 #define AUDMA_BASE BES2003_AUDMA_BASE 384 #define GPDMA_BASE BES2003_GPDMA_BASE 385 #else /*DSP_USE_GPDMA*/ 386 #ifdef CHIP_BEST2003_DSP 387 #define AUDMA_BASE BES2003_GPDMA_BASE //A7 use GPDMA 388 #else 389 #define AUDMA_BASE BES2003_AUDMA_BASE //MCU use AUDMA 390 #endif 391 #endif /*DSP_USE_GPDMA*/ 392 393 /* For linker scripts */ 394 #define VECTOR_SECTION_SIZE 360 395 #define REBOOT_PARAM_SECTION_SIZE 64 396 #define ROM_BUILD_INFO_SECTION_SIZE 40 397 #define ROM_EXPORT_FN_SECTION_SIZE 128 398 399 #define PSRAMX_TO_PSRAM(d) ((d) - PSRAMX_BASE + PSRAM_BASE) 400 #define PSRAM_TO_PSRAMX(d) ((d) - PSRAM_BASE + PSRAMX_BASE) 401 402 #define PSRAMUHSX_TO_PSRAMUHS(d) ((d) - PSRAMUHSX_BASE + PSRAMUHS_BASE) 403 #define PSRAMUHS_TO_PSRAMUHSX(d) ((d) - PSRAMUHS_BASE + PSRAMUHSX_BASE) 404 405 #define RAMCP_TO_RAMCPX(d) ((d) - (RAMCP_BASE) + (RAMCPX_BASE)) 406 #define RAMCPX_TO_RAMCP(d) ((d) - (RAMCPX_BASE) + (RAMCP_BASE)) 407 408 #define BT_INTESYS_MEM_OFFSET 0x00004000 409 410 /* For module features */ 411 #define I2S_TX_MULTI_CHAN 412 #define I2S_RX_MULTI_CHAN 413 #define SEC_ENG_HAS_HASH 414 415 /* For boot struct version */ 416 #ifndef SECURE_BOOT_VER 417 #define SECURE_BOOT_VER 4 418 #endif 419 420 #ifndef DSP_PSRAMUHS_SIZE 421 #define DSP_PSRAMUHS_SIZE (0) 422 #endif 423 424 #ifndef MCU_PSRAMUHS_SIZE 425 #define MCU_PSRAMUHS_SIZE (0) 426 #endif 427 428 #define DSP_PSRAMUHS_BASE (PSRAMUHS_BASE) 429 #define DSP_PSRAMUHS_NC_BASE (PSRAMUHS_NC_BASE) 430 #define DSP_PSRAMUHSX_BASE (PSRAMUHSX_BASE) 431 432 #define MCU_PSRAMUHS_BASE (PSRAMUHS_BASE + DSP_PSRAMUHS_SIZE) 433 #define MCU_PSRAMUHS_NC_BASE (PSRAMUHS_NC_BASE + DSP_PSRAMUHS_SIZE) 434 #define MCU_PSRAMUHSX_BASE (PSRAMUHSX_BASE + DSP_PSRAMUHS_SIZE) 435 436 #define PSRAMCP_BASE (PSRAM_BASE + PSRAM_SIZE) 437 #define PSRAMCPX_BASE (PSRAMX_BASE + PSRAM_SIZE) 438 439 #define PSRAMFS_BASE (PSRAM_BASE + MCU_PSRAM_SIZE + PSRAMCP_SIZE) 440 441 /* For ROM export functions */ 442 #define NO_MEMMOVE 443 444 #ifdef __cplusplus 445 } 446 #endif 447 448 #endif 449