1 /* 2 * include/linux/amlogic/media/utils/vdec_reg.h 3 * 4 * Copyright (C) 2017 Amlogic, Inc. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 */ 17 18 #ifndef VDEC_REG_H 19 #define VDEC_REG_H 20 21 #include <linux/kernel.h> 22 #include <linux/amlogic/media/video_sink/video.h> 23 #include <linux/amlogic/iomap.h> 24 #include <linux/io.h> 25 #include <linux/amlogic/media/registers/register.h> 26 #include <linux/amlogic/media/registers/register_ops.h> 27 28 #define READ_DMCREG(r) codec_dmcbus_read(r) 29 #define WRITE_DMCREG(r, val) codec_dmcbus_write(r, val) 30 31 #define READ_AOREG(r) codec_aobus_read(r) 32 #define WRITE_AOREG(r, val) codec_aobus_write(r, val) 33 34 #define READ_VREG(r) codec_dosbus_read(r) 35 #define WRITE_VREG(r, val) codec_dosbus_write(r, val) 36 37 #define BASE_IRQ 32 38 #define AM_IRQ(reg) (reg + BASE_IRQ) 39 #define INT_DOS_MAILBOX_0 AM_IRQ(43) 40 #define INT_DOS_MAILBOX_1 AM_IRQ(44) 41 #define INT_DOS_MAILBOX_2 AM_IRQ(45) 42 #define INT_VIU_VSYNC AM_IRQ(3) 43 44 #define INT_DEMUX AM_IRQ(23) 45 #define INT_DEMUX_1 AM_IRQ(5) 46 #define INT_DEMUX_2 AM_IRQ(53) 47 #define INT_ASYNC_FIFO_FILL AM_IRQ(18) 48 #define INT_ASYNC_FIFO_FLUSH AM_IRQ(19) 49 #define INT_ASYNC_FIFO2_FILL AM_IRQ(24) 50 #define INT_ASYNC_FIFO2_FLUSH AM_IRQ(25) 51 52 #define INT_PARSER AM_IRQ(32) 53 54 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ 55 56 /* 57 *#define READ_AOREG(r) (__raw_readl((volatile void __iomem *)\ 58 *AOBUS_REG_ADDR(r))) 59 */ 60 61 /* 62 *#define WRITE_AOREG(r, val) __raw_writel(val,\ 63 * (volatile void __iomem *)(AOBUS_REG_ADDR(r)))' 64 */ 65 66 /* aml_read_vcbus(unsigned int reg) */ 67 #define INT_VDEC INT_DOS_MAILBOX_1 68 #define INT_VDEC2 INT_DOS_MAILBOX_0 69 70 /* #else */ 71 72 /* /#define INT_VDEC INT_MAILBOX_1A */ 73 74 /* /#endif */ 75 76 /* static inline u32 READ_VREG(u32 r) */ 77 78 /* { */ 79 80 /* if (((r) > 0x2000) && ((r) < 0x3000) && !vdec_on(2)) dump_stack(); */ 81 82 /* return __raw_readl((volatile void __iomem *)DOS_REG_ADDR(r)); */ 83 84 /* } */ 85 86 /* static inline void WRITE_VREG(u32 r, u32 val) */ 87 88 /* { */ 89 90 /* if (((r) > 0x2000) && ((r) < 0x3000) && !vdec_on(2)) dump_stack(); */ 91 92 /* __raw_writel(val, (volatile void __iomem *)(DOS_REG_ADDR(r))); */ 93 94 /* } */ 95 96 #define WRITE_VREG_BITS(r, val, start, len) \ 97 WRITE_VREG(r, (READ_VREG(r) & ~(((1L<<(len))-1)<<(start)))|\ 98 ((unsigned int)((val)&((1L<<(len))-1)) << (start))) 99 #define SET_VREG_MASK(r, mask) WRITE_VREG(r, READ_VREG(r) | (mask)) 100 #define CLEAR_VREG_MASK(r, mask) WRITE_VREG(r, READ_VREG(r) & ~(mask)) 101 102 #define READ_HREG(r) codec_dosbus_read(r|0x1000) 103 #define WRITE_HREG(r, val) codec_dosbus_write(r|0x1000, val) 104 105 #define WRITE_HREG_BITS(r, val, start, len) \ 106 WRITE_HREG(r, (READ_HREG(r) & ~(((1L<<(len))-1)<<(start)))|\ 107 ((unsigned int)((val)&((1L<<(len))-1)) << (start))) 108 #define SET_HREG_MASK(r, mask) WRITE_HREG(r, READ_HREG(r) | (mask)) 109 #define CLEAR_HREG_MASK(r, mask) WRITE_HREG(r, READ_HREG(r) & ~(mask)) 110 111 /*TODO */ 112 #define READ_SEC_REG(r) 113 #define WRITE_SEC_REG(r, val) 114 #define WRITE_SEC_REG_BITS(r, val, start, len) \ 115 WRITE_SEC_REG(r, (READ_SEC_REG(r) & ~(((1L<<(len))-1)<<(start)))|\ 116 ((unsigned int)((val)&((1L<<(len))-1)) << (start))) 117 118 #define WRITE_MPEG_REG(r, val) codec_cbus_write(r, val) 119 #define READ_MPEG_REG(r) codec_cbus_read(r) 120 #define WRITE_MPEG_REG_BITS(r, val, start, len) \ 121 WRITE_MPEG_REG(r, (READ_MPEG_REG(r) & ~(((1L<<(len))-1)<<(start)))|\ 122 ((unsigned int)((val)&((1L<<(len))-1)) << (start))) 123 124 #define CLEAR_MPEG_REG_MASK(r, mask)\ 125 WRITE_MPEG_REG(r, READ_MPEG_REG(r) & ~(mask)) 126 #define SET_MPEG_REG_MASK(r, mask)\ 127 WRITE_MPEG_REG(r, READ_MPEG_REG(r) | (mask)) 128 129 #define WRITE_PARSER_REG(r, val) codec_parsbus_write(r, val) 130 #define READ_PARSER_REG(r) codec_parsbus_read(r) 131 #define WRITE_PARSER_REG_BITS(r, val, start, len) \ 132 WRITE_PARSER_REG(r, (READ_PARSER_REG(r) & ~(((1L<<(len))-1)<<(start)))|\ 133 ((unsigned int)((val)&((1L<<(len))-1)) << (start))) 134 135 #define CLEAR_PARSER_REG_MASK(r, mask)\ 136 WRITE_PARSER_REG(r, READ_PARSER_REG(r) & ~(mask)) 137 #define SET_PARSER_REG_MASK(r, mask)\ 138 WRITE_PARSER_REG(r, READ_PARSER_REG(r) | (mask)) 139 140 #define WRITE_HHI_REG(r, val) codec_hhibus_write(r, val) 141 #define READ_HHI_REG(r) codec_hhibus_read(r) 142 #define WRITE_HHI_REG_BITS(r, val, start, len) \ 143 WRITE_HHI_REG(r, (READ_HHI_REG(r) & ~(((1L<<(len))-1)<<(start)))|\ 144 ((unsigned int)((val)&((1L<<(len))-1)) << (start))) 145 146 #define WRITE_AIU_REG(r, val) codec_aiubus_write(r, val) 147 #define READ_AIU_REG(r) codec_aiubus_read(r) 148 #define WRITE_AIU_REG_BITS(r, val, start, len) \ 149 WRITE_AIU_REG(r, (READ_AIU_REG(r) & ~(((1L<<(len))-1)<<(start)))|\ 150 ((unsigned int)((val)&((1L<<(len))-1)) << (start))) 151 152 #define CLEAR_AIU_REG_MASK(r, mask)\ 153 WRITE_AIU_REG(r, READ_AIU_REG(r) & ~(mask)) 154 #define SET_AIU_REG_MASK(r, mask)\ 155 WRITE_AIU_REG(r, READ_AIU_REG(r) | (mask)) 156 157 #define WRITE_DEMUX_REG(r, val) codec_demuxbus_write(r, val) 158 #define READ_DEMUX_REG(r) codec_demuxbus_read(r) 159 #define WRITE_DEMUX_REG_BITS(r, val, start, len) \ 160 WRITE_DEMUX_REG(r, (READ_DEMUX_REG(r) & ~(((1L<<(len))-1)<<(start)))|\ 161 ((unsigned int)((val)&((1L<<(len))-1)) << (start))) 162 163 #define CLEAR_DEMUX_REG_MASK(r, mask)\ 164 WRITE_DEMUX_REG(r, READ_DEMUX_REG(r) & ~(mask)) 165 #define SET_DEMUX_REG_MASK(r, mask)\ 166 WRITE_DEMUX_REG(r, READ_DEMUX_REG(r) | (mask)) 167 168 #define WRITE_RESET_REG(r, val) codec_resetbus_write(r, val) 169 #define READ_RESET_REG(r) codec_resetbus_read(r) 170 #define WRITE_RESET_REG_BITS(r, val, start, len) \ 171 WRITE_RESET_REG(r, (READ_RESET_REG(r) & ~(((1L<<(len))-1)<<(start)))|\ 172 ((unsigned int)((val)&((1L<<(len))-1)) << (start))) 173 174 #define CLEAR_RESET_REG_MASK(r, mask)\ 175 WRITE_RESET_REG(r, READ_RESET_REG(r) & ~(mask)) 176 #define SET_RESET_REG_MASK(r, mask)\ 177 WRITE_RESET_REG(r, READ_RESET_REG(r) | (mask)) 178 179 #define WRITE_EFUSE_REG(r, val) codec_efusebus_write(r, val) 180 #define READ_EFUSE_REG(r) codec_efusebus_read(r) 181 #define WRITE_EFUSE_REG_BITS(r, val, start, len) \ 182 WRITE_EFUSE_REG(r, (READ_EFUSE_REG(r) & ~(((1L<<(len))-1)<<(start)))|\ 183 ((unsigned int)((val)&((1L<<(len))-1)) << (start))) 184 185 #define CLEAR_EFUSE_REG_MASK(r, mask)\ 186 WRITE_EFUSE_REG(r, READ_EFUSE_REG(r) & ~(mask)) 187 #define SET_EFUSE_REG_MASK(r, mask)\ 188 WRITE_EFUSE_REG(r, READ_EFUSE_REG(r) | (mask)) 189 190 #define ASSIST_MBOX1_CLR_REG VDEC_ASSIST_MBOX1_CLR_REG 191 #define ASSIST_MBOX1_MASK VDEC_ASSIST_MBOX1_MASK 192 #define ASSIST_AMR1_INT0 VDEC_ASSIST_AMR1_INT0 193 #define ASSIST_AMR1_INT1 VDEC_ASSIST_AMR1_INT1 194 #define ASSIST_AMR1_INT2 VDEC_ASSIST_AMR1_INT2 195 #define ASSIST_AMR1_INT3 VDEC_ASSIST_AMR1_INT3 196 #define ASSIST_AMR1_INT4 VDEC_ASSIST_AMR1_INT4 197 #define ASSIST_AMR1_INT5 VDEC_ASSIST_AMR1_INT5 198 #define ASSIST_AMR1_INT6 VDEC_ASSIST_AMR1_INT6 199 #define ASSIST_AMR1_INT7 VDEC_ASSIST_AMR1_INT7 200 #define ASSIST_AMR1_INT8 VDEC_ASSIST_AMR1_INT8 201 #define ASSIST_AMR1_INT9 VDEC_ASSIST_AMR1_INT9 202 203 /*TODO reg*/ 204 #define READ_VCBUS_REG(r) codec_vcbus_read(r) 205 #define WRITE_VCBUS_REG(r, val) codec_vcbus_write(r, val) 206 #define WRITE_VCBUS_REG_BITS(r, val, start, len)\ 207 WRITE_VCBUS_REG(r, (READ_VCBUS_REG(r) & ~(((1L<<(len))-1)<<(start)))|\ 208 ((unsigned int)((val)&((1L<<(len))-1)) << (start))) 209 #define CLEAR_VCBUS_REG_MASK(r, mask)\ 210 WRITE_VCBUS_REG(r, READ_VCBUS_REG(r) & ~(mask)) 211 #define SET_VCBUS_REG_MASK(r, mask)\ 212 WRITE_VCBUS_REG(r, READ_VCBUS_REG(r) | (mask)) 213 214 /****************logo relative part *****************************************/ 215 #define ASSIST_MBOX1_CLR_REG VDEC_ASSIST_MBOX1_CLR_REG 216 #define ASSIST_MBOX1_MASK VDEC_ASSIST_MBOX1_MASK 217 #define RESET_PSCALE (1<<4) 218 #define RESET_IQIDCT (1<<2) 219 #define RESET_MC (1<<3) 220 #define MEM_BUFCTRL_MANUAL (1<<1) 221 #define MEM_BUFCTRL_INIT (1<<0) 222 #define MEM_LEVEL_CNT_BIT 18 223 #define MEM_FIFO_CNT_BIT 16 224 #define MEM_FILL_ON_LEVEL (1<<10) 225 #define MEM_CTRL_EMPTY_EN (1<<2) 226 #define MEM_CTRL_FILL_EN (1<<1) 227 #define MEM_CTRL_INIT (1<<0) 228 229 230 #ifndef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA 231 #define VSYNC_WR_MPEG_REG(adr, val) WRITE_VCBUS_REG(adr, val) 232 #define VSYNC_RD_MPEG_REG(adr) READ_VCBUS_REG(adr) 233 #define VSYNC_WR_MPEG_REG_BITS(adr, val, start, len) \ 234 WRITE_VCBUS_REG_BITS(adr, val, start, len) 235 #else 236 extern int VSYNC_WR_MPEG_REG_BITS(u32 adr, u32 val, u32 start, u32 len); 237 extern u32 VSYNC_RD_MPEG_REG(u32 adr); 238 extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val); 239 #endif 240 #endif /* VDEC_REG_H */ 241