1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_EWDG_H 10 #define HPM_EWDG_H 11 12 typedef struct { 13 __RW uint32_t CTRL0; /* 0x0: wdog ctrl register 0 14 Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits */ 15 __RW uint32_t CTRL1; /* 0x4: wdog ctrl register 1 16 Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits */ 17 __RW uint32_t OT_INT_VAL; /* 0x8: wdog timeout interrupt counter value */ 18 __RW uint32_t OT_RST_VAL; /* 0xC: wdog timeout reset counter value */ 19 __W uint32_t WDT_REFRESH_REG; /* 0x10: wdog refresh register */ 20 __RW uint32_t WDT_STATUS; /* 0x14: wdog status register */ 21 __RW uint32_t CFG_PROT; /* 0x18: ctrl register protection register */ 22 __RW uint32_t REF_PROT; /* 0x1C: refresh protection register */ 23 __RW uint32_t WDT_EN; /* 0x20: Wdog enable */ 24 __RW uint32_t REF_TIME; /* 0x24: Refresh period value */ 25 } EWDG_Type; 26 27 28 /* Bitfield definition for register: CTRL0 */ 29 /* 30 * CLK_SEL (RW) 31 * 32 * clock select 33 * 0：bus clock 34 * 1：ext clock 35 */ 36 #define EWDG_CTRL0_CLK_SEL_MASK (0x20000000UL) 37 #define EWDG_CTRL0_CLK_SEL_SHIFT (29U) 38 #define EWDG_CTRL0_CLK_SEL_SET(x) (((uint32_t)(x) << EWDG_CTRL0_CLK_SEL_SHIFT) & EWDG_CTRL0_CLK_SEL_MASK) 39 #define EWDG_CTRL0_CLK_SEL_GET(x) (((uint32_t)(x) & EWDG_CTRL0_CLK_SEL_MASK) >> EWDG_CTRL0_CLK_SEL_SHIFT) 40 41 /* 42 * DIV_VALUE (RW) 43 * 44 * clock divider, the clock divider works as 2 ^ div_value for wdt counter 45 */ 46 #define EWDG_CTRL0_DIV_VALUE_MASK (0xE000000UL) 47 #define EWDG_CTRL0_DIV_VALUE_SHIFT (25U) 48 #define EWDG_CTRL0_DIV_VALUE_SET(x) (((uint32_t)(x) << EWDG_CTRL0_DIV_VALUE_SHIFT) & EWDG_CTRL0_DIV_VALUE_MASK) 49 #define EWDG_CTRL0_DIV_VALUE_GET(x) (((uint32_t)(x) & EWDG_CTRL0_DIV_VALUE_MASK) >> EWDG_CTRL0_DIV_VALUE_SHIFT) 50 51 /* 52 * WIN_EN (RW) 53 * 54 * window mode enable 55 */ 56 #define EWDG_CTRL0_WIN_EN_MASK (0x1000000UL) 57 #define EWDG_CTRL0_WIN_EN_SHIFT (24U) 58 #define EWDG_CTRL0_WIN_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_EN_SHIFT) & EWDG_CTRL0_WIN_EN_MASK) 59 #define EWDG_CTRL0_WIN_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_EN_MASK) >> EWDG_CTRL0_WIN_EN_SHIFT) 60 61 /* 62 * WIN_LOWER (RW) 63 * 64 * Once window mode is opened, the lower counter value to refresh wdt 65 * 00: 4/8 overtime value 66 * 01: 5/8 of overtime value 67 * 10: 6/8 of overtime value 68 * 11: 7/8 of overtime value 69 */ 70 #define EWDG_CTRL0_WIN_LOWER_MASK (0xC00000UL) 71 #define EWDG_CTRL0_WIN_LOWER_SHIFT (22U) 72 #define EWDG_CTRL0_WIN_LOWER_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_LOWER_SHIFT) & EWDG_CTRL0_WIN_LOWER_MASK) 73 #define EWDG_CTRL0_WIN_LOWER_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_LOWER_MASK) >> EWDG_CTRL0_WIN_LOWER_SHIFT) 74 75 /* 76 * CFG_LOCK (RW) 77 * 78 * The register is locked and unlock is needed before re-config registers 79 * Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. 80 * The register update needs to be finished in the required period defined by UPD_OT_TIME register 81 */ 82 #define EWDG_CTRL0_CFG_LOCK_MASK (0x200000UL) 83 #define EWDG_CTRL0_CFG_LOCK_SHIFT (21U) 84 #define EWDG_CTRL0_CFG_LOCK_SET(x) (((uint32_t)(x) << EWDG_CTRL0_CFG_LOCK_SHIFT) & EWDG_CTRL0_CFG_LOCK_MASK) 85 #define EWDG_CTRL0_CFG_LOCK_GET(x) (((uint32_t)(x) & EWDG_CTRL0_CFG_LOCK_MASK) >> EWDG_CTRL0_CFG_LOCK_SHIFT) 86 87 /* 88 * OT_SELF_CLEAR (RW) 89 * 90 * overtime reset can be self released after 32 function cycles 91 */ 92 #define EWDG_CTRL0_OT_SELF_CLEAR_MASK (0x20000UL) 93 #define EWDG_CTRL0_OT_SELF_CLEAR_SHIFT (17U) 94 #define EWDG_CTRL0_OT_SELF_CLEAR_SET(x) (((uint32_t)(x) << EWDG_CTRL0_OT_SELF_CLEAR_SHIFT) & EWDG_CTRL0_OT_SELF_CLEAR_MASK) 95 #define EWDG_CTRL0_OT_SELF_CLEAR_GET(x) (((uint32_t)(x) & EWDG_CTRL0_OT_SELF_CLEAR_MASK) >> EWDG_CTRL0_OT_SELF_CLEAR_SHIFT) 96 97 /* 98 * REF_OT_REQ (RW) 99 * 100 * If refresh event has to be limited into a period after refresh unlocked. 101 * Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter 102 */ 103 #define EWDG_CTRL0_REF_OT_REQ_MASK (0x8000U) 104 #define EWDG_CTRL0_REF_OT_REQ_SHIFT (15U) 105 #define EWDG_CTRL0_REF_OT_REQ_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_OT_REQ_SHIFT) & EWDG_CTRL0_REF_OT_REQ_MASK) 106 #define EWDG_CTRL0_REF_OT_REQ_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_OT_REQ_MASK) >> EWDG_CTRL0_REF_OT_REQ_SHIFT) 107 108 /* 109 * WIN_UPPER (RW) 110 * 111 * The upper threshold of window value 112 * The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value 113 * If this register value is zero, then no upper level limitation 114 */ 115 #define EWDG_CTRL0_WIN_UPPER_MASK (0x7000U) 116 #define EWDG_CTRL0_WIN_UPPER_SHIFT (12U) 117 #define EWDG_CTRL0_WIN_UPPER_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_UPPER_SHIFT) & EWDG_CTRL0_WIN_UPPER_MASK) 118 #define EWDG_CTRL0_WIN_UPPER_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_UPPER_MASK) >> EWDG_CTRL0_WIN_UPPER_SHIFT) 119 120 /* 121 * REF_LOCK (RW) 122 * 123 * WDT refresh has to be unlocked firstly once refresh lock is enable. 124 */ 125 #define EWDG_CTRL0_REF_LOCK_MASK (0x20U) 126 #define EWDG_CTRL0_REF_LOCK_SHIFT (5U) 127 #define EWDG_CTRL0_REF_LOCK_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_LOCK_SHIFT) & EWDG_CTRL0_REF_LOCK_MASK) 128 #define EWDG_CTRL0_REF_LOCK_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_LOCK_MASK) >> EWDG_CTRL0_REF_LOCK_SHIFT) 129 130 /* 131 * REF_UNLOCK_MEC (RW) 132 * 133 * Unlock refresh mechanism 134 * 00: the required unlock password is the same with refresh_psd_register 135 * 01: the required unlock password is a ring shift left value of refresh_psd_register 136 * 10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is 137 * 11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1 138 */ 139 #define EWDG_CTRL0_REF_UNLOCK_MEC_MASK (0x18U) 140 #define EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT (3U) 141 #define EWDG_CTRL0_REF_UNLOCK_MEC_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT) & EWDG_CTRL0_REF_UNLOCK_MEC_MASK) 142 #define EWDG_CTRL0_REF_UNLOCK_MEC_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_UNLOCK_MEC_MASK) >> EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT) 143 144 /* 145 * EN_DBG (RW) 146 * 147 * WTD enable or not in debug mode 148 */ 149 #define EWDG_CTRL0_EN_DBG_MASK (0x4U) 150 #define EWDG_CTRL0_EN_DBG_SHIFT (2U) 151 #define EWDG_CTRL0_EN_DBG_SET(x) (((uint32_t)(x) << EWDG_CTRL0_EN_DBG_SHIFT) & EWDG_CTRL0_EN_DBG_MASK) 152 #define EWDG_CTRL0_EN_DBG_GET(x) (((uint32_t)(x) & EWDG_CTRL0_EN_DBG_MASK) >> EWDG_CTRL0_EN_DBG_SHIFT) 153 154 /* 155 * EN_LP (RW) 156 * 157 * WDT enable or not in low power mode 158 * 2'b00: wdt is halted once in low power mode 159 * 2'b01: wdt will work with 1/4 normal clock freq in low power mode 160 * 2'b10: wdt will work with 1/2 normal clock freq in low power mode 161 * 2'b11: wdt will work with normal clock freq in low power mode 162 */ 163 #define EWDG_CTRL0_EN_LP_MASK (0x3U) 164 #define EWDG_CTRL0_EN_LP_SHIFT (0U) 165 #define EWDG_CTRL0_EN_LP_SET(x) (((uint32_t)(x) << EWDG_CTRL0_EN_LP_SHIFT) & EWDG_CTRL0_EN_LP_MASK) 166 #define EWDG_CTRL0_EN_LP_GET(x) (((uint32_t)(x) & EWDG_CTRL0_EN_LP_MASK) >> EWDG_CTRL0_EN_LP_SHIFT) 167 168 /* Bitfield definition for register: CTRL1 */ 169 /* 170 * REF_FAIL_RST_EN (RW) 171 * 172 * Refresh violation will trigger an reset. 173 * These event will be taken as a refresh violation: 174 * 1) Not refresh in the window once window mode is enabled 175 * 2) Not unlock refresh firstly if unlock is required 176 * 3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. 177 * 4) Not write the required word to refresh wdt. 178 */ 179 #define EWDG_CTRL1_REF_FAIL_RST_EN_MASK (0x800000UL) 180 #define EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT (23U) 181 #define EWDG_CTRL1_REF_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_REF_FAIL_RST_EN_MASK) 182 #define EWDG_CTRL1_REF_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_REF_FAIL_RST_EN_MASK) >> EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT) 183 184 /* 185 * REF_FAIL_INT_EN (RW) 186 * 187 * Refresh violation will trigger an interrupt 188 */ 189 #define EWDG_CTRL1_REF_FAIL_INT_EN_MASK (0x400000UL) 190 #define EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT (22U) 191 #define EWDG_CTRL1_REF_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_REF_FAIL_INT_EN_MASK) 192 #define EWDG_CTRL1_REF_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_REF_FAIL_INT_EN_MASK) >> EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT) 193 194 /* 195 * UNL_REF_FAIL_RST_EN (RW) 196 * 197 * Refresh unlock fail will trigger a reset 198 */ 199 #define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK (0x200000UL) 200 #define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT (21U) 201 #define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK) 202 #define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK) >> EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT) 203 204 /* 205 * UNL_REF_FAIL_INT_EN (RW) 206 * 207 * Refresh unlock fail will trigger a interrupt 208 */ 209 #define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK (0x100000UL) 210 #define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT (20U) 211 #define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK) 212 #define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK) >> EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT) 213 214 /* 215 * OT_RST_EN (RW) 216 * 217 * WDT overtime will generate a reset 218 */ 219 #define EWDG_CTRL1_OT_RST_EN_MASK (0x20000UL) 220 #define EWDG_CTRL1_OT_RST_EN_SHIFT (17U) 221 #define EWDG_CTRL1_OT_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_OT_RST_EN_SHIFT) & EWDG_CTRL1_OT_RST_EN_MASK) 222 #define EWDG_CTRL1_OT_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_OT_RST_EN_MASK) >> EWDG_CTRL1_OT_RST_EN_SHIFT) 223 224 /* 225 * OT_INT_EN (RW) 226 * 227 * WDT can generate an interrupt warning before timeout 228 */ 229 #define EWDG_CTRL1_OT_INT_EN_MASK (0x10000UL) 230 #define EWDG_CTRL1_OT_INT_EN_SHIFT (16U) 231 #define EWDG_CTRL1_OT_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_OT_INT_EN_SHIFT) & EWDG_CTRL1_OT_INT_EN_MASK) 232 #define EWDG_CTRL1_OT_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_OT_INT_EN_MASK) >> EWDG_CTRL1_OT_INT_EN_SHIFT) 233 234 /* 235 * CTL_VIO_RST_EN (RW) 236 * 237 * Ctrl update violation will trigger a reset 238 * The violation event is to try updating the locked register before unlock them 239 */ 240 #define EWDG_CTRL1_CTL_VIO_RST_EN_MASK (0x80U) 241 #define EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT (7U) 242 #define EWDG_CTRL1_CTL_VIO_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT) & EWDG_CTRL1_CTL_VIO_RST_EN_MASK) 243 #define EWDG_CTRL1_CTL_VIO_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_CTL_VIO_RST_EN_MASK) >> EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT) 244 245 /* 246 * CTL_VIO_INT_EN (RW) 247 * 248 * Ctrl update violation will trigger a interrupt 249 */ 250 #define EWDG_CTRL1_CTL_VIO_INT_EN_MASK (0x40U) 251 #define EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT (6U) 252 #define EWDG_CTRL1_CTL_VIO_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT) & EWDG_CTRL1_CTL_VIO_INT_EN_MASK) 253 #define EWDG_CTRL1_CTL_VIO_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_CTL_VIO_INT_EN_MASK) >> EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT) 254 255 /* 256 * UNL_CTL_FAIL_RST_EN (RW) 257 * 258 * Unlock register update failure will trigger a reset 259 */ 260 #define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK (0x20U) 261 #define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT (5U) 262 #define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK) 263 #define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK) >> EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT) 264 265 /* 266 * UNL_CTL_FAIL_INT_EN (RW) 267 * 268 * Unlock register update failure will trigger a interrupt 269 */ 270 #define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK (0x10U) 271 #define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT (4U) 272 #define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK) 273 #define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK) >> EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT) 274 275 /* 276 * PARITY_FAIL_RST_EN (RW) 277 * 278 * Parity error will trigger a reset 279 * A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits 280 */ 281 #define EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK (0x8U) 282 #define EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT (3U) 283 #define EWDG_CTRL1_PARITY_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK) 284 #define EWDG_CTRL1_PARITY_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK) >> EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT) 285 286 /* 287 * PARITY_FAIL_INT_EN (RW) 288 * 289 * Parity error will trigger a interrupt 290 */ 291 #define EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK (0x4U) 292 #define EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT (2U) 293 #define EWDG_CTRL1_PARITY_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK) 294 #define EWDG_CTRL1_PARITY_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK) >> EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT) 295 296 /* Bitfield definition for register: OT_INT_VAL */ 297 /* 298 * OT_INT_VAL (RW) 299 * 300 * WDT timeout interrupt value 301 */ 302 #define EWDG_OT_INT_VAL_OT_INT_VAL_MASK (0xFFFFU) 303 #define EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT (0U) 304 #define EWDG_OT_INT_VAL_OT_INT_VAL_SET(x) (((uint32_t)(x) << EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT) & EWDG_OT_INT_VAL_OT_INT_VAL_MASK) 305 #define EWDG_OT_INT_VAL_OT_INT_VAL_GET(x) (((uint32_t)(x) & EWDG_OT_INT_VAL_OT_INT_VAL_MASK) >> EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT) 306 307 /* Bitfield definition for register: OT_RST_VAL */ 308 /* 309 * OT_RST_VAL (RW) 310 * 311 * WDT timeout reset value 312 */ 313 #define EWDG_OT_RST_VAL_OT_RST_VAL_MASK (0xFFFFU) 314 #define EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT (0U) 315 #define EWDG_OT_RST_VAL_OT_RST_VAL_SET(x) (((uint32_t)(x) << EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT) & EWDG_OT_RST_VAL_OT_RST_VAL_MASK) 316 #define EWDG_OT_RST_VAL_OT_RST_VAL_GET(x) (((uint32_t)(x) & EWDG_OT_RST_VAL_OT_RST_VAL_MASK) >> EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT) 317 318 /* Bitfield definition for register: WDT_REFRESH_REG */ 319 /* 320 * WDT_REFRESH_REG (WO) 321 * 322 * Write this register by 32'h5A45_524F to refresh wdog 323 * Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose 324 */ 325 #define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK (0xFFFFFFFFUL) 326 #define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT (0U) 327 #define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SET(x) (((uint32_t)(x) << EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT) & EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK) 328 #define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_GET(x) (((uint32_t)(x) & EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK) >> EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT) 329 330 /* Bitfield definition for register: WDT_STATUS */ 331 /* 332 * PARITY_ERROR (RW) 333 * 334 * parity error 335 * Write one to clear the bit 336 */ 337 #define EWDG_WDT_STATUS_PARITY_ERROR_MASK (0x40U) 338 #define EWDG_WDT_STATUS_PARITY_ERROR_SHIFT (6U) 339 #define EWDG_WDT_STATUS_PARITY_ERROR_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_PARITY_ERROR_SHIFT) & EWDG_WDT_STATUS_PARITY_ERROR_MASK) 340 #define EWDG_WDT_STATUS_PARITY_ERROR_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_PARITY_ERROR_MASK) >> EWDG_WDT_STATUS_PARITY_ERROR_SHIFT) 341 342 /* 343 * OT_RST (RO) 344 * 345 * Timeout happens, a reset will happen once enable bit set 346 * This bit can be cleared only by refreshing wdt or reset 347 */ 348 #define EWDG_WDT_STATUS_OT_RST_MASK (0x20U) 349 #define EWDG_WDT_STATUS_OT_RST_SHIFT (5U) 350 #define EWDG_WDT_STATUS_OT_RST_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_OT_RST_MASK) >> EWDG_WDT_STATUS_OT_RST_SHIFT) 351 352 /* 353 * OT_INT (RO) 354 * 355 * Timeout happens, a interrupt will happen once enable bit set 356 * This bit can be cleared only by refreshing wdt or reset 357 */ 358 #define EWDG_WDT_STATUS_OT_INT_MASK (0x10U) 359 #define EWDG_WDT_STATUS_OT_INT_SHIFT (4U) 360 #define EWDG_WDT_STATUS_OT_INT_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_OT_INT_MASK) >> EWDG_WDT_STATUS_OT_INT_SHIFT) 361 362 /* 363 * CTL_UNL_FAIL (RW) 364 * 365 * Unlock ctrl reg update protection fail 366 * Write one to clear the bit 367 */ 368 #define EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK (0x8U) 369 #define EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT (3U) 370 #define EWDG_WDT_STATUS_CTL_UNL_FAIL_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT) & EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK) 371 #define EWDG_WDT_STATUS_CTL_UNL_FAIL_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK) >> EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT) 372 373 /* 374 * CTL_VIO (RW) 375 * 376 * Violate register update protection mechanism 377 * Write one to clear the bit 378 */ 379 #define EWDG_WDT_STATUS_CTL_VIO_MASK (0x4U) 380 #define EWDG_WDT_STATUS_CTL_VIO_SHIFT (2U) 381 #define EWDG_WDT_STATUS_CTL_VIO_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_CTL_VIO_SHIFT) & EWDG_WDT_STATUS_CTL_VIO_MASK) 382 #define EWDG_WDT_STATUS_CTL_VIO_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_CTL_VIO_MASK) >> EWDG_WDT_STATUS_CTL_VIO_SHIFT) 383 384 /* 385 * REF_UNL_FAIL (RW) 386 * 387 * Refresh unlock fail 388 * Write one to clear the bit 389 */ 390 #define EWDG_WDT_STATUS_REF_UNL_FAIL_MASK (0x2U) 391 #define EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT (1U) 392 #define EWDG_WDT_STATUS_REF_UNL_FAIL_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT) & EWDG_WDT_STATUS_REF_UNL_FAIL_MASK) 393 #define EWDG_WDT_STATUS_REF_UNL_FAIL_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_REF_UNL_FAIL_MASK) >> EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT) 394 395 /* 396 * REF_VIO (RW) 397 * 398 * Refresh fail 399 * Write one to clear the bit 400 */ 401 #define EWDG_WDT_STATUS_REF_VIO_MASK (0x1U) 402 #define EWDG_WDT_STATUS_REF_VIO_SHIFT (0U) 403 #define EWDG_WDT_STATUS_REF_VIO_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_REF_VIO_SHIFT) & EWDG_WDT_STATUS_REF_VIO_MASK) 404 #define EWDG_WDT_STATUS_REF_VIO_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_REF_VIO_MASK) >> EWDG_WDT_STATUS_REF_VIO_SHIFT) 405 406 /* Bitfield definition for register: CFG_PROT */ 407 /* 408 * UPD_OT_TIME (RW) 409 * 410 * The period in which register update has to be in after unlock 411 * The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle 412 */ 413 #define EWDG_CFG_PROT_UPD_OT_TIME_MASK (0xF0000UL) 414 #define EWDG_CFG_PROT_UPD_OT_TIME_SHIFT (16U) 415 #define EWDG_CFG_PROT_UPD_OT_TIME_SET(x) (((uint32_t)(x) << EWDG_CFG_PROT_UPD_OT_TIME_SHIFT) & EWDG_CFG_PROT_UPD_OT_TIME_MASK) 416 #define EWDG_CFG_PROT_UPD_OT_TIME_GET(x) (((uint32_t)(x) & EWDG_CFG_PROT_UPD_OT_TIME_MASK) >> EWDG_CFG_PROT_UPD_OT_TIME_SHIFT) 417 418 /* 419 * UPD_PSD (RW) 420 * 421 * The password of unlocking register update 422 */ 423 #define EWDG_CFG_PROT_UPD_PSD_MASK (0xFFFFU) 424 #define EWDG_CFG_PROT_UPD_PSD_SHIFT (0U) 425 #define EWDG_CFG_PROT_UPD_PSD_SET(x) (((uint32_t)(x) << EWDG_CFG_PROT_UPD_PSD_SHIFT) & EWDG_CFG_PROT_UPD_PSD_MASK) 426 #define EWDG_CFG_PROT_UPD_PSD_GET(x) (((uint32_t)(x) & EWDG_CFG_PROT_UPD_PSD_MASK) >> EWDG_CFG_PROT_UPD_PSD_SHIFT) 427 428 /* Bitfield definition for register: REF_PROT */ 429 /* 430 * REF_UNL_PSD (RW) 431 * 432 * The password to unlock refreshing 433 */ 434 #define EWDG_REF_PROT_REF_UNL_PSD_MASK (0xFFFFU) 435 #define EWDG_REF_PROT_REF_UNL_PSD_SHIFT (0U) 436 #define EWDG_REF_PROT_REF_UNL_PSD_SET(x) (((uint32_t)(x) << EWDG_REF_PROT_REF_UNL_PSD_SHIFT) & EWDG_REF_PROT_REF_UNL_PSD_MASK) 437 #define EWDG_REF_PROT_REF_UNL_PSD_GET(x) (((uint32_t)(x) & EWDG_REF_PROT_REF_UNL_PSD_MASK) >> EWDG_REF_PROT_REF_UNL_PSD_SHIFT) 438 439 /* Bitfield definition for register: WDT_EN */ 440 /* 441 * WDOG_EN (RW) 442 * 443 * Wdog is enabled, the re-written of this register is impacted by enable lock function 444 */ 445 #define EWDG_WDT_EN_WDOG_EN_MASK (0x1U) 446 #define EWDG_WDT_EN_WDOG_EN_SHIFT (0U) 447 #define EWDG_WDT_EN_WDOG_EN_SET(x) (((uint32_t)(x) << EWDG_WDT_EN_WDOG_EN_SHIFT) & EWDG_WDT_EN_WDOG_EN_MASK) 448 #define EWDG_WDT_EN_WDOG_EN_GET(x) (((uint32_t)(x) & EWDG_WDT_EN_WDOG_EN_MASK) >> EWDG_WDT_EN_WDOG_EN_SHIFT) 449 450 /* Bitfield definition for register: REF_TIME */ 451 /* 452 * REFRESH_PERIOD (RW) 453 * 454 * The refresh period after refresh unlocked 455 * Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter 456 */ 457 #define EWDG_REF_TIME_REFRESH_PERIOD_MASK (0xFFFFU) 458 #define EWDG_REF_TIME_REFRESH_PERIOD_SHIFT (0U) 459 #define EWDG_REF_TIME_REFRESH_PERIOD_SET(x) (((uint32_t)(x) << EWDG_REF_TIME_REFRESH_PERIOD_SHIFT) & EWDG_REF_TIME_REFRESH_PERIOD_MASK) 460 #define EWDG_REF_TIME_REFRESH_PERIOD_GET(x) (((uint32_t)(x) & EWDG_REF_TIME_REFRESH_PERIOD_MASK) >> EWDG_REF_TIME_REFRESH_PERIOD_SHIFT) 461 462 463 464 465 #endif /* HPM_EWDG_H */ 466