1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_CAN_H 10 #define HPM_CAN_H 11 12 typedef struct { 13 __RW uint32_t RBUF[20]; /* 0x0 - 0x4C: receive buffer registers and reception time stamp */ 14 __RW uint32_t TBUF[18]; /* 0x50 - 0x94: transmit buffer register */ 15 __R uint32_t TTS[2]; /* 0x98 - 0x9C: transmission time stamp, LSB 32bit */ 16 __RW uint32_t CMD_STA_CMD_CTRL; /* 0xA0: config, status, command and control bits */ 17 __RW uint8_t RTIE; /* 0xA4: Receive and Transmit Interrupt Enable Register RTIE */ 18 __W uint8_t RTIF; /* 0xA5: Receive and Transmit Interrupt Flag Register RTIF (0xa5) */ 19 __RW uint8_t ERRINT; /* 0xA6: ERRor INTerrupt Enable and Flag Register ERRINT */ 20 __RW uint8_t LIMIT; /* 0xA7: Warning Limits Register LIMIT */ 21 __RW uint32_t S_PRESC; /* 0xA8: Bit Timing Register(Slow Speed) */ 22 __RW uint32_t F_PRESC; /* 0xAC: Bit Timing Register(Fast Speed) */ 23 __R uint8_t EALCAP; /* 0xB0: Error and Arbitration Lost Capture Register EALCAP */ 24 __RW uint8_t TDC; /* 0xB1: Transmitter Delay Compensation Register TDC */ 25 __R uint8_t RECNT; /* 0xB2: Error Counter Registers RECNT */ 26 __R uint8_t TECNT; /* 0xB3: Error Counter Registers TECNT */ 27 __RW uint8_t ACFCTRL; /* 0xB4: Acceptance Filter Control Register ACFCTRL */ 28 __RW uint8_t TIMECFG; /* 0xB5: CiA 603 Time-Stamping TIMECFG */ 29 __RW uint16_t ACF_EN; /* 0xB6: Acceptance Filter Enable ACF_EN */ 30 __RW uint32_t ACF; /* 0xB8: Acceptance CODE ACODE or ACMASK */ 31 __RW uint16_t VER; /* 0xBC: Version Information VER */ 32 __RW uint8_t TBSLOT; /* 0xBE: TTCAN: TB Slot Pointer TBSLOT */ 33 __RW uint8_t TTCFG; /* 0xBF: TTCAN: Time Trigger Configuration TTCFG */ 34 __RW uint32_t REF_MSG; /* 0xC0: TTCAN: Reference Message REF_MSG */ 35 __RW uint16_t TRIG_CFG; /* 0xC4: TTCAN: Trigger Configuration TRIG_CFG */ 36 __RW uint16_t TT_TRIG; /* 0xC6: TTCAN: Trigger Time TT_TRIG */ 37 __RW uint16_t TT_WTRIG; /* 0xC8: TTCAN: Watch Trigger Time TT_WTRIG */ 38 } CAN_Type; 39 40 41 /* Bitfield definition for register array: RBUF */ 42 /* 43 * RBUF (RW) 44 * 45 * receive buffer 46 */ 47 #define CAN_RBUF_RBUF_MASK (0xFFFFFFFFUL) 48 #define CAN_RBUF_RBUF_SHIFT (0U) 49 #define CAN_RBUF_RBUF_SET(x) (((uint32_t)(x) << CAN_RBUF_RBUF_SHIFT) & CAN_RBUF_RBUF_MASK) 50 #define CAN_RBUF_RBUF_GET(x) (((uint32_t)(x) & CAN_RBUF_RBUF_MASK) >> CAN_RBUF_RBUF_SHIFT) 51 52 /* Bitfield definition for register array: TBUF */ 53 /* 54 * TBUF (RW) 55 * 56 * transmit buffer 57 */ 58 #define CAN_TBUF_TBUF_MASK (0xFFFFFFFFUL) 59 #define CAN_TBUF_TBUF_SHIFT (0U) 60 #define CAN_TBUF_TBUF_SET(x) (((uint32_t)(x) << CAN_TBUF_TBUF_SHIFT) & CAN_TBUF_TBUF_MASK) 61 #define CAN_TBUF_TBUF_GET(x) (((uint32_t)(x) & CAN_TBUF_TBUF_MASK) >> CAN_TBUF_TBUF_SHIFT) 62 63 /* Bitfield definition for register array: TTS */ 64 /* 65 * TTS_WRD0 (RO) 66 * 67 * transmission time stamp, word 0, LSB 32bit 68 */ 69 #define CAN_TTS_TTS_WRD0_MASK (0xFFFFFFFFUL) 70 #define CAN_TTS_TTS_WRD0_SHIFT (0U) 71 #define CAN_TTS_TTS_WRD0_GET(x) (((uint32_t)(x) & CAN_TTS_TTS_WRD0_MASK) >> CAN_TTS_TTS_WRD0_SHIFT) 72 73 /* Bitfield definition for register: CMD_STA_CMD_CTRL */ 74 /* 75 * SACK (RW) 76 * 77 * Self-ACKnowledge 78 * 0 – no self-ACK 79 * 1 – self-ACK when LBME=1 80 */ 81 #define CAN_CMD_STA_CMD_CTRL_SACK_MASK (0x80000000UL) 82 #define CAN_CMD_STA_CMD_CTRL_SACK_SHIFT (31U) 83 #define CAN_CMD_STA_CMD_CTRL_SACK_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_SACK_SHIFT) & CAN_CMD_STA_CMD_CTRL_SACK_MASK) 84 #define CAN_CMD_STA_CMD_CTRL_SACK_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_SACK_MASK) >> CAN_CMD_STA_CMD_CTRL_SACK_SHIFT) 85 86 /* 87 * ROM (RW) 88 * 89 * Receive buffer Overflow Mode 90 * In case of a full RBUF when a new message is received, then ROM selects the following: 91 * 1 – The new message will not be stored. 92 * 0 – The oldest message will be overwritten. 93 */ 94 #define CAN_CMD_STA_CMD_CTRL_ROM_MASK (0x40000000UL) 95 #define CAN_CMD_STA_CMD_CTRL_ROM_SHIFT (30U) 96 #define CAN_CMD_STA_CMD_CTRL_ROM_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_ROM_SHIFT) & CAN_CMD_STA_CMD_CTRL_ROM_MASK) 97 #define CAN_CMD_STA_CMD_CTRL_ROM_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_ROM_MASK) >> CAN_CMD_STA_CMD_CTRL_ROM_SHIFT) 98 99 /* 100 * ROV (RO) 101 * 102 * Receive buffer OVerflow 103 * 1 – Overflow. At least one message is lost. 104 * 0 – No Overflow. 105 * ROV is cleared by setting RREL=1. 106 */ 107 #define CAN_CMD_STA_CMD_CTRL_ROV_MASK (0x20000000UL) 108 #define CAN_CMD_STA_CMD_CTRL_ROV_SHIFT (29U) 109 #define CAN_CMD_STA_CMD_CTRL_ROV_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_ROV_MASK) >> CAN_CMD_STA_CMD_CTRL_ROV_SHIFT) 110 111 /* 112 * RREL (RW) 113 * 114 * Receive buffer RELease 115 * The host controller has read the actual RB slot and releases it. Afterwards the CAN-CTRL 116 * core points to the next RB slot. RSTAT gets updated. 117 * 1 – Release: The host has read the RB. 118 * 0 – No release 119 */ 120 #define CAN_CMD_STA_CMD_CTRL_RREL_MASK (0x10000000UL) 121 #define CAN_CMD_STA_CMD_CTRL_RREL_SHIFT (28U) 122 #define CAN_CMD_STA_CMD_CTRL_RREL_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_RREL_SHIFT) & CAN_CMD_STA_CMD_CTRL_RREL_MASK) 123 #define CAN_CMD_STA_CMD_CTRL_RREL_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RREL_MASK) >> CAN_CMD_STA_CMD_CTRL_RREL_SHIFT) 124 125 /* 126 * RBALL (RW) 127 * 128 * Receive Buffer stores ALL data frames 129 * 0 – normal operation 130 * 1 – RB stores correct data frames as well as data frames with error 131 */ 132 #define CAN_CMD_STA_CMD_CTRL_RBALL_MASK (0x8000000UL) 133 #define CAN_CMD_STA_CMD_CTRL_RBALL_SHIFT (27U) 134 #define CAN_CMD_STA_CMD_CTRL_RBALL_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_RBALL_SHIFT) & CAN_CMD_STA_CMD_CTRL_RBALL_MASK) 135 #define CAN_CMD_STA_CMD_CTRL_RBALL_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RBALL_MASK) >> CAN_CMD_STA_CMD_CTRL_RBALL_SHIFT) 136 137 /* 138 * RSTAT (RO) 139 * 140 * Receive buffer STATus 141 * 00 - empty 142 * 01 - > empty and < almost full (AFWL) 143 * 10 - almost full (programmable threshold by AFWL) but not full and no overflow 144 * 11 - full (stays set in case of overflow – for overflow signaling see ROV) 145 */ 146 #define CAN_CMD_STA_CMD_CTRL_RSTAT_MASK (0x3000000UL) 147 #define CAN_CMD_STA_CMD_CTRL_RSTAT_SHIFT (24U) 148 #define CAN_CMD_STA_CMD_CTRL_RSTAT_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RSTAT_MASK) >> CAN_CMD_STA_CMD_CTRL_RSTAT_SHIFT) 149 150 /* 151 * FD_ISO (RW) 152 * 153 * CAN FD ISO mode 154 * 0 - Bosch CAN FD (non-ISO) mode 155 * 1 - ISO CAN FD mode (ISO 11898-1:2015) 156 * ISO CAN FD mode has a different CRC initialization value and an additional stuff bit count. 157 * Both modes are incompatible and must not be mixed in one CAN network. 158 * This bit has no impact to CAN 2.0B. 159 * This bit is only writeable if RESET=1. 160 */ 161 #define CAN_CMD_STA_CMD_CTRL_FD_ISO_MASK (0x800000UL) 162 #define CAN_CMD_STA_CMD_CTRL_FD_ISO_SHIFT (23U) 163 #define CAN_CMD_STA_CMD_CTRL_FD_ISO_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_FD_ISO_SHIFT) & CAN_CMD_STA_CMD_CTRL_FD_ISO_MASK) 164 #define CAN_CMD_STA_CMD_CTRL_FD_ISO_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_FD_ISO_MASK) >> CAN_CMD_STA_CMD_CTRL_FD_ISO_SHIFT) 165 166 /* 167 * TSNEXT (RW) 168 * 169 * Transmit buffer Secondary NEXT 170 * 0 - no action 171 * 1 - STB slot filled, select next slot. 172 * After all frame bytes are written to the TBUF registers, the host controller has to set 173 * TSNEXT to signal that this slot has been filled. Then the CAN-CTRL core connects the TBUF 174 * registers to the next slot. Once a slot is marked as filled a transmission can be started 175 * using TSONE or TSALL. 176 * It is possible to set TSNEXT and TSONE or TSALL together in one write access. 177 * TSNEXT has to be set by the host controller and is automatically reset by the CAN-CTRL 178 * core immediately after it was set. 179 * Setting TSNEXT is meaningless if TBSEL=0. In this case TSNEXT is ignored and 180 * automatically cleared. It does not do any harm. 181 * If all slots of the STB are filled, TSNEXT stays set until a slot becomes free. 182 * TSNEXT has no meaning in TTCAN mode and is fixed to 0. 183 */ 184 #define CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK (0x400000UL) 185 #define CAN_CMD_STA_CMD_CTRL_TSNEXT_SHIFT (22U) 186 #define CAN_CMD_STA_CMD_CTRL_TSNEXT_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSNEXT_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK) 187 #define CAN_CMD_STA_CMD_CTRL_TSNEXT_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK) >> CAN_CMD_STA_CMD_CTRL_TSNEXT_SHIFT) 188 189 /* 190 * TSMODE (RW) 191 * 192 * Transmit buffer Secondary operation MODE 193 * 0 - FIFO mode 194 * 1 - priority decision mode 195 * In FIFO mode frames are transmitted in the order in that they are written into the STB. 196 * In priority decision mode the frame with the highest priority in the STB is automatically 197 * transmitted first. The ID of a frame is used for the priority decision. A lower ID means a 198 * higher priority of a frame. A frame in the PTB has always the highest priority regardless of 199 * the ID. 200 * TSMODE shall be switched only if the STB if empty 201 */ 202 #define CAN_CMD_STA_CMD_CTRL_TSMODE_MASK (0x200000UL) 203 #define CAN_CMD_STA_CMD_CTRL_TSMODE_SHIFT (21U) 204 #define CAN_CMD_STA_CMD_CTRL_TSMODE_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSMODE_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSMODE_MASK) 205 #define CAN_CMD_STA_CMD_CTRL_TSMODE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSMODE_MASK) >> CAN_CMD_STA_CMD_CTRL_TSMODE_SHIFT) 206 207 /* 208 * TTTBM (RW) 209 * 210 * TTCAN Transmit Buffer Mode 211 * If TTEN=0 then TTTBM is ignored, otherwise the following is valid: 212 * 0 - separate PTB and STB, behavior defined by TSMODE 213 * 1 - full TTCAN support: buffer slots selectable by TBPTR and TTPTR 214 * For event-driven CAN communication (TTEN=0), the system provides PTB and STB and 215 * the behavior of the STB is defined by TSMODE. Then TTTBM is ignored. 216 * For time-triggered CAN communication (TTEN=1) with full support of all features including 217 * time-triggered transmissions, TTTBM=1 needs to be chosen. Then the all TB slots are 218 * addressable using TTPTR and TBPTR. 219 * For time-triggered CAN communication (TTEN=1) with only support of reception timestamps, TTTBM=0 can be chosen. Then the transmit buffer acts as in event-driven mode 220 * and the behavior can be selected by TSMODE. 221 * TTTBM shall be switched only if the TBUF is empty. 222 */ 223 #define CAN_CMD_STA_CMD_CTRL_TTTBM_MASK (0x100000UL) 224 #define CAN_CMD_STA_CMD_CTRL_TTTBM_SHIFT (20U) 225 #define CAN_CMD_STA_CMD_CTRL_TTTBM_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TTTBM_SHIFT) & CAN_CMD_STA_CMD_CTRL_TTTBM_MASK) 226 #define CAN_CMD_STA_CMD_CTRL_TTTBM_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TTTBM_MASK) >> CAN_CMD_STA_CMD_CTRL_TTTBM_SHIFT) 227 228 /* 229 * TSSTAT (RO) 230 * 231 * Transmission Secondary STATus bits 232 * If TTEN=0 or TTTBM=0: 233 * 00 – STB is empty 234 * 01 – STB is less than or equal to half full 235 * 10 – STB is more than half full 236 * 11 – STB is full 237 * If the STB is disabled using STB_DISABLE, then TSSTAT=00. 238 * If TTEN=1 and TTTBM=1: 239 * 00 – PTB and STB are empty 240 * 01 – PTB and STB are not empty and not full 241 * 11 – PTB and STB are full 242 */ 243 #define CAN_CMD_STA_CMD_CTRL_TSSTAT_MASK (0x30000UL) 244 #define CAN_CMD_STA_CMD_CTRL_TSSTAT_SHIFT (16U) 245 #define CAN_CMD_STA_CMD_CTRL_TSSTAT_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSSTAT_MASK) >> CAN_CMD_STA_CMD_CTRL_TSSTAT_SHIFT) 246 247 /* 248 * TBSEL (RW) 249 * 250 * Transmit Buffer Select 251 * Selects the transmit buffer to be loaded with a message. Use the TBUF registers for 252 * access. TBSEL needs to be stable all the time the TBUF registers are written and when 253 * TSNEXT is set. 254 * 0 - PTB (high-priority buffer) 255 * 1 - STB 256 * The bit will be reset to the hardware reset value if (TTEN=1 and TTTBM=1) 257 */ 258 #define CAN_CMD_STA_CMD_CTRL_TBSEL_MASK (0x8000U) 259 #define CAN_CMD_STA_CMD_CTRL_TBSEL_SHIFT (15U) 260 #define CAN_CMD_STA_CMD_CTRL_TBSEL_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TBSEL_SHIFT) & CAN_CMD_STA_CMD_CTRL_TBSEL_MASK) 261 #define CAN_CMD_STA_CMD_CTRL_TBSEL_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TBSEL_MASK) >> CAN_CMD_STA_CMD_CTRL_TBSEL_SHIFT) 262 263 /* 264 * LOM (RW) 265 * 266 * Listen Only Mode 267 * 0 - Disabled 268 * 1 - Enabled 269 * LOM cannot be set if TPE, TSONE or TSALL is set. No transmission can be started if LOM 270 * is enabled and LBME is disabled. 271 * LOM=1 and LBME=0 disables all transmissions. 272 * LOM=1 and LBME=1 disables the ACK for received frames and error frames, but enables 273 * the transmission of own frames. 274 */ 275 #define CAN_CMD_STA_CMD_CTRL_LOM_MASK (0x4000U) 276 #define CAN_CMD_STA_CMD_CTRL_LOM_SHIFT (14U) 277 #define CAN_CMD_STA_CMD_CTRL_LOM_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_LOM_SHIFT) & CAN_CMD_STA_CMD_CTRL_LOM_MASK) 278 #define CAN_CMD_STA_CMD_CTRL_LOM_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_LOM_MASK) >> CAN_CMD_STA_CMD_CTRL_LOM_SHIFT) 279 280 /* 281 * STBY (RW) 282 * 283 * Transceiver Standby Mode 284 * 0 - Disabled 285 * 1 - Enabled 286 * This register bit is connected to the output signal stby which can be used to control a 287 * standby mode of a transceiver. 288 * STBY cannot be set to 1 if TPE=1, TSONE=1 or TSALL=1. 289 * If the host sets STBY to 0 then the host needs to wait for the time required by the 290 * transceiver to start up before the host requests a new transmission. 291 */ 292 #define CAN_CMD_STA_CMD_CTRL_STBY_MASK (0x2000U) 293 #define CAN_CMD_STA_CMD_CTRL_STBY_SHIFT (13U) 294 #define CAN_CMD_STA_CMD_CTRL_STBY_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_STBY_SHIFT) & CAN_CMD_STA_CMD_CTRL_STBY_MASK) 295 #define CAN_CMD_STA_CMD_CTRL_STBY_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_STBY_MASK) >> CAN_CMD_STA_CMD_CTRL_STBY_SHIFT) 296 297 /* 298 * TPE (RW) 299 * 300 * Transmit Primary Enable 301 * 1 - Transmission enable for the message in the high-priority PTB 302 * 0 - No transmission for the PTB 303 * If TPE is set, the message from the PTB will be transmitted at the next possible transmit 304 * position. A started transmission from the STB will be completed before, but pending new 305 * messages are delayed until the PTB message has been transmitted. 306 * TPE stays set until the message has been transmitted successfully or it is aborted using 307 * TPA. 308 * The host controller can set TPE to 1 but can not reset it to 0. This would only be possible 309 * using TPA and aborting the message. 310 * The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and 311 * LBME=0) or (TTEN=1 and TTTBM=1). 312 */ 313 #define CAN_CMD_STA_CMD_CTRL_TPE_MASK (0x1000U) 314 #define CAN_CMD_STA_CMD_CTRL_TPE_SHIFT (12U) 315 #define CAN_CMD_STA_CMD_CTRL_TPE_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TPE_SHIFT) & CAN_CMD_STA_CMD_CTRL_TPE_MASK) 316 #define CAN_CMD_STA_CMD_CTRL_TPE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TPE_MASK) >> CAN_CMD_STA_CMD_CTRL_TPE_SHIFT) 317 318 /* 319 * TPA (RW) 320 * 321 * Transmit Primary Abort 322 * 1 – Aborts a transmission from PTB which has been requested by TPE=1 but not 323 * started yet. (The data bytes of the message remains in the PTB.) 324 * 0 – no abort 325 * The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TPA 326 * automatically de-asserts TPE. 327 * The host controller can set TPA to 1 but can not reset it to 0. 328 * During the short time while the CAN-CTRL core resets the bit, it cannot be set by the 329 * host. 330 * The bit will be reset to the hardware reset value if RESET=1 or (TTEN=1 and TTTBM=1). 331 * TPA should not be set simultaneously with TPE. 332 */ 333 #define CAN_CMD_STA_CMD_CTRL_TPA_MASK (0x800U) 334 #define CAN_CMD_STA_CMD_CTRL_TPA_SHIFT (11U) 335 #define CAN_CMD_STA_CMD_CTRL_TPA_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TPA_SHIFT) & CAN_CMD_STA_CMD_CTRL_TPA_MASK) 336 #define CAN_CMD_STA_CMD_CTRL_TPA_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TPA_MASK) >> CAN_CMD_STA_CMD_CTRL_TPA_SHIFT) 337 338 /* 339 * TSONE (RW) 340 * 341 * Transmit Secondary ONE frame 342 * 1 – Transmission enable of one in the STB. In FIFO mode this is the oldest message 343 * and in priority mode this is the one with the highest priority. 344 * TSONE in priority mode is difficult to handle, because it is not always clear which 345 * message will be transmitted if new messages are written to the STB meanwhile. 346 * The controller starts the transmission as soon as the bus becomes vacant and 347 * no request of the PTB (bit TPE) is pending. 348 * 0 – No transmission for the STB. 349 * TSONE stays set until the message has been transmitted successfully or it is aborted 350 * using TSA. 351 * The host controller can set TSONE to 1 but can not reset it to 0. This would only be 352 * possible using TSA and aborting the message. 353 * The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and 354 * LBME=0) or (TTEN=1 and TTTBM=1). 355 */ 356 #define CAN_CMD_STA_CMD_CTRL_TSONE_MASK (0x400U) 357 #define CAN_CMD_STA_CMD_CTRL_TSONE_SHIFT (10U) 358 #define CAN_CMD_STA_CMD_CTRL_TSONE_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSONE_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSONE_MASK) 359 #define CAN_CMD_STA_CMD_CTRL_TSONE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSONE_MASK) >> CAN_CMD_STA_CMD_CTRL_TSONE_SHIFT) 360 361 /* 362 * TSALL (RW) 363 * 364 * Transmit Secondary ALL frames 365 * 1 – Transmission enable of all messages in the STB. 366 * The controller starts the transmission as soon as the bus becomes vacant and 367 * no request of the PTB (bit TPE) is pending. 368 * 0 – No transmission for the STB. 369 * TSALL stays set until all messages have been transmitted successfully or they are aborted 370 * using TSA. 371 * The host controller can set TSALL to 1 but can not reset it to 0. This would only be 372 * possible using TSA and aborting the messages. 373 * The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and 374 * LBME=0) or (TTEN=1 and TTTBM=1). 375 * If during a transmission the STB is loaded with a new frame then the new frame will be 376 * transmitted too. In other words: a transmission initiated by TSALL is finished when the 377 * STB becomes empty. 378 */ 379 #define CAN_CMD_STA_CMD_CTRL_TSALL_MASK (0x200U) 380 #define CAN_CMD_STA_CMD_CTRL_TSALL_SHIFT (9U) 381 #define CAN_CMD_STA_CMD_CTRL_TSALL_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSALL_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSALL_MASK) 382 #define CAN_CMD_STA_CMD_CTRL_TSALL_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSALL_MASK) >> CAN_CMD_STA_CMD_CTRL_TSALL_SHIFT) 383 384 /* 385 * TSA (RW) 386 * 387 * Transmit Secondary Abort 388 * 1 – Aborts a transmission from STB which has been requested but not started yet. 389 * For a TSONE transmission, only one frame is aborted while for a TSALL 390 * Transmission, all frames are aborted. 391 * One or all message slots will be released which updates TSSTAT. 392 * All aborted messages are lost because they are not accessible any more. 393 * If in priority mode a TSONE transmission is aborted, then it is not clear which 394 * frame will be aborted if new frames are written to the STB meanwhile. 395 * 0 – no abort 396 * The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TSA,automatically de-asserts TSONE or TSALL respectively. 397 * The host controller can set TSA to 1 but can not reset it to 0. 398 * The bit will be reset to the hardware reset value if RESET=1. 399 * TSA should not be set simultaneously with TSONE or TSALL. 400 */ 401 #define CAN_CMD_STA_CMD_CTRL_TSA_MASK (0x100U) 402 #define CAN_CMD_STA_CMD_CTRL_TSA_SHIFT (8U) 403 #define CAN_CMD_STA_CMD_CTRL_TSA_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSA_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSA_MASK) 404 #define CAN_CMD_STA_CMD_CTRL_TSA_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSA_MASK) >> CAN_CMD_STA_CMD_CTRL_TSA_SHIFT) 405 406 /* 407 * RESET (RW) 408 * 409 * RESET request bit 410 * 1 - The host controller performs a local reset of CAN-CTRL. 411 * 0 - no local reset of CAN-CTRLThe some register (e.g for node configuration) can only be modified if RESET=1. 412 * Bit RESET forces several components to a reset state. 413 * RESET is automatically set if the node enters “bus off” state. 414 * Note that a CAN node will participate in CAN communication after RESET is switched to 0after 11 CAN bit times. 415 * This delay is required by the CAN standard (bus idle time).If RESET is set to 1 and immediately set to 0, then it takes some time until RESET can beread as 0 and becomes inactive. 416 * The reason is clock domain crossing from host to CAN clockdomain. RESET is held active as long as needed depending on the relation between host andCAN clock. 417 */ 418 #define CAN_CMD_STA_CMD_CTRL_RESET_MASK (0x80U) 419 #define CAN_CMD_STA_CMD_CTRL_RESET_SHIFT (7U) 420 #define CAN_CMD_STA_CMD_CTRL_RESET_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_RESET_SHIFT) & CAN_CMD_STA_CMD_CTRL_RESET_MASK) 421 #define CAN_CMD_STA_CMD_CTRL_RESET_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RESET_MASK) >> CAN_CMD_STA_CMD_CTRL_RESET_SHIFT) 422 423 /* 424 * LBME (RW) 425 * 426 * Loop Back Mode, External 427 * 0 - Disabled 428 * 1 - EnabledLBME should not be enabled while a transmission is active 429 */ 430 #define CAN_CMD_STA_CMD_CTRL_LBME_MASK (0x40U) 431 #define CAN_CMD_STA_CMD_CTRL_LBME_SHIFT (6U) 432 #define CAN_CMD_STA_CMD_CTRL_LBME_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_LBME_SHIFT) & CAN_CMD_STA_CMD_CTRL_LBME_MASK) 433 #define CAN_CMD_STA_CMD_CTRL_LBME_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_LBME_MASK) >> CAN_CMD_STA_CMD_CTRL_LBME_SHIFT) 434 435 /* 436 * LBMI (RW) 437 * 438 * Loop Back Mode, Internal 439 * 0 - Disabled1 - EnabledLBMI should not be enabled while a transmission is active. 440 */ 441 #define CAN_CMD_STA_CMD_CTRL_LBMI_MASK (0x20U) 442 #define CAN_CMD_STA_CMD_CTRL_LBMI_SHIFT (5U) 443 #define CAN_CMD_STA_CMD_CTRL_LBMI_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_LBMI_SHIFT) & CAN_CMD_STA_CMD_CTRL_LBMI_MASK) 444 #define CAN_CMD_STA_CMD_CTRL_LBMI_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_LBMI_MASK) >> CAN_CMD_STA_CMD_CTRL_LBMI_SHIFT) 445 446 /* 447 * TPSS (RW) 448 * 449 * Transmission Primary Single Shot mode for PTB 450 * 0 - Disabled 451 * 1 - Enabled 452 */ 453 #define CAN_CMD_STA_CMD_CTRL_TPSS_MASK (0x10U) 454 #define CAN_CMD_STA_CMD_CTRL_TPSS_SHIFT (4U) 455 #define CAN_CMD_STA_CMD_CTRL_TPSS_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TPSS_SHIFT) & CAN_CMD_STA_CMD_CTRL_TPSS_MASK) 456 #define CAN_CMD_STA_CMD_CTRL_TPSS_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TPSS_MASK) >> CAN_CMD_STA_CMD_CTRL_TPSS_SHIFT) 457 458 /* 459 * TSSS (RW) 460 * 461 * Transmission Secondary Single Shot mode for STB 462 * 0 - Disabled 463 * 1 - Enabled 464 */ 465 #define CAN_CMD_STA_CMD_CTRL_TSSS_MASK (0x8U) 466 #define CAN_CMD_STA_CMD_CTRL_TSSS_SHIFT (3U) 467 #define CAN_CMD_STA_CMD_CTRL_TSSS_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSSS_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSSS_MASK) 468 #define CAN_CMD_STA_CMD_CTRL_TSSS_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSSS_MASK) >> CAN_CMD_STA_CMD_CTRL_TSSS_SHIFT) 469 470 /* 471 * RACTIVE (RO) 472 * 473 * Reception ACTIVE (Receive Status bit) 474 * 1 - The controller is currently receiving a frame. 475 * 0 - No receive activity. 476 */ 477 #define CAN_CMD_STA_CMD_CTRL_RACTIVE_MASK (0x4U) 478 #define CAN_CMD_STA_CMD_CTRL_RACTIVE_SHIFT (2U) 479 #define CAN_CMD_STA_CMD_CTRL_RACTIVE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RACTIVE_MASK) >> CAN_CMD_STA_CMD_CTRL_RACTIVE_SHIFT) 480 481 /* 482 * TACTIVE (RO) 483 * 484 * Transmission ACTIVE (Transmit Status bit) 485 * 1 - The controller is currently transmitting a frame. 486 * 0 - No transmit activity. 487 */ 488 #define CAN_CMD_STA_CMD_CTRL_TACTIVE_MASK (0x2U) 489 #define CAN_CMD_STA_CMD_CTRL_TACTIVE_SHIFT (1U) 490 #define CAN_CMD_STA_CMD_CTRL_TACTIVE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TACTIVE_MASK) >> CAN_CMD_STA_CMD_CTRL_TACTIVE_SHIFT) 491 492 /* 493 * BUSOFF (RW) 494 * 495 * Bus Off (Bus Status bit) 496 * 1 - The controller status is “bus off”. 497 * 0 - The controller status is “bus on”. 498 * Writing a 1 to BUSOFF will reset TECNT and RECNT. This should be done only for debugging. 499 * See Chapter 3.9.10.6 for details. 500 */ 501 #define CAN_CMD_STA_CMD_CTRL_BUSOFF_MASK (0x1U) 502 #define CAN_CMD_STA_CMD_CTRL_BUSOFF_SHIFT (0U) 503 #define CAN_CMD_STA_CMD_CTRL_BUSOFF_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_BUSOFF_SHIFT) & CAN_CMD_STA_CMD_CTRL_BUSOFF_MASK) 504 #define CAN_CMD_STA_CMD_CTRL_BUSOFF_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_BUSOFF_MASK) >> CAN_CMD_STA_CMD_CTRL_BUSOFF_SHIFT) 505 506 /* Bitfield definition for register: RTIE */ 507 /* 508 * RIE (RW) 509 * 510 * Receive Interrupt Enable 511 * 0 – Disabled, 1 – Enabled 512 */ 513 #define CAN_RTIE_RIE_MASK (0x80U) 514 #define CAN_RTIE_RIE_SHIFT (7U) 515 #define CAN_RTIE_RIE_SET(x) (((uint8_t)(x) << CAN_RTIE_RIE_SHIFT) & CAN_RTIE_RIE_MASK) 516 #define CAN_RTIE_RIE_GET(x) (((uint8_t)(x) & CAN_RTIE_RIE_MASK) >> CAN_RTIE_RIE_SHIFT) 517 518 /* 519 * ROIE (RW) 520 * 521 * RB Overrun Interrupt Enable 522 * 0 – Disabled, 1 – Enabled 523 */ 524 #define CAN_RTIE_ROIE_MASK (0x40U) 525 #define CAN_RTIE_ROIE_SHIFT (6U) 526 #define CAN_RTIE_ROIE_SET(x) (((uint8_t)(x) << CAN_RTIE_ROIE_SHIFT) & CAN_RTIE_ROIE_MASK) 527 #define CAN_RTIE_ROIE_GET(x) (((uint8_t)(x) & CAN_RTIE_ROIE_MASK) >> CAN_RTIE_ROIE_SHIFT) 528 529 /* 530 * RFIE (RW) 531 * 532 * RB Full Interrupt Enable 533 * 0 – Disabled, 1 – Enabled 534 */ 535 #define CAN_RTIE_RFIE_MASK (0x20U) 536 #define CAN_RTIE_RFIE_SHIFT (5U) 537 #define CAN_RTIE_RFIE_SET(x) (((uint8_t)(x) << CAN_RTIE_RFIE_SHIFT) & CAN_RTIE_RFIE_MASK) 538 #define CAN_RTIE_RFIE_GET(x) (((uint8_t)(x) & CAN_RTIE_RFIE_MASK) >> CAN_RTIE_RFIE_SHIFT) 539 540 /* 541 * RAFIE (RW) 542 * 543 * RB Almost Full Interrupt Enable 544 * 0 – Disabled, 1 – Enabled 545 */ 546 #define CAN_RTIE_RAFIE_MASK (0x10U) 547 #define CAN_RTIE_RAFIE_SHIFT (4U) 548 #define CAN_RTIE_RAFIE_SET(x) (((uint8_t)(x) << CAN_RTIE_RAFIE_SHIFT) & CAN_RTIE_RAFIE_MASK) 549 #define CAN_RTIE_RAFIE_GET(x) (((uint8_t)(x) & CAN_RTIE_RAFIE_MASK) >> CAN_RTIE_RAFIE_SHIFT) 550 551 /* 552 * TPIE (RW) 553 * 554 * Transmission Primary Interrupt Enable 555 * 0 – Disabled, 1 – Enabled 556 */ 557 #define CAN_RTIE_TPIE_MASK (0x8U) 558 #define CAN_RTIE_TPIE_SHIFT (3U) 559 #define CAN_RTIE_TPIE_SET(x) (((uint8_t)(x) << CAN_RTIE_TPIE_SHIFT) & CAN_RTIE_TPIE_MASK) 560 #define CAN_RTIE_TPIE_GET(x) (((uint8_t)(x) & CAN_RTIE_TPIE_MASK) >> CAN_RTIE_TPIE_SHIFT) 561 562 /* 563 * TSIE (RW) 564 * 565 * Transmission Secondary Interrupt Enable 566 * 0 – Disabled, 1 – Enabled 567 */ 568 #define CAN_RTIE_TSIE_MASK (0x4U) 569 #define CAN_RTIE_TSIE_SHIFT (2U) 570 #define CAN_RTIE_TSIE_SET(x) (((uint8_t)(x) << CAN_RTIE_TSIE_SHIFT) & CAN_RTIE_TSIE_MASK) 571 #define CAN_RTIE_TSIE_GET(x) (((uint8_t)(x) & CAN_RTIE_TSIE_MASK) >> CAN_RTIE_TSIE_SHIFT) 572 573 /* 574 * EIE (RW) 575 * 576 * Error Interrupt Enable 577 * 0 – Disabled, 1 – Enabled 578 */ 579 #define CAN_RTIE_EIE_MASK (0x2U) 580 #define CAN_RTIE_EIE_SHIFT (1U) 581 #define CAN_RTIE_EIE_SET(x) (((uint8_t)(x) << CAN_RTIE_EIE_SHIFT) & CAN_RTIE_EIE_MASK) 582 #define CAN_RTIE_EIE_GET(x) (((uint8_t)(x) & CAN_RTIE_EIE_MASK) >> CAN_RTIE_EIE_SHIFT) 583 584 /* 585 * TSFF (RO) 586 * 587 * If TTEN=0 or TTTBM=0: Transmit Secondary buffer Full Flag 588 * 1 - The STB is filled with the maximal number of messages. 589 * 0 - The STB is not filled with the maximal number of messages. 590 * If the STB is disabled using STB_DISABLE, then TSFF=0. 591 * If TTEN=1 and TTTBM=1: Transmit buffer Slot Full Flag 592 * 1 - The buffer slot selected by TBPTR is filled. 593 * 0 - The buffer slot selected by TBPTR is empty. 594 */ 595 #define CAN_RTIE_TSFF_MASK (0x1U) 596 #define CAN_RTIE_TSFF_SHIFT (0U) 597 #define CAN_RTIE_TSFF_GET(x) (((uint8_t)(x) & CAN_RTIE_TSFF_MASK) >> CAN_RTIE_TSFF_SHIFT) 598 599 /* Bitfield definition for register: RTIF */ 600 /* 601 * RIF (W1C) 602 * 603 * Receive Interrupt Flag 604 * 1 - Data or a remote frame has been received and is available in the receive buffer. 605 * 0 - No frame has been received. 606 */ 607 #define CAN_RTIF_RIF_MASK (0x80U) 608 #define CAN_RTIF_RIF_SHIFT (7U) 609 #define CAN_RTIF_RIF_SET(x) (((uint8_t)(x) << CAN_RTIF_RIF_SHIFT) & CAN_RTIF_RIF_MASK) 610 #define CAN_RTIF_RIF_GET(x) (((uint8_t)(x) & CAN_RTIF_RIF_MASK) >> CAN_RTIF_RIF_SHIFT) 611 612 /* 613 * ROIF (W1C) 614 * 615 * RB Overrun Interrupt Flag 616 * 1 - At least one received message has been overwritten in the RB. 617 * 0 - No RB overwritten. 618 * In case of an overrun both ROIF and RFIF will be set. 619 */ 620 #define CAN_RTIF_ROIF_MASK (0x40U) 621 #define CAN_RTIF_ROIF_SHIFT (6U) 622 #define CAN_RTIF_ROIF_SET(x) (((uint8_t)(x) << CAN_RTIF_ROIF_SHIFT) & CAN_RTIF_ROIF_MASK) 623 #define CAN_RTIF_ROIF_GET(x) (((uint8_t)(x) & CAN_RTIF_ROIF_MASK) >> CAN_RTIF_ROIF_SHIFT) 624 625 /* 626 * RFIF (W1C) 627 * 628 * RB Full Interrupt Flag 629 * 1 - All RBs are full. If no RB will be released until the next valid message is received, 630 * the oldest message will be lost. 631 * 0 - The RB FIFO is not full. 632 */ 633 #define CAN_RTIF_RFIF_MASK (0x20U) 634 #define CAN_RTIF_RFIF_SHIFT (5U) 635 #define CAN_RTIF_RFIF_SET(x) (((uint8_t)(x) << CAN_RTIF_RFIF_SHIFT) & CAN_RTIF_RFIF_MASK) 636 #define CAN_RTIF_RFIF_GET(x) (((uint8_t)(x) & CAN_RTIF_RFIF_MASK) >> CAN_RTIF_RFIF_SHIFT) 637 638 /* 639 * RAFIF (W1C) 640 * 641 * RB Almost Full Interrupt Flag 642 * 1 - number of filled RB slots >= AFWL_i 643 * 0 - number of filled RB slots < AFWL_i 644 */ 645 #define CAN_RTIF_RAFIF_MASK (0x10U) 646 #define CAN_RTIF_RAFIF_SHIFT (4U) 647 #define CAN_RTIF_RAFIF_SET(x) (((uint8_t)(x) << CAN_RTIF_RAFIF_SHIFT) & CAN_RTIF_RAFIF_MASK) 648 #define CAN_RTIF_RAFIF_GET(x) (((uint8_t)(x) & CAN_RTIF_RAFIF_MASK) >> CAN_RTIF_RAFIF_SHIFT) 649 650 /* 651 * TPIF (W1C) 652 * 653 * Transmission Primary Interrupt Flag 654 * 1 - The requested transmission of the PTB has been successfully completed. 655 * 0 - No transmission of the PTB has been completed. 656 * In TTCAN mode, TPIF will never be set. Then only TSIF is valid. 657 */ 658 #define CAN_RTIF_TPIF_MASK (0x8U) 659 #define CAN_RTIF_TPIF_SHIFT (3U) 660 #define CAN_RTIF_TPIF_SET(x) (((uint8_t)(x) << CAN_RTIF_TPIF_SHIFT) & CAN_RTIF_TPIF_MASK) 661 #define CAN_RTIF_TPIF_GET(x) (((uint8_t)(x) & CAN_RTIF_TPIF_MASK) >> CAN_RTIF_TPIF_SHIFT) 662 663 /* 664 * TSIF (W1C) 665 * 666 * Transmission Secondary Interrupt Flag 667 * 1 - The requested transmission of the STB has been successfully completed. 668 * 0 - No transmission of the STB has been completed successfully. 669 * In TTCAN mode TSIF will signal all successful transmissions, regardless of storage location of 670 * the message. 671 */ 672 #define CAN_RTIF_TSIF_MASK (0x4U) 673 #define CAN_RTIF_TSIF_SHIFT (2U) 674 #define CAN_RTIF_TSIF_SET(x) (((uint8_t)(x) << CAN_RTIF_TSIF_SHIFT) & CAN_RTIF_TSIF_MASK) 675 #define CAN_RTIF_TSIF_GET(x) (((uint8_t)(x) & CAN_RTIF_TSIF_MASK) >> CAN_RTIF_TSIF_SHIFT) 676 677 /* 678 * EIF (W1C) 679 * 680 * Error Interrupt Flag 681 * 1 - The border of the error warning limit has been crossed in either direction, 682 * or the BUSOFF bit has been changed in either direction. 683 * 0 - There has been no change. 684 */ 685 #define CAN_RTIF_EIF_MASK (0x2U) 686 #define CAN_RTIF_EIF_SHIFT (1U) 687 #define CAN_RTIF_EIF_SET(x) (((uint8_t)(x) << CAN_RTIF_EIF_SHIFT) & CAN_RTIF_EIF_MASK) 688 #define CAN_RTIF_EIF_GET(x) (((uint8_t)(x) & CAN_RTIF_EIF_MASK) >> CAN_RTIF_EIF_SHIFT) 689 690 /* 691 * AIF (W1C) 692 * 693 * Abort Interrupt Flag 694 * 1 - After setting TPA or TSA the appropriated message(s) have been aborted. 695 * It is recommended to not set both TPA and TSA simultaneously because both 696 * source AIF. 697 * 0 - No abort has been executed. 698 * The AIF does not have an associated enable register. 699 */ 700 #define CAN_RTIF_AIF_MASK (0x1U) 701 #define CAN_RTIF_AIF_SHIFT (0U) 702 #define CAN_RTIF_AIF_SET(x) (((uint8_t)(x) << CAN_RTIF_AIF_SHIFT) & CAN_RTIF_AIF_MASK) 703 #define CAN_RTIF_AIF_GET(x) (((uint8_t)(x) & CAN_RTIF_AIF_MASK) >> CAN_RTIF_AIF_SHIFT) 704 705 /* Bitfield definition for register: ERRINT */ 706 /* 707 * EWARN (RO) 708 * 709 * Error WARNing limit reached 710 * 1 - One of the error counters RECNT or TECNT is equal or bigger than EWL0 - The values in both counters are less than EWL. 711 */ 712 #define CAN_ERRINT_EWARN_MASK (0x80U) 713 #define CAN_ERRINT_EWARN_SHIFT (7U) 714 #define CAN_ERRINT_EWARN_GET(x) (((uint8_t)(x) & CAN_ERRINT_EWARN_MASK) >> CAN_ERRINT_EWARN_SHIFT) 715 716 /* 717 * EPASS (RO) 718 * 719 * Error Passive mode active 720 * 0 - not active (node is error active) 721 * 1 - active (node is error passive) 722 */ 723 #define CAN_ERRINT_EPASS_MASK (0x40U) 724 #define CAN_ERRINT_EPASS_SHIFT (6U) 725 #define CAN_ERRINT_EPASS_GET(x) (((uint8_t)(x) & CAN_ERRINT_EPASS_MASK) >> CAN_ERRINT_EPASS_SHIFT) 726 727 /* 728 * EPIE (RW) 729 * 730 * Error Passive Interrupt Enable 731 */ 732 #define CAN_ERRINT_EPIE_MASK (0x20U) 733 #define CAN_ERRINT_EPIE_SHIFT (5U) 734 #define CAN_ERRINT_EPIE_SET(x) (((uint8_t)(x) << CAN_ERRINT_EPIE_SHIFT) & CAN_ERRINT_EPIE_MASK) 735 #define CAN_ERRINT_EPIE_GET(x) (((uint8_t)(x) & CAN_ERRINT_EPIE_MASK) >> CAN_ERRINT_EPIE_SHIFT) 736 737 /* 738 * EPIF (W1C) 739 * 740 * Error Passive Interrupt Flag. EPIF will be activated if the error status changes from error 741 * active to error passive or vice versa and if this interrupt is enabled. 742 */ 743 #define CAN_ERRINT_EPIF_MASK (0x10U) 744 #define CAN_ERRINT_EPIF_SHIFT (4U) 745 #define CAN_ERRINT_EPIF_SET(x) (((uint8_t)(x) << CAN_ERRINT_EPIF_SHIFT) & CAN_ERRINT_EPIF_MASK) 746 #define CAN_ERRINT_EPIF_GET(x) (((uint8_t)(x) & CAN_ERRINT_EPIF_MASK) >> CAN_ERRINT_EPIF_SHIFT) 747 748 /* 749 * ALIE (RW) 750 * 751 * Arbitration Lost Interrupt Enable 752 */ 753 #define CAN_ERRINT_ALIE_MASK (0x8U) 754 #define CAN_ERRINT_ALIE_SHIFT (3U) 755 #define CAN_ERRINT_ALIE_SET(x) (((uint8_t)(x) << CAN_ERRINT_ALIE_SHIFT) & CAN_ERRINT_ALIE_MASK) 756 #define CAN_ERRINT_ALIE_GET(x) (((uint8_t)(x) & CAN_ERRINT_ALIE_MASK) >> CAN_ERRINT_ALIE_SHIFT) 757 758 /* 759 * ALIF (W1C) 760 * 761 * Arbitration Lost Interrupt Flag 762 */ 763 #define CAN_ERRINT_ALIF_MASK (0x4U) 764 #define CAN_ERRINT_ALIF_SHIFT (2U) 765 #define CAN_ERRINT_ALIF_SET(x) (((uint8_t)(x) << CAN_ERRINT_ALIF_SHIFT) & CAN_ERRINT_ALIF_MASK) 766 #define CAN_ERRINT_ALIF_GET(x) (((uint8_t)(x) & CAN_ERRINT_ALIF_MASK) >> CAN_ERRINT_ALIF_SHIFT) 767 768 /* 769 * BEIE (RW) 770 * 771 * Bus Error Interrupt Enable 772 */ 773 #define CAN_ERRINT_BEIE_MASK (0x2U) 774 #define CAN_ERRINT_BEIE_SHIFT (1U) 775 #define CAN_ERRINT_BEIE_SET(x) (((uint8_t)(x) << CAN_ERRINT_BEIE_SHIFT) & CAN_ERRINT_BEIE_MASK) 776 #define CAN_ERRINT_BEIE_GET(x) (((uint8_t)(x) & CAN_ERRINT_BEIE_MASK) >> CAN_ERRINT_BEIE_SHIFT) 777 778 /* 779 * BEIF (W1C) 780 * 781 * Bus Error Interrupt Flag 782 */ 783 #define CAN_ERRINT_BEIF_MASK (0x1U) 784 #define CAN_ERRINT_BEIF_SHIFT (0U) 785 #define CAN_ERRINT_BEIF_SET(x) (((uint8_t)(x) << CAN_ERRINT_BEIF_SHIFT) & CAN_ERRINT_BEIF_MASK) 786 #define CAN_ERRINT_BEIF_GET(x) (((uint8_t)(x) & CAN_ERRINT_BEIF_MASK) >> CAN_ERRINT_BEIF_SHIFT) 787 788 /* Bitfield definition for register: LIMIT */ 789 /* 790 * AFWL (RW) 791 * 792 * receive buffer Almost Full Warning Limit 793 * AFWL defines the internal warning limit AFWL_i with being the number of availableRB slots. 794 * AFWL_i is compared to the number of filled RB slots and triggers RAFIF if equal. Thevalid range of . 795 * AFWL = 0 is meaningless and automatically treated as 0x1. (Note that AFWL is meant in this rule and not AFWL_i.) 796 * AFWL_i > nRB is meaningless and automatically treated as nRB. 797 * AFWL_i = nRB is a valid value, but note that RFIF also exists. 798 */ 799 #define CAN_LIMIT_AFWL_MASK (0xF0U) 800 #define CAN_LIMIT_AFWL_SHIFT (4U) 801 #define CAN_LIMIT_AFWL_SET(x) (((uint8_t)(x) << CAN_LIMIT_AFWL_SHIFT) & CAN_LIMIT_AFWL_MASK) 802 #define CAN_LIMIT_AFWL_GET(x) (((uint8_t)(x) & CAN_LIMIT_AFWL_MASK) >> CAN_LIMIT_AFWL_SHIFT) 803 804 /* 805 * EWL (RW) 806 * 807 * Programmable Error Warning Limit = (EWL+1)*8. Possible Limit values: 8, 16, … 128. 808 * The value of EWL controls EIF. 809 */ 810 #define CAN_LIMIT_EWL_MASK (0xFU) 811 #define CAN_LIMIT_EWL_SHIFT (0U) 812 #define CAN_LIMIT_EWL_SET(x) (((uint8_t)(x) << CAN_LIMIT_EWL_SHIFT) & CAN_LIMIT_EWL_MASK) 813 #define CAN_LIMIT_EWL_GET(x) (((uint8_t)(x) & CAN_LIMIT_EWL_MASK) >> CAN_LIMIT_EWL_SHIFT) 814 815 /* Bitfield definition for register: S_PRESC */ 816 /* 817 * S_PRESC (RW) 818 * 819 * Prescaler (slow speed) 820 * The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. 821 */ 822 #define CAN_S_PRESC_S_PRESC_MASK (0xFF000000UL) 823 #define CAN_S_PRESC_S_PRESC_SHIFT (24U) 824 #define CAN_S_PRESC_S_PRESC_SET(x) (((uint32_t)(x) << CAN_S_PRESC_S_PRESC_SHIFT) & CAN_S_PRESC_S_PRESC_MASK) 825 #define CAN_S_PRESC_S_PRESC_GET(x) (((uint32_t)(x) & CAN_S_PRESC_S_PRESC_MASK) >> CAN_S_PRESC_S_PRESC_SHIFT) 826 827 /* 828 * S_SJW (RW) 829 * 830 * Synchronization Jump Width (slow speed) 831 * The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. 832 */ 833 #define CAN_S_PRESC_S_SJW_MASK (0x7F0000UL) 834 #define CAN_S_PRESC_S_SJW_SHIFT (16U) 835 #define CAN_S_PRESC_S_SJW_SET(x) (((uint32_t)(x) << CAN_S_PRESC_S_SJW_SHIFT) & CAN_S_PRESC_S_SJW_MASK) 836 #define CAN_S_PRESC_S_SJW_GET(x) (((uint32_t)(x) & CAN_S_PRESC_S_SJW_MASK) >> CAN_S_PRESC_S_SJW_SHIFT) 837 838 /* 839 * S_SEG_2 (RW) 840 * 841 * Bit Timing Segment 2 (slow speed) 842 * Time after the sample point. 843 */ 844 #define CAN_S_PRESC_S_SEG_2_MASK (0x7F00U) 845 #define CAN_S_PRESC_S_SEG_2_SHIFT (8U) 846 #define CAN_S_PRESC_S_SEG_2_SET(x) (((uint32_t)(x) << CAN_S_PRESC_S_SEG_2_SHIFT) & CAN_S_PRESC_S_SEG_2_MASK) 847 #define CAN_S_PRESC_S_SEG_2_GET(x) (((uint32_t)(x) & CAN_S_PRESC_S_SEG_2_MASK) >> CAN_S_PRESC_S_SEG_2_SHIFT) 848 849 /* 850 * S_SEG_1 (RW) 851 * 852 * Bit Timing Segment 1 (slow speed) 853 * The sample point will be set to after start of bit time. 854 */ 855 #define CAN_S_PRESC_S_SEG_1_MASK (0xFFU) 856 #define CAN_S_PRESC_S_SEG_1_SHIFT (0U) 857 #define CAN_S_PRESC_S_SEG_1_SET(x) (((uint32_t)(x) << CAN_S_PRESC_S_SEG_1_SHIFT) & CAN_S_PRESC_S_SEG_1_MASK) 858 #define CAN_S_PRESC_S_SEG_1_GET(x) (((uint32_t)(x) & CAN_S_PRESC_S_SEG_1_MASK) >> CAN_S_PRESC_S_SEG_1_SHIFT) 859 860 /* Bitfield definition for register: F_PRESC */ 861 /* 862 * F_PRESC (RW) 863 * 864 * Prescaler (fast speed) 865 * The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. 866 */ 867 #define CAN_F_PRESC_F_PRESC_MASK (0xFF000000UL) 868 #define CAN_F_PRESC_F_PRESC_SHIFT (24U) 869 #define CAN_F_PRESC_F_PRESC_SET(x) (((uint32_t)(x) << CAN_F_PRESC_F_PRESC_SHIFT) & CAN_F_PRESC_F_PRESC_MASK) 870 #define CAN_F_PRESC_F_PRESC_GET(x) (((uint32_t)(x) & CAN_F_PRESC_F_PRESC_MASK) >> CAN_F_PRESC_F_PRESC_SHIFT) 871 872 /* 873 * F_SJW (RW) 874 * 875 * Synchronization Jump Width (fast speed) 876 * The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. 877 */ 878 #define CAN_F_PRESC_F_SJW_MASK (0xF0000UL) 879 #define CAN_F_PRESC_F_SJW_SHIFT (16U) 880 #define CAN_F_PRESC_F_SJW_SET(x) (((uint32_t)(x) << CAN_F_PRESC_F_SJW_SHIFT) & CAN_F_PRESC_F_SJW_MASK) 881 #define CAN_F_PRESC_F_SJW_GET(x) (((uint32_t)(x) & CAN_F_PRESC_F_SJW_MASK) >> CAN_F_PRESC_F_SJW_SHIFT) 882 883 /* 884 * F_SEG_2 (RW) 885 * 886 * Bit Timing Segment 2 (fast speed) 887 * Time after the sample point 888 */ 889 #define CAN_F_PRESC_F_SEG_2_MASK (0xF00U) 890 #define CAN_F_PRESC_F_SEG_2_SHIFT (8U) 891 #define CAN_F_PRESC_F_SEG_2_SET(x) (((uint32_t)(x) << CAN_F_PRESC_F_SEG_2_SHIFT) & CAN_F_PRESC_F_SEG_2_MASK) 892 #define CAN_F_PRESC_F_SEG_2_GET(x) (((uint32_t)(x) & CAN_F_PRESC_F_SEG_2_MASK) >> CAN_F_PRESC_F_SEG_2_SHIFT) 893 894 /* 895 * F_SEG_1 (RW) 896 * 897 * Bit Timing Segment 1 (fast speed) 898 * The sample point will be set to after start of bit time. 899 */ 900 #define CAN_F_PRESC_F_SEG_1_MASK (0xFU) 901 #define CAN_F_PRESC_F_SEG_1_SHIFT (0U) 902 #define CAN_F_PRESC_F_SEG_1_SET(x) (((uint32_t)(x) << CAN_F_PRESC_F_SEG_1_SHIFT) & CAN_F_PRESC_F_SEG_1_MASK) 903 #define CAN_F_PRESC_F_SEG_1_GET(x) (((uint32_t)(x) & CAN_F_PRESC_F_SEG_1_MASK) >> CAN_F_PRESC_F_SEG_1_SHIFT) 904 905 /* Bitfield definition for register: EALCAP */ 906 /* 907 * KOER (RO) 908 * 909 * Kind Of ERror (Error code) 910 * 000 - no error 911 * 001 - BIT ERROR 912 * 010 - FORM ERROR 913 * 011 - STUFF ERROR 914 * 100 - ACKNOWLEDGEMENT ERROR 915 * 101 - CRC ERROR 916 * 110 - OTHER ERROR(dominant bits after own error flag, received active Error Flag too long,dominant bit during Passive-Error-Flag after ACK error) 917 * 111 - not used 918 * KOER is updated with each new error. Therefore it stays untouched when frames aresuccessfully transmitted or received. 919 */ 920 #define CAN_EALCAP_KOER_MASK (0xE0U) 921 #define CAN_EALCAP_KOER_SHIFT (5U) 922 #define CAN_EALCAP_KOER_GET(x) (((uint8_t)(x) & CAN_EALCAP_KOER_MASK) >> CAN_EALCAP_KOER_SHIFT) 923 924 /* 925 * ALC (RO) 926 * 927 * Arbitration Lost Capture (bit position in the frame where the arbitration has been lost) 928 */ 929 #define CAN_EALCAP_ALC_MASK (0x1FU) 930 #define CAN_EALCAP_ALC_SHIFT (0U) 931 #define CAN_EALCAP_ALC_GET(x) (((uint8_t)(x) & CAN_EALCAP_ALC_MASK) >> CAN_EALCAP_ALC_SHIFT) 932 933 /* Bitfield definition for register: TDC */ 934 /* 935 * TDCEN (RW) 936 * 937 * Transmitter Delay Compensation ENable 938 * TDC will be activated during the data phase of a CAN FD frame if BRS is active if TDCEN=1. 939 */ 940 #define CAN_TDC_TDCEN_MASK (0x80U) 941 #define CAN_TDC_TDCEN_SHIFT (7U) 942 #define CAN_TDC_TDCEN_SET(x) (((uint8_t)(x) << CAN_TDC_TDCEN_SHIFT) & CAN_TDC_TDCEN_MASK) 943 #define CAN_TDC_TDCEN_GET(x) (((uint8_t)(x) & CAN_TDC_TDCEN_MASK) >> CAN_TDC_TDCEN_SHIFT) 944 945 /* 946 * SSPOFF (RW) 947 * 948 * Secondary Sample Point OFFset 949 * The transmitter delay plus SSPOFF defines the time of the secondary sample point for TDC. 950 * SSPOFF is given as a number of TQ. 951 */ 952 #define CAN_TDC_SSPOFF_MASK (0x7FU) 953 #define CAN_TDC_SSPOFF_SHIFT (0U) 954 #define CAN_TDC_SSPOFF_SET(x) (((uint8_t)(x) << CAN_TDC_SSPOFF_SHIFT) & CAN_TDC_SSPOFF_MASK) 955 #define CAN_TDC_SSPOFF_GET(x) (((uint8_t)(x) & CAN_TDC_SSPOFF_MASK) >> CAN_TDC_SSPOFF_SHIFT) 956 957 /* Bitfield definition for register: RECNT */ 958 /* 959 * RECNT (RO) 960 * 961 * Receive Error CouNT (number of errors during reception) 962 * RECNT is incremented and decremented as defined in the CAN specification. 963 * RECNT does not overflow. 964 * If TXB=1, then the error counters are frozen. 965 */ 966 #define CAN_RECNT_RECNT_MASK (0xFFU) 967 #define CAN_RECNT_RECNT_SHIFT (0U) 968 #define CAN_RECNT_RECNT_GET(x) (((uint8_t)(x) & CAN_RECNT_RECNT_MASK) >> CAN_RECNT_RECNT_SHIFT) 969 970 /* Bitfield definition for register: TECNT */ 971 /* 972 * TECNT (RO) 973 * 974 * Transmit Error CouNT (number of errors during transmission) 975 * TECNT is incremented and decremented as defined in the CAN specification. 976 * In case of the “bus off state” TECNT may overflow. 977 * If TXB=1, then the error counters are frozen. 978 */ 979 #define CAN_TECNT_TECNT_MASK (0xFFU) 980 #define CAN_TECNT_TECNT_SHIFT (0U) 981 #define CAN_TECNT_TECNT_GET(x) (((uint8_t)(x) & CAN_TECNT_TECNT_MASK) >> CAN_TECNT_TECNT_SHIFT) 982 983 /* Bitfield definition for register: ACFCTRL */ 984 /* 985 * SELMASK (RW) 986 * 987 * SELect acceptance MASK 988 * 0 - Registers ACF_x point to acceptance code 989 * 1 - Registers ACF_x point to acceptance mask. 990 * ACFADR selects one specific acceptance filter. 991 */ 992 #define CAN_ACFCTRL_SELMASK_MASK (0x20U) 993 #define CAN_ACFCTRL_SELMASK_SHIFT (5U) 994 #define CAN_ACFCTRL_SELMASK_SET(x) (((uint8_t)(x) << CAN_ACFCTRL_SELMASK_SHIFT) & CAN_ACFCTRL_SELMASK_MASK) 995 #define CAN_ACFCTRL_SELMASK_GET(x) (((uint8_t)(x) & CAN_ACFCTRL_SELMASK_MASK) >> CAN_ACFCTRL_SELMASK_SHIFT) 996 997 /* 998 * ACFADR (RW) 999 * 1000 * acceptance filter address 1001 * ACFADR points to a specific acceptance filter. 1002 * The selected filter is accessible using theregisters ACF_x. 1003 * Bit SELMASK selects between acceptance code and mask for theselected acceptance filter. 1004 * A value of ACFADR>ACF_NUMBER-1 is meaningless and automatically treated as value ACF_NUMBER-1. 1005 * ACF_NUMBER = 16. 1006 */ 1007 #define CAN_ACFCTRL_ACFADR_MASK (0xFU) 1008 #define CAN_ACFCTRL_ACFADR_SHIFT (0U) 1009 #define CAN_ACFCTRL_ACFADR_SET(x) (((uint8_t)(x) << CAN_ACFCTRL_ACFADR_SHIFT) & CAN_ACFCTRL_ACFADR_MASK) 1010 #define CAN_ACFCTRL_ACFADR_GET(x) (((uint8_t)(x) & CAN_ACFCTRL_ACFADR_MASK) >> CAN_ACFCTRL_ACFADR_SHIFT) 1011 1012 /* Bitfield definition for register: TIMECFG */ 1013 /* 1014 * TIMEPOS (RW) 1015 * 1016 * TIME-stamping POSition 1017 * 0 – SOF1 – EOF (see Chapter 7)TIMEPOS can only be changed if TIMEEN=0, but it is possible to modify TIMPOS withthe same write access that sets TIMEEN=1. 1018 */ 1019 #define CAN_TIMECFG_TIMEPOS_MASK (0x2U) 1020 #define CAN_TIMECFG_TIMEPOS_SHIFT (1U) 1021 #define CAN_TIMECFG_TIMEPOS_SET(x) (((uint8_t)(x) << CAN_TIMECFG_TIMEPOS_SHIFT) & CAN_TIMECFG_TIMEPOS_MASK) 1022 #define CAN_TIMECFG_TIMEPOS_GET(x) (((uint8_t)(x) & CAN_TIMECFG_TIMEPOS_MASK) >> CAN_TIMECFG_TIMEPOS_SHIFT) 1023 1024 /* 1025 * TIMEEN (RW) 1026 * 1027 * TIME-stamping ENable 1028 * 0 – disabled 1029 * 1 – enabled 1030 */ 1031 #define CAN_TIMECFG_TIMEEN_MASK (0x1U) 1032 #define CAN_TIMECFG_TIMEEN_SHIFT (0U) 1033 #define CAN_TIMECFG_TIMEEN_SET(x) (((uint8_t)(x) << CAN_TIMECFG_TIMEEN_SHIFT) & CAN_TIMECFG_TIMEEN_MASK) 1034 #define CAN_TIMECFG_TIMEEN_GET(x) (((uint8_t)(x) & CAN_TIMECFG_TIMEEN_MASK) >> CAN_TIMECFG_TIMEEN_SHIFT) 1035 1036 /* Bitfield definition for register: ACF_EN */ 1037 /* 1038 * ACF_EN (RW) 1039 * 1040 * Acceptance filter Enable 1041 * 1 - acceptance filter enabled 1042 * 0 - acceptance filter disable 1043 * Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled. 1044 * Disabled filters reject a message. Only enabled filters can accept a message if the 1045 * appropriate AMASK / ACODE configuration matches. 1046 */ 1047 #define CAN_ACF_EN_ACF_EN_MASK (0xFFFFU) 1048 #define CAN_ACF_EN_ACF_EN_SHIFT (0U) 1049 #define CAN_ACF_EN_ACF_EN_SET(x) (((uint16_t)(x) << CAN_ACF_EN_ACF_EN_SHIFT) & CAN_ACF_EN_ACF_EN_MASK) 1050 #define CAN_ACF_EN_ACF_EN_GET(x) (((uint16_t)(x) & CAN_ACF_EN_ACF_EN_MASK) >> CAN_ACF_EN_ACF_EN_SHIFT) 1051 1052 /* Bitfield definition for register: ACF */ 1053 /* 1054 * AIDEE (RW) 1055 * 1056 * Acceptance mask IDE bit check enable 1057 * 1 - acceptance filter accepts either standard or extended as defined by AIDE 1058 * 0 - acceptance filter accepts both standard or extended frames 1059 * Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. 1060 */ 1061 #define CAN_ACF_AIDEE_MASK (0x40000000UL) 1062 #define CAN_ACF_AIDEE_SHIFT (30U) 1063 #define CAN_ACF_AIDEE_SET(x) (((uint32_t)(x) << CAN_ACF_AIDEE_SHIFT) & CAN_ACF_AIDEE_MASK) 1064 #define CAN_ACF_AIDEE_GET(x) (((uint32_t)(x) & CAN_ACF_AIDEE_MASK) >> CAN_ACF_AIDEE_SHIFT) 1065 1066 /* 1067 * AIDE (RW) 1068 * 1069 * Acceptance mask IDE bit value 1070 * If AIDEE=1 then: 1071 * 1 - acceptance filter accepts only extended frames 1072 * 0 - acceptance filter accepts only standard frames 1073 * Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. 1074 */ 1075 #define CAN_ACF_AIDE_MASK (0x20000000UL) 1076 #define CAN_ACF_AIDE_SHIFT (29U) 1077 #define CAN_ACF_AIDE_SET(x) (((uint32_t)(x) << CAN_ACF_AIDE_SHIFT) & CAN_ACF_AIDE_MASK) 1078 #define CAN_ACF_AIDE_GET(x) (((uint32_t)(x) & CAN_ACF_AIDE_MASK) >> CAN_ACF_AIDE_SHIFT) 1079 1080 /* 1081 * CODE_MASK (RW) 1082 * 1083 * Acceptance CODE 1084 * 1 - ACC bit value to compare with ID bit of the received message 1085 * 0 - ACC bit value to compare with ID bit of the received message 1086 * ACODE_x(10:0) will be used for extended frames. 1087 * ACODE_x(28:0) will be used for extended frames. 1088 * Only filter 0 is affected by the power-on reset. 1089 * Acceptance MASK(if SELMASK ==1 ) 1090 * 1 - acceptance check for these bits of receive identifier disabled 1091 * 0 - acceptance check for these bits of receive identifier enable 1092 * AMASK_x(10:0) will be used for extended frames. 1093 * AMASK_x(28:0) will be used for extended frames. 1094 * Disabled bits result in accepting the message. Therefore the default configuration after 1095 * reset for filter 0 accepts all messages. 1096 * Only filter 0 is affected by the power-on reset. 1097 */ 1098 #define CAN_ACF_CODE_MASK_MASK (0x1FFFFFFFUL) 1099 #define CAN_ACF_CODE_MASK_SHIFT (0U) 1100 #define CAN_ACF_CODE_MASK_SET(x) (((uint32_t)(x) << CAN_ACF_CODE_MASK_SHIFT) & CAN_ACF_CODE_MASK_MASK) 1101 #define CAN_ACF_CODE_MASK_GET(x) (((uint32_t)(x) & CAN_ACF_CODE_MASK_MASK) >> CAN_ACF_CODE_MASK_SHIFT) 1102 1103 /* Bitfield definition for register: VER */ 1104 /* 1105 * VERSION (RW) 1106 * 1107 * Version of CAN-CTRL, given as decimal value. VER_1 holds the major version and 1108 * VER_0 the minor version.Example: version 5x16N00S00 is represented by VER_1=5 and VER_0=16 1109 */ 1110 #define CAN_VER_VERSION_MASK (0xFFFFU) 1111 #define CAN_VER_VERSION_SHIFT (0U) 1112 #define CAN_VER_VERSION_SET(x) (((uint16_t)(x) << CAN_VER_VERSION_SHIFT) & CAN_VER_VERSION_MASK) 1113 #define CAN_VER_VERSION_GET(x) (((uint16_t)(x) & CAN_VER_VERSION_MASK) >> CAN_VER_VERSION_SHIFT) 1114 1115 /* Bitfield definition for register: TBSLOT */ 1116 /* 1117 * TBE (RW) 1118 * 1119 * set TB slot to “Empty” 1120 * 1 - slot selected by TBPTR shall be marked as “empty” 1121 * 0 - no actionTBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. 1122 * If atransmission from this slot is active, then TBE stays set as long as either the transmission completes or after a transmission error or arbitration loss the 1123 * transmissionis not active any more. 1124 * If both TBF and TBE are set, then TBE wins 1125 */ 1126 #define CAN_TBSLOT_TBE_MASK (0x80U) 1127 #define CAN_TBSLOT_TBE_SHIFT (7U) 1128 #define CAN_TBSLOT_TBE_SET(x) (((uint8_t)(x) << CAN_TBSLOT_TBE_SHIFT) & CAN_TBSLOT_TBE_MASK) 1129 #define CAN_TBSLOT_TBE_GET(x) (((uint8_t)(x) & CAN_TBSLOT_TBE_MASK) >> CAN_TBSLOT_TBE_SHIFT) 1130 1131 /* 1132 * TBF (RW) 1133 * 1134 * set TB slot to “Filled” 1135 * 1 - slot selected by TBPTR shall be marked as “filled” 1136 * 0 - no actionTBF is automatically reset to 0 as soon as the slot is marked as filled and TSFF=1. 1137 * If both TBF and TBE are set, then TBE wins. 1138 */ 1139 #define CAN_TBSLOT_TBF_MASK (0x40U) 1140 #define CAN_TBSLOT_TBF_SHIFT (6U) 1141 #define CAN_TBSLOT_TBF_SET(x) (((uint8_t)(x) << CAN_TBSLOT_TBF_SHIFT) & CAN_TBSLOT_TBF_MASK) 1142 #define CAN_TBSLOT_TBF_GET(x) (((uint8_t)(x) & CAN_TBSLOT_TBF_MASK) >> CAN_TBSLOT_TBF_SHIFT) 1143 1144 /* 1145 * TBPTR (RW) 1146 * 1147 * Pointer to a TB message slot. 1148 * 0x00 - Pointer to the PTB 1149 * others - Pointer to a slot in the STB 1150 * The message slot pointed to by TBPTR is readable / writable using the TBUF registers. 1151 * Write access is only possible if TSFF=0. 1152 * Setting TBF to 1 marks the selected slot asfilled and setting TBE to 1 marks the selected slot as empty. 1153 * TBSEL and TSNEXT are unused in TTCAN mode and have no meaning. 1154 * TBPTR can only point to buffer slots, that exist in the hardware. 1155 * Unusable bits ofTBPTR are fixed to 0. 1156 * TBPTR is limited to the PTB and 63 STB slots. 1157 * More slots cannot be used in TTCANmode.If TBPTR is too big and points to a slot that is not available, then TBF and TBE arereset automatically and no action takes place. 1158 */ 1159 #define CAN_TBSLOT_TBPTR_MASK (0x3FU) 1160 #define CAN_TBSLOT_TBPTR_SHIFT (0U) 1161 #define CAN_TBSLOT_TBPTR_SET(x) (((uint8_t)(x) << CAN_TBSLOT_TBPTR_SHIFT) & CAN_TBSLOT_TBPTR_MASK) 1162 #define CAN_TBSLOT_TBPTR_GET(x) (((uint8_t)(x) & CAN_TBSLOT_TBPTR_MASK) >> CAN_TBSLOT_TBPTR_SHIFT) 1163 1164 /* Bitfield definition for register: TTCFG */ 1165 /* 1166 * WTIE (RW) 1167 * 1168 * Watch Trigger Interrupt Enable 1169 */ 1170 #define CAN_TTCFG_WTIE_MASK (0x80U) 1171 #define CAN_TTCFG_WTIE_SHIFT (7U) 1172 #define CAN_TTCFG_WTIE_SET(x) (((uint8_t)(x) << CAN_TTCFG_WTIE_SHIFT) & CAN_TTCFG_WTIE_MASK) 1173 #define CAN_TTCFG_WTIE_GET(x) (((uint8_t)(x) & CAN_TTCFG_WTIE_MASK) >> CAN_TTCFG_WTIE_SHIFT) 1174 1175 /* 1176 * WTIF (RW) 1177 * 1178 * Watch Trigger Interrupt Flag 1179 * WTIF will be set if the cycle count reaches the limited defined by TT_WTRIG and WTIE is set. 1180 */ 1181 #define CAN_TTCFG_WTIF_MASK (0x40U) 1182 #define CAN_TTCFG_WTIF_SHIFT (6U) 1183 #define CAN_TTCFG_WTIF_SET(x) (((uint8_t)(x) << CAN_TTCFG_WTIF_SHIFT) & CAN_TTCFG_WTIF_MASK) 1184 #define CAN_TTCFG_WTIF_GET(x) (((uint8_t)(x) & CAN_TTCFG_WTIF_MASK) >> CAN_TTCFG_WTIF_SHIFT) 1185 1186 /* 1187 * TEIF (RW) 1188 * 1189 * Trigger Error Interrupt Flag 1190 * The conditions when TEIF will be set, are defined in Chapter 6.4. There is no bit toenable or disable the handling of TEIF 1191 */ 1192 #define CAN_TTCFG_TEIF_MASK (0x20U) 1193 #define CAN_TTCFG_TEIF_SHIFT (5U) 1194 #define CAN_TTCFG_TEIF_SET(x) (((uint8_t)(x) << CAN_TTCFG_TEIF_SHIFT) & CAN_TTCFG_TEIF_MASK) 1195 #define CAN_TTCFG_TEIF_GET(x) (((uint8_t)(x) & CAN_TTCFG_TEIF_MASK) >> CAN_TTCFG_TEIF_SHIFT) 1196 1197 /* 1198 * TTIE (RW) 1199 * 1200 * Time Trigger Interrupt Enable 1201 * If TTIE is set, then TTIF will be set if the cycle time is equal to the trigger timeTT_TRIG. 1202 */ 1203 #define CAN_TTCFG_TTIE_MASK (0x10U) 1204 #define CAN_TTCFG_TTIE_SHIFT (4U) 1205 #define CAN_TTCFG_TTIE_SET(x) (((uint8_t)(x) << CAN_TTCFG_TTIE_SHIFT) & CAN_TTCFG_TTIE_MASK) 1206 #define CAN_TTCFG_TTIE_GET(x) (((uint8_t)(x) & CAN_TTCFG_TTIE_MASK) >> CAN_TTCFG_TTIE_SHIFT) 1207 1208 /* 1209 * TTIF (RW) 1210 * 1211 * Time Trigger Interrupt Flag 1212 * TTIF will be set if TTIE is set and the cycle time is equal to the trigger time TT_TRIG. 1213 * Writing an one to TTIF resets it. Writing a zero has no impact.TTIF will be set only once. 1214 * If TT_TRIG gets not updated, then TTIF will be not setagain in the next basic cycle. 1215 */ 1216 #define CAN_TTCFG_TTIF_MASK (0x8U) 1217 #define CAN_TTCFG_TTIF_SHIFT (3U) 1218 #define CAN_TTCFG_TTIF_SET(x) (((uint8_t)(x) << CAN_TTCFG_TTIF_SHIFT) & CAN_TTCFG_TTIF_MASK) 1219 #define CAN_TTCFG_TTIF_GET(x) (((uint8_t)(x) & CAN_TTCFG_TTIF_MASK) >> CAN_TTCFG_TTIF_SHIFT) 1220 1221 /* 1222 * T_PRESC (RW) 1223 * 1224 * TTCAN Timer PRESCaler 1225 * 00b - 1 1226 * 01b - 2 1227 * 10b - 4 1228 * 11b - 8 1229 * The TTCAN time base is a CAN bittime defined by S_PRES, S_SEG_1 and S_SEG_2.With T_PRESC an additional prescaling factor of 1, 2, 4 or 8 is defined. 1230 * T_PRESC can only be modified if TTEN=0, but it is possible to modify T_PRESC and setTTEN simultaneously with one write access. 1231 */ 1232 #define CAN_TTCFG_T_PRESC_MASK (0x6U) 1233 #define CAN_TTCFG_T_PRESC_SHIFT (1U) 1234 #define CAN_TTCFG_T_PRESC_SET(x) (((uint8_t)(x) << CAN_TTCFG_T_PRESC_SHIFT) & CAN_TTCFG_T_PRESC_MASK) 1235 #define CAN_TTCFG_T_PRESC_GET(x) (((uint8_t)(x) & CAN_TTCFG_T_PRESC_MASK) >> CAN_TTCFG_T_PRESC_SHIFT) 1236 1237 /* 1238 * TTEN (RW) 1239 * 1240 * Time Trigger Enable 1241 * 1 - TTCAN enabled, timer is running0 - disabled 1242 */ 1243 #define CAN_TTCFG_TTEN_MASK (0x1U) 1244 #define CAN_TTCFG_TTEN_SHIFT (0U) 1245 #define CAN_TTCFG_TTEN_SET(x) (((uint8_t)(x) << CAN_TTCFG_TTEN_SHIFT) & CAN_TTCFG_TTEN_MASK) 1246 #define CAN_TTCFG_TTEN_GET(x) (((uint8_t)(x) & CAN_TTCFG_TTEN_MASK) >> CAN_TTCFG_TTEN_SHIFT) 1247 1248 /* Bitfield definition for register: REF_MSG */ 1249 /* 1250 * REF_IDE (RW) 1251 * 1252 * REFerence message IDE bit. 1253 */ 1254 #define CAN_REF_MSG_REF_IDE_MASK (0x80000000UL) 1255 #define CAN_REF_MSG_REF_IDE_SHIFT (31U) 1256 #define CAN_REF_MSG_REF_IDE_SET(x) (((uint32_t)(x) << CAN_REF_MSG_REF_IDE_SHIFT) & CAN_REF_MSG_REF_IDE_MASK) 1257 #define CAN_REF_MSG_REF_IDE_GET(x) (((uint32_t)(x) & CAN_REF_MSG_REF_IDE_MASK) >> CAN_REF_MSG_REF_IDE_SHIFT) 1258 1259 /* 1260 * REF_MSG (RW) 1261 * 1262 * REFerence message IDentifier. 1263 * If REF_IDE is 1264 * 1 - REF_ID(28:0) is valid (extended ID) 1265 * 0 - REF_ID(10:0) is valid (standard ID) 1266 * REF_ID is used in TTCAN mode to detect a reference message. This holds for time 1267 * slaves (reception) as well as for the time master (transmission). If the reference 1268 * message is detected and there are no errors, then the Sync_Mark of this frame will 1269 * become the Ref_Mark. 1270 * REF_ID(2:0) is not tested and therefore the appropriate register bits are forced to 0. 1271 * These bits are used for up to 8 potential time masters. 1272 * CAN-CTRL recognizes the reference message only by ID. The payload is not tested. 1273 * Additional note: A time master will transmit a reference message in the same way as a 1274 * normal frame. REF_ID is intended for detection of a successful transmission of a 1275 * reference message. 1276 */ 1277 #define CAN_REF_MSG_REF_MSG_MASK (0x1FFFFFFFUL) 1278 #define CAN_REF_MSG_REF_MSG_SHIFT (0U) 1279 #define CAN_REF_MSG_REF_MSG_SET(x) (((uint32_t)(x) << CAN_REF_MSG_REF_MSG_SHIFT) & CAN_REF_MSG_REF_MSG_MASK) 1280 #define CAN_REF_MSG_REF_MSG_GET(x) (((uint32_t)(x) & CAN_REF_MSG_REF_MSG_MASK) >> CAN_REF_MSG_REF_MSG_SHIFT) 1281 1282 /* Bitfield definition for register: TRIG_CFG */ 1283 /* 1284 * TEW (RW) 1285 * 1286 * Transmit Enable Window 1287 * For a single shot transmit trigger there is a time of up to 16 ticks of the cycle time 1288 * where the frame is allowed to start. TWE+1 defines the number of ticks. 1289 * TEW=0 is a valid setting and shortens the transmit enable window to 1 tick 1290 */ 1291 #define CAN_TRIG_CFG_TEW_MASK (0xF000U) 1292 #define CAN_TRIG_CFG_TEW_SHIFT (12U) 1293 #define CAN_TRIG_CFG_TEW_SET(x) (((uint16_t)(x) << CAN_TRIG_CFG_TEW_SHIFT) & CAN_TRIG_CFG_TEW_MASK) 1294 #define CAN_TRIG_CFG_TEW_GET(x) (((uint16_t)(x) & CAN_TRIG_CFG_TEW_MASK) >> CAN_TRIG_CFG_TEW_SHIFT) 1295 1296 /* 1297 * TTYPE (RW) 1298 * 1299 * Trigger Type 1300 * 000b - Immediate Trigger for immediate transmission 1301 * 001b - Time Trigger for receive triggers 1302 * 010b - Single Shot Transmit Trigger for exclusive time windows 1303 * 011b - Transmit Start Trigger for merged arbitrating time windows 1304 * 100b - Transmit Stop Trigger for merged arbitrating time windows 1305 * others - no action 1306 * The time of the trigger is defined by TT_TRIG. TTPTR selects the TB slot for the 1307 * transmit triggers. See Chapter 6.4 for more details. 1308 */ 1309 #define CAN_TRIG_CFG_TTYPE_MASK (0x700U) 1310 #define CAN_TRIG_CFG_TTYPE_SHIFT (8U) 1311 #define CAN_TRIG_CFG_TTYPE_SET(x) (((uint16_t)(x) << CAN_TRIG_CFG_TTYPE_SHIFT) & CAN_TRIG_CFG_TTYPE_MASK) 1312 #define CAN_TRIG_CFG_TTYPE_GET(x) (((uint16_t)(x) & CAN_TRIG_CFG_TTYPE_MASK) >> CAN_TRIG_CFG_TTYPE_SHIFT) 1313 1314 /* 1315 * TTPTR (RW) 1316 * 1317 * Transmit Trigger TB slot Pointer 1318 * If TTPTR is too big and points to a slot that is not available, then TEIF is set and no 1319 * new trigger can be activated after a write access to TT_TRIG_1. 1320 * If TTPTR points to an empty slot, then TEIF will be set at the moment, when the 1321 * trigger time is reached. 1322 */ 1323 #define CAN_TRIG_CFG_TTPTR_MASK (0x3FU) 1324 #define CAN_TRIG_CFG_TTPTR_SHIFT (0U) 1325 #define CAN_TRIG_CFG_TTPTR_SET(x) (((uint16_t)(x) << CAN_TRIG_CFG_TTPTR_SHIFT) & CAN_TRIG_CFG_TTPTR_MASK) 1326 #define CAN_TRIG_CFG_TTPTR_GET(x) (((uint16_t)(x) & CAN_TRIG_CFG_TTPTR_MASK) >> CAN_TRIG_CFG_TTPTR_SHIFT) 1327 1328 /* Bitfield definition for register: TT_TRIG */ 1329 /* 1330 * TT_TRIG (RW) 1331 * 1332 * Trigger Time 1333 * TT_TRIG(15:0) defines the cycle time for a trigger. 1334 * For a transmission trigger theearliest point of transmission of the SOF of the appropriate frame will be TT_TRIG+1. 1335 */ 1336 #define CAN_TT_TRIG_TT_TRIG_MASK (0xFFFFU) 1337 #define CAN_TT_TRIG_TT_TRIG_SHIFT (0U) 1338 #define CAN_TT_TRIG_TT_TRIG_SET(x) (((uint16_t)(x) << CAN_TT_TRIG_TT_TRIG_SHIFT) & CAN_TT_TRIG_TT_TRIG_MASK) 1339 #define CAN_TT_TRIG_TT_TRIG_GET(x) (((uint16_t)(x) & CAN_TT_TRIG_TT_TRIG_MASK) >> CAN_TT_TRIG_TT_TRIG_SHIFT) 1340 1341 /* Bitfield definition for register: TT_WTRIG */ 1342 /* 1343 * TT_WTRIG (RW) 1344 * 1345 * Watch Trigger Time 1346 * TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch trigger isthe maximum cycle time 0xffff. 1347 */ 1348 #define CAN_TT_WTRIG_TT_WTRIG_MASK (0xFFFFU) 1349 #define CAN_TT_WTRIG_TT_WTRIG_SHIFT (0U) 1350 #define CAN_TT_WTRIG_TT_WTRIG_SET(x) (((uint16_t)(x) << CAN_TT_WTRIG_TT_WTRIG_SHIFT) & CAN_TT_WTRIG_TT_WTRIG_MASK) 1351 #define CAN_TT_WTRIG_TT_WTRIG_GET(x) (((uint16_t)(x) & CAN_TT_WTRIG_TT_WTRIG_MASK) >> CAN_TT_WTRIG_TT_WTRIG_SHIFT) 1352 1353 1354 1355 /* RBUF register group index macro definition */ 1356 #define CAN_RBUF_BUF0 (0UL) 1357 #define CAN_RBUF_BUF1 (1UL) 1358 #define CAN_RBUF_BUF2 (2UL) 1359 #define CAN_RBUF_BUF3 (3UL) 1360 #define CAN_RBUF_BUF4 (4UL) 1361 #define CAN_RBUF_BUF5 (5UL) 1362 #define CAN_RBUF_BUF6 (6UL) 1363 #define CAN_RBUF_BUF7 (7UL) 1364 #define CAN_RBUF_BUF8 (8UL) 1365 #define CAN_RBUF_BUF9 (9UL) 1366 #define CAN_RBUF_BUF10 (10UL) 1367 #define CAN_RBUF_BUF11 (11UL) 1368 #define CAN_RBUF_BUF12 (12UL) 1369 #define CAN_RBUF_BUF13 (13UL) 1370 #define CAN_RBUF_BUF14 (14UL) 1371 #define CAN_RBUF_BUF15 (15UL) 1372 #define CAN_RBUF_BUF16 (16UL) 1373 #define CAN_RBUF_BUF17 (17UL) 1374 #define CAN_RBUF_BUF18 (18UL) 1375 #define CAN_RBUF_BUF19 (19UL) 1376 1377 /* TBUF register group index macro definition */ 1378 #define CAN_TBUF_BUF0 (0UL) 1379 #define CAN_TBUF_BUF1 (1UL) 1380 #define CAN_TBUF_BUF2 (2UL) 1381 #define CAN_TBUF_BUF3 (3UL) 1382 #define CAN_TBUF_BUF4 (4UL) 1383 #define CAN_TBUF_BUF5 (5UL) 1384 #define CAN_TBUF_BUF6 (6UL) 1385 #define CAN_TBUF_BUF7 (7UL) 1386 #define CAN_TBUF_BUF8 (8UL) 1387 #define CAN_TBUF_BUF9 (9UL) 1388 #define CAN_TBUF_BUF10 (10UL) 1389 #define CAN_TBUF_BUF11 (11UL) 1390 #define CAN_TBUF_BUF12 (12UL) 1391 #define CAN_TBUF_BUF13 (13UL) 1392 #define CAN_TBUF_BUF14 (14UL) 1393 #define CAN_TBUF_BUF15 (15UL) 1394 #define CAN_TBUF_BUF16 (16UL) 1395 #define CAN_TBUF_BUF17 (17UL) 1396 1397 /* TTS register group index macro definition */ 1398 #define CAN_TTS_WRD0 (0UL) 1399 #define CAN_TTS_WRD1 (1UL) 1400 1401 1402 #endif /* HPM_CAN_H */ 1403