1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_SDMMC_REG_H_ 15 #define _SOC_SDMMC_REG_H_ 16 #include "soc.h" 17 18 #define SDMMC_CTRL_REG (DR_REG_SDMMC_BASE + 0x00) 19 #define SDMMC_PWREN_REG (DR_REG_SDMMC_BASE + 0x04) 20 #define SDMMC_CLKDIV_REG (DR_REG_SDMMC_BASE + 0x08) 21 #define SDMMC_CLKSRC_REG (DR_REG_SDMMC_BASE + 0x0c) 22 #define SDMMC_CLKENA_REG (DR_REG_SDMMC_BASE + 0x10) 23 #define SDMMC_TMOUT_REG (DR_REG_SDMMC_BASE + 0x14) 24 #define SDMMC_CTYPE_REG (DR_REG_SDMMC_BASE + 0x18) 25 #define SDMMC_BLKSIZ_REG (DR_REG_SDMMC_BASE + 0x1c) 26 #define SDMMC_BYTCNT_REG (DR_REG_SDMMC_BASE + 0x20) 27 #define SDMMC_INTMASK_REG (DR_REG_SDMMC_BASE + 0x24) 28 #define SDMMC_CMDARG_REG (DR_REG_SDMMC_BASE + 0x28) 29 #define SDMMC_CMD_REG (DR_REG_SDMMC_BASE + 0x2c) 30 #define SDMMC_RESP0_REG (DR_REG_SDMMC_BASE + 0x30) 31 #define SDMMC_RESP1_REG (DR_REG_SDMMC_BASE + 0x34) 32 #define SDMMC_RESP2_REG (DR_REG_SDMMC_BASE + 0x38) 33 #define SDMMC_RESP3_REG (DR_REG_SDMMC_BASE + 0x3c) 34 35 #define SDMMC_MINTSTS_REG (DR_REG_SDMMC_BASE + 0x40) 36 #define SDMMC_RINTSTS_REG (DR_REG_SDMMC_BASE + 0x44) 37 #define SDMMC_STATUS_REG (DR_REG_SDMMC_BASE + 0x48) 38 #define SDMMC_FIFOTH_REG (DR_REG_SDMMC_BASE + 0x4c) 39 #define SDMMC_CDETECT_REG (DR_REG_SDMMC_BASE + 0x50) 40 #define SDMMC_WRTPRT_REG (DR_REG_SDMMC_BASE + 0x54) 41 #define SDMMC_GPIO_REG (DR_REG_SDMMC_BASE + 0x58) 42 #define SDMMC_TCBCNT_REG (DR_REG_SDMMC_BASE + 0x5c) 43 #define SDMMC_TBBCNT_REG (DR_REG_SDMMC_BASE + 0x60) 44 #define SDMMC_DEBNCE_REG (DR_REG_SDMMC_BASE + 0x64) 45 #define SDMMC_USRID_REG (DR_REG_SDMMC_BASE + 0x68) 46 #define SDMMC_VERID_REG (DR_REG_SDMMC_BASE + 0x6c) 47 #define SDMMC_HCON_REG (DR_REG_SDMMC_BASE + 0x70) 48 #define SDMMC_UHS_REG_REG (DR_REG_SDMMC_BASE + 0x74) 49 #define SDMMC_RST_N_REG (DR_REG_SDMMC_BASE + 0x78) 50 #define SDMMC_BMOD_REG (DR_REG_SDMMC_BASE + 0x80) 51 #define SDMMC_PLDMND_REG (DR_REG_SDMMC_BASE + 0x84) 52 #define SDMMC_DBADDR_REG (DR_REG_SDMMC_BASE + 0x88) 53 #define SDMMC_DBADDRU_REG (DR_REG_SDMMC_BASE + 0x8c) 54 #define SDMMC_IDSTS_REG (DR_REG_SDMMC_BASE + 0x8c) 55 #define SDMMC_IDINTEN_REG (DR_REG_SDMMC_BASE + 0x90) 56 #define SDMMC_DSCADDR_REG (DR_REG_SDMMC_BASE + 0x94) 57 #define SDMMC_DSCADDRL_REG (DR_REG_SDMMC_BASE + 0x98) 58 #define SDMMC_DSCADDRU_REG (DR_REG_SDMMC_BASE + 0x9c) 59 #define SDMMC_BUFADDRL_REG (DR_REG_SDMMC_BASE + 0xa0) 60 #define SDMMC_BUFADDRU_REG (DR_REG_SDMMC_BASE + 0xa4) 61 #define SDMMC_CARDTHRCTL_REG (DR_REG_SDMMC_BASE + 0x100) 62 #define SDMMC_BACK_END_POWER_REG (DR_REG_SDMMC_BASE + 0x104) 63 #define SDMMC_UHS_REG_EXT_REG (DR_REG_SDMMC_BASE + 0x108) 64 #define SDMMC_EMMC_DDR_REG_REG (DR_REG_SDMMC_BASE + 0x10c) 65 #define SDMMC_ENABLE_SHIFT_REG (DR_REG_SDMMC_BASE + 0x110) 66 67 #define SDMMC_CLOCK_REG (DR_REG_SDMMC_BASE + 0x800) 68 69 #define SDMMC_INTMASK_IO_SLOT1 BIT(17) 70 #define SDMMC_INTMASK_IO_SLOT0 BIT(16) 71 #define SDMMC_INTMASK_EBE BIT(15) 72 #define SDMMC_INTMASK_ACD BIT(14) 73 #define SDMMC_INTMASK_SBE BIT(13) 74 #define SDMMC_INTMASK_BCI BIT(13) 75 #define SDMMC_INTMASK_HLE BIT(12) 76 #define SDMMC_INTMASK_FRUN BIT(11) 77 #define SDMMC_INTMASK_HTO BIT(10) 78 #define SDMMC_INTMASK_DTO BIT(9) 79 #define SDMMC_INTMASK_RTO BIT(8) 80 #define SDMMC_INTMASK_DCRC BIT(7) 81 #define SDMMC_INTMASK_RCRC BIT(6) 82 #define SDMMC_INTMASK_RXDR BIT(5) 83 #define SDMMC_INTMASK_TXDR BIT(4) 84 #define SDMMC_INTMASK_DATA_OVER BIT(3) 85 #define SDMMC_INTMASK_CMD_DONE BIT(2) 86 #define SDMMC_INTMASK_RESP_ERR BIT(1) 87 #define SDMMC_INTMASK_CD BIT(0) 88 89 #define SDMMC_IDMAC_INTMASK_AI BIT(9) 90 #define SDMMC_IDMAC_INTMASK_NI BIT(8) 91 #define SDMMC_IDMAC_INTMASK_CES BIT(5) 92 #define SDMMC_IDMAC_INTMASK_DU BIT(4) 93 #define SDMMC_IDMAC_INTMASK_FBE BIT(2) 94 #define SDMMC_IDMAC_INTMASK_RI BIT(1) 95 #define SDMMC_IDMAC_INTMASK_TI BIT(0) 96 97 #endif /* _SOC_SDMMC_REG_H_ */ 98