1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_SDMV2_H 10 #define HPM_SDMV2_H 11 12 typedef struct { 13 __RW uint32_t CTRL; /* 0x0: SDM control register */ 14 __RW uint32_t INT_EN; /* 0x4: Interrupt enable register. */ 15 __R uint32_t STATUS; /* 0x8: Status Registers */ 16 __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ 17 struct { 18 __RW uint32_t SDFIFOCTRL; /* 0x10: Data FIFO Path Control Register */ 19 __RW uint32_t SDCTRLP; /* 0x14: Data Path Control Primary Register */ 20 __RW uint32_t SDCTRLE; /* 0x18: Data Path Control Extra Register */ 21 __RW uint32_t SDST; /* 0x1C: Data Path Status */ 22 __R uint32_t SDATA; /* 0x20: Data */ 23 __R uint32_t SDFIFO; /* 0x24: FIFO Data */ 24 __R uint32_t SCAMP; /* 0x28: instant Amplitude Results */ 25 __RW uint32_t SCHTL; /* 0x2C: Amplitude Threshold for High Limit */ 26 __RW uint32_t SCHTLZ; /* 0x30: Amplitude Threshold for zero crossing */ 27 __RW uint32_t SCLLT; /* 0x34: Amplitude Threshold for low limit */ 28 __RW uint32_t SCCTRL; /* 0x38: Amplitude Path Control */ 29 __RW uint32_t SCST; /* 0x3C: Amplitude Path Status */ 30 __R uint8_t RESERVED0[16]; /* 0x40 - 0x4F: Reserved */ 31 } CH[1]; 32 } SDMV2_Type; 33 34 35 /* Bitfield definition for register: CTRL */ 36 /* 37 * SFTRST (RW) 38 * 39 * software reset the module if asserted to be1’b1. 40 */ 41 #define SDMV2_CTRL_SFTRST_MASK (0x80000000UL) 42 #define SDMV2_CTRL_SFTRST_SHIFT (31U) 43 #define SDMV2_CTRL_SFTRST_SET(x) (((uint32_t)(x) << SDMV2_CTRL_SFTRST_SHIFT) & SDMV2_CTRL_SFTRST_MASK) 44 #define SDMV2_CTRL_SFTRST_GET(x) (((uint32_t)(x) & SDMV2_CTRL_SFTRST_MASK) >> SDMV2_CTRL_SFTRST_SHIFT) 45 46 /* 47 * CHMD (RW) 48 * 49 * Channel Rcv mode 50 * Bits[2:0] for Ch0. 51 * Bits[5:3] for Ch1 52 * Bits[8:6] for Ch2 53 * Bits[11:9] for Ch3 54 * 3'b000: Capture at posedge of MCLK 55 * 3'b001: Capture at both posedge and negedge of MCLK 56 * 3'b010: Manchestor Mode 57 * 3'b011: Capture at negedge of MCLK 58 * 3'b100: Capture at every other posedge of MCLK 59 * 3'b101: Capture at every other negedge of MCLK 60 * Others: Undefined 61 */ 62 #define SDMV2_CTRL_CHMD_MASK (0x3FFC000UL) 63 #define SDMV2_CTRL_CHMD_SHIFT (14U) 64 #define SDMV2_CTRL_CHMD_SET(x) (((uint32_t)(x) << SDMV2_CTRL_CHMD_SHIFT) & SDMV2_CTRL_CHMD_MASK) 65 #define SDMV2_CTRL_CHMD_GET(x) (((uint32_t)(x) & SDMV2_CTRL_CHMD_MASK) >> SDMV2_CTRL_CHMD_SHIFT) 66 67 /* 68 * SYNC_MCLK (RW) 69 * 70 * Asserted to double sync the mclk input pin before its usage inside the module 71 */ 72 #define SDMV2_CTRL_SYNC_MCLK_MASK (0x3C00U) 73 #define SDMV2_CTRL_SYNC_MCLK_SHIFT (10U) 74 #define SDMV2_CTRL_SYNC_MCLK_SET(x) (((uint32_t)(x) << SDMV2_CTRL_SYNC_MCLK_SHIFT) & SDMV2_CTRL_SYNC_MCLK_MASK) 75 #define SDMV2_CTRL_SYNC_MCLK_GET(x) (((uint32_t)(x) & SDMV2_CTRL_SYNC_MCLK_MASK) >> SDMV2_CTRL_SYNC_MCLK_SHIFT) 76 77 /* 78 * SYNC_MDAT (RW) 79 * 80 * Asserted to double sync the mdat input pin before its usage inside the module 81 */ 82 #define SDMV2_CTRL_SYNC_MDAT_MASK (0x3C0U) 83 #define SDMV2_CTRL_SYNC_MDAT_SHIFT (6U) 84 #define SDMV2_CTRL_SYNC_MDAT_SET(x) (((uint32_t)(x) << SDMV2_CTRL_SYNC_MDAT_SHIFT) & SDMV2_CTRL_SYNC_MDAT_MASK) 85 #define SDMV2_CTRL_SYNC_MDAT_GET(x) (((uint32_t)(x) & SDMV2_CTRL_SYNC_MDAT_MASK) >> SDMV2_CTRL_SYNC_MDAT_SHIFT) 86 87 /* 88 * CH_EN (RW) 89 * 90 * Channel Enable 91 */ 92 #define SDMV2_CTRL_CH_EN_MASK (0x3CU) 93 #define SDMV2_CTRL_CH_EN_SHIFT (2U) 94 #define SDMV2_CTRL_CH_EN_SET(x) (((uint32_t)(x) << SDMV2_CTRL_CH_EN_SHIFT) & SDMV2_CTRL_CH_EN_MASK) 95 #define SDMV2_CTRL_CH_EN_GET(x) (((uint32_t)(x) & SDMV2_CTRL_CH_EN_MASK) >> SDMV2_CTRL_CH_EN_SHIFT) 96 97 /* 98 * IE (RW) 99 * 100 * Interrupt Enable 101 */ 102 #define SDMV2_CTRL_IE_MASK (0x2U) 103 #define SDMV2_CTRL_IE_SHIFT (1U) 104 #define SDMV2_CTRL_IE_SET(x) (((uint32_t)(x) << SDMV2_CTRL_IE_SHIFT) & SDMV2_CTRL_IE_MASK) 105 #define SDMV2_CTRL_IE_GET(x) (((uint32_t)(x) & SDMV2_CTRL_IE_MASK) >> SDMV2_CTRL_IE_SHIFT) 106 107 /* Bitfield definition for register: INT_EN */ 108 /* 109 * CH0DRY (RW) 110 * 111 * Ch0 Data Ready interrupt enable 112 */ 113 #define SDMV2_INT_EN_CH0DRY_MASK (0x10U) 114 #define SDMV2_INT_EN_CH0DRY_SHIFT (4U) 115 #define SDMV2_INT_EN_CH0DRY_SET(x) (((uint32_t)(x) << SDMV2_INT_EN_CH0DRY_SHIFT) & SDMV2_INT_EN_CH0DRY_MASK) 116 #define SDMV2_INT_EN_CH0DRY_GET(x) (((uint32_t)(x) & SDMV2_INT_EN_CH0DRY_MASK) >> SDMV2_INT_EN_CH0DRY_SHIFT) 117 118 /* 119 * CH0ERR (RW) 120 * 121 * Ch0 Error interrupt enable 122 */ 123 #define SDMV2_INT_EN_CH0ERR_MASK (0x1U) 124 #define SDMV2_INT_EN_CH0ERR_SHIFT (0U) 125 #define SDMV2_INT_EN_CH0ERR_SET(x) (((uint32_t)(x) << SDMV2_INT_EN_CH0ERR_SHIFT) & SDMV2_INT_EN_CH0ERR_MASK) 126 #define SDMV2_INT_EN_CH0ERR_GET(x) (((uint32_t)(x) & SDMV2_INT_EN_CH0ERR_MASK) >> SDMV2_INT_EN_CH0ERR_SHIFT) 127 128 /* Bitfield definition for register: STATUS */ 129 /* 130 * CH0DRY (RO) 131 * 132 * Ch0 Data Ready 133 */ 134 #define SDMV2_STATUS_CH0DRY_MASK (0x2U) 135 #define SDMV2_STATUS_CH0DRY_SHIFT (1U) 136 #define SDMV2_STATUS_CH0DRY_GET(x) (((uint32_t)(x) & SDMV2_STATUS_CH0DRY_MASK) >> SDMV2_STATUS_CH0DRY_SHIFT) 137 138 /* 139 * CH0ERR (RO) 140 * 141 * Ch0 Error 142 */ 143 #define SDMV2_STATUS_CH0ERR_MASK (0x1U) 144 #define SDMV2_STATUS_CH0ERR_SHIFT (0U) 145 #define SDMV2_STATUS_CH0ERR_GET(x) (((uint32_t)(x) & SDMV2_STATUS_CH0ERR_MASK) >> SDMV2_STATUS_CH0ERR_SHIFT) 146 147 /* Bitfield definition for register of struct array CH: SDFIFOCTRL */ 148 /* 149 * THRSH (RW) 150 * 151 * FIFO threshold (0,..,16) (fillings > threshold, then gen int) 152 */ 153 #define SDMV2_CH_SDFIFOCTRL_THRSH_MASK (0x1F0U) 154 #define SDMV2_CH_SDFIFOCTRL_THRSH_SHIFT (4U) 155 #define SDMV2_CH_SDFIFOCTRL_THRSH_SET(x) (((uint32_t)(x) << SDMV2_CH_SDFIFOCTRL_THRSH_SHIFT) & SDMV2_CH_SDFIFOCTRL_THRSH_MASK) 156 #define SDMV2_CH_SDFIFOCTRL_THRSH_GET(x) (((uint32_t)(x) & SDMV2_CH_SDFIFOCTRL_THRSH_MASK) >> SDMV2_CH_SDFIFOCTRL_THRSH_SHIFT) 157 158 /* 159 * D_RDY_INT_EN (RW) 160 * 161 * FIFO data ready interrupt enable 162 */ 163 #define SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK (0x4U) 164 #define SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT (2U) 165 #define SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_SET(x) (((uint32_t)(x) << SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT) & SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK) 166 #define SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_GET(x) (((uint32_t)(x) & SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK) >> SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT) 167 168 /* Bitfield definition for register of struct array CH: SDCTRLP */ 169 /* 170 * MANCH_THR (RW) 171 * 172 * Manchester Decoding threshold. 3/4 of PERIOD_MCLK[7:0] 173 */ 174 #define SDMV2_CH_SDCTRLP_MANCH_THR_MASK (0xFE000000UL) 175 #define SDMV2_CH_SDCTRLP_MANCH_THR_SHIFT (25U) 176 #define SDMV2_CH_SDCTRLP_MANCH_THR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_MANCH_THR_SHIFT) & SDMV2_CH_SDCTRLP_MANCH_THR_MASK) 177 #define SDMV2_CH_SDCTRLP_MANCH_THR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_MANCH_THR_MASK) >> SDMV2_CH_SDCTRLP_MANCH_THR_SHIFT) 178 179 /* 180 * WDOG_THR (RW) 181 * 182 * Watch dog threshold for channel failure of CLK halting 183 */ 184 #define SDMV2_CH_SDCTRLP_WDOG_THR_MASK (0x1FE0000UL) 185 #define SDMV2_CH_SDCTRLP_WDOG_THR_SHIFT (17U) 186 #define SDMV2_CH_SDCTRLP_WDOG_THR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_WDOG_THR_SHIFT) & SDMV2_CH_SDCTRLP_WDOG_THR_MASK) 187 #define SDMV2_CH_SDCTRLP_WDOG_THR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_WDOG_THR_MASK) >> SDMV2_CH_SDCTRLP_WDOG_THR_SHIFT) 188 189 /* 190 * AF_IE (RW) 191 * 192 * Acknowledge feedback interrupt enable 193 */ 194 #define SDMV2_CH_SDCTRLP_AF_IE_MASK (0x10000UL) 195 #define SDMV2_CH_SDCTRLP_AF_IE_SHIFT (16U) 196 #define SDMV2_CH_SDCTRLP_AF_IE_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_AF_IE_SHIFT) & SDMV2_CH_SDCTRLP_AF_IE_MASK) 197 #define SDMV2_CH_SDCTRLP_AF_IE_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_AF_IE_MASK) >> SDMV2_CH_SDCTRLP_AF_IE_SHIFT) 198 199 /* 200 * DFFOVIE (RW) 201 * 202 * Ch Data FIFO overflow interrupt enable 203 */ 204 #define SDMV2_CH_SDCTRLP_DFFOVIE_MASK (0x8000U) 205 #define SDMV2_CH_SDCTRLP_DFFOVIE_SHIFT (15U) 206 #define SDMV2_CH_SDCTRLP_DFFOVIE_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_DFFOVIE_SHIFT) & SDMV2_CH_SDCTRLP_DFFOVIE_MASK) 207 #define SDMV2_CH_SDCTRLP_DFFOVIE_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_DFFOVIE_MASK) >> SDMV2_CH_SDCTRLP_DFFOVIE_SHIFT) 208 209 /* 210 * DSATIE (RW) 211 * 212 * Ch CIC Data Saturation Interrupt Enable 213 */ 214 #define SDMV2_CH_SDCTRLP_DSATIE_MASK (0x4000U) 215 #define SDMV2_CH_SDCTRLP_DSATIE_SHIFT (14U) 216 #define SDMV2_CH_SDCTRLP_DSATIE_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_DSATIE_SHIFT) & SDMV2_CH_SDCTRLP_DSATIE_MASK) 217 #define SDMV2_CH_SDCTRLP_DSATIE_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_DSATIE_MASK) >> SDMV2_CH_SDCTRLP_DSATIE_SHIFT) 218 219 /* 220 * DRIE (RW) 221 * 222 * Ch Data Ready Interrupt Enable 223 */ 224 #define SDMV2_CH_SDCTRLP_DRIE_MASK (0x2000U) 225 #define SDMV2_CH_SDCTRLP_DRIE_SHIFT (13U) 226 #define SDMV2_CH_SDCTRLP_DRIE_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_DRIE_SHIFT) & SDMV2_CH_SDCTRLP_DRIE_MASK) 227 #define SDMV2_CH_SDCTRLP_DRIE_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_DRIE_MASK) >> SDMV2_CH_SDCTRLP_DRIE_SHIFT) 228 229 /* 230 * SYNCSEL (RW) 231 * 232 * Select the PWM SYNC Source 233 */ 234 #define SDMV2_CH_SDCTRLP_SYNCSEL_MASK (0x1F80U) 235 #define SDMV2_CH_SDCTRLP_SYNCSEL_SHIFT (7U) 236 #define SDMV2_CH_SDCTRLP_SYNCSEL_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_SYNCSEL_SHIFT) & SDMV2_CH_SDCTRLP_SYNCSEL_MASK) 237 #define SDMV2_CH_SDCTRLP_SYNCSEL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_SYNCSEL_MASK) >> SDMV2_CH_SDCTRLP_SYNCSEL_SHIFT) 238 239 /* 240 * FFSYNCCLREN (RW) 241 * 242 * Auto clear FIFO when a new SDSYNC event is found. Only valid when WTSYNCEN=1 243 */ 244 #define SDMV2_CH_SDCTRLP_FFSYNCCLREN_MASK (0x40U) 245 #define SDMV2_CH_SDCTRLP_FFSYNCCLREN_SHIFT (6U) 246 #define SDMV2_CH_SDCTRLP_FFSYNCCLREN_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_FFSYNCCLREN_SHIFT) & SDMV2_CH_SDCTRLP_FFSYNCCLREN_MASK) 247 #define SDMV2_CH_SDCTRLP_FFSYNCCLREN_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_FFSYNCCLREN_MASK) >> SDMV2_CH_SDCTRLP_FFSYNCCLREN_SHIFT) 248 249 /* 250 * WTSYNACLR (RW) 251 * 252 * 1: Asserted to Auto clear WTSYNFLG when the SDFFINT is gen 253 * 0: WTSYNFLG should be cleared manually by WTSYNMCLR 254 */ 255 #define SDMV2_CH_SDCTRLP_WTSYNACLR_MASK (0x20U) 256 #define SDMV2_CH_SDCTRLP_WTSYNACLR_SHIFT (5U) 257 #define SDMV2_CH_SDCTRLP_WTSYNACLR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_WTSYNACLR_SHIFT) & SDMV2_CH_SDCTRLP_WTSYNACLR_MASK) 258 #define SDMV2_CH_SDCTRLP_WTSYNACLR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_WTSYNACLR_MASK) >> SDMV2_CH_SDCTRLP_WTSYNACLR_SHIFT) 259 260 /* 261 * WTSYNMCLR (RW) 262 * 263 * 1: Manually clear WTSYNFLG. Auto-clear. 264 */ 265 #define SDMV2_CH_SDCTRLP_WTSYNMCLR_MASK (0x10U) 266 #define SDMV2_CH_SDCTRLP_WTSYNMCLR_SHIFT (4U) 267 #define SDMV2_CH_SDCTRLP_WTSYNMCLR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_WTSYNMCLR_SHIFT) & SDMV2_CH_SDCTRLP_WTSYNMCLR_MASK) 268 #define SDMV2_CH_SDCTRLP_WTSYNMCLR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_WTSYNMCLR_MASK) >> SDMV2_CH_SDCTRLP_WTSYNMCLR_SHIFT) 269 270 /* 271 * WTSYNCEN (RW) 272 * 273 * 1: Start to store data only after PWM SYNC event 274 * 0: Start to store data whenever enabled 275 */ 276 #define SDMV2_CH_SDCTRLP_WTSYNCEN_MASK (0x8U) 277 #define SDMV2_CH_SDCTRLP_WTSYNCEN_SHIFT (3U) 278 #define SDMV2_CH_SDCTRLP_WTSYNCEN_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_WTSYNCEN_SHIFT) & SDMV2_CH_SDCTRLP_WTSYNCEN_MASK) 279 #define SDMV2_CH_SDCTRLP_WTSYNCEN_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_WTSYNCEN_MASK) >> SDMV2_CH_SDCTRLP_WTSYNCEN_SHIFT) 280 281 /* 282 * D32 (RW) 283 * 284 * 1:32 bit data 285 * 0:16 bit data 286 */ 287 #define SDMV2_CH_SDCTRLP_D32_MASK (0x4U) 288 #define SDMV2_CH_SDCTRLP_D32_SHIFT (2U) 289 #define SDMV2_CH_SDCTRLP_D32_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_D32_SHIFT) & SDMV2_CH_SDCTRLP_D32_MASK) 290 #define SDMV2_CH_SDCTRLP_D32_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_D32_MASK) >> SDMV2_CH_SDCTRLP_D32_SHIFT) 291 292 /* 293 * DR_OPT (RW) 294 * 295 * 1: Use Data FIFO Ready as data ready when fifo fillings are greater than the threshold 296 * 0: Use Data Reg Ready as data ready 297 */ 298 #define SDMV2_CH_SDCTRLP_DR_OPT_MASK (0x2U) 299 #define SDMV2_CH_SDCTRLP_DR_OPT_SHIFT (1U) 300 #define SDMV2_CH_SDCTRLP_DR_OPT_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_DR_OPT_SHIFT) & SDMV2_CH_SDCTRLP_DR_OPT_MASK) 301 #define SDMV2_CH_SDCTRLP_DR_OPT_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_DR_OPT_MASK) >> SDMV2_CH_SDCTRLP_DR_OPT_SHIFT) 302 303 /* 304 * EN (RW) 305 * 306 * Data Path Enable 307 */ 308 #define SDMV2_CH_SDCTRLP_EN_MASK (0x1U) 309 #define SDMV2_CH_SDCTRLP_EN_SHIFT (0U) 310 #define SDMV2_CH_SDCTRLP_EN_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_EN_SHIFT) & SDMV2_CH_SDCTRLP_EN_MASK) 311 #define SDMV2_CH_SDCTRLP_EN_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_EN_MASK) >> SDMV2_CH_SDCTRLP_EN_SHIFT) 312 313 /* Bitfield definition for register of struct array CH: SDCTRLE */ 314 /* 315 * 2ND_CIC_SCL (RW) 316 * 317 * the shifter pace for the output of the 2ns stage CIC 318 * 0: shift right 0 319 * … 320 * n: shift right n steps 321 * max 17, so needs 5 bits 322 */ 323 #define SDMV2_CH_SDCTRLE_2ND_CIC_SCL_MASK (0x3E00000UL) 324 #define SDMV2_CH_SDCTRLE_2ND_CIC_SCL_SHIFT (21U) 325 #define SDMV2_CH_SDCTRLE_2ND_CIC_SCL_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_2ND_CIC_SCL_SHIFT) & SDMV2_CH_SDCTRLE_2ND_CIC_SCL_MASK) 326 #define SDMV2_CH_SDCTRLE_2ND_CIC_SCL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_2ND_CIC_SCL_MASK) >> SDMV2_CH_SDCTRLE_2ND_CIC_SCL_SHIFT) 327 328 /* 329 * 2ND_SGD_ORDER (RW) 330 * 331 * 2nd CIC order 332 * 0: SYNC1 333 * 1: SYNC2 334 * 2: SYNC3 335 * 3: FAST_SYNC 336 */ 337 #define SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_MASK (0x180000UL) 338 #define SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_SHIFT (19U) 339 #define SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_SHIFT) & SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_MASK) 340 #define SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_MASK) >> SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_SHIFT) 341 342 /* 343 * SGD_ORDR (RW) 344 * 345 * CIC order 346 * 0: SYNC1 347 * 1: SYNC2 348 * 2: SYNC3 349 * 3: FAST_SYNC 350 */ 351 #define SDMV2_CH_SDCTRLE_SGD_ORDR_MASK (0x60000UL) 352 #define SDMV2_CH_SDCTRLE_SGD_ORDR_SHIFT (17U) 353 #define SDMV2_CH_SDCTRLE_SGD_ORDR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_SGD_ORDR_SHIFT) & SDMV2_CH_SDCTRLE_SGD_ORDR_MASK) 354 #define SDMV2_CH_SDCTRLE_SGD_ORDR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_SGD_ORDR_MASK) >> SDMV2_CH_SDCTRLE_SGD_ORDR_SHIFT) 355 356 /* 357 * PWMSYNC (RW) 358 * 359 * Asserted to double sync the PWM trigger signal 360 */ 361 #define SDMV2_CH_SDCTRLE_PWMSYNC_MASK (0x10000UL) 362 #define SDMV2_CH_SDCTRLE_PWMSYNC_SHIFT (16U) 363 #define SDMV2_CH_SDCTRLE_PWMSYNC_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_PWMSYNC_SHIFT) & SDMV2_CH_SDCTRLE_PWMSYNC_MASK) 364 #define SDMV2_CH_SDCTRLE_PWMSYNC_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_PWMSYNC_MASK) >> SDMV2_CH_SDCTRLE_PWMSYNC_SHIFT) 365 366 /* 367 * USE_ALT (RW) 368 * 369 * Asserted to use alternative input. 370 * Alternative input has a restart_filt to reset the counter and start data transfer, and also it has an intermittent input clock to accompany the input data. 371 */ 372 #define SDMV2_CH_SDCTRLE_USE_ALT_MASK (0x8000U) 373 #define SDMV2_CH_SDCTRLE_USE_ALT_SHIFT (15U) 374 #define SDMV2_CH_SDCTRLE_USE_ALT_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_USE_ALT_SHIFT) & SDMV2_CH_SDCTRLE_USE_ALT_MASK) 375 #define SDMV2_CH_SDCTRLE_USE_ALT_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_USE_ALT_MASK) >> SDMV2_CH_SDCTRLE_USE_ALT_SHIFT) 376 377 /* 378 * CIC_SCL (RW) 379 * 380 * CIC shift control 381 */ 382 #define SDMV2_CH_SDCTRLE_CIC_SCL_MASK (0x7800U) 383 #define SDMV2_CH_SDCTRLE_CIC_SCL_SHIFT (11U) 384 #define SDMV2_CH_SDCTRLE_CIC_SCL_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_CIC_SCL_SHIFT) & SDMV2_CH_SDCTRLE_CIC_SCL_MASK) 385 #define SDMV2_CH_SDCTRLE_CIC_SCL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_CIC_SCL_MASK) >> SDMV2_CH_SDCTRLE_CIC_SCL_SHIFT) 386 387 /* 388 * CIC_DEC_RATIO (RW) 389 * 390 * CIC decimation ratio. 0 means div-by-256 391 */ 392 #define SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_MASK (0x7F8U) 393 #define SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT (3U) 394 #define SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) & SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_MASK) 395 #define SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_MASK) >> SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) 396 397 /* 398 * IGN_INI_SAMPLES (RW) 399 * 400 * NotZero: Don't store the first samples that are not accurate 401 * Zero: Store all samples 402 */ 403 #define SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_MASK (0x7U) 404 #define SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT (0U) 405 #define SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) & SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) 406 #define SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) >> SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) 407 408 /* Bitfield definition for register of struct array CH: SDST */ 409 /* 410 * PERIOD_MCLK (RO) 411 * 412 * maxim of mclk spacing in cycles, using edges of mclk signal. In manchester coding mode, it is just the period of MCLK. In other modes, it is almost the half period. 413 */ 414 #define SDMV2_CH_SDST_PERIOD_MCLK_MASK (0x7F800000UL) 415 #define SDMV2_CH_SDST_PERIOD_MCLK_SHIFT (23U) 416 #define SDMV2_CH_SDST_PERIOD_MCLK_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_PERIOD_MCLK_MASK) >> SDMV2_CH_SDST_PERIOD_MCLK_SHIFT) 417 418 /* 419 * 2ND_DSAT_ERR (W1C) 420 * 421 * CIC out Data saturation err. Error flag. 422 */ 423 #define SDMV2_CH_SDST_2ND_DSAT_ERR_MASK (0x800U) 424 #define SDMV2_CH_SDST_2ND_DSAT_ERR_SHIFT (11U) 425 #define SDMV2_CH_SDST_2ND_DSAT_ERR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDST_2ND_DSAT_ERR_SHIFT) & SDMV2_CH_SDST_2ND_DSAT_ERR_MASK) 426 #define SDMV2_CH_SDST_2ND_DSAT_ERR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_2ND_DSAT_ERR_MASK) >> SDMV2_CH_SDST_2ND_DSAT_ERR_SHIFT) 427 428 /* 429 * FIFO_DR (W1C) 430 * 431 * FIFO data ready 432 */ 433 #define SDMV2_CH_SDST_FIFO_DR_MASK (0x200U) 434 #define SDMV2_CH_SDST_FIFO_DR_SHIFT (9U) 435 #define SDMV2_CH_SDST_FIFO_DR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDST_FIFO_DR_SHIFT) & SDMV2_CH_SDST_FIFO_DR_MASK) 436 #define SDMV2_CH_SDST_FIFO_DR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_FIFO_DR_MASK) >> SDMV2_CH_SDST_FIFO_DR_SHIFT) 437 438 /* 439 * AF (W1C) 440 * 441 * Achnowledge flag 442 */ 443 #define SDMV2_CH_SDST_AF_MASK (0x100U) 444 #define SDMV2_CH_SDST_AF_SHIFT (8U) 445 #define SDMV2_CH_SDST_AF_SET(x) (((uint32_t)(x) << SDMV2_CH_SDST_AF_SHIFT) & SDMV2_CH_SDST_AF_MASK) 446 #define SDMV2_CH_SDST_AF_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_AF_MASK) >> SDMV2_CH_SDST_AF_SHIFT) 447 448 /* 449 * DOV_ERR (W1C) 450 * 451 * Data FIFO Overflow Error. Error flag. 452 */ 453 #define SDMV2_CH_SDST_DOV_ERR_MASK (0x80U) 454 #define SDMV2_CH_SDST_DOV_ERR_SHIFT (7U) 455 #define SDMV2_CH_SDST_DOV_ERR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDST_DOV_ERR_SHIFT) & SDMV2_CH_SDST_DOV_ERR_MASK) 456 #define SDMV2_CH_SDST_DOV_ERR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_DOV_ERR_MASK) >> SDMV2_CH_SDST_DOV_ERR_SHIFT) 457 458 /* 459 * DSAT_ERR (W1C) 460 * 461 * CIC out Data saturation err. Error flag. 462 */ 463 #define SDMV2_CH_SDST_DSAT_ERR_MASK (0x40U) 464 #define SDMV2_CH_SDST_DSAT_ERR_SHIFT (6U) 465 #define SDMV2_CH_SDST_DSAT_ERR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDST_DSAT_ERR_SHIFT) & SDMV2_CH_SDST_DSAT_ERR_MASK) 466 #define SDMV2_CH_SDST_DSAT_ERR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_DSAT_ERR_MASK) >> SDMV2_CH_SDST_DSAT_ERR_SHIFT) 467 468 /* 469 * WTSYNFLG (RO) 470 * 471 * Wait-for-sync event found 472 */ 473 #define SDMV2_CH_SDST_WTSYNFLG_MASK (0x20U) 474 #define SDMV2_CH_SDST_WTSYNFLG_SHIFT (5U) 475 #define SDMV2_CH_SDST_WTSYNFLG_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_WTSYNFLG_MASK) >> SDMV2_CH_SDST_WTSYNFLG_SHIFT) 476 477 /* 478 * FILL (RO) 479 * 480 * Data FIFO Fillings 481 */ 482 #define SDMV2_CH_SDST_FILL_MASK (0x1FU) 483 #define SDMV2_CH_SDST_FILL_SHIFT (0U) 484 #define SDMV2_CH_SDST_FILL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_FILL_MASK) >> SDMV2_CH_SDST_FILL_SHIFT) 485 486 /* Bitfield definition for register of struct array CH: SDATA */ 487 /* 488 * VAL (RO) 489 * 490 * Data 491 */ 492 #define SDMV2_CH_SDATA_VAL_MASK (0xFFFFFFFFUL) 493 #define SDMV2_CH_SDATA_VAL_SHIFT (0U) 494 #define SDMV2_CH_SDATA_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDATA_VAL_MASK) >> SDMV2_CH_SDATA_VAL_SHIFT) 495 496 /* Bitfield definition for register of struct array CH: SDFIFO */ 497 /* 498 * VAL (RO) 499 * 500 * FIFO Data 501 */ 502 #define SDMV2_CH_SDFIFO_VAL_MASK (0xFFFFFFFFUL) 503 #define SDMV2_CH_SDFIFO_VAL_SHIFT (0U) 504 #define SDMV2_CH_SDFIFO_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDFIFO_VAL_MASK) >> SDMV2_CH_SDFIFO_VAL_SHIFT) 505 506 /* Bitfield definition for register of struct array CH: SCAMP */ 507 /* 508 * VAL (RO) 509 * 510 * instant Amplitude Results 511 */ 512 #define SDMV2_CH_SCAMP_VAL_MASK (0xFFFFU) 513 #define SDMV2_CH_SCAMP_VAL_SHIFT (0U) 514 #define SDMV2_CH_SCAMP_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SCAMP_VAL_MASK) >> SDMV2_CH_SCAMP_VAL_SHIFT) 515 516 /* Bitfield definition for register of struct array CH: SCHTL */ 517 /* 518 * VAL (RW) 519 * 520 * Amplitude Threshold for High Limit 521 */ 522 #define SDMV2_CH_SCHTL_VAL_MASK (0xFFFFU) 523 #define SDMV2_CH_SCHTL_VAL_SHIFT (0U) 524 #define SDMV2_CH_SCHTL_VAL_SET(x) (((uint32_t)(x) << SDMV2_CH_SCHTL_VAL_SHIFT) & SDMV2_CH_SCHTL_VAL_MASK) 525 #define SDMV2_CH_SCHTL_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SCHTL_VAL_MASK) >> SDMV2_CH_SCHTL_VAL_SHIFT) 526 527 /* Bitfield definition for register of struct array CH: SCHTLZ */ 528 /* 529 * VAL (RW) 530 * 531 * Amplitude Threshold for zero crossing 532 */ 533 #define SDMV2_CH_SCHTLZ_VAL_MASK (0xFFFFU) 534 #define SDMV2_CH_SCHTLZ_VAL_SHIFT (0U) 535 #define SDMV2_CH_SCHTLZ_VAL_SET(x) (((uint32_t)(x) << SDMV2_CH_SCHTLZ_VAL_SHIFT) & SDMV2_CH_SCHTLZ_VAL_MASK) 536 #define SDMV2_CH_SCHTLZ_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SCHTLZ_VAL_MASK) >> SDMV2_CH_SCHTLZ_VAL_SHIFT) 537 538 /* Bitfield definition for register of struct array CH: SCLLT */ 539 /* 540 * VAL (RW) 541 * 542 * Amplitude Threshold for low limit 543 */ 544 #define SDMV2_CH_SCLLT_VAL_MASK (0xFFFFU) 545 #define SDMV2_CH_SCLLT_VAL_SHIFT (0U) 546 #define SDMV2_CH_SCLLT_VAL_SET(x) (((uint32_t)(x) << SDMV2_CH_SCLLT_VAL_SHIFT) & SDMV2_CH_SCLLT_VAL_MASK) 547 #define SDMV2_CH_SCLLT_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SCLLT_VAL_MASK) >> SDMV2_CH_SCLLT_VAL_SHIFT) 548 549 /* Bitfield definition for register of struct array CH: SCCTRL */ 550 /* 551 * 2ND_SGD_ORDR (RW) 552 * 553 * CIC decimation ratio. 0 means div-by-256 554 */ 555 #define SDMV2_CH_SCCTRL_2ND_SGD_ORDR_MASK (0xFF000000UL) 556 #define SDMV2_CH_SCCTRL_2ND_SGD_ORDR_SHIFT (24U) 557 #define SDMV2_CH_SCCTRL_2ND_SGD_ORDR_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_2ND_SGD_ORDR_SHIFT) & SDMV2_CH_SCCTRL_2ND_SGD_ORDR_MASK) 558 #define SDMV2_CH_SCCTRL_2ND_SGD_ORDR_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_2ND_SGD_ORDR_MASK) >> SDMV2_CH_SCCTRL_2ND_SGD_ORDR_SHIFT) 559 560 /* 561 * HZ_EN (RW) 562 * 563 * Zero Crossing Enable 564 */ 565 #define SDMV2_CH_SCCTRL_HZ_EN_MASK (0x800000UL) 566 #define SDMV2_CH_SCCTRL_HZ_EN_SHIFT (23U) 567 #define SDMV2_CH_SCCTRL_HZ_EN_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_HZ_EN_SHIFT) & SDMV2_CH_SCCTRL_HZ_EN_MASK) 568 #define SDMV2_CH_SCCTRL_HZ_EN_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_HZ_EN_MASK) >> SDMV2_CH_SCCTRL_HZ_EN_SHIFT) 569 570 /* 571 * MF_IE (RW) 572 * 573 * Module failure Interrupt enable 574 */ 575 #define SDMV2_CH_SCCTRL_MF_IE_MASK (0x400000UL) 576 #define SDMV2_CH_SCCTRL_MF_IE_SHIFT (22U) 577 #define SDMV2_CH_SCCTRL_MF_IE_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_MF_IE_SHIFT) & SDMV2_CH_SCCTRL_MF_IE_MASK) 578 #define SDMV2_CH_SCCTRL_MF_IE_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_MF_IE_MASK) >> SDMV2_CH_SCCTRL_MF_IE_SHIFT) 579 580 /* 581 * HL_IE (RW) 582 * 583 * HLT Interrupt Enable 584 */ 585 #define SDMV2_CH_SCCTRL_HL_IE_MASK (0x200000UL) 586 #define SDMV2_CH_SCCTRL_HL_IE_SHIFT (21U) 587 #define SDMV2_CH_SCCTRL_HL_IE_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_HL_IE_SHIFT) & SDMV2_CH_SCCTRL_HL_IE_MASK) 588 #define SDMV2_CH_SCCTRL_HL_IE_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_HL_IE_MASK) >> SDMV2_CH_SCCTRL_HL_IE_SHIFT) 589 590 /* 591 * LL_IE (RW) 592 * 593 * LLT interrupt Enable 594 */ 595 #define SDMV2_CH_SCCTRL_LL_IE_MASK (0x100000UL) 596 #define SDMV2_CH_SCCTRL_LL_IE_SHIFT (20U) 597 #define SDMV2_CH_SCCTRL_LL_IE_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_LL_IE_SHIFT) & SDMV2_CH_SCCTRL_LL_IE_MASK) 598 #define SDMV2_CH_SCCTRL_LL_IE_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_LL_IE_MASK) >> SDMV2_CH_SCCTRL_LL_IE_SHIFT) 599 600 /* 601 * SGD_ORDR (RW) 602 * 603 * CIC order 604 * 0: SYNC1 605 * 1: SYNC2 606 * 2: SYNC3 607 * 3: FAST_SYNC 608 */ 609 #define SDMV2_CH_SCCTRL_SGD_ORDR_MASK (0xC0000UL) 610 #define SDMV2_CH_SCCTRL_SGD_ORDR_SHIFT (18U) 611 #define SDMV2_CH_SCCTRL_SGD_ORDR_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_SGD_ORDR_SHIFT) & SDMV2_CH_SCCTRL_SGD_ORDR_MASK) 612 #define SDMV2_CH_SCCTRL_SGD_ORDR_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_SGD_ORDR_MASK) >> SDMV2_CH_SCCTRL_SGD_ORDR_SHIFT) 613 614 /* 615 * CIC_DEC_RATIO (RW) 616 * 617 * CIC decimation ratio. 0 means div-by-32 618 */ 619 #define SDMV2_CH_SCCTRL_CIC_DEC_RATIO_MASK (0x1F0U) 620 #define SDMV2_CH_SCCTRL_CIC_DEC_RATIO_SHIFT (4U) 621 #define SDMV2_CH_SCCTRL_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) & SDMV2_CH_SCCTRL_CIC_DEC_RATIO_MASK) 622 #define SDMV2_CH_SCCTRL_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_CIC_DEC_RATIO_MASK) >> SDMV2_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) 623 624 /* 625 * IGN_INI_SAMPLES (RW) 626 * 627 * NotZero: Ignore the first samples that are not accurate 628 * Zero: Use all samples 629 */ 630 #define SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_MASK (0xEU) 631 #define SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT (1U) 632 #define SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) & SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_MASK) 633 #define SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_MASK) >> SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) 634 635 /* 636 * EN (RW) 637 * 638 * Amplitude Path Enable 639 */ 640 #define SDMV2_CH_SCCTRL_EN_MASK (0x1U) 641 #define SDMV2_CH_SCCTRL_EN_SHIFT (0U) 642 #define SDMV2_CH_SCCTRL_EN_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_EN_SHIFT) & SDMV2_CH_SCCTRL_EN_MASK) 643 #define SDMV2_CH_SCCTRL_EN_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_EN_MASK) >> SDMV2_CH_SCCTRL_EN_SHIFT) 644 645 /* Bitfield definition for register of struct array CH: SCST */ 646 /* 647 * HZ (W1C) 648 * 649 * Amplitude rising above HZ event found. 650 */ 651 #define SDMV2_CH_SCST_HZ_MASK (0x8U) 652 #define SDMV2_CH_SCST_HZ_SHIFT (3U) 653 #define SDMV2_CH_SCST_HZ_SET(x) (((uint32_t)(x) << SDMV2_CH_SCST_HZ_SHIFT) & SDMV2_CH_SCST_HZ_MASK) 654 #define SDMV2_CH_SCST_HZ_GET(x) (((uint32_t)(x) & SDMV2_CH_SCST_HZ_MASK) >> SDMV2_CH_SCST_HZ_SHIFT) 655 656 /* 657 * MF (W1C) 658 * 659 * power modulator Failure found. MCLK not found. Error flag. 660 */ 661 #define SDMV2_CH_SCST_MF_MASK (0x4U) 662 #define SDMV2_CH_SCST_MF_SHIFT (2U) 663 #define SDMV2_CH_SCST_MF_SET(x) (((uint32_t)(x) << SDMV2_CH_SCST_MF_SHIFT) & SDMV2_CH_SCST_MF_MASK) 664 #define SDMV2_CH_SCST_MF_GET(x) (((uint32_t)(x) & SDMV2_CH_SCST_MF_MASK) >> SDMV2_CH_SCST_MF_SHIFT) 665 666 /* 667 * CMPH (W1C) 668 * 669 * HLT out of range. Error flag. 670 */ 671 #define SDMV2_CH_SCST_CMPH_MASK (0x2U) 672 #define SDMV2_CH_SCST_CMPH_SHIFT (1U) 673 #define SDMV2_CH_SCST_CMPH_SET(x) (((uint32_t)(x) << SDMV2_CH_SCST_CMPH_SHIFT) & SDMV2_CH_SCST_CMPH_MASK) 674 #define SDMV2_CH_SCST_CMPH_GET(x) (((uint32_t)(x) & SDMV2_CH_SCST_CMPH_MASK) >> SDMV2_CH_SCST_CMPH_SHIFT) 675 676 /* 677 * CMPL (W1C) 678 * 679 * LLT out of range. Error flag. 680 */ 681 #define SDMV2_CH_SCST_CMPL_MASK (0x1U) 682 #define SDMV2_CH_SCST_CMPL_SHIFT (0U) 683 #define SDMV2_CH_SCST_CMPL_SET(x) (((uint32_t)(x) << SDMV2_CH_SCST_CMPL_SHIFT) & SDMV2_CH_SCST_CMPL_MASK) 684 #define SDMV2_CH_SCST_CMPL_GET(x) (((uint32_t)(x) & SDMV2_CH_SCST_CMPL_MASK) >> SDMV2_CH_SCST_CMPL_SHIFT) 685 686 687 688 /* CH register group index macro definition */ 689 #define SDMV2_CH_0 (0UL) 690 691 692 #endif /* HPM_SDMV2_H */ 693