1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_SDM_H 10 #define HPM_SDM_H 11 12 typedef struct { 13 __RW uint32_t CTRL; /* 0x0: SDM control register */ 14 __RW uint32_t INT_EN; /* 0x4: Interrupt enable register. */ 15 __R uint32_t STATUS; /* 0x8: Status Registers */ 16 __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ 17 struct { 18 __RW uint32_t SDFIFOCTRL; /* 0x10: Data FIFO Path Control Register */ 19 __RW uint32_t SDCTRLP; /* 0x14: Data Path Control Primary Register */ 20 __RW uint32_t SDCTRLE; /* 0x18: Data Path Control Extra Register */ 21 __RW uint32_t SDST; /* 0x1C: Data Path Status */ 22 __R uint32_t SDATA; /* 0x20: Data */ 23 __R uint32_t SDFIFO; /* 0x24: FIFO Data */ 24 __R uint32_t SCAMP; /* 0x28: instant Amplitude Results */ 25 __RW uint32_t SCHTL; /* 0x2C: Amplitude Threshold for High Limit */ 26 __RW uint32_t SCHTLZ; /* 0x30: Amplitude Threshold for zero crossing */ 27 __RW uint32_t SCLLT; /* 0x34: Amplitude Threshold for low limit */ 28 __RW uint32_t SCCTRL; /* 0x38: Amplitude Path Control */ 29 __RW uint32_t SCST; /* 0x3C: Amplitude Path Status */ 30 __R uint8_t RESERVED0[16]; /* 0x40 - 0x4F: Reserved */ 31 } CH[4]; 32 } SDM_Type; 33 34 35 /* Bitfield definition for register: CTRL */ 36 /* 37 * SFTRST (RW) 38 * 39 * software reset the module if asserted to be1’b1. 40 */ 41 #define SDM_CTRL_SFTRST_MASK (0x80000000UL) 42 #define SDM_CTRL_SFTRST_SHIFT (31U) 43 #define SDM_CTRL_SFTRST_SET(x) (((uint32_t)(x) << SDM_CTRL_SFTRST_SHIFT) & SDM_CTRL_SFTRST_MASK) 44 #define SDM_CTRL_SFTRST_GET(x) (((uint32_t)(x) & SDM_CTRL_SFTRST_MASK) >> SDM_CTRL_SFTRST_SHIFT) 45 46 /* 47 * CHMD (RW) 48 * 49 * Channel Rcv mode 50 * Bits[2:0] for Ch0. 51 * Bits[5:3] for Ch1 52 * Bits[8:6] for Ch2 53 * Bits[11:9] for Ch3 54 * 3'b000: Capture at posedge of MCLK 55 * 3'b001: Capture at both posedge and negedge of MCLK 56 * 3'b010: Manchestor Mode 57 * 3'b011: Capture at negedge of MCLK 58 * 3'b100: Capture at every other posedge of MCLK 59 * 3'b101: Capture at every other negedge of MCLK 60 * Others: Undefined 61 */ 62 #define SDM_CTRL_CHMD_MASK (0x3FFC000UL) 63 #define SDM_CTRL_CHMD_SHIFT (14U) 64 #define SDM_CTRL_CHMD_SET(x) (((uint32_t)(x) << SDM_CTRL_CHMD_SHIFT) & SDM_CTRL_CHMD_MASK) 65 #define SDM_CTRL_CHMD_GET(x) (((uint32_t)(x) & SDM_CTRL_CHMD_MASK) >> SDM_CTRL_CHMD_SHIFT) 66 67 /* 68 * SYNC_MCLK (RW) 69 * 70 * Asserted to double sync the mclk input pin before its usage inside the module 71 */ 72 #define SDM_CTRL_SYNC_MCLK_MASK (0x3C00U) 73 #define SDM_CTRL_SYNC_MCLK_SHIFT (10U) 74 #define SDM_CTRL_SYNC_MCLK_SET(x) (((uint32_t)(x) << SDM_CTRL_SYNC_MCLK_SHIFT) & SDM_CTRL_SYNC_MCLK_MASK) 75 #define SDM_CTRL_SYNC_MCLK_GET(x) (((uint32_t)(x) & SDM_CTRL_SYNC_MCLK_MASK) >> SDM_CTRL_SYNC_MCLK_SHIFT) 76 77 /* 78 * SYNC_MDAT (RW) 79 * 80 * Asserted to double sync the mdat input pin before its usage inside the module 81 */ 82 #define SDM_CTRL_SYNC_MDAT_MASK (0x3C0U) 83 #define SDM_CTRL_SYNC_MDAT_SHIFT (6U) 84 #define SDM_CTRL_SYNC_MDAT_SET(x) (((uint32_t)(x) << SDM_CTRL_SYNC_MDAT_SHIFT) & SDM_CTRL_SYNC_MDAT_MASK) 85 #define SDM_CTRL_SYNC_MDAT_GET(x) (((uint32_t)(x) & SDM_CTRL_SYNC_MDAT_MASK) >> SDM_CTRL_SYNC_MDAT_SHIFT) 86 87 /* 88 * CH_EN (RW) 89 * 90 * Channel Enable 91 */ 92 #define SDM_CTRL_CH_EN_MASK (0x3CU) 93 #define SDM_CTRL_CH_EN_SHIFT (2U) 94 #define SDM_CTRL_CH_EN_SET(x) (((uint32_t)(x) << SDM_CTRL_CH_EN_SHIFT) & SDM_CTRL_CH_EN_MASK) 95 #define SDM_CTRL_CH_EN_GET(x) (((uint32_t)(x) & SDM_CTRL_CH_EN_MASK) >> SDM_CTRL_CH_EN_SHIFT) 96 97 /* 98 * IE (RW) 99 * 100 * Interrupt Enable 101 */ 102 #define SDM_CTRL_IE_MASK (0x2U) 103 #define SDM_CTRL_IE_SHIFT (1U) 104 #define SDM_CTRL_IE_SET(x) (((uint32_t)(x) << SDM_CTRL_IE_SHIFT) & SDM_CTRL_IE_MASK) 105 #define SDM_CTRL_IE_GET(x) (((uint32_t)(x) & SDM_CTRL_IE_MASK) >> SDM_CTRL_IE_SHIFT) 106 107 /* Bitfield definition for register: INT_EN */ 108 /* 109 * CH3DRY (RW) 110 * 111 * Ch3 Data Ready interrupt enable. 112 */ 113 #define SDM_INT_EN_CH3DRY_MASK (0x80U) 114 #define SDM_INT_EN_CH3DRY_SHIFT (7U) 115 #define SDM_INT_EN_CH3DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH3DRY_SHIFT) & SDM_INT_EN_CH3DRY_MASK) 116 #define SDM_INT_EN_CH3DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH3DRY_MASK) >> SDM_INT_EN_CH3DRY_SHIFT) 117 118 /* 119 * CH2DRY (RW) 120 * 121 * Ch2 Data Ready interrupt enable 122 */ 123 #define SDM_INT_EN_CH2DRY_MASK (0x40U) 124 #define SDM_INT_EN_CH2DRY_SHIFT (6U) 125 #define SDM_INT_EN_CH2DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH2DRY_SHIFT) & SDM_INT_EN_CH2DRY_MASK) 126 #define SDM_INT_EN_CH2DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH2DRY_MASK) >> SDM_INT_EN_CH2DRY_SHIFT) 127 128 /* 129 * CH1DRY (RW) 130 * 131 * Ch1 Data Ready interrupt enable 132 */ 133 #define SDM_INT_EN_CH1DRY_MASK (0x20U) 134 #define SDM_INT_EN_CH1DRY_SHIFT (5U) 135 #define SDM_INT_EN_CH1DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH1DRY_SHIFT) & SDM_INT_EN_CH1DRY_MASK) 136 #define SDM_INT_EN_CH1DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH1DRY_MASK) >> SDM_INT_EN_CH1DRY_SHIFT) 137 138 /* 139 * CH0DRY (RW) 140 * 141 * Ch0 Data Ready interrupt enable 142 */ 143 #define SDM_INT_EN_CH0DRY_MASK (0x10U) 144 #define SDM_INT_EN_CH0DRY_SHIFT (4U) 145 #define SDM_INT_EN_CH0DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH0DRY_SHIFT) & SDM_INT_EN_CH0DRY_MASK) 146 #define SDM_INT_EN_CH0DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH0DRY_MASK) >> SDM_INT_EN_CH0DRY_SHIFT) 147 148 /* 149 * CH3ERR (RW) 150 * 151 * Ch3 Error interrupt enable. 152 */ 153 #define SDM_INT_EN_CH3ERR_MASK (0x8U) 154 #define SDM_INT_EN_CH3ERR_SHIFT (3U) 155 #define SDM_INT_EN_CH3ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH3ERR_SHIFT) & SDM_INT_EN_CH3ERR_MASK) 156 #define SDM_INT_EN_CH3ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH3ERR_MASK) >> SDM_INT_EN_CH3ERR_SHIFT) 157 158 /* 159 * CH2ERR (RW) 160 * 161 * Ch2 Error interrupt enable 162 */ 163 #define SDM_INT_EN_CH2ERR_MASK (0x4U) 164 #define SDM_INT_EN_CH2ERR_SHIFT (2U) 165 #define SDM_INT_EN_CH2ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH2ERR_SHIFT) & SDM_INT_EN_CH2ERR_MASK) 166 #define SDM_INT_EN_CH2ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH2ERR_MASK) >> SDM_INT_EN_CH2ERR_SHIFT) 167 168 /* 169 * CH1ERR (RW) 170 * 171 * Ch1 Error interrupt enable 172 */ 173 #define SDM_INT_EN_CH1ERR_MASK (0x2U) 174 #define SDM_INT_EN_CH1ERR_SHIFT (1U) 175 #define SDM_INT_EN_CH1ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH1ERR_SHIFT) & SDM_INT_EN_CH1ERR_MASK) 176 #define SDM_INT_EN_CH1ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH1ERR_MASK) >> SDM_INT_EN_CH1ERR_SHIFT) 177 178 /* 179 * CH0ERR (RW) 180 * 181 * Ch0 Error interrupt enable 182 */ 183 #define SDM_INT_EN_CH0ERR_MASK (0x1U) 184 #define SDM_INT_EN_CH0ERR_SHIFT (0U) 185 #define SDM_INT_EN_CH0ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH0ERR_SHIFT) & SDM_INT_EN_CH0ERR_MASK) 186 #define SDM_INT_EN_CH0ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH0ERR_MASK) >> SDM_INT_EN_CH0ERR_SHIFT) 187 188 /* Bitfield definition for register: STATUS */ 189 /* 190 * CH3DRY (RO) 191 * 192 * Ch3 Data Ready. 193 * De-assert this bit by reading the data (or data fifo) registers. 194 */ 195 #define SDM_STATUS_CH3DRY_MASK (0x80U) 196 #define SDM_STATUS_CH3DRY_SHIFT (7U) 197 #define SDM_STATUS_CH3DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH3DRY_MASK) >> SDM_STATUS_CH3DRY_SHIFT) 198 199 /* 200 * CH2DRY (RO) 201 * 202 * Ch2 Data Ready 203 */ 204 #define SDM_STATUS_CH2DRY_MASK (0x40U) 205 #define SDM_STATUS_CH2DRY_SHIFT (6U) 206 #define SDM_STATUS_CH2DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH2DRY_MASK) >> SDM_STATUS_CH2DRY_SHIFT) 207 208 /* 209 * CH1DRY (RO) 210 * 211 * Ch1 Data Ready 212 */ 213 #define SDM_STATUS_CH1DRY_MASK (0x20U) 214 #define SDM_STATUS_CH1DRY_SHIFT (5U) 215 #define SDM_STATUS_CH1DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH1DRY_MASK) >> SDM_STATUS_CH1DRY_SHIFT) 216 217 /* 218 * CH0DRY (RO) 219 * 220 * Ch0 Data Ready 221 */ 222 #define SDM_STATUS_CH0DRY_MASK (0x10U) 223 #define SDM_STATUS_CH0DRY_SHIFT (4U) 224 #define SDM_STATUS_CH0DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH0DRY_MASK) >> SDM_STATUS_CH0DRY_SHIFT) 225 226 /* 227 * CH3ERR (RO) 228 * 229 * Ch3 Error. 230 * ORed together by channel related error signals and corresponding error interrupt enable signals. 231 * De-assert this bit by write-1-clear the corresponding error status bits in the channel status registers. 232 */ 233 #define SDM_STATUS_CH3ERR_MASK (0x8U) 234 #define SDM_STATUS_CH3ERR_SHIFT (3U) 235 #define SDM_STATUS_CH3ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH3ERR_MASK) >> SDM_STATUS_CH3ERR_SHIFT) 236 237 /* 238 * CH2ERR (RO) 239 * 240 * Ch2 Error 241 */ 242 #define SDM_STATUS_CH2ERR_MASK (0x4U) 243 #define SDM_STATUS_CH2ERR_SHIFT (2U) 244 #define SDM_STATUS_CH2ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH2ERR_MASK) >> SDM_STATUS_CH2ERR_SHIFT) 245 246 /* 247 * CH1ERR (RO) 248 * 249 * Ch1 Error 250 */ 251 #define SDM_STATUS_CH1ERR_MASK (0x2U) 252 #define SDM_STATUS_CH1ERR_SHIFT (1U) 253 #define SDM_STATUS_CH1ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH1ERR_MASK) >> SDM_STATUS_CH1ERR_SHIFT) 254 255 /* 256 * CH0ERR (RO) 257 * 258 * Ch0 Error 259 */ 260 #define SDM_STATUS_CH0ERR_MASK (0x1U) 261 #define SDM_STATUS_CH0ERR_SHIFT (0U) 262 #define SDM_STATUS_CH0ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH0ERR_MASK) >> SDM_STATUS_CH0ERR_SHIFT) 263 264 /* Bitfield definition for register of struct array CH: SDFIFOCTRL */ 265 /* 266 * THRSH (RW) 267 * 268 * FIFO threshold (0,..,16) (fillings > threshold, then gen int) 269 */ 270 #define SDM_CH_SDFIFOCTRL_THRSH_MASK (0x1F0U) 271 #define SDM_CH_SDFIFOCTRL_THRSH_SHIFT (4U) 272 #define SDM_CH_SDFIFOCTRL_THRSH_SET(x) (((uint32_t)(x) << SDM_CH_SDFIFOCTRL_THRSH_SHIFT) & SDM_CH_SDFIFOCTRL_THRSH_MASK) 273 #define SDM_CH_SDFIFOCTRL_THRSH_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFOCTRL_THRSH_MASK) >> SDM_CH_SDFIFOCTRL_THRSH_SHIFT) 274 275 /* 276 * D_RDY_INT_EN (RW) 277 * 278 * FIFO data ready interrupt enable 279 */ 280 #define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK (0x4U) 281 #define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT (2U) 282 #define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SET(x) (((uint32_t)(x) << SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT) & SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK) 283 #define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK) >> SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT) 284 285 /* Bitfield definition for register of struct array CH: SDCTRLP */ 286 /* 287 * MANCH_THR (RW) 288 * 289 * Manchester Decoding threshold. 3/4 of PERIOD_MCLK[7:0] 290 */ 291 #define SDM_CH_SDCTRLP_MANCH_THR_MASK (0xFE000000UL) 292 #define SDM_CH_SDCTRLP_MANCH_THR_SHIFT (25U) 293 #define SDM_CH_SDCTRLP_MANCH_THR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_MANCH_THR_SHIFT) & SDM_CH_SDCTRLP_MANCH_THR_MASK) 294 #define SDM_CH_SDCTRLP_MANCH_THR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_MANCH_THR_MASK) >> SDM_CH_SDCTRLP_MANCH_THR_SHIFT) 295 296 /* 297 * WDOG_THR (RW) 298 * 299 * Watch dog threshold for channel failure of CLK halting 300 */ 301 #define SDM_CH_SDCTRLP_WDOG_THR_MASK (0x1FE0000UL) 302 #define SDM_CH_SDCTRLP_WDOG_THR_SHIFT (17U) 303 #define SDM_CH_SDCTRLP_WDOG_THR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WDOG_THR_SHIFT) & SDM_CH_SDCTRLP_WDOG_THR_MASK) 304 #define SDM_CH_SDCTRLP_WDOG_THR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WDOG_THR_MASK) >> SDM_CH_SDCTRLP_WDOG_THR_SHIFT) 305 306 /* 307 * AF_IE (RW) 308 * 309 * Acknowledge feedback interrupt enable 310 */ 311 #define SDM_CH_SDCTRLP_AF_IE_MASK (0x10000UL) 312 #define SDM_CH_SDCTRLP_AF_IE_SHIFT (16U) 313 #define SDM_CH_SDCTRLP_AF_IE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_AF_IE_SHIFT) & SDM_CH_SDCTRLP_AF_IE_MASK) 314 #define SDM_CH_SDCTRLP_AF_IE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_AF_IE_MASK) >> SDM_CH_SDCTRLP_AF_IE_SHIFT) 315 316 /* 317 * DFFOVIE (RW) 318 * 319 * Ch Data FIFO overflow interrupt enable 320 */ 321 #define SDM_CH_SDCTRLP_DFFOVIE_MASK (0x8000U) 322 #define SDM_CH_SDCTRLP_DFFOVIE_SHIFT (15U) 323 #define SDM_CH_SDCTRLP_DFFOVIE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DFFOVIE_SHIFT) & SDM_CH_SDCTRLP_DFFOVIE_MASK) 324 #define SDM_CH_SDCTRLP_DFFOVIE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DFFOVIE_MASK) >> SDM_CH_SDCTRLP_DFFOVIE_SHIFT) 325 326 /* 327 * DSATIE (RW) 328 * 329 * Ch CIC Data Saturation Interrupt Enable 330 */ 331 #define SDM_CH_SDCTRLP_DSATIE_MASK (0x4000U) 332 #define SDM_CH_SDCTRLP_DSATIE_SHIFT (14U) 333 #define SDM_CH_SDCTRLP_DSATIE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DSATIE_SHIFT) & SDM_CH_SDCTRLP_DSATIE_MASK) 334 #define SDM_CH_SDCTRLP_DSATIE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DSATIE_MASK) >> SDM_CH_SDCTRLP_DSATIE_SHIFT) 335 336 /* 337 * DRIE (RW) 338 * 339 * Ch Data Ready Interrupt Enable 340 */ 341 #define SDM_CH_SDCTRLP_DRIE_MASK (0x2000U) 342 #define SDM_CH_SDCTRLP_DRIE_SHIFT (13U) 343 #define SDM_CH_SDCTRLP_DRIE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DRIE_SHIFT) & SDM_CH_SDCTRLP_DRIE_MASK) 344 #define SDM_CH_SDCTRLP_DRIE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DRIE_MASK) >> SDM_CH_SDCTRLP_DRIE_SHIFT) 345 346 /* 347 * SYNCSEL (RW) 348 * 349 * Select the PWM SYNC Source 350 */ 351 #define SDM_CH_SDCTRLP_SYNCSEL_MASK (0x1F80U) 352 #define SDM_CH_SDCTRLP_SYNCSEL_SHIFT (7U) 353 #define SDM_CH_SDCTRLP_SYNCSEL_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_SYNCSEL_SHIFT) & SDM_CH_SDCTRLP_SYNCSEL_MASK) 354 #define SDM_CH_SDCTRLP_SYNCSEL_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_SYNCSEL_MASK) >> SDM_CH_SDCTRLP_SYNCSEL_SHIFT) 355 356 /* 357 * FFSYNCCLREN (RW) 358 * 359 * Auto clear FIFO when a new SDSYNC event is found. Only valid when WTSYNCEN=1 360 */ 361 #define SDM_CH_SDCTRLP_FFSYNCCLREN_MASK (0x40U) 362 #define SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT (6U) 363 #define SDM_CH_SDCTRLP_FFSYNCCLREN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT) & SDM_CH_SDCTRLP_FFSYNCCLREN_MASK) 364 #define SDM_CH_SDCTRLP_FFSYNCCLREN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_FFSYNCCLREN_MASK) >> SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT) 365 366 /* 367 * WTSYNACLR (RW) 368 * 369 * 1: Asserted to Auto clear WTSYNFLG when the SDFFINT is gen 370 * 0: WTSYNFLG should be cleared manually by WTSYNMCLR 371 */ 372 #define SDM_CH_SDCTRLP_WTSYNACLR_MASK (0x20U) 373 #define SDM_CH_SDCTRLP_WTSYNACLR_SHIFT (5U) 374 #define SDM_CH_SDCTRLP_WTSYNACLR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNACLR_SHIFT) & SDM_CH_SDCTRLP_WTSYNACLR_MASK) 375 #define SDM_CH_SDCTRLP_WTSYNACLR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNACLR_MASK) >> SDM_CH_SDCTRLP_WTSYNACLR_SHIFT) 376 377 /* 378 * WTSYNMCLR (RW) 379 * 380 * 1: Manually clear WTSYNFLG. Auto-clear. 381 */ 382 #define SDM_CH_SDCTRLP_WTSYNMCLR_MASK (0x10U) 383 #define SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT (4U) 384 #define SDM_CH_SDCTRLP_WTSYNMCLR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT) & SDM_CH_SDCTRLP_WTSYNMCLR_MASK) 385 #define SDM_CH_SDCTRLP_WTSYNMCLR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNMCLR_MASK) >> SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT) 386 387 /* 388 * WTSYNCEN (RW) 389 * 390 * 1: Start to store data only after PWM SYNC event 391 * 0: Start to store data whenever enabled 392 */ 393 #define SDM_CH_SDCTRLP_WTSYNCEN_MASK (0x8U) 394 #define SDM_CH_SDCTRLP_WTSYNCEN_SHIFT (3U) 395 #define SDM_CH_SDCTRLP_WTSYNCEN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNCEN_SHIFT) & SDM_CH_SDCTRLP_WTSYNCEN_MASK) 396 #define SDM_CH_SDCTRLP_WTSYNCEN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNCEN_MASK) >> SDM_CH_SDCTRLP_WTSYNCEN_SHIFT) 397 398 /* 399 * D32 (RW) 400 * 401 * 1:32 bit data 402 * 0:16 bit data 403 */ 404 #define SDM_CH_SDCTRLP_D32_MASK (0x4U) 405 #define SDM_CH_SDCTRLP_D32_SHIFT (2U) 406 #define SDM_CH_SDCTRLP_D32_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_D32_SHIFT) & SDM_CH_SDCTRLP_D32_MASK) 407 #define SDM_CH_SDCTRLP_D32_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_D32_MASK) >> SDM_CH_SDCTRLP_D32_SHIFT) 408 409 /* 410 * DR_OPT (RW) 411 * 412 * 1: Use Data FIFO Ready as data ready when fifo fillings are greater than the threshold 413 * 0: Use Data Reg Ready as data ready 414 */ 415 #define SDM_CH_SDCTRLP_DR_OPT_MASK (0x2U) 416 #define SDM_CH_SDCTRLP_DR_OPT_SHIFT (1U) 417 #define SDM_CH_SDCTRLP_DR_OPT_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DR_OPT_SHIFT) & SDM_CH_SDCTRLP_DR_OPT_MASK) 418 #define SDM_CH_SDCTRLP_DR_OPT_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DR_OPT_MASK) >> SDM_CH_SDCTRLP_DR_OPT_SHIFT) 419 420 /* 421 * EN (RW) 422 * 423 * Data Path Enable 424 */ 425 #define SDM_CH_SDCTRLP_EN_MASK (0x1U) 426 #define SDM_CH_SDCTRLP_EN_SHIFT (0U) 427 #define SDM_CH_SDCTRLP_EN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_EN_SHIFT) & SDM_CH_SDCTRLP_EN_MASK) 428 #define SDM_CH_SDCTRLP_EN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_EN_MASK) >> SDM_CH_SDCTRLP_EN_SHIFT) 429 430 /* Bitfield definition for register of struct array CH: SDCTRLE */ 431 /* 432 * SGD_ORDR (RW) 433 * 434 * CIC order 435 * 0: SYNC1 436 * 1: SYNC2 437 * 2: SYNC3 438 * 3: FAST_SYNC 439 */ 440 #define SDM_CH_SDCTRLE_SGD_ORDR_MASK (0x60000UL) 441 #define SDM_CH_SDCTRLE_SGD_ORDR_SHIFT (17U) 442 #define SDM_CH_SDCTRLE_SGD_ORDR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_SGD_ORDR_SHIFT) & SDM_CH_SDCTRLE_SGD_ORDR_MASK) 443 #define SDM_CH_SDCTRLE_SGD_ORDR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_SGD_ORDR_MASK) >> SDM_CH_SDCTRLE_SGD_ORDR_SHIFT) 444 445 /* 446 * PWMSYNC (RW) 447 * 448 * Asserted to double sync the PWM trigger signal 449 */ 450 #define SDM_CH_SDCTRLE_PWMSYNC_MASK (0x10000UL) 451 #define SDM_CH_SDCTRLE_PWMSYNC_SHIFT (16U) 452 #define SDM_CH_SDCTRLE_PWMSYNC_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_PWMSYNC_SHIFT) & SDM_CH_SDCTRLE_PWMSYNC_MASK) 453 #define SDM_CH_SDCTRLE_PWMSYNC_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_PWMSYNC_MASK) >> SDM_CH_SDCTRLE_PWMSYNC_SHIFT) 454 455 /* 456 * CIC_SCL (RW) 457 * 458 * CIC shift control 459 */ 460 #define SDM_CH_SDCTRLE_CIC_SCL_MASK (0x7800U) 461 #define SDM_CH_SDCTRLE_CIC_SCL_SHIFT (11U) 462 #define SDM_CH_SDCTRLE_CIC_SCL_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_SCL_SHIFT) & SDM_CH_SDCTRLE_CIC_SCL_MASK) 463 #define SDM_CH_SDCTRLE_CIC_SCL_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_SCL_MASK) >> SDM_CH_SDCTRLE_CIC_SCL_SHIFT) 464 465 /* 466 * CIC_DEC_RATIO (RW) 467 * 468 * CIC decimation ratio. 0 means div-by-256 469 */ 470 #define SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK (0x7F8U) 471 #define SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT (3U) 472 #define SDM_CH_SDCTRLE_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) & SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK) 473 #define SDM_CH_SDCTRLE_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK) >> SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) 474 475 /* 476 * IGN_INI_SAMPLES (RW) 477 * 478 * NotZero: Don't store the first samples that are not accurate 479 * Zero: Store all samples 480 */ 481 #define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK (0x7U) 482 #define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT (0U) 483 #define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) & SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) 484 #define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) >> SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) 485 486 /* Bitfield definition for register of struct array CH: SDST */ 487 /* 488 * PERIOD_MCLK (RO) 489 * 490 * maxim of mclk spacing in cycles, using edges of mclk signal. In manchester coding mode, it is just the period of MCLK. In other modes, it is almost the half period. 491 */ 492 #define SDM_CH_SDST_PERIOD_MCLK_MASK (0x7F800000UL) 493 #define SDM_CH_SDST_PERIOD_MCLK_SHIFT (23U) 494 #define SDM_CH_SDST_PERIOD_MCLK_GET(x) (((uint32_t)(x) & SDM_CH_SDST_PERIOD_MCLK_MASK) >> SDM_CH_SDST_PERIOD_MCLK_SHIFT) 495 496 /* 497 * FIFO_DR (W1C) 498 * 499 * FIFO data ready 500 */ 501 #define SDM_CH_SDST_FIFO_DR_MASK (0x200U) 502 #define SDM_CH_SDST_FIFO_DR_SHIFT (9U) 503 #define SDM_CH_SDST_FIFO_DR_SET(x) (((uint32_t)(x) << SDM_CH_SDST_FIFO_DR_SHIFT) & SDM_CH_SDST_FIFO_DR_MASK) 504 #define SDM_CH_SDST_FIFO_DR_GET(x) (((uint32_t)(x) & SDM_CH_SDST_FIFO_DR_MASK) >> SDM_CH_SDST_FIFO_DR_SHIFT) 505 506 /* 507 * AF (W1C) 508 * 509 * Achnowledge flag 510 */ 511 #define SDM_CH_SDST_AF_MASK (0x100U) 512 #define SDM_CH_SDST_AF_SHIFT (8U) 513 #define SDM_CH_SDST_AF_SET(x) (((uint32_t)(x) << SDM_CH_SDST_AF_SHIFT) & SDM_CH_SDST_AF_MASK) 514 #define SDM_CH_SDST_AF_GET(x) (((uint32_t)(x) & SDM_CH_SDST_AF_MASK) >> SDM_CH_SDST_AF_SHIFT) 515 516 /* 517 * DOV_ERR (W1C) 518 * 519 * Data FIFO Overflow Error. Error flag. 520 */ 521 #define SDM_CH_SDST_DOV_ERR_MASK (0x80U) 522 #define SDM_CH_SDST_DOV_ERR_SHIFT (7U) 523 #define SDM_CH_SDST_DOV_ERR_SET(x) (((uint32_t)(x) << SDM_CH_SDST_DOV_ERR_SHIFT) & SDM_CH_SDST_DOV_ERR_MASK) 524 #define SDM_CH_SDST_DOV_ERR_GET(x) (((uint32_t)(x) & SDM_CH_SDST_DOV_ERR_MASK) >> SDM_CH_SDST_DOV_ERR_SHIFT) 525 526 /* 527 * DSAT_ERR (W1C) 528 * 529 * CIC out Data saturation err. Error flag. 530 */ 531 #define SDM_CH_SDST_DSAT_ERR_MASK (0x40U) 532 #define SDM_CH_SDST_DSAT_ERR_SHIFT (6U) 533 #define SDM_CH_SDST_DSAT_ERR_SET(x) (((uint32_t)(x) << SDM_CH_SDST_DSAT_ERR_SHIFT) & SDM_CH_SDST_DSAT_ERR_MASK) 534 #define SDM_CH_SDST_DSAT_ERR_GET(x) (((uint32_t)(x) & SDM_CH_SDST_DSAT_ERR_MASK) >> SDM_CH_SDST_DSAT_ERR_SHIFT) 535 536 /* 537 * WTSYNFLG (RO) 538 * 539 * Wait-for-sync event found 540 */ 541 #define SDM_CH_SDST_WTSYNFLG_MASK (0x20U) 542 #define SDM_CH_SDST_WTSYNFLG_SHIFT (5U) 543 #define SDM_CH_SDST_WTSYNFLG_GET(x) (((uint32_t)(x) & SDM_CH_SDST_WTSYNFLG_MASK) >> SDM_CH_SDST_WTSYNFLG_SHIFT) 544 545 /* 546 * FILL (RO) 547 * 548 * Data FIFO Fillings 549 */ 550 #define SDM_CH_SDST_FILL_MASK (0x1FU) 551 #define SDM_CH_SDST_FILL_SHIFT (0U) 552 #define SDM_CH_SDST_FILL_GET(x) (((uint32_t)(x) & SDM_CH_SDST_FILL_MASK) >> SDM_CH_SDST_FILL_SHIFT) 553 554 /* Bitfield definition for register of struct array CH: SDATA */ 555 /* 556 * VAL (RO) 557 * 558 * Data 559 */ 560 #define SDM_CH_SDATA_VAL_MASK (0xFFFFFFFFUL) 561 #define SDM_CH_SDATA_VAL_SHIFT (0U) 562 #define SDM_CH_SDATA_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SDATA_VAL_MASK) >> SDM_CH_SDATA_VAL_SHIFT) 563 564 /* Bitfield definition for register of struct array CH: SDFIFO */ 565 /* 566 * VAL (RO) 567 * 568 * FIFO Data 569 */ 570 #define SDM_CH_SDFIFO_VAL_MASK (0xFFFFFFFFUL) 571 #define SDM_CH_SDFIFO_VAL_SHIFT (0U) 572 #define SDM_CH_SDFIFO_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFO_VAL_MASK) >> SDM_CH_SDFIFO_VAL_SHIFT) 573 574 /* Bitfield definition for register of struct array CH: SCAMP */ 575 /* 576 * VAL (RO) 577 * 578 * instant Amplitude Results 579 */ 580 #define SDM_CH_SCAMP_VAL_MASK (0xFFFFU) 581 #define SDM_CH_SCAMP_VAL_SHIFT (0U) 582 #define SDM_CH_SCAMP_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCAMP_VAL_MASK) >> SDM_CH_SCAMP_VAL_SHIFT) 583 584 /* Bitfield definition for register of struct array CH: SCHTL */ 585 /* 586 * VAL (RW) 587 * 588 * Amplitude Threshold for High Limit 589 */ 590 #define SDM_CH_SCHTL_VAL_MASK (0xFFFFU) 591 #define SDM_CH_SCHTL_VAL_SHIFT (0U) 592 #define SDM_CH_SCHTL_VAL_SET(x) (((uint32_t)(x) << SDM_CH_SCHTL_VAL_SHIFT) & SDM_CH_SCHTL_VAL_MASK) 593 #define SDM_CH_SCHTL_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCHTL_VAL_MASK) >> SDM_CH_SCHTL_VAL_SHIFT) 594 595 /* Bitfield definition for register of struct array CH: SCHTLZ */ 596 /* 597 * VAL (RW) 598 * 599 * Amplitude Threshold for zero crossing 600 */ 601 #define SDM_CH_SCHTLZ_VAL_MASK (0xFFFFU) 602 #define SDM_CH_SCHTLZ_VAL_SHIFT (0U) 603 #define SDM_CH_SCHTLZ_VAL_SET(x) (((uint32_t)(x) << SDM_CH_SCHTLZ_VAL_SHIFT) & SDM_CH_SCHTLZ_VAL_MASK) 604 #define SDM_CH_SCHTLZ_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCHTLZ_VAL_MASK) >> SDM_CH_SCHTLZ_VAL_SHIFT) 605 606 /* Bitfield definition for register of struct array CH: SCLLT */ 607 /* 608 * VAL (RW) 609 * 610 * Amplitude Threshold for low limit 611 */ 612 #define SDM_CH_SCLLT_VAL_MASK (0xFFFFU) 613 #define SDM_CH_SCLLT_VAL_SHIFT (0U) 614 #define SDM_CH_SCLLT_VAL_SET(x) (((uint32_t)(x) << SDM_CH_SCLLT_VAL_SHIFT) & SDM_CH_SCLLT_VAL_MASK) 615 #define SDM_CH_SCLLT_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCLLT_VAL_MASK) >> SDM_CH_SCLLT_VAL_SHIFT) 616 617 /* Bitfield definition for register of struct array CH: SCCTRL */ 618 /* 619 * HZ_EN (RW) 620 * 621 * Zero Crossing Enable 622 */ 623 #define SDM_CH_SCCTRL_HZ_EN_MASK (0x800000UL) 624 #define SDM_CH_SCCTRL_HZ_EN_SHIFT (23U) 625 #define SDM_CH_SCCTRL_HZ_EN_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_HZ_EN_SHIFT) & SDM_CH_SCCTRL_HZ_EN_MASK) 626 #define SDM_CH_SCCTRL_HZ_EN_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_HZ_EN_MASK) >> SDM_CH_SCCTRL_HZ_EN_SHIFT) 627 628 /* 629 * MF_IE (RW) 630 * 631 * Module failure Interrupt enable 632 */ 633 #define SDM_CH_SCCTRL_MF_IE_MASK (0x400000UL) 634 #define SDM_CH_SCCTRL_MF_IE_SHIFT (22U) 635 #define SDM_CH_SCCTRL_MF_IE_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_MF_IE_SHIFT) & SDM_CH_SCCTRL_MF_IE_MASK) 636 #define SDM_CH_SCCTRL_MF_IE_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_MF_IE_MASK) >> SDM_CH_SCCTRL_MF_IE_SHIFT) 637 638 /* 639 * HL_IE (RW) 640 * 641 * HLT Interrupt Enable 642 */ 643 #define SDM_CH_SCCTRL_HL_IE_MASK (0x200000UL) 644 #define SDM_CH_SCCTRL_HL_IE_SHIFT (21U) 645 #define SDM_CH_SCCTRL_HL_IE_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_HL_IE_SHIFT) & SDM_CH_SCCTRL_HL_IE_MASK) 646 #define SDM_CH_SCCTRL_HL_IE_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_HL_IE_MASK) >> SDM_CH_SCCTRL_HL_IE_SHIFT) 647 648 /* 649 * LL_IE (RW) 650 * 651 * LLT interrupt Enable 652 */ 653 #define SDM_CH_SCCTRL_LL_IE_MASK (0x100000UL) 654 #define SDM_CH_SCCTRL_LL_IE_SHIFT (20U) 655 #define SDM_CH_SCCTRL_LL_IE_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_LL_IE_SHIFT) & SDM_CH_SCCTRL_LL_IE_MASK) 656 #define SDM_CH_SCCTRL_LL_IE_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_LL_IE_MASK) >> SDM_CH_SCCTRL_LL_IE_SHIFT) 657 658 /* 659 * SGD_ORDR (RW) 660 * 661 * CIC order 662 * 0: SYNC1 663 * 1: SYNC2 664 * 2: SYNC3 665 * 3: FAST_SYNC 666 */ 667 #define SDM_CH_SCCTRL_SGD_ORDR_MASK (0xC0000UL) 668 #define SDM_CH_SCCTRL_SGD_ORDR_SHIFT (18U) 669 #define SDM_CH_SCCTRL_SGD_ORDR_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_SGD_ORDR_SHIFT) & SDM_CH_SCCTRL_SGD_ORDR_MASK) 670 #define SDM_CH_SCCTRL_SGD_ORDR_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_SGD_ORDR_MASK) >> SDM_CH_SCCTRL_SGD_ORDR_SHIFT) 671 672 /* 673 * CIC_DEC_RATIO (RW) 674 * 675 * CIC decimation ratio. 0 means div-by-32 676 */ 677 #define SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK (0x1F0U) 678 #define SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT (4U) 679 #define SDM_CH_SCCTRL_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) & SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK) 680 #define SDM_CH_SCCTRL_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK) >> SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) 681 682 /* 683 * IGN_INI_SAMPLES (RW) 684 * 685 * NotZero: Ignore the first samples that are not accurate 686 * Zero: Use all samples 687 */ 688 #define SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK (0xEU) 689 #define SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT (1U) 690 #define SDM_CH_SCCTRL_IGN_INI_SAMPLES_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) & SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK) 691 #define SDM_CH_SCCTRL_IGN_INI_SAMPLES_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK) >> SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) 692 693 /* 694 * EN (RW) 695 * 696 * Amplitude Path Enable 697 */ 698 #define SDM_CH_SCCTRL_EN_MASK (0x1U) 699 #define SDM_CH_SCCTRL_EN_SHIFT (0U) 700 #define SDM_CH_SCCTRL_EN_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_EN_SHIFT) & SDM_CH_SCCTRL_EN_MASK) 701 #define SDM_CH_SCCTRL_EN_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_EN_MASK) >> SDM_CH_SCCTRL_EN_SHIFT) 702 703 /* Bitfield definition for register of struct array CH: SCST */ 704 /* 705 * HZ (W1C) 706 * 707 * Amplitude rising above HZ event found. 708 */ 709 #define SDM_CH_SCST_HZ_MASK (0x8U) 710 #define SDM_CH_SCST_HZ_SHIFT (3U) 711 #define SDM_CH_SCST_HZ_SET(x) (((uint32_t)(x) << SDM_CH_SCST_HZ_SHIFT) & SDM_CH_SCST_HZ_MASK) 712 #define SDM_CH_SCST_HZ_GET(x) (((uint32_t)(x) & SDM_CH_SCST_HZ_MASK) >> SDM_CH_SCST_HZ_SHIFT) 713 714 /* 715 * MF (W1C) 716 * 717 * power modulator Failure found. MCLK not found. Error flag. 718 */ 719 #define SDM_CH_SCST_MF_MASK (0x4U) 720 #define SDM_CH_SCST_MF_SHIFT (2U) 721 #define SDM_CH_SCST_MF_SET(x) (((uint32_t)(x) << SDM_CH_SCST_MF_SHIFT) & SDM_CH_SCST_MF_MASK) 722 #define SDM_CH_SCST_MF_GET(x) (((uint32_t)(x) & SDM_CH_SCST_MF_MASK) >> SDM_CH_SCST_MF_SHIFT) 723 724 /* 725 * CMPH (W1C) 726 * 727 * HLT out of range. Error flag. 728 */ 729 #define SDM_CH_SCST_CMPH_MASK (0x2U) 730 #define SDM_CH_SCST_CMPH_SHIFT (1U) 731 #define SDM_CH_SCST_CMPH_SET(x) (((uint32_t)(x) << SDM_CH_SCST_CMPH_SHIFT) & SDM_CH_SCST_CMPH_MASK) 732 #define SDM_CH_SCST_CMPH_GET(x) (((uint32_t)(x) & SDM_CH_SCST_CMPH_MASK) >> SDM_CH_SCST_CMPH_SHIFT) 733 734 /* 735 * CMPL (W1C) 736 * 737 * LLT out of range. Error flag. 738 */ 739 #define SDM_CH_SCST_CMPL_MASK (0x1U) 740 #define SDM_CH_SCST_CMPL_SHIFT (0U) 741 #define SDM_CH_SCST_CMPL_SET(x) (((uint32_t)(x) << SDM_CH_SCST_CMPL_SHIFT) & SDM_CH_SCST_CMPL_MASK) 742 #define SDM_CH_SCST_CMPL_GET(x) (((uint32_t)(x) & SDM_CH_SCST_CMPL_MASK) >> SDM_CH_SCST_CMPL_SHIFT) 743 744 745 746 /* CH register group index macro definition */ 747 #define SDM_CH_0 (0UL) 748 #define SDM_CH_1 (1UL) 749 #define SDM_CH_2 (2UL) 750 #define SDM_CH_3 (3UL) 751 752 753 #endif /* HPM_SDM_H */ 754