1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __REG_SEC_BEST2003_H__ 16 #define __REG_SEC_BEST2003_H__ 17 18 #include "plat_types.h" 19 20 struct HAL_SEC_T { 21 __IO uint32_t REG_000; 22 __IO uint32_t REG_004; 23 __IO uint32_t REG_008; 24 __IO uint32_t REG_00C; 25 __IO uint32_t REG_010; 26 __IO uint32_t REG_014; 27 __IO uint32_t REG_018; 28 __IO uint32_t REG_01C; 29 __IO uint32_t REG_020; 30 __IO uint32_t REG_024; 31 __IO uint32_t REG_028; 32 __IO uint32_t REG_02C; 33 __IO uint32_t REG_030; 34 __IO uint32_t REG_034; 35 __IO uint32_t REG_038; 36 __IO uint32_t REG_03C; 37 }; 38 39 // reg_00 40 #define SEC_CFG_AP_PROT_CODEC (1 << 0) 41 #define SEC_CFG_NONSEC_PROT_CODEC (1 << 1) 42 #define SEC_CFG_SEC_RESP_PROT_CODEC (1 << 2) 43 #define SEC_CFG_NONSEC_BYPASS_PROT_CODEC (1 << 3) 44 #define SEC_CFG_AP_PROT_MCU2BT (1 << 4) 45 #define SEC_CFG_NONSEC_PROT_MCU2BT (1 << 5) 46 #define SEC_CFG_SEC_RESP_PROT_MCU2BT (1 << 6) 47 #define SEC_CFG_NONSEC_BYPASS_PROT_MCU2BT (1 << 7) 48 #define SEC_CFG_AP_PROT_MCU2WF (1 << 8) 49 #define SEC_CFG_NONSEC_PROT_MCU2WF (1 << 9) 50 #define SEC_CFG_SEC_RESP_PROT_MCU2WF (1 << 10) 51 #define SEC_CFG_NONSEC_BYPASS_PROT_MCU2WF (1 << 11) 52 53 // reg_08 54 #define SEC_IRQ_CLR_PPC_CODEC (1 << 0) 55 #define SEC_IRQ_EN_PPC_CODEC (1 << 1) 56 #define SEC_IRQ_CLR_PPC_MCU2BT (1 << 2) 57 #define SEC_IRQ_EN_PPC_MCU2BT (1 << 3) 58 #define SEC_IRQ_CLR_PPC_MCU2WF (1 << 4) 59 #define SEC_IRQ_EN_PPC_MCU2WF (1 << 5) 60 61 // reg_0c 62 #define SEC_CFG_NONSEC_A7_AUTO (1 << 0) 63 #define SEC_CFG_NONSEC_A7 (1 << 1) 64 #define SEC_CFG_NONSEC_CP_AUTO (1 << 2) 65 #define SEC_CFG_NONSEC_CP (1 << 3) 66 #define SEC_CFG_NONSEC_ADMA1 (1 << 4) 67 #define SEC_CFG_NONSEC_ADMA2 (1 << 5) 68 #define SEC_CFG_NONSEC_GDMA1 (1 << 6) 69 #define SEC_CFG_NONSEC_GDMA2 (1 << 7) 70 #define SEC_CFG_NONSEC_BCM (1 << 8) 71 #define SEC_CFG_NONSEC_CKSUM (1 << 9) 72 #define SEC_CFG_NONSEC_CRC (1 << 10) 73 #define SEC_CFG_NONSEC_USB (1 << 11) 74 #define SEC_CFG_NONSEC_I2C_SLV (1 << 12) 75 #define SEC_CFG_NONSEC_BT2MCU (1 << 13) 76 #define SEC_CFG_NONSEC_WF2MCU (1 << 14) 77 #define SEC_CFG_RD_SEC_DMA(n) (((n) & 0x3) << 15) 78 #define SEC_CFG_RD_SEC_DMA_MASK (0x3 << 15) 79 #define SEC_CFG_RD_SEC_DMA_SHIFT (15) 80 #define SEC_CFG_WR_SEC_DMA(n) (((n) & 0x3) << 17) 81 #define SEC_CFG_WR_SEC_DMA_MASK (0x3 << 17) 82 #define SEC_CFG_WR_SEC_DMA_SHIFT (17) 83 84 // reg_10 85 #define SEC_CFG_NONSEC_PROT_AHB1(n) (((n) & 0xFFFF) << 0) 86 #define SEC_CFG_NONSEC_PROT_AHB1_MASK (0xFFFF << 0) 87 #define SEC_CFG_NONSEC_PROT_AHB1_SHIFT (0) 88 #define SEC_CFG_NONSEC_BYPASS_PROT_AHB1(n) (((n) & 0xFFFF) << 16) 89 #define SEC_CFG_NONSEC_BYPASS_PROT_AHB1_MASK (0xFFFF << 16) 90 #define SEC_CFG_NONSEC_BYPASS_PROT_AHB1_SHIFT (16) 91 92 // reg_14 93 #define SEC_CFG_NONSEC_PROT_APB0(n) (((n) & 0x3FFFFFFF) << 0) 94 #define SEC_CFG_NONSEC_PROT_APB0_MASK (0x3FFFFFFF << 0) 95 #define SEC_CFG_NONSEC_PROT_APB0_SHIFT (0) 96 97 // reg_18 98 #define SEC_CFG_NONSEC_BYPASS_PROT_APB0(n) (((n) & 0x3FFFFFFF) << 0) 99 #define SEC_CFG_NONSEC_BYPASS_PROT_APB0_MASK (0x3FFFFFFF << 0) 100 #define SEC_CFG_NONSEC_BYPASS_PROT_APB0_SHIFT (0) 101 102 // reg_1c 103 #define SEC_CFG_NONSEC_PROT_AONAPB(n) (((n) & 0x3FFFFFFF) << 0) 104 #define SEC_CFG_NONSEC_PROT_AONAPB_MASK (0x3FFFFFFF << 0) 105 #define SEC_CFG_NONSEC_PROT_AONAPB_SHIFT (0) 106 107 // reg_20 108 #define SEC_CFG_NONSEC_BYPASS_PROT_AONAPB(n) (((n) & 0x3FFFFFFF) << 0) 109 #define SEC_CFG_NONSEC_BYPASS_PROT_AONAPB_MASK (0x3FFFFFFF << 0) 110 #define SEC_CFG_NONSEC_BYPASS_PROT_AONAPB_SHIFT (0) 111 112 // reg_24 113 #define SEC_CFG_NONSEC_PROT_PERAPB(n) (((n) & 0x3FFFFFFF) << 0) 114 #define SEC_CFG_NONSEC_PROT_PERAPB_MASK (0x3FFFFFFF << 0) 115 #define SEC_CFG_NONSEC_PROT_PERAPB_SHIFT (0) 116 117 // reg_28 118 #define SEC_CFG_NONSEC_BYPASS_PROT_PERAPB(n) (((n) & 0x3FFFFFFF) << 0) 119 #define SEC_CFG_NONSEC_BYPASS_PROT_PERAPB_MASK (0x3FFFFFFF << 0) 120 #define SEC_CFG_NONSEC_BYPASS_PROT_PERAPB_SHIFT (0) 121 122 // reg_2c 123 #define SEC_IRQ_PPC_CODEC (1 << 0) 124 #define SEC_IRQ_PPC_MCU2BT (1 << 1) 125 #define SEC_IRQ_PPC_MCU2WF (1 << 2) 126 #define SEC_IRQ_MPC_SRAM5 (1 << 3) 127 #define SEC_IRQ_MPC_SRAM4 (1 << 4) 128 #define SEC_IRQ_MPC_SRAM3 (1 << 5) 129 #define SEC_IRQ_MPC_SRAM2 (1 << 6) 130 #define SEC_IRQ_MPC_SRAM1 (1 << 7) 131 #define SEC_IRQ_MPC_ROM0 (1 << 8) 132 #define SEC_IRQ_MPC_PSRAM1G (1 << 9) 133 #define SEC_IRQ_MPC_PSRAM200 (1 << 10) 134 #define SEC_IRQ_MPC_PSRAM0 (1 << 11) 135 #define SEC_IRQ_MPC_PSRAM1 (1 << 12) 136 #define SEC_IRQ_MPC_FLASH0 (1 << 13) 137 #define SEC_IRQ_MPC_FLASH1 (1 << 14) 138 #define SEC_IRQ_MPC_SRAM0 (1 << 15) 139 #define SEC_IRQ_MPC_IMEM_LO (1 << 16) 140 #define SEC_IRQ_MPC_IMEM_HI (1 << 17) 141 142 // reg_30 143 #define SEC_SPIDEN_CORE0 (1 << 0) 144 #define SEC_SPNIDEN_CORE0 (1 << 1) 145 #define SEC_SPIDEN_CORE1 (1 << 2) 146 #define SEC_SPNIDEN_CORE1 (1 << 3) 147 #define SEC_CFGSECEXT_CORE1 (1 << 4) 148 149 // reg_34 150 #define SEC_IDAUEN_CORE0 (1 << 0) 151 #define SEC_IDAUIDV_EN_CORE0 (1 << 1) 152 #define SEC_IDAU_CALL_ADDR_CORE0(n) (((n) & 0x7FFFFFF) << 2) 153 #define SEC_IDAU_CALL_ADDR_CORE0_MASK (0x7FFFFFF << 2) 154 #define SEC_IDAU_CALL_ADDR_CORE0_SHIFT (2) 155 156 // reg_38 157 #define SEC_IDAUEN_CORE1 (1 << 0) 158 #define SEC_IDAUIDV_EN_CORE1 (1 << 1) 159 #define SEC_IDAU_CALL_ADDR_CORE1(n) (((n) & 0x7FFFFFF) << 2) 160 #define SEC_IDAU_CALL_ADDR_CORE1_MASK (0x7FFFFFF << 2) 161 #define SEC_IDAU_CALL_ADDR_CORE1_SHIFT (2) 162 163 // reg_3c 164 #define SEC_IRQ_SPY_SRAM5 (1 << 0) 165 #define SEC_IRQ_SPY_SRAM4 (1 << 1) 166 #define SEC_IRQ_SPY_SRAM3 (1 << 2) 167 #define SEC_IRQ_SPY_SRAM2 (1 << 3) 168 #define SEC_IRQ_SPY_SRAM1 (1 << 4) 169 #define SEC_IRQ_SPY_ROM0 (1 << 5) 170 #define SEC_IRQ_SPY_PSRAM1G (1 << 6) 171 #define SEC_IRQ_SPY_PSRAM200 (1 << 7) 172 #define SEC_IRQ_SPY_PSRAM0 (1 << 8) 173 #define SEC_IRQ_SPY_PSRAM1 (1 << 9) 174 #define SEC_IRQ_SPY_FLASH0 (1 << 10) 175 #define SEC_IRQ_SPY_FLASH1 (1 << 11) 176 #define SEC_IRQ_SPY_SRAM0 (1 << 12) 177 #define SEC_IRQ_SPY_IMEM_LO (1 << 13) 178 #define SEC_IRQ_SPY_IMEM_HI (1 << 14) 179 180 #endif 181