1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_SEC_H 10 #define HPM_SEC_H 11 12 typedef struct { 13 __RW uint32_t SECURE_STATE; /* 0x0: Secure state */ 14 __RW uint32_t SECURE_STATE_CONFIG; /* 0x4: secure state configuration */ 15 __RW uint32_t VIOLATION_CONFIG; /* 0x8: Security violation config */ 16 __RW uint32_t ESCALATE_CONFIG; /* 0xC: Escalate behavior on security event */ 17 __R uint32_t EVENT; /* 0x10: Event and escalate status */ 18 __R uint32_t LIFECYCLE; /* 0x14: Lifecycle */ 19 } SEC_Type; 20 21 22 /* Bitfield definition for register: SECURE_STATE */ 23 /* 24 * ALLOW_NSC (RO) 25 * 26 * Non-secure state allow 27 * 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state 28 * 1: system is healthy to enter non-secure state 29 */ 30 #define SEC_SECURE_STATE_ALLOW_NSC_MASK (0x20000UL) 31 #define SEC_SECURE_STATE_ALLOW_NSC_SHIFT (17U) 32 #define SEC_SECURE_STATE_ALLOW_NSC_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_ALLOW_NSC_MASK) >> SEC_SECURE_STATE_ALLOW_NSC_SHIFT) 33 34 /* 35 * ALLOW_SEC (RO) 36 * 37 * Secure state allow 38 * 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state 39 * 1: system is healthy to enter secure state 40 */ 41 #define SEC_SECURE_STATE_ALLOW_SEC_MASK (0x10000UL) 42 #define SEC_SECURE_STATE_ALLOW_SEC_SHIFT (16U) 43 #define SEC_SECURE_STATE_ALLOW_SEC_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_ALLOW_SEC_MASK) >> SEC_SECURE_STATE_ALLOW_SEC_SHIFT) 44 45 /* 46 * PMIC_FAIL (RW) 47 * 48 * PMIC secure state one hot indicator 49 * 0: secure state is not in fail state 50 * 1: secure state is in fail state 51 */ 52 #define SEC_SECURE_STATE_PMIC_FAIL_MASK (0x80U) 53 #define SEC_SECURE_STATE_PMIC_FAIL_SHIFT (7U) 54 #define SEC_SECURE_STATE_PMIC_FAIL_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_FAIL_SHIFT) & SEC_SECURE_STATE_PMIC_FAIL_MASK) 55 #define SEC_SECURE_STATE_PMIC_FAIL_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_FAIL_MASK) >> SEC_SECURE_STATE_PMIC_FAIL_SHIFT) 56 57 /* 58 * PMIC_NSC (RW) 59 * 60 * PMIC secure state one hot indicator 61 * 0: secure state is not in non-secure state 62 * 1: secure state is in non-secure state 63 */ 64 #define SEC_SECURE_STATE_PMIC_NSC_MASK (0x40U) 65 #define SEC_SECURE_STATE_PMIC_NSC_SHIFT (6U) 66 #define SEC_SECURE_STATE_PMIC_NSC_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_NSC_SHIFT) & SEC_SECURE_STATE_PMIC_NSC_MASK) 67 #define SEC_SECURE_STATE_PMIC_NSC_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_NSC_MASK) >> SEC_SECURE_STATE_PMIC_NSC_SHIFT) 68 69 /* 70 * PMIC_SEC (RW) 71 * 72 * PMIC secure state one hot indicator 73 * 0: secure state is not in secure state 74 * 1: secure state is in secure state 75 */ 76 #define SEC_SECURE_STATE_PMIC_SEC_MASK (0x20U) 77 #define SEC_SECURE_STATE_PMIC_SEC_SHIFT (5U) 78 #define SEC_SECURE_STATE_PMIC_SEC_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_SEC_SHIFT) & SEC_SECURE_STATE_PMIC_SEC_MASK) 79 #define SEC_SECURE_STATE_PMIC_SEC_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_SEC_MASK) >> SEC_SECURE_STATE_PMIC_SEC_SHIFT) 80 81 /* 82 * PMIC_INS (RW) 83 * 84 * PMIC secure state one hot indicator 85 * 0: secure state is not in inspect state 86 * 1: secure state is in inspect state 87 */ 88 #define SEC_SECURE_STATE_PMIC_INS_MASK (0x10U) 89 #define SEC_SECURE_STATE_PMIC_INS_SHIFT (4U) 90 #define SEC_SECURE_STATE_PMIC_INS_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_INS_SHIFT) & SEC_SECURE_STATE_PMIC_INS_MASK) 91 #define SEC_SECURE_STATE_PMIC_INS_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_INS_MASK) >> SEC_SECURE_STATE_PMIC_INS_SHIFT) 92 93 /* Bitfield definition for register: SECURE_STATE_CONFIG */ 94 /* 95 * LOCK (RW) 96 * 97 * Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset 98 * 0: not locked, register can be modified 99 * 1: register locked, write access to the register is ignored 100 */ 101 #define SEC_SECURE_STATE_CONFIG_LOCK_MASK (0x8U) 102 #define SEC_SECURE_STATE_CONFIG_LOCK_SHIFT (3U) 103 #define SEC_SECURE_STATE_CONFIG_LOCK_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & SEC_SECURE_STATE_CONFIG_LOCK_MASK) 104 #define SEC_SECURE_STATE_CONFIG_LOCK_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_CONFIG_LOCK_MASK) >> SEC_SECURE_STATE_CONFIG_LOCK_SHIFT) 105 106 /* 107 * ALLOW_RESTART (RW) 108 * 109 * allow secure state restart from fail state 110 * 0: restart is not allowed, only hardware reset can recover secure state 111 * 1: software is allowed to switch to inspect state from fail state 112 */ 113 #define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK (0x1U) 114 #define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT (0U) 115 #define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) 116 #define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) 117 118 /* Bitfield definition for register: VIOLATION_CONFIG */ 119 /* 120 * LOCK_NSC (RW) 121 * 122 * Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset 123 * 0: not locked, configuration can be modified 124 * 1: register locked, write access to the configuration is ignored 125 */ 126 #define SEC_VIOLATION_CONFIG_LOCK_NSC_MASK (0x80000000UL) 127 #define SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT (31U) 128 #define SEC_VIOLATION_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & SEC_VIOLATION_CONFIG_LOCK_NSC_MASK) 129 #define SEC_VIOLATION_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & SEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) 130 131 /* 132 * NSC_VIO_CFG (RW) 133 * 134 * configuration of non-secure state violations, each bit represents one security event 135 * 0: event is not a security violation 136 * 1: event is a security violation 137 */ 138 #define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) 139 #define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT (16U) 140 #define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) 141 #define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) 142 143 /* 144 * LOCK_SEC (RW) 145 * 146 * Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset 147 * 0: not locked, configuration can be modified 148 * 1: register locked, write access to the configuration is ignored 149 */ 150 #define SEC_VIOLATION_CONFIG_LOCK_SEC_MASK (0x8000U) 151 #define SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT (15U) 152 #define SEC_VIOLATION_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & SEC_VIOLATION_CONFIG_LOCK_SEC_MASK) 153 #define SEC_VIOLATION_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & SEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) 154 155 /* 156 * SEC_VIO_CFG (RW) 157 * 158 * configuration of secure state violations, each bit represents one security event 159 * 0: event is not a security violation 160 * 1: event is a security violation 161 */ 162 #define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) 163 #define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT (0U) 164 #define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) 165 #define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) 166 167 /* Bitfield definition for register: ESCALATE_CONFIG */ 168 /* 169 * LOCK_NSC (RW) 170 * 171 * Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset 172 * 0: not locked, configuration can be modified 173 * 1: register locked, write access to the configuration is ignored 174 */ 175 #define SEC_ESCALATE_CONFIG_LOCK_NSC_MASK (0x80000000UL) 176 #define SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT (31U) 177 #define SEC_ESCALATE_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & SEC_ESCALATE_CONFIG_LOCK_NSC_MASK) 178 #define SEC_ESCALATE_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & SEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) 179 180 /* 181 * NSC_VIO_CFG (RW) 182 * 183 * configuration of non-secure state escalates, each bit represents one security event 184 * 0: event is not a security escalate 185 * 1: event is a security escalate 186 */ 187 #define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) 188 #define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT (16U) 189 #define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) 190 #define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) 191 192 /* 193 * LOCK_SEC (RW) 194 * 195 * Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset 196 * 0: not locked, configuration can be modified 197 * 1: register locked, write access to the configuration is ignored 198 */ 199 #define SEC_ESCALATE_CONFIG_LOCK_SEC_MASK (0x8000U) 200 #define SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT (15U) 201 #define SEC_ESCALATE_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & SEC_ESCALATE_CONFIG_LOCK_SEC_MASK) 202 #define SEC_ESCALATE_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & SEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) 203 204 /* 205 * SEC_VIO_CFG (RW) 206 * 207 * configuration of secure state escalates, each bit represents one security event 208 * 0: event is not a security escalate 209 * 1: event is a security escalate 210 */ 211 #define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) 212 #define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT (0U) 213 #define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) 214 #define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) 215 216 /* Bitfield definition for register: EVENT */ 217 /* 218 * EVENT (RO) 219 * 220 * local event statue, each bit represents one security event 221 */ 222 #define SEC_EVENT_EVENT_MASK (0xFFFF0000UL) 223 #define SEC_EVENT_EVENT_SHIFT (16U) 224 #define SEC_EVENT_EVENT_GET(x) (((uint32_t)(x) & SEC_EVENT_EVENT_MASK) >> SEC_EVENT_EVENT_SHIFT) 225 226 /* 227 * PMIC_ESC_NSC (RO) 228 * 229 * PMIC is escalating non-secure event 230 */ 231 #define SEC_EVENT_PMIC_ESC_NSC_MASK (0x8U) 232 #define SEC_EVENT_PMIC_ESC_NSC_SHIFT (3U) 233 #define SEC_EVENT_PMIC_ESC_NSC_GET(x) (((uint32_t)(x) & SEC_EVENT_PMIC_ESC_NSC_MASK) >> SEC_EVENT_PMIC_ESC_NSC_SHIFT) 234 235 /* 236 * PMIC_ESC_SEC (RO) 237 * 238 * PMIC is escalting secure event 239 */ 240 #define SEC_EVENT_PMIC_ESC_SEC_MASK (0x4U) 241 #define SEC_EVENT_PMIC_ESC_SEC_SHIFT (2U) 242 #define SEC_EVENT_PMIC_ESC_SEC_GET(x) (((uint32_t)(x) & SEC_EVENT_PMIC_ESC_SEC_MASK) >> SEC_EVENT_PMIC_ESC_SEC_SHIFT) 243 244 /* Bitfield definition for register: LIFECYCLE */ 245 /* 246 * LIFECYCLE (RO) 247 * 248 * lifecycle status, 249 * bit7: lifecycle_debate, 250 * bit6: lifecycle_scribe, 251 * bit5: lifecycle_no_ret, 252 * bit4: lifecycle_return, 253 * bit3: lifecycle_secure, 254 * bit2: lifecycle_nonsec, 255 * bit1: lifecycle_create, 256 * bit0: lifecycle_unknow 257 */ 258 #define SEC_LIFECYCLE_LIFECYCLE_MASK (0xFFU) 259 #define SEC_LIFECYCLE_LIFECYCLE_SHIFT (0U) 260 #define SEC_LIFECYCLE_LIFECYCLE_GET(x) (((uint32_t)(x) & SEC_LIFECYCLE_LIFECYCLE_MASK) >> SEC_LIFECYCLE_LIFECYCLE_SHIFT) 261 262 263 264 265 #endif /* HPM_SEC_H */ 266