1 /* 2 * Allwinner SoCs display driver. 3 * 4 * Copyright (C) 2017 Allwinner. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #ifndef _DE_TOP_H_ 12 #define _DE_TOP_H_ 13 14 #include <linux/types.h> 15 16 #define DE_TOP_REG_OFFSET (0x8000) 17 #define DE_TOP_REG_SIZE (0x0220) 18 19 #define DE_TOP_RTWB_OFFSET (0x010000) 20 #define DE_TOP_RTMX_OFFSET (0x100000) 21 22 #define DE_CHN_SIZE (0x20000) /* 128K */ 23 #define DE_CHN_OFFSET(phy_chn) (0x100000 + DE_CHN_SIZE * (phy_chn)) 24 25 #define DE_DISP_SIZE (0x20000) /* 128K */ 26 #define DE_DISP_OFFSET(disp) (0x280000 + DE_DISP_SIZE * (disp)) 27 28 #define CHN_CCSC_OFFSET (0x00800) 29 #define CHN_OVL_OFFSET (0x01000) 30 #define CHN_DBV_OFFSET (0x02000) 31 #define CHN_SCALER_OFFSET (0x04000) 32 #define CHN_FBD_ATW_OFFSET (0x05000) 33 #define CHN_CDC_OFFSET (0x08000) 34 #define CHN_FCE_OFFSET (0x10000) 35 #define CHN_PEAK_OFFSET (0x10800) 36 #define CHN_LTI_OFFSET (0x10C00) 37 #define CHN_BLS_OFFSET (0x11000) 38 #define CHN_FCC_OFFSET (0x11400) 39 #define CHN_DNS_OFFSET (0x14000) 40 #define CHN_DI300_OFFSET (0x14400) 41 #define CHN_SNR_OFFSET (0x14000) 42 43 #define DISP_BLD_OFFSET (0x01000) 44 #define DISP_DEP_OFFSET (0x02000) 45 #define DISP_DB3_OFFSET (0x03000) 46 #define DISP_FMT_OFFSET (0x05000) 47 #define DISP_DSC_OFFSET (0x06000) 48 #define DISP_KSC_OFFSET (0x08000) 49 50 #define RTWB_WB_OFFSET (0x01000) 51 #define RTWB_CDC_OFFSET (0x08000) 52 53 enum de_rtwb_mode { 54 TIMING_FROM_TCON = 0, 55 SELF_GENERATED_TIMING = 1, 56 }; 57 58 enum de_clk_id { 59 DE_CLK_NONE = 0, 60 DE_CLK_CORE0 = 1, 61 DE_CLK_CORE1 = 2, 62 DE_CLK_CORE2 = 3, 63 DE_CLK_CORE3 = 4, 64 DE_CLK_WB = 5, 65 }; 66 67 enum de_rtwb_mux_id { 68 RTWB_MUX_FROM_BLENDER0 = 0, 69 RTWB_MUX_FROM_DSC0 = 1, 70 RTWB_MUX_FROM_BLENDER1 = 2, 71 RTWB_MUX_FROM_DSC1 = 3, 72 RTWB_MUX_FROM_BLENDER2 = 4, 73 RTWB_MUX_FROM_DSC2 = 5, 74 RTWB_MUX_FROM_BLENDER3 = 6, 75 RTWB_MUX_FROM_DSC3 = 7, 76 }; 77 78 enum de_irq_flag { 79 DE_IRQ_FLAG_FRAME_END = 0x1 << 4, 80 DE_IRQ_FLAG_ERROR = 0, 81 DE_IRQ_FLAG_RCQ_FINISH = 0x1 << 6, 82 DE_IRQ_FLAG_RCQ_ACCEPT = 0x1 << 7, 83 DE_IRQ_FLAG_MASK = 84 DE_IRQ_FLAG_FRAME_END 85 | DE_IRQ_FLAG_ERROR 86 | DE_IRQ_FLAG_RCQ_FINISH 87 | DE_IRQ_FLAG_RCQ_ACCEPT, 88 }; 89 90 enum de_irq_state { 91 DE_IRQ_STATE_FRAME_END = 0x1 << 0, 92 DE_IRQ_STATE_ERROR = 0, 93 DE_IRQ_STATE_RCQ_FINISH = 0x1 << 2, 94 DE_IRQ_STATE_RCQ_ACCEPT = 0x1 << 3, 95 DE_IRQ_STATE_MASK = 96 DE_IRQ_STATE_FRAME_END 97 | DE_IRQ_STATE_ERROR 98 | DE_IRQ_STATE_RCQ_FINISH 99 | DE_IRQ_STATE_RCQ_ACCEPT, 100 }; 101 102 enum de_wb_irq_flag { 103 DE_WB_IRQ_FLAG_RCQ_FINISH = 0x1 << 6, 104 DE_WB_IRQ_FLAG_RCQ_ACCEPT = 0x1 << 7, 105 DE_WB_IRQ_FLAG_MASK = 106 DE_WB_IRQ_FLAG_RCQ_FINISH 107 | DE_WB_IRQ_FLAG_RCQ_ACCEPT, 108 }; 109 110 enum de_wb_irq_state { 111 DE_WB_IRQ_STATE_RCQ_FINISH = 0x1 << 2, 112 DE_WB_IRQ_STATE_RCQ_ACCEPT = 0x1 << 3, 113 DE_WB_IRQ_STATE_MASK = 114 DE_WB_IRQ_STATE_RCQ_FINISH 115 | DE_WB_IRQ_STATE_RCQ_ACCEPT, 116 }; 117 118 119 uintptr_t de_top_get_reg_base(void); 120 void de_top_set_reg_base(u8 __iomem *reg_base); 121 122 s32 de_top_set_clk_enable(u32 clk_no, u8 en); 123 124 s32 de_top_set_de2tcon_mux(u32 disp, u32 tcon); 125 u32 de_top_get_tcon_from_mux(u32 disp); 126 127 u32 de_top_get_ip_version(void); 128 129 s32 de_top_set_rtwb_mux(u32 wb_id, enum de_rtwb_mux_id id); 130 enum de_rtwb_mux_id de_top_get_rtwb_mux(u32 wb_id); 131 132 s32 de_top_set_vchn2core_mux(u32 phy_chn, u32 phy_disp); 133 s32 de_top_set_uchn2core_mux(u32 phy_chn, u32 phy_disp); 134 s32 de_top_set_port2vchn_mux(u32 phy_disp, u32 port, u32 phy_chn); 135 s32 de_top_set_port2uchn_mux(u32 phy_disp, u32 port, u32 phy_chn); 136 137 u32 de_top_get_ahb_config_flag(void); 138 s32 de_top_set_lut_debug_enable(u8 en); 139 140 s32 de_top_set_rtmx_enable(u32 disp, u8 en); 141 s32 de_top_enable_irq(u32 disp, u32 irq_flag, u32 en); 142 u32 de_top_query_state_with_clear(u32 disp, u32 irq_state); 143 s32 de_top_set_out_size(u32 disp, u32 width, u32 height); 144 s32 de_top_get_out_size(u32 disp, u32 *width, u32 *height); 145 s32 de_top_set_rcq_update(u32 disp, u32 update); 146 s32 de_top_set_rcq_head(u32 disp, u64 addr, u32 len); 147 148 s32 de_top_wb_enable_irq(u32 wb, u32 irq_flag, u32 en); 149 u32 de_top_wb_query_state_with_clear(u32 wb, u32 irq_state); 150 s32 de_top_wb_set_rcq_update(u32 wb, u32 update); 151 s32 de_top_wb_set_rcq_head(u32 wb, u64 addr, u32 len); 152 153 154 extern void *disp_malloc(u32 num_bytes, void *phys_addr); 155 extern void disp_free(void *virt_addr, void *phys_addr, u32 num_bytes); 156 void *de_top_reg_memory_alloc( 157 u32 size, void *phy_addr, u32 rcq_used); 158 void de_top_reg_memory_free( 159 void *virt_addr, void *phys_addr, u32 num_bytes); 160 s32 de_top_mem_pool_alloc(void); 161 s32 de_top_start_rtwb(u32 wb_id, u32 en); 162 s32 de_top_set_rtwb_mode(u32 wb_id, enum de_rtwb_mode mode); 163 void de_top_mem_pool_free(void); 164 165 #endif /* #ifndef _DE_TOP_H_ */ 166