1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __REG_CMU_BEST2003_H__ 16 #define __REG_CMU_BEST2003_H__ 17 18 #include "plat_types.h" 19 20 struct CMU_T { 21 __IO uint32_t HCLK_ENABLE; // 0x00 22 __IO uint32_t HCLK_DISABLE; // 0x04 23 __IO uint32_t PCLK_ENABLE; // 0x08 24 __IO uint32_t PCLK_DISABLE; // 0x0C 25 __IO uint32_t OCLK_ENABLE; // 0x10 26 __IO uint32_t OCLK_DISABLE; // 0x14 27 __IO uint32_t HCLK_MODE; // 0x18 28 __IO uint32_t PCLK_MODE; // 0x1C 29 __IO uint32_t OCLK_MODE; // 0x20 30 __IO uint32_t RESERVED_024; // 0x24 31 __IO uint32_t HRESET_PULSE; // 0x28 32 __IO uint32_t PRESET_PULSE; // 0x2C 33 __IO uint32_t ORESET_PULSE; // 0x30 34 __IO uint32_t HRESET_SET; // 0x34 35 __IO uint32_t HRESET_CLR; // 0x38 36 __IO uint32_t PRESET_SET; // 0x3C 37 __IO uint32_t PRESET_CLR; // 0x40 38 __IO uint32_t ORESET_SET; // 0x44 39 __IO uint32_t ORESET_CLR; // 0x48 40 __IO uint32_t TIMER0_CLK; // 0x4C 41 __IO uint32_t BOOTMODE; // 0x50 42 __IO uint32_t MCU_TIMER; // 0x54 43 __IO uint32_t SLEEP; // 0x58 44 __IO uint32_t PERIPH_CLK; // 0x5C 45 __IO uint32_t SYS_CLK_ENABLE; // 0x60 46 __IO uint32_t SYS_CLK_DISABLE; // 0x64 47 __IO uint32_t ADMA_CH15_REQ; // 0x68 48 __IO uint32_t BOOT_DVS; // 0x6C 49 __IO uint32_t UART_CLK; // 0x70 50 __IO uint32_t I2C_CLK; // 0x74 51 __IO uint32_t RAM_CFG0; // 0x78 52 __IO uint32_t RAM_CFG1; // 0x7C 53 __IO uint32_t WRITE_UNLOCK; // 0x80 54 __IO uint32_t WAKEUP_MASK0; // 0x84 55 __IO uint32_t WAKEUP_MASK1; // 0x88 56 __IO uint32_t WAKEUP_CLK_CFG; // 0x8C 57 __IO uint32_t TIMER1_CLK; // 0x90 58 __IO uint32_t TIMER2_CLK; // 0x94 59 __IO uint32_t CP2MCU_IRQ_SET; // 0x98 60 __IO uint32_t CP2MCU_IRQ_CLR; // 0x9C 61 __IO uint32_t ISIRQ_SET; // 0xA0 62 __IO uint32_t ISIRQ_CLR; // 0xA4 63 __IO uint32_t SYS_DIV; // 0xA8 64 __IO uint32_t RESERVED_0AC; // 0xAC 65 __IO uint32_t MCU2BT_INTMASK0; // 0xB0 66 __IO uint32_t MCU2BT_INTMASK1; // 0xB4 67 __IO uint32_t MCU2CP_IRQ_SET; // 0xB8 68 __IO uint32_t MCU2CP_IRQ_CLR; // 0xBC 69 __IO uint32_t MEMSC[4]; // 0xC0 70 __I uint32_t MEMSC_STATUS; // 0xD0 71 __IO uint32_t ADMA_CH0_4_REQ; // 0xD4 72 __IO uint32_t ADMA_CH5_9_REQ; // 0xD8 73 __IO uint32_t ADMA_CH10_14_REQ; // 0xDC 74 __IO uint32_t GDMA_CH0_4_REQ; // 0xE0 75 __IO uint32_t GDMA_CH5_9_REQ; // 0xE4 76 __IO uint32_t GDMA_CH10_14_REQ; // 0xE8 77 __IO uint32_t GDMA_CH15_REQ; // 0xEC 78 __IO uint32_t MISC; // 0xF0 79 __IO uint32_t SIMU_RES; // 0xF4 80 __IO uint32_t SEC_ROM_CFG; // 0xF8 81 __IO uint32_t ACC_CTRL; // 0xFC 82 __IO uint32_t CP_VTOR; // 0x100 83 __IO uint32_t XCLK_ENABLE; // 0x104 84 __IO uint32_t XCLK_DISABLE; // 0x108 85 __IO uint32_t XCLK_MODE; // 0x10C 86 __IO uint32_t XRESET_PULSE; // 0x110 87 __IO uint32_t XRESET_SET; // 0x114 88 __IO uint32_t XRESET_CLR; // 0x118 89 __IO uint32_t DSP_DIV; // 0x11C 90 __IO uint32_t WAKEUP_MASK2; // 0x120 91 __IO uint32_t MCU2BT_INTMASK2; // 0x124 92 __IO uint32_t MCU2WF_INTMASK0; // 0x128 93 __IO uint32_t MCU2WF_INTMASK1; // 0x12C 94 __IO uint32_t MCU2WF_INTMASK2; // 0x130 95 __IO uint32_t MCU2DSP_INTMASK0; // 0x134 96 __IO uint32_t MCU2DSP_INTMASK1; // 0x138 97 __IO uint32_t MCU2DSP_INTMASK2; // 0x13C 98 __IO uint32_t DSP_CFG0; // 0x140 99 __IO uint32_t DSP_CFG1; // 0x144 100 __IO uint32_t DSP_CFG2; // 0x148 101 __IO uint32_t DSP_CFG3; // 0x14C 102 __IO uint32_t APCLK_ENABLE; // 0x150 103 __IO uint32_t APCLK_DISABLE; // 0x154 104 __IO uint32_t APCLK_MODE; // 0x158 105 __IO uint32_t APRESET_PULSE; // 0x15C 106 __IO uint32_t APRESET_SET; // 0x160 107 __IO uint32_t APRESET_CLR; // 0x164 108 __IO uint32_t AP_TIMER1_CLK; // 0x168 109 __IO uint32_t AP_TIMER2_CLK; // 0x16C 110 __IO uint32_t RESERVED_170[4]; // 0x170 111 __IO uint32_t MEMSC_AUX[0x1C]; // 0x180 112 __IO uint32_t RESERVED_1F0[4]; // 0x1F0 113 __IO uint32_t QCLK_ENABLE; // 0x200 114 __IO uint32_t QCLK_DISABLE; // 0x204 115 __IO uint32_t QCLK_MODE; // 0x208 116 __IO uint32_t QRESET_PULSE; // 0x20C 117 __IO uint32_t QRESET_SET; // 0x210 118 __IO uint32_t QRESET_CLR; // 0x214 119 __IO uint32_t BT_PLAYTIME; // 0x218 120 __IO uint32_t CMU_REMAP; // 0x21C 121 __IO uint32_t INTMSK_CORE0; // 0x220 122 __IO uint32_t INTMSK1_CORE0; // 0x224 123 __IO uint32_t INTMSK2_CORE0; // 0x224 124 __IO uint32_t INTMSK_CORE1; // 0x22C 125 __IO uint32_t INTMSK1_CORE1; // 0x230 126 __IO uint32_t INTMSK2_CORE1; // 0x234 127 }; 128 129 // reg_000 130 #define CMU_MANUAL_HCLK_ENABLE(n) (((n) & 0xFFFFFFFF) << 0) 131 #define CMU_MANUAL_HCLK_ENABLE_MASK (0xFFFFFFFF << 0) 132 #define CMU_MANUAL_HCLK_ENABLE_SHIFT (0) 133 134 // reg_004 135 #define CMU_MANUAL_HCLK_DISABLE(n) (((n) & 0xFFFFFFFF) << 0) 136 #define CMU_MANUAL_HCLK_DISABLE_MASK (0xFFFFFFFF << 0) 137 #define CMU_MANUAL_HCLK_DISABLE_SHIFT (0) 138 139 // reg_008 140 #define CMU_MANUAL_PCLK_ENABLE(n) (((n) & 0xFFFFFFFF) << 0) 141 #define CMU_MANUAL_PCLK_ENABLE_MASK (0xFFFFFFFF << 0) 142 #define CMU_MANUAL_PCLK_ENABLE_SHIFT (0) 143 144 // reg_00c 145 #define CMU_MANUAL_PCLK_DISABLE(n) (((n) & 0xFFFFFFFF) << 0) 146 #define CMU_MANUAL_PCLK_DISABLE_MASK (0xFFFFFFFF << 0) 147 #define CMU_MANUAL_PCLK_DISABLE_SHIFT (0) 148 149 // reg_010 150 #define CMU_MANUAL_OCLK_ENABLE(n) (((n) & 0xFFFFFFFF) << 0) 151 #define CMU_MANUAL_OCLK_ENABLE_MASK (0xFFFFFFFF << 0) 152 #define CMU_MANUAL_OCLK_ENABLE_SHIFT (0) 153 154 // reg_014 155 #define CMU_MANUAL_OCLK_DISABLE(n) (((n) & 0xFFFFFFFF) << 0) 156 #define CMU_MANUAL_OCLK_DISABLE_MASK (0xFFFFFFFF << 0) 157 #define CMU_MANUAL_OCLK_DISABLE_SHIFT (0) 158 159 // reg_018 160 #define CMU_MODE_HCLK(n) (((n) & 0xFFFFFFFF) << 0) 161 #define CMU_MODE_HCLK_MASK (0xFFFFFFFF << 0) 162 #define CMU_MODE_HCLK_SHIFT (0) 163 164 // reg_01c 165 #define CMU_MODE_PCLK(n) (((n) & 0xFFFFFFFF) << 0) 166 #define CMU_MODE_PCLK_MASK (0xFFFFFFFF << 0) 167 #define CMU_MODE_PCLK_SHIFT (0) 168 169 // reg_020 170 #define CMU_MODE_OCLK(n) (((n) & 0xFFFFFFFF) << 0) 171 #define CMU_MODE_OCLK_MASK (0xFFFFFFFF << 0) 172 #define CMU_MODE_OCLK_SHIFT (0) 173 174 // reg_028 175 #define CMU_HRESETN_PULSE(n) (((n) & 0xFFFFFFFF) << 0) 176 #define CMU_HRESETN_PULSE_MASK (0xFFFFFFFF << 0) 177 #define CMU_HRESETN_PULSE_SHIFT (0) 178 179 #define SYS_PRST_NUM 26 180 181 // reg_2c 182 #define CMU_PRESETN_PULSE(n) (((n) & 0xFFFFFFFF) << 0) 183 #define CMU_PRESETN_PULSE_MASK (0xFFFFFFFF << 0) 184 #define CMU_PRESETN_PULSE_SHIFT (0) 185 #define CMU_GLOBAL_RESETN_PULSE (1 << (SYS_PRST_NUM+1-1)) 186 187 // reg_030 188 #define CMU_ORESETN_PULSE(n) (((n) & 0xFFFFFFFF) << 0) 189 #define CMU_ORESETN_PULSE_MASK (0xFFFFFFFF << 0) 190 #define CMU_ORESETN_PULSE_SHIFT (0) 191 192 // reg_034 193 #define CMU_HRESETN_SET(n) (((n) & 0xFFFFFFFF) << 0) 194 #define CMU_HRESETN_SET_MASK (0xFFFFFFFF << 0) 195 #define CMU_HRESETN_SET_SHIFT (0) 196 197 // reg_038 198 #define CMU_HRESETN_CLR(n) (((n) & 0xFFFFFFFF) << 0) 199 #define CMU_HRESETN_CLR_MASK (0xFFFFFFFF << 0) 200 #define CMU_HRESETN_CLR_SHIFT (0) 201 202 // reg_03c 203 #define CMU_PRESETN_SET(n) (((n) & 0xFFFFFFFF) << 0) 204 #define CMU_PRESETN_SET_MASK (0xFFFFFFFF << 0) 205 #define CMU_PRESETN_SET_SHIFT (0) 206 #define CMU_GLOBAL_RESETN_SET (1 << (SYS_PRST_NUM+1-1)) 207 208 // reg_040 209 #define CMU_PRESETN_CLR(n) (((n) & 0xFFFFFFFF) << 0) 210 #define CMU_PRESETN_CLR_MASK (0xFFFFFFFF << 0) 211 #define CMU_PRESETN_CLR_SHIFT (0) 212 #define CMU_GLOBAL_RESETN_CLR (1 << (SYS_PRST_NUM+1-1)) 213 214 // reg_044 215 #define CMU_ORESETN_SET(n) (((n) & 0xFFFFFFFF) << 0) 216 #define CMU_ORESETN_SET_MASK (0xFFFFFFFF << 0) 217 #define CMU_ORESETN_SET_SHIFT (0) 218 219 // reg_048 220 #define CMU_ORESETN_CLR(n) (((n) & 0xFFFFFFFF) << 0) 221 #define CMU_ORESETN_CLR_MASK (0xFFFFFFFF << 0) 222 #define CMU_ORESETN_CLR_SHIFT (0) 223 224 // reg_04c 225 #define CMU_CFG_DIV_TIMER00(n) (((n) & 0xFFFF) << 0) 226 #define CMU_CFG_DIV_TIMER00_MASK (0xFFFF << 0) 227 #define CMU_CFG_DIV_TIMER00_SHIFT (0) 228 #define CMU_CFG_DIV_TIMER01(n) (((n) & 0xFFFF) << 16) 229 #define CMU_CFG_DIV_TIMER01_MASK (0xFFFF << 16) 230 #define CMU_CFG_DIV_TIMER01_SHIFT (16) 231 232 // reg_050 233 #define CMU_WATCHDOG_RESET (1 << 0) 234 #define CMU_SOFT_GLOBLE_RESET (1 << 1) 235 #define CMU_RTC_INTR_H (1 << 2) 236 #define CMU_CHG_INTR_H (1 << 3) 237 #define CMU_SOFT_BOOT_MODE(n) (((n) & 0xFFFFFFF) << 4) 238 #define CMU_SOFT_BOOT_MODE_MASK (0xFFFFFFF << 4) 239 #define CMU_SOFT_BOOT_MODE_SHIFT (4) 240 241 // reg_054 242 #define CMU_CFG_HCLK_MCU_OFF_TIMER(n) (((n) & 0xFF) << 0) 243 #define CMU_CFG_HCLK_MCU_OFF_TIMER_MASK (0xFF << 0) 244 #define CMU_CFG_HCLK_MCU_OFF_TIMER_SHIFT (0) 245 #define CMU_HCLK_MCU_ENABLE (1 << 8) 246 #define CMU_SECURE_BOOT_JTAG (1 << 9) 247 #define CMU_RAM_RETN_UP_EARLY (1 << 10) 248 #define CMU_FLS_SEC_MSK_EN (1 << 11) 249 #define CMU_SECURE_BOOT_I2C (1 << 12) 250 #define CMU_DEBUG_REG_SEL(n) (((n) & 0x7) << 13) 251 #define CMU_DEBUG_REG_SEL_MASK (0x7 << 13) 252 #define CMU_DEBUG_REG_SEL_SHIFT (13) 253 #define CMU_FLS1_IO_SEL (1 << 16) 254 #define CMU_FLS0_X8_SEL (1 << 17) 255 256 // reg_058 257 #define CMU_SLEEP_TIMER(n) (((n) & 0xFFFFFF) << 0) 258 #define CMU_SLEEP_TIMER_MASK (0xFFFFFF << 0) 259 #define CMU_SLEEP_TIMER_SHIFT (0) 260 #define CMU_SLEEP_TIMER_EN (1 << 24) 261 #define CMU_DEEPSLEEP_EN (1 << 25) 262 #define CMU_DEEPSLEEP_ROMRAM_EN (1 << 26) 263 #define CMU_MANUAL_RAM_RETN (1 << 27) 264 #define CMU_DEEPSLEEP_START (1 << 28) 265 #define CMU_DEEPSLEEP_MODE (1 << 29) 266 #define CMU_PU_OSC (1 << 30) 267 #define CMU_WAKEDOWN_DEEPSLEEP_L (1 << 31) 268 269 // reg_05c 270 #define CMU_CFG_DIV_SDMMC(n) (((n) & 0xF) << 0) 271 #define CMU_CFG_DIV_SDMMC_MASK (0xF << 0) 272 #define CMU_CFG_DIV_SDMMC_SHIFT (0) 273 #define CMU_SEL_OSCX2_SDMMC (1 << 4) 274 #define CMU_SEL_PLL_SDMMC (1 << 5) 275 #define CMU_EN_PLL_SDMMC (1 << 6) 276 #define CMU_SEL_32K_TIMER(n) (((n) & 0x7) << 7) 277 #define CMU_SEL_32K_TIMER_MASK (0x7 << 7) 278 #define CMU_SEL_32K_TIMER_SHIFT (7) 279 #define CMU_SEL_32K_WDT (1 << 10) 280 #define CMU_SEL_TIMER_FAST(n) (((n) & 0x7) << 11) 281 #define CMU_SEL_TIMER_FAST_MASK (0x7 << 11) 282 #define CMU_SEL_TIMER_FAST_SHIFT (11) 283 #define CMU_CFG_CLK_OUT(n) (((n) & 0xF) << 14) 284 #define CMU_CFG_CLK_OUT_MASK (0xF << 14) 285 #define CMU_CFG_CLK_OUT_SHIFT (14) 286 #define CMU_SPI_I2C_DMAREQ_SEL (1 << 18) 287 #define CMU_MASK_OBS(n) (((n) & 0x3F) << 19) 288 #define CMU_MASK_OBS_MASK (0x3F << 19) 289 #define CMU_MASK_OBS_SHIFT (19) 290 #define CMU_JTAG_SEL_MASK (3 << 25) 291 #define CMU_JTAG_SEL_CP (1 << 25) 292 #define CMU_JTAG_SEL_A7 (1 << 26) 293 #define CMU_WF_ALLIRQ_MASK (1 << 27) 294 #define CMU_A7_ALLIRQ_MASK (1 << 28) 295 #define CMU_SEL_PSRAMX2 (1 << 29) 296 297 // reg_060 298 #define CMU_RSTN_DIV_MCU_ENABLE (1 << 0) 299 #define CMU_BYPASS_DIV_MCU_ENABLE (1 << 1) 300 #define CMU_SEL_MCU_OSC_4_ENABLE (1 << 2) 301 #define CMU_SEL_MCU_OSC_2_ENABLE (1 << 3) 302 #define CMU_SEL_MCU_OSCX4_ENABLE (1 << 4) 303 #define CMU_SEL_MCU_SLOW_ENABLE (1 << 5) 304 #define CMU_SEL_MCU_FAST_ENABLE (1 << 6) 305 #define CMU_SEL_MCU_PLL_ENABLE (1 << 7) 306 #define CMU_RSTN_DIV_A7_ENABLE (1 << 8) 307 #define CMU_BYPASS_DIV_A7_ENABLE (1 << 9) 308 #define CMU_SEL_A7_OSC_4_ENABLE (1 << 10) 309 #define CMU_SEL_A7_OSC_2_ENABLE (1 << 11) 310 #define CMU_SEL_A7_OSCX4_ENABLE (1 << 12) 311 #define CMU_SEL_A7_SLOW_ENABLE (1 << 13) 312 #define CMU_SEL_A7_FAST_ENABLE (1 << 14) 313 #define CMU_SEL_A7_PLL_ENABLE (1 << 15) 314 #define CMU_EN_PLLMCU_ENABLE (1 << 16) 315 #define CMU_PU_PLLMCU_ENABLE (1 << 17) 316 #define CMU_EN_PLLA7_ENABLE (1 << 18) 317 #define CMU_PU_PLLA7_ENABLE (1 << 19) 318 319 // reg_064 320 #define CMU_RSTN_DIV_MCU_DISABLE (1 << 0) 321 #define CMU_BYPASS_DIV_MCU_DISABLE (1 << 1) 322 #define CMU_SEL_MCU_OSC_4_DISABLE (1 << 2) 323 #define CMU_SEL_MCU_OSC_2_DISABLE (1 << 3) 324 #define CMU_SEL_MCU_OSCX4_DISABLE (1 << 4) 325 #define CMU_SEL_MCU_SLOW_DISABLE (1 << 5) 326 #define CMU_SEL_MCU_FAST_DISABLE (1 << 6) 327 #define CMU_SEL_MCU_PLL_DISABLE (1 << 7) 328 #define CMU_RSTN_DIV_A7_DISABLE (1 << 8) 329 #define CMU_BYPASS_DIV_A7_DISABLE (1 << 9) 330 #define CMU_SEL_A7_OSC_4_DISABLE (1 << 10) 331 #define CMU_SEL_A7_OSC_2_DISABLE (1 << 11) 332 #define CMU_SEL_A7_OSCX4_DISABLE (1 << 12) 333 #define CMU_SEL_A7_SLOW_DISABLE (1 << 13) 334 #define CMU_SEL_A7_FAST_DISABLE (1 << 14) 335 #define CMU_SEL_A7_PLL_DISABLE (1 << 15) 336 #define CMU_EN_PLLMCU_DISABLE (1 << 16) 337 #define CMU_PU_PLLMCU_DISABLE (1 << 17) 338 #define CMU_EN_PLLA7_DISABLE (1 << 18) 339 #define CMU_PU_PLLA7_DISABLE (1 << 19) 340 341 // reg_068 342 #define CMU_ADMA_CH15_REQ_IDX(n) (((n) & 0x3F) << 0) 343 #define CMU_ADMA_CH15_REQ_IDX_MASK (0x3F << 0) 344 #define CMU_ADMA_CH15_REQ_IDX_SHIFT (0) 345 346 // reg_06c 347 #define CMU_ROM_EMA(n) (((n) & 0x7) << 0) 348 #define CMU_ROM_EMA_MASK (0x7 << 0) 349 #define CMU_ROM_EMA_SHIFT (0) 350 #define CMU_ROM_KEN (1 << 3) 351 #define CMU_ROM_PGEN(n) (((n) & 0x3) << 4) 352 #define CMU_ROM_PGEN_MASK (0x3 << 4) 353 #define CMU_ROM_PGEN_SHIFT (4) 354 #define CMU_RAM_EMA(n) (((n) & 0x7) << 6) 355 #define CMU_RAM_EMA_MASK (0x7 << 6) 356 #define CMU_RAM_EMA_SHIFT (6) 357 #define CMU_RAM_EMAW(n) (((n) & 0x3) << 9) 358 #define CMU_RAM_EMAW_MASK (0x3 << 9) 359 #define CMU_RAM_EMAW_SHIFT (9) 360 #define CMU_RAM_EMAS (1 << 11) 361 #define CMU_RAM_WABL (1 << 12) 362 #define CMU_RAM_WABLM(n) (((n) & 0x3) << 13) 363 #define CMU_RAM_WABLM_MASK (0x3 << 13) 364 #define CMU_RAM_WABLM_SHIFT (13) 365 #define CMU_RAM_RAWL (1 << 15) 366 #define CMU_RAM_RAWLM(n) (((n) & 0x3) << 16) 367 #define CMU_RAM_RAWLM_MASK (0x3 << 16) 368 #define CMU_RAM_RAWLM_SHIFT (16) 369 #define CMU_RF_EMA(n) (((n) & 0x7) << 18) 370 #define CMU_RF_EMA_MASK (0x7 << 18) 371 #define CMU_RF_EMA_SHIFT (18) 372 #define CMU_RF_EMAW(n) (((n) & 0x3) << 21) 373 #define CMU_RF_EMAW_MASK (0x3 << 21) 374 #define CMU_RF_EMAW_SHIFT (21) 375 #define CMU_RF_EMAS (1 << 23) 376 #define CMU_RF_WABL (1 << 24) 377 #define CMU_RF_WABLM(n) (((n) & 0x3) << 25) 378 #define CMU_RF_WABLM_MASK (0x3 << 25) 379 #define CMU_RF_WABLM_SHIFT (25) 380 #define CMU_RF_RAWL (1 << 27) 381 #define CMU_RF_RAWLM(n) (((n) & 0x3) << 28) 382 #define CMU_RF_RAWLM_MASK (0x3 << 28) 383 #define CMU_RF_RAWLM_SHIFT (28) 384 385 // reg_070 386 #define CMU_CFG_DIV_UART0(n) (((n) & 0x1F) << 0) 387 #define CMU_CFG_DIV_UART0_MASK (0x1F << 0) 388 #define CMU_CFG_DIV_UART0_SHIFT (0) 389 #define CMU_SEL_OSCX2_UART0 (1 << 5) 390 #define CMU_SEL_PLL_UART0 (1 << 6) 391 #define CMU_EN_PLL_UART0 (1 << 7) 392 #define CMU_CFG_DIV_UART1(n) (((n) & 0x1F) << 8) 393 #define CMU_CFG_DIV_UART1_MASK (0x1F << 8) 394 #define CMU_CFG_DIV_UART1_SHIFT (8) 395 #define CMU_SEL_OSCX2_UART1 (1 << 13) 396 #define CMU_SEL_PLL_UART1 (1 << 14) 397 #define CMU_EN_PLL_UART1 (1 << 15) 398 #define CMU_CFG_DIV_UART2(n) (((n) & 0x1F) << 16) 399 #define CMU_CFG_DIV_UART2_MASK (0x1F << 16) 400 #define CMU_CFG_DIV_UART2_SHIFT (16) 401 #define CMU_SEL_OSCX2_UART2 (1 << 21) 402 #define CMU_SEL_PLL_UART2 (1 << 22) 403 #define CMU_EN_PLL_UART2 (1 << 23) 404 #define CMU_CFG_DIV_UART3(n) (((n) & 0x1F) << 24) 405 #define CMU_CFG_DIV_UART3_MASK (0x1F << 24) 406 #define CMU_CFG_DIV_UART3_SHIFT (24) 407 #define CMU_SEL_OSCX2_UART3 (1 << 29) 408 #define CMU_SEL_PLL_UART3 (1 << 30) 409 #define CMU_EN_PLL_UART3 (1 << 31) 410 411 // reg_074 412 #define CMU_CFG_DIV_I2C(n) (((n) & 0xFF) << 0) 413 #define CMU_CFG_DIV_I2C_MASK (0xFF << 0) 414 #define CMU_CFG_DIV_I2C_SHIFT (0) 415 #define CMU_SEL_OSC_I2C (1 << 8) 416 #define CMU_SEL_OSCX2_I2C (1 << 9) 417 #define CMU_SEL_PLL_I2C (1 << 10) 418 #define CMU_EN_PLL_I2C (1 << 11) 419 #define CMU_POL_CLK_PCM_IN (1 << 12) 420 #define CMU_SEL_PCM_CLKIN (1 << 13) 421 #define CMU_EN_CLK_PCM_OUT (1 << 14) 422 #define CMU_POL_CLK_PCM_OUT (1 << 15) 423 #define CMU_POL_CLK_I2S0_IN (1 << 16) 424 #define CMU_SEL_I2S0_CLKIN (1 << 17) 425 #define CMU_EN_CLK_I2S0_OUT (1 << 18) 426 #define CMU_POL_CLK_I2S0_OUT (1 << 19) 427 #define CMU_FORCE_PU_OFF (1 << 20) 428 #define CMU_LOCK_CPU_EN (1 << 21) 429 #define CMU_SEL_ROM_FAST (1 << 22) 430 #define CMU_POL_CLK_I2S1_IN (1 << 23) 431 #define CMU_SEL_I2S1_CLKIN (1 << 24) 432 #define CMU_EN_CLK_I2S1_OUT (1 << 25) 433 #define CMU_POL_CLK_I2S1_OUT (1 << 26) 434 #define CMU_SEL_OSC_2_UART0 (1 << 27) 435 #define CMU_SEL_OSC_2_UART1 (1 << 28) 436 #define CMU_SEL_OSC_2_UART2 (1 << 29) 437 #define CMU_SEL_OSC_2_UART3 (1 << 30) 438 #define CMU_SEL_OSC_2_SPI1 (1 << 31) 439 440 // reg_078 441 #define CMU_RAM_RET1N0(n) (((n) & 0xFFFFFFFF) << 0) 442 #define CMU_RAM_RET1N0_MASK (0xFFFFFFFF << 0) 443 #define CMU_RAM_RET1N0_SHIFT (0) 444 445 // reg_07c 446 #define CMU_RAM_RET1N1(n) (((n) & 0xFFFFFFFF) << 0) 447 #define CMU_RAM_RET1N1_MASK (0xFFFFFFFF << 0) 448 #define CMU_RAM_RET1N1_SHIFT (0) 449 450 // reg_080 451 #define CMU_WRITE_UNLOCK_H (1 << 0) 452 #define CMU_WRITE_UNLOCK_STATUS (1 << 1) 453 454 // reg_084 455 #define CMU_WAKEUP_IRQ_MASK0(n) (((n) & 0xFFFFFFFF) << 0) 456 #define CMU_WAKEUP_IRQ_MASK0_MASK (0xFFFFFFFF << 0) 457 #define CMU_WAKEUP_IRQ_MASK0_SHIFT (0) 458 459 // reg_088 460 #define CMU_WAKEUP_IRQ_MASK1(n) (((n) & 0xFFFFFFFF) << 0) 461 #define CMU_WAKEUP_IRQ_MASK1_MASK (0xFFFFFFFF << 0) 462 #define CMU_WAKEUP_IRQ_MASK1_SHIFT (0) 463 464 // reg_08c 465 #define CMU_TIMER_WT26(n) (((n) & 0xFF) << 0) 466 #define CMU_TIMER_WT26_MASK (0xFF << 0) 467 #define CMU_TIMER_WT26_SHIFT (0) 468 #define CMU_TIMER_WTPLL(n) (((n) & 0xF) << 8) 469 #define CMU_TIMER_WTPLL_MASK (0xF << 8) 470 #define CMU_TIMER_WTPLL_SHIFT (8) 471 #define CMU_LPU_AUTO_SWITCH26 (1 << 12) 472 #define CMU_LPU_AUTO_SWITCHPLL (1 << 13) 473 #define CMU_LPU_STATUS_26M (1 << 14) 474 #define CMU_LPU_STATUS_PLL (1 << 15) 475 #define CMU_LPU_EN_MCU (1 << 16) 476 #define CMU_LPU_EN_A7 (1 << 17) 477 #define CMU_OSC_READY_MODE (1 << 18) 478 #define CMU_CFG_SRAM_IN_M33(n) (((n) & 0x1FF) << 19) 479 #define CMU_CFG_SRAM_IN_M33_MASK (0x1FF << 19) 480 #define CMU_CFG_SRAM_IN_M33_SHIFT (19) 481 482 // reg_090 483 #define CMU_CFG_DIV_TIMER10(n) (((n) & 0xFFFF) << 0) 484 #define CMU_CFG_DIV_TIMER10_MASK (0xFFFF << 0) 485 #define CMU_CFG_DIV_TIMER10_SHIFT (0) 486 #define CMU_CFG_DIV_TIMER11(n) (((n) & 0xFFFF) << 16) 487 #define CMU_CFG_DIV_TIMER11_MASK (0xFFFF << 16) 488 #define CMU_CFG_DIV_TIMER11_SHIFT (16) 489 490 // reg_094 491 #define CMU_CFG_DIV_TIMER20(n) (((n) & 0xFFFF) << 0) 492 #define CMU_CFG_DIV_TIMER20_MASK (0xFFFF << 0) 493 #define CMU_CFG_DIV_TIMER20_SHIFT (0) 494 #define CMU_CFG_DIV_TIMER21(n) (((n) & 0xFFFF) << 16) 495 #define CMU_CFG_DIV_TIMER21_MASK (0xFFFF << 16) 496 #define CMU_CFG_DIV_TIMER21_SHIFT (16) 497 498 // reg_098 499 #define CMU_MCU2CP_DATA_DONE_SET (1 << 0) 500 #define CMU_MCU2CP_DATA1_DONE_SET (1 << 1) 501 #define CMU_MCU2CP_DATA2_DONE_SET (1 << 2) 502 #define CMU_MCU2CP_DATA3_DONE_SET (1 << 3) 503 #define CMU_CP2MCU_DATA_IND_SET (1 << 4) 504 #define CMU_CP2MCU_DATA1_IND_SET (1 << 5) 505 #define CMU_CP2MCU_DATA2_IND_SET (1 << 6) 506 #define CMU_CP2MCU_DATA3_IND_SET (1 << 7) 507 508 // reg_09c 509 #define CMU_MCU2CP_DATA_DONE_CLR (1 << 0) 510 #define CMU_MCU2CP_DATA1_DONE_CLR (1 << 1) 511 #define CMU_MCU2CP_DATA2_DONE_CLR (1 << 2) 512 #define CMU_MCU2CP_DATA3_DONE_CLR (1 << 3) 513 #define CMU_CP2MCU_DATA_IND_CLR (1 << 4) 514 #define CMU_CP2MCU_DATA1_IND_CLR (1 << 5) 515 #define CMU_CP2MCU_DATA2_IND_CLR (1 << 6) 516 #define CMU_CP2MCU_DATA3_IND_CLR (1 << 7) 517 518 // reg_0a0 519 #define CMU_BT2MCU_DATA_DONE_SET (1 << 0) 520 #define CMU_BT2MCU_DATA1_DONE_SET (1 << 1) 521 #define CMU_MCU2BT_DATA_IND_SET (1 << 2) 522 #define CMU_MCU2BT_DATA1_IND_SET (1 << 3) 523 #define CMU_BT_ALLIRQ_MASK_SET (1 << 4) 524 #define CMU_BT_PLAYTIME_STAMP_INTR (1 << 5) 525 #define CMU_BT_PLAYTIME_STAMP1_INTR (1 << 6) 526 #define CMU_BT_PLAYTIME_STAMP2_INTR (1 << 7) 527 #define CMU_BT_PLAYTIME_STAMP3_INTR (1 << 8) 528 #define CMU_BT_PLAYTIME_STAMP_INTR_MSK (1 << 9) 529 #define CMU_BT_PLAYTIME_STAMP1_INTR_MSK (1 << 10) 530 #define CMU_BT_PLAYTIME_STAMP2_INTR_MSK (1 << 11) 531 #define CMU_BT_PLAYTIME_STAMP3_INTR_MSK (1 << 12) 532 #define CMU_BT2MCU_DATA_MSK_SET (1 << 13) 533 #define CMU_BT2MCU_DATA1_MSK_SET (1 << 14) 534 #define CMU_MCU2BT_DATA_MSK_SET (1 << 15) 535 #define CMU_MCU2BT_DATA1_MSK_SET (1 << 16) 536 #define CMU_BT2MCU_DATA_INTR (1 << 17) 537 #define CMU_BT2MCU_DATA1_INTR (1 << 18) 538 #define CMU_MCU2BT_DATA_INTR (1 << 19) 539 #define CMU_MCU2BT_DATA1_INTR (1 << 20) 540 #define CMU_BT2MCU_DATA_INTR_MSK (1 << 21) 541 #define CMU_BT2MCU_DATA1_INTR_MSK (1 << 22) 542 #define CMU_MCU2BT_DATA_INTR_MSK (1 << 23) 543 #define CMU_MCU2BT_DATA1_INTR_MSK (1 << 24) 544 545 // reg_0a4 546 #define CMU_BT2MCU_DATA_DONE_CLR (1 << 0) 547 #define CMU_BT2MCU_DATA1_DONE_CLR (1 << 1) 548 #define CMU_MCU2BT_DATA_IND_CLR (1 << 2) 549 #define CMU_MCU2BT_DATA1_IND_CLR (1 << 3) 550 #define CMU_BT_ALLIRQ_MASK_CLR (1 << 4) 551 #define CMU_BT_PLAYTIME_STAMP_INTR_CLR (1 << 5) 552 #define CMU_BT_PLAYTIME_STAMP1_INTR_CLR (1 << 6) 553 #define CMU_BT_PLAYTIME_STAMP2_INTR_CLR (1 << 7) 554 #define CMU_BT_PLAYTIME_STAMP3_INTR_CLR (1 << 8) 555 #define CMU_BT2MCU_DATA_MSK_CLR (1 << 13) 556 #define CMU_BT2MCU_DATA1_MSK_CLR (1 << 14) 557 #define CMU_MCU2BT_DATA_MSK_CLR (1 << 15) 558 #define CMU_MCU2BT_DATA1_MSK_CLR (1 << 16) 559 560 // reg_0a8 561 #define CMU_CFG_DIV_MCU(n) (((n) & 0x3) << 0) 562 #define CMU_CFG_DIV_MCU_MASK (0x3 << 0) 563 #define CMU_CFG_DIV_MCU_SHIFT (0) 564 #define CMU_SEL_SMP_MCU(n) (((n) & 0x7) << 2) 565 #define CMU_SEL_SMP_MCU_MASK (0x7 << 2) 566 #define CMU_SEL_SMP_MCU_SHIFT (2) 567 #define CMU_SEL_USB_6M (1 << 5) 568 #define CMU_SEL_USB_SRC(n) (((n) & 0x7) << 6) 569 #define CMU_SEL_USB_SRC_MASK (0x7 << 6) 570 #define CMU_SEL_USB_SRC_SHIFT (6) 571 #define CMU_POL_CLK_USB (1 << 9) 572 #define CMU_USB_ID (1 << 10) 573 #define CMU_CFG_DIV_PCLK(n) (((n) & 0x3) << 11) 574 #define CMU_CFG_DIV_PCLK_MASK (0x3 << 11) 575 #define CMU_CFG_DIV_PCLK_SHIFT (11) 576 #define CMU_CFG_DIV_SPI0(n) (((n) & 0xF) << 13) 577 #define CMU_CFG_DIV_SPI0_MASK (0xF << 13) 578 #define CMU_CFG_DIV_SPI0_SHIFT (13) 579 #define CMU_SEL_OSCX2_SPI0 (1 << 17) 580 #define CMU_SEL_PLL_SPI0 (1 << 18) 581 #define CMU_EN_PLL_SPI0 (1 << 19) 582 #define CMU_CFG_DIV_SPI1(n) (((n) & 0xF) << 20) 583 #define CMU_CFG_DIV_SPI1_MASK (0xF << 20) 584 #define CMU_CFG_DIV_SPI1_SHIFT (20) 585 #define CMU_SEL_OSCX2_SPI1 (1 << 24) 586 #define CMU_SEL_PLL_SPI1 (1 << 25) 587 #define CMU_EN_PLL_SPI1 (1 << 26) 588 #define CMU_SEL_OSCX2_SPI2 (1 << 27) 589 #define CMU_DSD_PCM_DMAREQ_SEL (1 << 28) 590 591 // reg_0ac 592 #define CMU_DMA_HANDSHAKE_SWAP(n) (((n) & 0xFFFF) << 0) 593 #define CMU_DMA_HANDSHAKE_SWAP_MASK (0xFFFF << 0) 594 #define CMU_DMA_HANDSHAKE_SWAP_SHIFT (0) 595 #define CMU_RESERVED_2(n) (((n) & 0xFFFF) << 16) 596 #define CMU_RESERVED_2_MASK (0xFFFF << 16) 597 #define CMU_RESERVED_2_SHIFT (16) 598 599 // reg_0b0 600 #define CMU_MCU2BT_INTISR_MASK0(n) (((n) & 0xFFFFFFFF) << 0) 601 #define CMU_MCU2BT_INTISR_MASK0_MASK (0xFFFFFFFF << 0) 602 #define CMU_MCU2BT_INTISR_MASK0_SHIFT (0) 603 604 // reg_0b4 605 #define CMU_MCU2BT_INTISR_MASK1(n) (((n) & 0xFFFFFFFF) << 0) 606 #define CMU_MCU2BT_INTISR_MASK1_MASK (0xFFFFFFFF << 0) 607 #define CMU_MCU2BT_INTISR_MASK1_SHIFT (0) 608 609 // reg_0b8 610 #define CMU_CP2MCU_DATA_DONE_SET (1 << 0) 611 #define CMU_CP2MCU_DATA1_DONE_SET (1 << 1) 612 #define CMU_CP2MCU_DATA2_DONE_SET (1 << 2) 613 #define CMU_CP2MCU_DATA3_DONE_SET (1 << 3) 614 #define CMU_MCU2CP_DATA_IND_SET (1 << 4) 615 #define CMU_MCU2CP_DATA1_IND_SET (1 << 5) 616 #define CMU_MCU2CP_DATA2_IND_SET (1 << 6) 617 #define CMU_MCU2CP_DATA3_IND_SET (1 << 7) 618 619 // reg_0bc 620 #define CMU_CP2MCU_DATA_DONE_CLR (1 << 0) 621 #define CMU_CP2MCU_DATA1_DONE_CLR (1 << 1) 622 #define CMU_CP2MCU_DATA2_DONE_CLR (1 << 2) 623 #define CMU_CP2MCU_DATA3_DONE_CLR (1 << 3) 624 #define CMU_MCU2CP_DATA_IND_CLR (1 << 4) 625 #define CMU_MCU2CP_DATA1_IND_CLR (1 << 5) 626 #define CMU_MCU2CP_DATA2_IND_CLR (1 << 6) 627 #define CMU_MCU2CP_DATA3_IND_CLR (1 << 7) 628 629 // reg_0c0 630 #define CMU_MEMSC0 (1 << 0) 631 632 // reg_0c4 633 #define CMU_MEMSC1 (1 << 0) 634 635 // reg_0c8 636 #define CMU_MEMSC2 (1 << 0) 637 638 // reg_0cc 639 #define CMU_MEMSC3 (1 << 0) 640 641 // reg_0d0 642 #define CMU_MEMSC_STATUS0 (1 << 0) 643 #define CMU_MEMSC_STATUS1 (1 << 1) 644 #define CMU_MEMSC_STATUS2 (1 << 2) 645 #define CMU_MEMSC_STATUS3 (1 << 3) 646 #define CMU_MEMSC_STATUS4 (1 << 4) 647 #define CMU_MEMSC_STATUS5 (1 << 5) 648 #define CMU_MEMSC_STATUS6 (1 << 6) 649 #define CMU_MEMSC_STATUS7 (1 << 7) 650 #define CMU_MEMSC_STATUS8 (1 << 8) 651 #define CMU_MEMSC_STATUS9 (1 << 9) 652 #define CMU_MEMSC_STATUS10 (1 << 10) 653 #define CMU_MEMSC_STATUS11 (1 << 11) 654 #define CMU_MEMSC_STATUS12 (1 << 12) 655 #define CMU_MEMSC_STATUS13 (1 << 13) 656 #define CMU_MEMSC_STATUS14 (1 << 14) 657 #define CMU_MEMSC_STATUS15 (1 << 15) 658 #define CMU_MEMSC_STATUS16 (1 << 16) 659 #define CMU_MEMSC_STATUS17 (1 << 17) 660 #define CMU_MEMSC_STATUS18 (1 << 18) 661 #define CMU_MEMSC_STATUS19 (1 << 19) 662 #define CMU_MEMSC_STATUS20 (1 << 20) 663 #define CMU_MEMSC_STATUS21 (1 << 21) 664 #define CMU_MEMSC_STATUS22 (1 << 22) 665 #define CMU_MEMSC_STATUS23 (1 << 23) 666 #define CMU_MEMSC_STATUS24 (1 << 24) 667 #define CMU_MEMSC_STATUS25 (1 << 25) 668 #define CMU_MEMSC_STATUS26 (1 << 26) 669 #define CMU_MEMSC_STATUS27 (1 << 27) 670 #define CMU_MEMSC_STATUS28 (1 << 28) 671 #define CMU_MEMSC_STATUS29 (1 << 29) 672 #define CMU_MEMSC_STATUS30 (1 << 30) 673 #define CMU_MEMSC_STATUS31 (1 << 31) 674 675 // reg_0d4 676 #define CMU_ADMA_CH0_REQ_IDX(n) (((n) & 0x3F) << 0) 677 #define CMU_ADMA_CH0_REQ_IDX_MASK (0x3F << 0) 678 #define CMU_ADMA_CH0_REQ_IDX_SHIFT (0) 679 #define CMU_ADMA_CH1_REQ_IDX(n) (((n) & 0x3F) << 6) 680 #define CMU_ADMA_CH1_REQ_IDX_MASK (0x3F << 6) 681 #define CMU_ADMA_CH1_REQ_IDX_SHIFT (6) 682 #define CMU_ADMA_CH2_REQ_IDX(n) (((n) & 0x3F) << 12) 683 #define CMU_ADMA_CH2_REQ_IDX_MASK (0x3F << 12) 684 #define CMU_ADMA_CH2_REQ_IDX_SHIFT (12) 685 #define CMU_ADMA_CH3_REQ_IDX(n) (((n) & 0x3F) << 18) 686 #define CMU_ADMA_CH3_REQ_IDX_MASK (0x3F << 18) 687 #define CMU_ADMA_CH3_REQ_IDX_SHIFT (18) 688 #define CMU_ADMA_CH4_REQ_IDX(n) (((n) & 0x3F) << 24) 689 #define CMU_ADMA_CH4_REQ_IDX_MASK (0x3F << 24) 690 #define CMU_ADMA_CH4_REQ_IDX_SHIFT (24) 691 692 // reg_0d8 693 #define CMU_ADMA_CH5_REQ_IDX(n) (((n) & 0x3F) << 0) 694 #define CMU_ADMA_CH5_REQ_IDX_MASK (0x3F << 0) 695 #define CMU_ADMA_CH5_REQ_IDX_SHIFT (0) 696 #define CMU_ADMA_CH6_REQ_IDX(n) (((n) & 0x3F) << 6) 697 #define CMU_ADMA_CH6_REQ_IDX_MASK (0x3F << 6) 698 #define CMU_ADMA_CH6_REQ_IDX_SHIFT (6) 699 #define CMU_ADMA_CH7_REQ_IDX(n) (((n) & 0x3F) << 12) 700 #define CMU_ADMA_CH7_REQ_IDX_MASK (0x3F << 12) 701 #define CMU_ADMA_CH7_REQ_IDX_SHIFT (12) 702 #define CMU_ADMA_CH8_REQ_IDX(n) (((n) & 0x3F) << 18) 703 #define CMU_ADMA_CH8_REQ_IDX_MASK (0x3F << 18) 704 #define CMU_ADMA_CH8_REQ_IDX_SHIFT (18) 705 #define CMU_ADMA_CH9_REQ_IDX(n) (((n) & 0x3F) << 24) 706 #define CMU_ADMA_CH9_REQ_IDX_MASK (0x3F << 24) 707 #define CMU_ADMA_CH9_REQ_IDX_SHIFT (24) 708 709 // reg_0dc 710 #define CMU_ADMA_CH10_REQ_IDX(n) (((n) & 0x3F) << 0) 711 #define CMU_ADMA_CH10_REQ_IDX_MASK (0x3F << 0) 712 #define CMU_ADMA_CH10_REQ_IDX_SHIFT (0) 713 #define CMU_ADMA_CH11_REQ_IDX(n) (((n) & 0x3F) << 6) 714 #define CMU_ADMA_CH11_REQ_IDX_MASK (0x3F << 6) 715 #define CMU_ADMA_CH11_REQ_IDX_SHIFT (6) 716 #define CMU_ADMA_CH12_REQ_IDX(n) (((n) & 0x3F) << 12) 717 #define CMU_ADMA_CH12_REQ_IDX_MASK (0x3F << 12) 718 #define CMU_ADMA_CH12_REQ_IDX_SHIFT (12) 719 #define CMU_ADMA_CH13_REQ_IDX(n) (((n) & 0x3F) << 18) 720 #define CMU_ADMA_CH13_REQ_IDX_MASK (0x3F << 18) 721 #define CMU_ADMA_CH13_REQ_IDX_SHIFT (18) 722 #define CMU_ADMA_CH14_REQ_IDX(n) (((n) & 0x3F) << 24) 723 #define CMU_ADMA_CH14_REQ_IDX_MASK (0x3F << 24) 724 #define CMU_ADMA_CH14_REQ_IDX_SHIFT (24) 725 726 // reg_0e0 727 #define CMU_GDMA_CH0_REQ_IDX(n) (((n) & 0x3F) << 0) 728 #define CMU_GDMA_CH0_REQ_IDX_MASK (0x3F << 0) 729 #define CMU_GDMA_CH0_REQ_IDX_SHIFT (0) 730 #define CMU_GDMA_CH1_REQ_IDX(n) (((n) & 0x3F) << 6) 731 #define CMU_GDMA_CH1_REQ_IDX_MASK (0x3F << 6) 732 #define CMU_GDMA_CH1_REQ_IDX_SHIFT (6) 733 #define CMU_GDMA_CH2_REQ_IDX(n) (((n) & 0x3F) << 12) 734 #define CMU_GDMA_CH2_REQ_IDX_MASK (0x3F << 12) 735 #define CMU_GDMA_CH2_REQ_IDX_SHIFT (12) 736 #define CMU_GDMA_CH3_REQ_IDX(n) (((n) & 0x3F) << 18) 737 #define CMU_GDMA_CH3_REQ_IDX_MASK (0x3F << 18) 738 #define CMU_GDMA_CH3_REQ_IDX_SHIFT (18) 739 #define CMU_GDMA_CH4_REQ_IDX(n) (((n) & 0x3F) << 24) 740 #define CMU_GDMA_CH4_REQ_IDX_MASK (0x3F << 24) 741 #define CMU_GDMA_CH4_REQ_IDX_SHIFT (24) 742 743 // reg_0e4 744 #define CMU_GDMA_CH5_REQ_IDX(n) (((n) & 0x3F) << 0) 745 #define CMU_GDMA_CH5_REQ_IDX_MASK (0x3F << 0) 746 #define CMU_GDMA_CH5_REQ_IDX_SHIFT (0) 747 #define CMU_GDMA_CH6_REQ_IDX(n) (((n) & 0x3F) << 6) 748 #define CMU_GDMA_CH6_REQ_IDX_MASK (0x3F << 6) 749 #define CMU_GDMA_CH6_REQ_IDX_SHIFT (6) 750 #define CMU_GDMA_CH7_REQ_IDX(n) (((n) & 0x3F) << 12) 751 #define CMU_GDMA_CH7_REQ_IDX_MASK (0x3F << 12) 752 #define CMU_GDMA_CH7_REQ_IDX_SHIFT (12) 753 #define CMU_GDMA_CH8_REQ_IDX(n) (((n) & 0x3F) << 18) 754 #define CMU_GDMA_CH8_REQ_IDX_MASK (0x3F << 18) 755 #define CMU_GDMA_CH8_REQ_IDX_SHIFT (18) 756 #define CMU_GDMA_CH9_REQ_IDX(n) (((n) & 0x3F) << 24) 757 #define CMU_GDMA_CH9_REQ_IDX_MASK (0x3F << 24) 758 #define CMU_GDMA_CH9_REQ_IDX_SHIFT (24) 759 760 // reg_0e8 761 #define CMU_GDMA_CH10_REQ_IDX(n) (((n) & 0x3F) << 0) 762 #define CMU_GDMA_CH10_REQ_IDX_MASK (0x3F << 0) 763 #define CMU_GDMA_CH10_REQ_IDX_SHIFT (0) 764 #define CMU_GDMA_CH11_REQ_IDX(n) (((n) & 0x3F) << 6) 765 #define CMU_GDMA_CH11_REQ_IDX_MASK (0x3F << 6) 766 #define CMU_GDMA_CH11_REQ_IDX_SHIFT (6) 767 #define CMU_GDMA_CH12_REQ_IDX(n) (((n) & 0x3F) << 12) 768 #define CMU_GDMA_CH12_REQ_IDX_MASK (0x3F << 12) 769 #define CMU_GDMA_CH12_REQ_IDX_SHIFT (12) 770 #define CMU_GDMA_CH13_REQ_IDX(n) (((n) & 0x3F) << 18) 771 #define CMU_GDMA_CH13_REQ_IDX_MASK (0x3F << 18) 772 #define CMU_GDMA_CH13_REQ_IDX_SHIFT (18) 773 #define CMU_GDMA_CH14_REQ_IDX(n) (((n) & 0x3F) << 24) 774 #define CMU_GDMA_CH14_REQ_IDX_MASK (0x3F << 24) 775 #define CMU_GDMA_CH14_REQ_IDX_SHIFT (24) 776 777 // reg_0ec 778 #define CMU_GDMA_CH15_REQ_IDX(n) (((n) & 0x3F) << 0) 779 #define CMU_GDMA_CH15_REQ_IDX_MASK (0x3F << 0) 780 #define CMU_GDMA_CH15_REQ_IDX_SHIFT (0) 781 782 // reg_0f0 783 #define CMU_RESERVED(n) (((n) & 0xFFFFFFFF) << 0) 784 #define CMU_RESERVED_MASK (0xFFFFFFFF << 0) 785 #define CMU_RESERVED_SHIFT (0) 786 787 // reg_0f4 788 #define CMU_DEBUG(n) (((n) & 0xFFFFFFFF) << 0) 789 #define CMU_DEBUG_MASK (0xFFFFFFFF << 0) 790 #define CMU_DEBUG_SHIFT (0) 791 792 // reg_0f8 793 #define CMU_SEC_ROM_STR_ADDR(n) (((n) & 0xFFFF) << 0) 794 #define CMU_SEC_ROM_STR_ADDR_MASK (0xFFFF << 0) 795 #define CMU_SEC_ROM_STR_ADDR_SHIFT (0) 796 #define CMU_SEC_ROM_END_ADDR(n) (((n) & 0xFFFF) << 16) 797 #define CMU_SEC_ROM_END_ADDR_MASK (0xFFFF << 16) 798 #define CMU_SEC_ROM_END_ADDR_SHIFT (16) 799 800 // reg_0fc 801 #define CMU_CPU_ACC_RAM_EN (1 << 0) 802 #define CMU_BCM_ACC_RAM_EN (1 << 1) 803 #define CMU_NONSEC_ACC_RAM_EN (1 << 2) 804 #define CMU_JTAG_ACC_RAM_EN (1 << 3) 805 #define CMU_JTAG_ACC_SECROM_EN (1 << 4) 806 #define CMU_DCODE_ACC_SECROM_EN (1 << 5) 807 #define CMU_SRAM0_ACC_REFUSE (1 << 6) 808 809 // reg_100 810 #define CMU_VTOR_CORE1(n) (((n) & 0x1FFFFFF) << 7) 811 #define CMU_VTOR_CORE1_MASK (0x1FFFFFF << 7) 812 #define CMU_VTOR_CORE1_SHIFT (7) 813 814 // reg_104 815 #define CMU_MANUAL_XCLK_ENABLE(n) (((n) & 0xFFFFFFFF) << 0) 816 #define CMU_MANUAL_XCLK_ENABLE_MASK (0xFFFFFFFF << 0) 817 #define CMU_MANUAL_XCLK_ENABLE_SHIFT (0) 818 819 // reg_108 820 #define CMU_MANUAL_XCLK_DISABLE(n) (((n) & 0xFFFFFFFF) << 0) 821 #define CMU_MANUAL_XCLK_DISABLE_MASK (0xFFFFFFFF << 0) 822 #define CMU_MANUAL_XCLK_DISABLE_SHIFT (0) 823 824 // reg_10c 825 #define CMU_MODE_XCLK(n) (((n) & 0xFFFFFFFF) << 0) 826 #define CMU_MODE_XCLK_MASK (0xFFFFFFFF << 0) 827 #define CMU_MODE_XCLK_SHIFT (0) 828 829 // reg_110 830 #define CMU_XRESETN_PULSE(n) (((n) & 0xFFFFFFFF) << 0) 831 #define CMU_XRESETN_PULSE_MASK (0xFFFFFFFF << 0) 832 #define CMU_XRESETN_PULSE_SHIFT (0) 833 834 // reg_114 835 #define CMU_XRESETN_SET(n) (((n) & 0xFFFFFFFF) << 0) 836 #define CMU_XRESETN_SET_MASK (0xFFFFFFFF << 0) 837 #define CMU_XRESETN_SET_SHIFT (0) 838 839 // reg_118 840 #define CMU_XRESETN_CLR(n) (((n) & 0xFFFFFFFF) << 0) 841 #define CMU_XRESETN_CLR_MASK (0xFFFFFFFF << 0) 842 #define CMU_XRESETN_CLR_SHIFT (0) 843 844 // reg_11c 845 #define CMU_CFG_DIV_A7(n) (((n) & 0x3) << 0) 846 #define CMU_CFG_DIV_A7_MASK (0x3 << 0) 847 #define CMU_CFG_DIV_A7_SHIFT (0) 848 #define CMU_CFG_DIV_XCLK(n) (((n) & 0x3) << 2) 849 #define CMU_CFG_DIV_XCLK_MASK (0x3 << 2) 850 #define CMU_CFG_DIV_XCLK_SHIFT (2) 851 #define CMU_CFG_DIV_APCLK(n) (((n) & 0x3) << 4) 852 #define CMU_CFG_DIV_APCLK_MASK (0x3 << 4) 853 #define CMU_CFG_DIV_APCLK_SHIFT (4) 854 #define CMU_SEL_32K_TIMER_AP(n) (((n) & 0x3) << 6) 855 #define CMU_SEL_32K_TIMER_AP_MASK (0x3 << 6) 856 #define CMU_SEL_32K_TIMER_AP_SHIFT (6) 857 #define CMU_SEL_32K_WDT_AP (1 << 8) 858 #define CMU_SEL_TIMER_FAST_AP(n) (((n) & 0x3) << 9) 859 #define CMU_SEL_TIMER_FAST_AP_MASK (0x3 << 9) 860 #define CMU_SEL_TIMER_FAST_AP_SHIFT (9) 861 #define CMU_CFG_DIV_IR(n) (((n) & 0x1F) << 11) 862 #define CMU_CFG_DIV_IR_MASK (0x1F << 11) 863 #define CMU_CFG_DIV_IR_SHIFT (11) 864 #define CMU_SEL_OSCX2_IR (1 << 16) 865 #define CMU_SEL_PLL_IR (1 << 17) 866 #define CMU_EN_PLL_IR (1 << 18) 867 868 // reg_120 869 #define CMU_WAKEUP_IRQ_MASK2(n) (((n) & 0xFF) << 0) 870 #define CMU_WAKEUP_IRQ_MASK2_MASK (0xFF << 0) 871 #define CMU_WAKEUP_IRQ_MASK2_SHIFT (0) 872 873 // reg_124 874 #define CMU_MCU2BT_INTISR_MASK2(n) (((n) & 0xFF) << 0) 875 #define CMU_MCU2BT_INTISR_MASK2_MASK (0xFF << 0) 876 #define CMU_MCU2BT_INTISR_MASK2_SHIFT (0) 877 878 // reg_128 879 #define CMU_MCU2WF_INTISR_MASK0(n) (((n) & 0xFFFFFFFF) << 0) 880 #define CMU_MCU2WF_INTISR_MASK0_MASK (0xFFFFFFFF << 0) 881 #define CMU_MCU2WF_INTISR_MASK0_SHIFT (0) 882 883 // reg_12c 884 #define CMU_MCU2WF_INTISR_MASK1(n) (((n) & 0xFFFFFFFF) << 0) 885 #define CMU_MCU2WF_INTISR_MASK1_MASK (0xFFFFFFFF << 0) 886 #define CMU_MCU2WF_INTISR_MASK1_SHIFT (0) 887 888 // reg_130 889 #define CMU_MCU2WF_INTISR_MASK2(n) (((n) & 0xFF) << 0) 890 #define CMU_MCU2WF_INTISR_MASK2_MASK (0xFF << 0) 891 #define CMU_MCU2WF_INTISR_MASK2_SHIFT (0) 892 893 // reg_134 894 #define CMU_M33TOA7_INTISR_MASK0(n) (((n) & 0xFFFFFFFF) << 0) 895 #define CMU_M33TOA7_INTISR_MASK0_MASK (0xFFFFFFFF << 0) 896 #define CMU_M33TOA7_INTISR_MASK0_SHIFT (0) 897 898 // reg_138 899 #define CMU_M33TOA7_INTISR_MASK1(n) (((n) & 0xFFFFFFFF) << 0) 900 #define CMU_M33TOA7_INTISR_MASK1_MASK (0xFFFFFFFF << 0) 901 #define CMU_M33TOA7_INTISR_MASK1_SHIFT (0) 902 903 // reg_13c 904 #define CMU_M33TOA7_INTISR_MASK2(n) (((n) & 0xFF) << 0) 905 #define CMU_M33TOA7_INTISR_MASK2_MASK (0xFF << 0) 906 #define CMU_M33TOA7_INTISR_MASK2_SHIFT (0) 907 908 // reg_140 909 #define CMU_A7TOM33_IRQS_MASK(n) (((n) & 0xFF) << 0) 910 #define CMU_A7TOM33_IRQS_MASK_MASK (0xFF << 0) 911 #define CMU_A7TOM33_IRQS_MASK_SHIFT (0) 912 #define CMU_CA7_L1RSTDISABLE(n) (((n) & 0x3) << 8) 913 #define CMU_CA7_L1RSTDISABLE_MASK (0x3 << 8) 914 #define CMU_CA7_L1RSTDISABLE_SHIFT (8) 915 #define CMU_CA7_L2RSTDISABLE (1 << 10) 916 #define CMU_CA7_DBGEN(n) (((n) & 0x3) << 11) 917 #define CMU_CA7_DBGEN_MASK (0x3 << 11) 918 #define CMU_CA7_DBGEN_SHIFT (11) 919 #define CMU_CA7_SPIDEN(n) (((n) & 0x3) << 13) 920 #define CMU_CA7_SPIDEN_MASK (0x3 << 13) 921 #define CMU_CA7_SPIDEN_SHIFT (13) 922 #define CMU_CA7_NIDEN(n) (((n) & 0x3) << 15) 923 #define CMU_CA7_NIDEN_MASK (0x3 << 15) 924 #define CMU_CA7_NIDEN_SHIFT (15) 925 #define CMU_CA7_SPNIDEN(n) (((n) & 0x3) << 17) 926 #define CMU_CA7_SPNIDEN_MASK (0x3 << 17) 927 #define CMU_CA7_SPNIDEN_SHIFT (17) 928 #define CMU_CA7_DBGROMADDRV (1 << 19) 929 #define CMU_CA7_DBGSELFADDRV (1 << 20) 930 #define CMU_CA7_DBGRESTART(n) (((n) & 0x3) << 21) 931 #define CMU_CA7_DBGRESTART_MASK (0x3 << 21) 932 #define CMU_CA7_DBGRESTART_SHIFT (21) 933 #define CMU_CA7_CP15SDISABLE(n) (((n) & 0x3) << 23) 934 #define CMU_CA7_CP15SDISABLE_MASK (0x3 << 23) 935 #define CMU_CA7_CP15SDISABLE_SHIFT (23) 936 #define CMU_CA7_TEINIT(n) (((n) & 0x3) << 25) 937 #define CMU_CA7_TEINIT_MASK (0x3 << 25) 938 #define CMU_CA7_TEINIT_SHIFT (25) 939 #define CMU_CA7_CFGSDISABLE (1 << 27) 940 #define CMU_M33TOA7_INTR_MASK_AP (1 << 28) 941 #define CMU_COUNTER_EN_AP (1 << 29) 942 943 // reg_148 944 #define CMU_AWQOS_CA7(n) (((n) & 0xF) << 0) 945 #define CMU_AWQOS_CA7_MASK (0xF << 0) 946 #define CMU_AWQOS_CA7_SHIFT (0) 947 #define CMU_ARQOS_CA7(n) (((n) & 0xF) << 4) 948 #define CMU_ARQOS_CA7_MASK (0xF << 4) 949 #define CMU_ARQOS_CA7_SHIFT (4) 950 #define CMU_AWQOS_DMA_M(n) (((n) & 0xF) << 8) 951 #define CMU_AWQOS_DMA_M_MASK (0xF << 8) 952 #define CMU_AWQOS_DMA_M_SHIFT (8) 953 #define CMU_ARQOS_DMA_M(n) (((n) & 0xF) << 12) 954 #define CMU_ARQOS_DMA_M_MASK (0xF << 12) 955 #define CMU_ARQOS_DMA_M_SHIFT (12) 956 957 // reg_14c 958 #define CMU_XDMA_CHL_SECURE(n) (((n) & 0xFFFF) << 0) 959 #define CMU_XDMA_CHL_SECURE_MASK (0xFFFF << 0) 960 #define CMU_XDMA_CHL_SECURE_SHIFT (0) 961 #define CMU_XDMA_GLOBAL_SECURE_ENABLE (1 << 16) 962 #define CMU_XDMA_ID_TYPE (1 << 17) 963 #define CMU_XDMA_SRAM_CLK_ON (1 << 18) 964 965 // reg_150 966 #define CMU_MANUAL_APCLK_ENABLE(n) (((n) & 0xFFFFFFFF) << 0) 967 #define CMU_MANUAL_APCLK_ENABLE_MASK (0xFFFFFFFF << 0) 968 #define CMU_MANUAL_APCLK_ENABLE_SHIFT (0) 969 970 // reg_154 971 #define CMU_MANUAL_APCLK_DISABLE(n) (((n) & 0xFFFFFFFF) << 0) 972 #define CMU_MANUAL_APCLK_DISABLE_MASK (0xFFFFFFFF << 0) 973 #define CMU_MANUAL_APCLK_DISABLE_SHIFT (0) 974 975 // reg_158 976 #define CMU_MODE_APCLK(n) (((n) & 0xFFFFFFFF) << 0) 977 #define CMU_MODE_APCLK_MASK (0xFFFFFFFF << 0) 978 #define CMU_MODE_APCLK_SHIFT (0) 979 980 // reg_15c 981 #define CMU_APRESETN_PULSE(n) (((n) & 0xFFFFFFFF) << 0) 982 #define CMU_APRESETN_PULSE_MASK (0xFFFFFFFF << 0) 983 #define CMU_APRESETN_PULSE_SHIFT (0) 984 985 // reg_160 986 #define CMU_APRESETN_SET(n) (((n) & 0xFFFFFFFF) << 0) 987 #define CMU_APRESETN_SET_MASK (0xFFFFFFFF << 0) 988 #define CMU_APRESETN_SET_SHIFT (0) 989 990 // reg_164 991 #define CMU_APRESETN_CLR(n) (((n) & 0xFFFFFFFF) << 0) 992 #define CMU_APRESETN_CLR_MASK (0xFFFFFFFF << 0) 993 #define CMU_APRESETN_CLR_SHIFT (0) 994 995 // reg_168 996 #define CMU_CFG_DIV_TIMER00_AP(n) (((n) & 0xFFFF) << 0) 997 #define CMU_CFG_DIV_TIMER00_AP_MASK (0xFFFF << 0) 998 #define CMU_CFG_DIV_TIMER00_AP_SHIFT (0) 999 #define CMU_CFG_DIV_TIMER01_AP(n) (((n) & 0xFFFF) << 16) 1000 #define CMU_CFG_DIV_TIMER01_AP_MASK (0xFFFF << 16) 1001 #define CMU_CFG_DIV_TIMER01_AP_SHIFT (16) 1002 1003 // reg_16c 1004 #define CMU_CFG_DIV_TIMER10_AP(n) (((n) & 0xFFFF) << 0) 1005 #define CMU_CFG_DIV_TIMER10_AP_MASK (0xFFFF << 0) 1006 #define CMU_CFG_DIV_TIMER10_AP_SHIFT (0) 1007 #define CMU_CFG_DIV_TIMER11_AP(n) (((n) & 0xFFFF) << 16) 1008 #define CMU_CFG_DIV_TIMER11_AP_MASK (0xFFFF << 16) 1009 #define CMU_CFG_DIV_TIMER11_AP_SHIFT (16) 1010 1011 // reg_170 1012 #define CMU_RAM_RET2N0(n) (((n) & 0xFFFFFFFF) << 0) 1013 #define CMU_RAM_RET2N0_MASK (0xFFFFFFFF << 0) 1014 #define CMU_RAM_RET2N0_SHIFT (0) 1015 1016 // reg_174 1017 #define CMU_RAM_RET2N1(n) (((n) & 0xFFFFFFFF) << 0) 1018 #define CMU_RAM_RET2N1_MASK (0xFFFFFFFF << 0) 1019 #define CMU_RAM_RET2N1_SHIFT (0) 1020 1021 // reg_178 1022 #define CMU_RAM_PGEN0(n) (((n) & 0xFFFFFFFF) << 0) 1023 #define CMU_RAM_PGEN0_MASK (0xFFFFFFFF << 0) 1024 #define CMU_RAM_PGEN0_SHIFT (0) 1025 1026 // reg_17c 1027 #define CMU_RAM_PGEN1(n) (((n) & 0xFFFFFFFF) << 0) 1028 #define CMU_RAM_PGEN1_MASK (0xFFFFFFFF << 0) 1029 #define CMU_RAM_PGEN1_SHIFT (0) 1030 1031 // reg_180 1032 #define CMU_MEMSC4 (1 << 0) 1033 1034 // reg_184 1035 #define CMU_MEMSC5 (1 << 0) 1036 1037 // reg_188 1038 #define CMU_MEMSC6 (1 << 0) 1039 1040 // reg_18c 1041 #define CMU_MEMSC7 (1 << 0) 1042 1043 // reg_190 1044 #define CMU_MEMSC8 (1 << 0) 1045 1046 // reg_194 1047 #define CMU_MEMSC9 (1 << 0) 1048 1049 // reg_198 1050 #define CMU_MEMSC10 (1 << 0) 1051 1052 // reg_19c 1053 #define CMU_MEMSC11 (1 << 0) 1054 1055 // reg_1a0 1056 #define CMU_MEMSC12 (1 << 0) 1057 1058 // reg_1a4 1059 #define CMU_MEMSC13 (1 << 0) 1060 1061 // reg_1a8 1062 #define CMU_MEMSC14 (1 << 0) 1063 1064 // reg_1ac 1065 #define CMU_MEMSC15 (1 << 0) 1066 1067 // reg_1b0 1068 #define CMU_MEMSC16 (1 << 0) 1069 1070 // reg_1b4 1071 #define CMU_MEMSC17 (1 << 0) 1072 1073 // reg_1b8 1074 #define CMU_MEMSC18 (1 << 0) 1075 1076 // reg_1bc 1077 #define CMU_MEMSC19 (1 << 0) 1078 1079 // reg_1c0 1080 #define CMU_MEMSC20 (1 << 0) 1081 1082 // reg_1c4 1083 #define CMU_MEMSC21 (1 << 0) 1084 1085 // reg_1c8 1086 #define CMU_MEMSC22 (1 << 0) 1087 1088 // reg_1cc 1089 #define CMU_MEMSC23 (1 << 0) 1090 1091 // reg_1d0 1092 #define CMU_MEMSC24 (1 << 0) 1093 1094 // reg_1d4 1095 #define CMU_MEMSC25 (1 << 0) 1096 1097 // reg_1d8 1098 #define CMU_MEMSC26 (1 << 0) 1099 1100 // reg_1dc 1101 #define CMU_MEMSC27 (1 << 0) 1102 1103 // reg_1e0 1104 #define CMU_MEMSC28 (1 << 0) 1105 1106 // reg_1e4 1107 #define CMU_MEMSC29 (1 << 0) 1108 1109 // reg_1e8 1110 #define CMU_MEMSC30 (1 << 0) 1111 1112 // reg_1ec 1113 #define CMU_MEMSC31 (1 << 0) 1114 1115 // reg_1f0 1116 #define CMU_RF2_EMAA(n) (((n) & 0x7) << 0) 1117 #define CMU_RF2_EMAA_MASK (0x7 << 0) 1118 #define CMU_RF2_EMAA_SHIFT (0) 1119 #define CMU_RF2_EMASA (1 << 3) 1120 #define CMU_RF2_EMAB(n) (((n) & 0x7) << 4) 1121 #define CMU_RF2_EMAB_MASK (0x7 << 4) 1122 #define CMU_RF2_EMAB_SHIFT (4) 1123 #define CMU_RAMDP_EMAA(n) (((n) & 0x7) << 7) 1124 #define CMU_RAMDP_EMAA_MASK (0x7 << 7) 1125 #define CMU_RAMDP_EMAA_SHIFT (7) 1126 #define CMU_RAMDP_EMAWA(n) (((n) & 0x3) << 10) 1127 #define CMU_RAMDP_EMAWA_MASK (0x3 << 10) 1128 #define CMU_RAMDP_EMAWA_SHIFT (10) 1129 #define CMU_RAMDP_EMASA (1 << 12) 1130 #define CMU_RAMDP_EMAB(n) (((n) & 0x7) << 13) 1131 #define CMU_RAMDP_EMAB_MASK (0x7 << 13) 1132 #define CMU_RAMDP_EMAB_SHIFT (13) 1133 #define CMU_RAMDP_EMAWB(n) (((n) & 0x3) << 16) 1134 #define CMU_RAMDP_EMAWB_MASK (0x3 << 16) 1135 #define CMU_RAMDP_EMAWB_SHIFT (16) 1136 #define CMU_RAMDP_EMASB (1 << 18) 1137 1138 // reg_1f4 1139 #define CMU_RF_RET1N0(n) (((n) & 0x1F) << 0) 1140 #define CMU_RF_RET1N0_MASK (0x1F << 0) 1141 #define CMU_RF_RET1N0_SHIFT (0) 1142 #define CMU_RF_RET1N1(n) (((n) & 0x1F) << 5) 1143 #define CMU_RF_RET1N1_MASK (0x1F << 5) 1144 #define CMU_RF_RET1N1_SHIFT (5) 1145 #define CMU_RF_RET2N0(n) (((n) & 0x1F) << 10) 1146 #define CMU_RF_RET2N0_MASK (0x1F << 10) 1147 #define CMU_RF_RET2N0_SHIFT (10) 1148 #define CMU_RF_RET2N1(n) (((n) & 0x1F) << 15) 1149 #define CMU_RF_RET2N1_MASK (0x1F << 15) 1150 #define CMU_RF_RET2N1_SHIFT (15) 1151 #define CMU_RF_PGEN0(n) (((n) & 0x1F) << 20) 1152 #define CMU_RF_PGEN0_MASK (0x1F << 20) 1153 #define CMU_RF_PGEN0_SHIFT (20) 1154 #define CMU_RF_PGEN1(n) (((n) & 0x1F) << 25) 1155 #define CMU_RF_PGEN1_MASK (0x1F << 25) 1156 #define CMU_RF_PGEN1_SHIFT (25) 1157 1158 // reg_1f8 1159 #define CMU_RF2_RET1N0(n) (((n) & 0x1F) << 0) 1160 #define CMU_RF2_RET1N0_MASK (0x1F << 0) 1161 #define CMU_RF2_RET1N0_SHIFT (0) 1162 #define CMU_RF2_RET1N1(n) (((n) & 0x1F) << 5) 1163 #define CMU_RF2_RET1N1_MASK (0x1F << 5) 1164 #define CMU_RF2_RET1N1_SHIFT (5) 1165 #define CMU_RF2_RET2N0(n) (((n) & 0x1F) << 10) 1166 #define CMU_RF2_RET2N0_MASK (0x1F << 10) 1167 #define CMU_RF2_RET2N0_SHIFT (10) 1168 #define CMU_RF2_RET2N1(n) (((n) & 0x1F) << 15) 1169 #define CMU_RF2_RET2N1_MASK (0x1F << 15) 1170 #define CMU_RF2_RET2N1_SHIFT (15) 1171 #define CMU_RF2_PGEN0(n) (((n) & 0x1F) << 20) 1172 #define CMU_RF2_PGEN0_MASK (0x1F << 20) 1173 #define CMU_RF2_PGEN0_SHIFT (20) 1174 #define CMU_RF2_PGEN1(n) (((n) & 0x1F) << 25) 1175 #define CMU_RF2_PGEN1_MASK (0x1F << 25) 1176 #define CMU_RF2_PGEN1_SHIFT (25) 1177 1178 // reg_200 1179 #define CMU_MANUAL_QCLK_ENABLE(n) (((n) & 0xFFFFFFFF) << 0) 1180 #define CMU_MANUAL_QCLK_ENABLE_MASK (0xFFFFFFFF << 0) 1181 #define CMU_MANUAL_QCLK_ENABLE_SHIFT (0) 1182 1183 // reg_204 1184 #define CMU_MANUAL_QCLK_DISABLE(n) (((n) & 0xFFFFFFFF) << 0) 1185 #define CMU_MANUAL_QCLK_DISABLE_MASK (0xFFFFFFFF << 0) 1186 #define CMU_MANUAL_QCLK_DISABLE_SHIFT (0) 1187 1188 // reg_208 1189 #define CMU_MODE_QCLK(n) (((n) & 0xFFFFFFFF) << 0) 1190 #define CMU_MODE_QCLK_MASK (0xFFFFFFFF << 0) 1191 #define CMU_MODE_QCLK_SHIFT (0) 1192 1193 // reg_20c 1194 #define CMU_QRESETN_PULSE(n) (((n) & 0xFFFFFFFF) << 0) 1195 #define CMU_QRESETN_PULSE_MASK (0xFFFFFFFF << 0) 1196 #define CMU_QRESETN_PULSE_SHIFT (0) 1197 1198 // reg_210 1199 #define CMU_QRESETN_SET(n) (((n) & 0xFFFFFFFF) << 0) 1200 #define CMU_QRESETN_SET_MASK (0xFFFFFFFF << 0) 1201 #define CMU_QRESETN_SET_SHIFT (0) 1202 1203 // reg_214 1204 #define CMU_QRESETN_CLR(n) (((n) & 0xFFFFFFFF) << 0) 1205 #define CMU_QRESETN_CLR_MASK (0xFFFFFFFF << 0) 1206 #define CMU_QRESETN_CLR_SHIFT (0) 1207 1208 // reg_218 1209 #define CMU_BT_PLAYTIME_STAMP_MASK (1 << 0) 1210 #define CMU_BT_PLAYTIME_STAMP1_MASK (1 << 1) 1211 #define CMU_BT_PLAYTIME_STAMP2_MASK (1 << 2) 1212 #define CMU_BT_PLAYTIME_STAMP3_MASK (1 << 3) 1213 1214 // reg_21c 1215 #define CMU_REMAP(n) (((n) & 0xF) << 0) 1216 #define CMU_REMAP_MASK (0xF << 0) 1217 #define CMU_REMAP_SHIFT (0) 1218 1219 // reg_220 1220 #define CMU_INTISR_CORE0_MSK0(n) (((n) & 0xFFFFFFFF) << 0) 1221 #define CMU_INTISR_CORE0_MSK0_MASK (0xFFFFFFFF << 0) 1222 #define CMU_INTISR_CORE0_MSK0_SHIFT (0) 1223 1224 // reg_224 1225 #define CMU_INTISR_CORE0_MSK1(n) (((n) & 0xFFFFFFFF) << 0) 1226 #define CMU_INTISR_CORE0_MSK1_MASK (0xFFFFFFFF << 0) 1227 #define CMU_INTISR_CORE0_MSK1_SHIFT (0) 1228 1229 // reg_228 1230 #define CMU_INTISR_CORE0_MSK2(n) (((n) & 0xFF) << 0) 1231 #define CMU_INTISR_CORE0_MSK2_MASK (0xFF << 0) 1232 #define CMU_INTISR_CORE0_MSK2_SHIFT (0) 1233 1234 // reg_22c 1235 #define CMU_INTISR_CORE1_MSK0(n) (((n) & 0xFFFFFFFF) << 0) 1236 #define CMU_INTISR_CORE1_MSK0_MASK (0xFFFFFFFF << 0) 1237 #define CMU_INTISR_CORE1_MSK0_SHIFT (0) 1238 1239 // reg_230 1240 #define CMU_INTISR_CORE1_MSK1(n) (((n) & 0xFFFFFFFF) << 0) 1241 #define CMU_INTISR_CORE1_MSK1_MASK (0xFFFFFFFF << 0) 1242 #define CMU_INTISR_CORE1_MSK1_SHIFT (0) 1243 1244 // reg_234 1245 #define CMU_INTISR_CORE1_MSK2(n) (((n) & 0xFF) << 0) 1246 #define CMU_INTISR_CORE1_MSK2_MASK (0xFF << 0) 1247 #define CMU_INTISR_CORE1_MSK2_SHIFT (0) 1248 1249 // MCU System AHB Clocks: 1250 #define SYS_HCLK_CORE0 (1 << 0) 1251 #define SYS_HRST_CORE0 (1 << 0) 1252 #define SYS_HCLK_CACHE0 (1 << 1) 1253 #define SYS_HRST_CACHE0 (1 << 1) 1254 #define SYS_HCLK_CORE1 (1 << 2) 1255 #define SYS_HRST_CORE1 (1 << 2) 1256 #define SYS_HCLK_CACHE1 (1 << 3) 1257 #define SYS_HRST_CACHE1 (1 << 3) 1258 #define SYS_HCLK_ADMA (1 << 4) 1259 #define SYS_HRST_ADMA (1 << 4) 1260 #define SYS_HCLK_GDMA (1 << 5) 1261 #define SYS_HRST_GDMA (1 << 5) 1262 #define SYS_HCLK_BCM (1 << 6) 1263 #define SYS_HRST_BCM (1 << 6) 1264 #define SYS_HCLK_USBC (1 << 7) 1265 #define SYS_HRST_USBC (1 << 7) 1266 #define SYS_HCLK_USBH (1 << 8) 1267 #define SYS_HRST_USBH (1 << 8) 1268 #define SYS_HCLK_I2C_SLAVE (1 << 9) 1269 #define SYS_HRST_I2C_SLAVE (1 << 9) 1270 #define SYS_HCLK_AX2H_A7 (1 << 10) 1271 #define SYS_HRST_AX2H_A7 (1 << 10) 1272 #define SYS_HCLK_AH2H_WF (1 << 11) 1273 #define SYS_HRST_AH2H_WF (1 << 11) 1274 #define SYS_HCLK_AH2H_BT (1 << 12) 1275 #define SYS_HRST_AH2H_BT (1 << 12) 1276 #define SYS_HCLK_CODEC (1 << 13) 1277 #define SYS_HRST_CODEC (1 << 13) 1278 #define SYS_HCLK_AHB1 (1 << 14) 1279 #define SYS_HRST_AHB1 (1 << 14) 1280 #define SYS_HCLK_AHB0 (1 << 15) 1281 #define SYS_HRST_AHB0 (1 << 15) 1282 #define SYS_HCLK_PSRAM1G (1 << 16) 1283 #define SYS_HRST_PSRAM1G (1 << 16) 1284 #define SYS_HCLK_PSRAM200 (1 << 17) 1285 #define SYS_HRST_PSRAM200 (1 << 17) 1286 #define SYS_HCLK_FLASH (1 << 18) 1287 #define SYS_HRST_FLASH (1 << 18) 1288 #define SYS_HCLK_RAM5 (1 << 19) 1289 #define SYS_HRST_RAM5 (1 << 19) 1290 #define SYS_HCLK_RAM4 (1 << 20) 1291 #define SYS_HRST_RAM4 (1 << 20) 1292 #define SYS_HCLK_RAM3 (1 << 21) 1293 #define SYS_HRST_RAM3 (1 << 21) 1294 #define SYS_HCLK_RAM2 (1 << 22) 1295 #define SYS_HRST_RAM2 (1 << 22) 1296 #define SYS_HCLK_RAM1 (1 << 23) 1297 #define SYS_HRST_RAM1 (1 << 23) 1298 #define SYS_HCLK_RAM0 (1 << 24) 1299 #define SYS_HRST_RAM0 (1 << 24) 1300 #define SYS_HCLK_ROM0 (1 << 25) 1301 #define SYS_HRST_ROM0 (1 << 25) 1302 #define SYS_HCLK_BT_DUMP (1 << 26) 1303 #define SYS_HRST_BT_DUMP (1 << 26) 1304 #define SYS_HCLK_WF_DUMP (1 << 27) 1305 #define SYS_HRST_WF_DUMP (1 << 27) 1306 #define SYS_HCLK_SDMMC (1 << 28) 1307 #define SYS_HRST_SDMMC (1 << 28) 1308 #define SYS_HCLK_CHECKSUM (1 << 29) 1309 #define SYS_HRST_CHECKSUM (1 << 29) 1310 #define SYS_HCLK_CRC (1 << 30) 1311 #define SYS_HRST_CRC (1 << 30) 1312 #define SYS_HCLK_FLASH1 (1 << 31) 1313 #define SYS_HRST_FLASH1 (1 << 31) 1314 1315 // MCU System APB Clocks: 1316 #define SYS_PCLK_CMU (1 << 0) 1317 #define SYS_PRST_CMU (1 << 0) 1318 #define SYS_PCLK_WDT (1 << 1) 1319 #define SYS_PRST_WDT (1 << 1) 1320 #define SYS_PCLK_TIMER0 (1 << 2) 1321 #define SYS_PRST_TIMER0 (1 << 2) 1322 #define SYS_PCLK_TIMER1 (1 << 3) 1323 #define SYS_PRST_TIMER1 (1 << 3) 1324 #define SYS_PCLK_TIMER2 (1 << 4) 1325 #define SYS_PRST_TIMER2 (1 << 4) 1326 #define SYS_PCLK_I2C0 (1 << 5) 1327 #define SYS_PRST_I2C0 (1 << 5) 1328 #define SYS_PCLK_I2C1 (1 << 6) 1329 #define SYS_PRST_I2C1 (1 << 6) 1330 #define SYS_PCLK_SPI (1 << 7) 1331 #define SYS_PRST_SPI (1 << 7) 1332 #define SYS_PCLK_SLCD (1 << 8) 1333 #define SYS_PRST_SLCD (1 << 8) 1334 #define SYS_PCLK_SPI_ITN (1 << 9) 1335 #define SYS_PRST_SPI_ITN (1 << 9) 1336 #define SYS_PCLK_SPI_PHY (1 << 10) 1337 #define SYS_PRST_SPI_PHY (1 << 10) 1338 #define SYS_PCLK_UART0 (1 << 11) 1339 #define SYS_PRST_UART0 (1 << 11) 1340 #define SYS_PCLK_UART1 (1 << 12) 1341 #define SYS_PRST_UART1 (1 << 12) 1342 #define SYS_PCLK_UART2 (1 << 13) 1343 #define SYS_PRST_UART2 (1 << 13) 1344 #define SYS_PCLK_PCM (1 << 14) 1345 #define SYS_PRST_PCM (1 << 14) 1346 #define SYS_PCLK_I2S0 (1 << 15) 1347 #define SYS_PRST_I2S0 (1 << 15) 1348 #define SYS_PCLK_SPDIF0 (1 << 16) 1349 #define SYS_PRST_SPDIF0 (1 << 16) 1350 #define SYS_PCLK_TQWF (1 << 17) 1351 #define SYS_PRST_TQWF (1 << 17) 1352 #define SYS_PCLK_TQA7 (1 << 18) 1353 #define SYS_PRST_TQA7 (1 << 18) 1354 #define SYS_PCLK_TRNG (1 << 19) 1355 #define SYS_PRST_TRNG (1 << 19) 1356 #define SYS_PCLK_BCM (1 << 20) 1357 #define SYS_PRST_BCM (1 << 20) 1358 #define SYS_PCLK_TZC (1 << 21) 1359 #define SYS_PRST_TZC (1 << 21) 1360 #define SYS_PCLK_IR (1 << 22) 1361 #define SYS_PRST_IR (1 << 22) 1362 #define SYS_PCLK_I2C2 (1 << 23) 1363 #define SYS_PRST_I2C2 (1 << 23) 1364 #define SYS_PCLK_UART3 (1 << 24) 1365 #define SYS_PRST_UART3 (1 << 24) 1366 #define SYS_PCLK_I2S1 (1 << 25) 1367 #define SYS_PRST_I2S1 (1 << 25) 1368 1369 // MCU System Other Clocks: 1370 #define SYS_OCLK_SLEEP (1 << 0) 1371 #define SYS_ORST_SLEEP (1 << 0) 1372 #define SYS_OCLK_USB (1 << 1) 1373 #define SYS_ORST_USB (1 << 1) 1374 #define SYS_OCLK_USB32K (1 << 2) 1375 #define SYS_ORST_USB32K (1 << 2) 1376 #define SYS_OCLK_PSRAM1G (1 << 3) 1377 #define SYS_ORST_PSRAM1G (1 << 3) 1378 #define SYS_OCLK_PSRAM200 (1 << 4) 1379 #define SYS_ORST_PSRAM200 (1 << 4) 1380 #define SYS_OCLK_FLASH (1 << 5) 1381 #define SYS_ORST_FLASH (1 << 5) 1382 #define SYS_OCLK_SDMMC (1 << 6) 1383 #define SYS_ORST_SDMMC (1 << 6) 1384 #define SYS_OCLK_WDT (1 << 7) 1385 #define SYS_ORST_WDT (1 << 7) 1386 #define SYS_OCLK_TIMER0 (1 << 8) 1387 #define SYS_ORST_TIMER0 (1 << 8) 1388 #define SYS_OCLK_TIMER1 (1 << 9) 1389 #define SYS_ORST_TIMER1 (1 << 9) 1390 #define SYS_OCLK_TIMER2 (1 << 10) 1391 #define SYS_ORST_TIMER2 (1 << 10) 1392 #define SYS_OCLK_I2C0 (1 << 11) 1393 #define SYS_ORST_I2C0 (1 << 11) 1394 #define SYS_OCLK_I2C1 (1 << 12) 1395 #define SYS_ORST_I2C1 (1 << 12) 1396 #define SYS_OCLK_SPI (1 << 13) 1397 #define SYS_ORST_SPI (1 << 13) 1398 #define SYS_OCLK_SLCD (1 << 14) 1399 #define SYS_ORST_SLCD (1 << 14) 1400 #define SYS_OCLK_SPI_ITN (1 << 15) 1401 #define SYS_ORST_SPI_ITN (1 << 15) 1402 #define SYS_OCLK_SPI_PHY (1 << 16) 1403 #define SYS_ORST_SPI_PHY (1 << 16) 1404 #define SYS_OCLK_UART0 (1 << 17) 1405 #define SYS_ORST_UART0 (1 << 17) 1406 #define SYS_OCLK_UART1 (1 << 18) 1407 #define SYS_ORST_UART1 (1 << 18) 1408 #define SYS_OCLK_UART2 (1 << 19) 1409 #define SYS_ORST_UART2 (1 << 19) 1410 #define SYS_OCLK_PCM (1 << 20) 1411 #define SYS_ORST_PCM (1 << 20) 1412 #define SYS_OCLK_I2S0 (1 << 21) 1413 #define SYS_ORST_I2S0 (1 << 21) 1414 #define SYS_OCLK_SPDIF0 (1 << 22) 1415 #define SYS_ORST_SPDIF0 (1 << 22) 1416 #define SYS_OCLK_I2S1 (1 << 23) 1417 #define SYS_ORST_I2S1 (1 << 23) 1418 #define SYS_OCLK_A7 (1 << 24) 1419 #define SYS_ORST_A7 (1 << 24) 1420 #define SYS_OCLK_TSF (1 << 25) 1421 #define SYS_ORST_TSF (1 << 25) 1422 #define SYS_OCLK_WDT_AP (1 << 26) 1423 #define SYS_ORST_WDT_AP (1 << 26) 1424 #define SYS_OCLK_TIMER0_AP (1 << 27) 1425 #define SYS_ORST_TIMER0_AP (1 << 27) 1426 #define SYS_OCLK_TIMER1_AP (1 << 28) 1427 #define SYS_ORST_TIMER1_AP (1 << 28) 1428 #define SYS_OCLK_FLASH1 (1 << 29) 1429 #define SYS_ORST_FLASH1 (1 << 29) 1430 #define SYS_OCLK_I2C2 (1 << 30) 1431 #define SYS_ORST_I2C2 (1 << 30) 1432 #define SYS_OCLK_UART3 (1 << 31) 1433 #define SYS_ORST_UART3 (1 << 31) 1434 1435 // MCU System Other Clocks2: 1436 #define SYS_QCLK_DSI_32K (1 << 1) 1437 #define SYS_QRST_DSI_32K (1 << 1) 1438 #define SYS_QCLK_DSI_PN (1 << 2) 1439 #define SYS_QRST_DSI_PN (1 << 2) 1440 #define SYS_QCLK_DSI_TV (1 << 3) 1441 #define SYS_QRST_DSI_TV (1 << 3) 1442 #define SYS_QCLK_DSI_PIX (1 << 4) 1443 #define SYS_QRST_DSI_PIX (1 << 4) 1444 #define SYS_QCLK_DSI_DSI (1 << 5) 1445 #define SYS_QRST_DSI_DSI (1 << 5) 1446 #define SYS_QCLK_CSI_LANE (1 << 6) 1447 #define SYS_QRST_CSI_LANE (1 << 6) 1448 #define SYS_QCLK_CSI_PIX (1 << 7) 1449 #define SYS_QRST_CSI_PIX (1 << 7) 1450 #define SYS_QCLK_CSI_LANG (1 << 8) 1451 #define SYS_QRST_CSI_LANG (1 << 8) 1452 #define SYS_QCLK_IR (1 << 9) 1453 #define SYS_QRST_IR (1 << 9) 1454 1455 // AXI Clocks: 1456 #define SYS_XCLK_DMA (1 << 0) 1457 #define SYS_XRST_DMA (1 << 0) 1458 #define SYS_XCLK_NIC (1 << 1) 1459 #define SYS_XRST_NIC (1 << 1) 1460 #define SYS_XCLK_IMEMLO (1 << 2) 1461 #define SYS_XRST_IMEMLO (1 << 2) 1462 #define SYS_XCLK_IMEMHI (1 << 3) 1463 #define SYS_XRST_IMEMHI (1 << 3) 1464 #define SYS_XCLK_PSRAM1G (1 << 4) 1465 #define SYS_XRST_PSRAM1G (1 << 4) 1466 #define SYS_XCLK_PER (1 << 5) 1467 #define SYS_XRST_PER (1 << 5) 1468 #define SYS_XCLK_PDBG (1 << 6) 1469 #define SYS_XRST_PDBG (1 << 6) 1470 #define SYS_XCLK_CORE0 (1 << 7) 1471 #define SYS_XRST_CORE0 (1 << 7) 1472 #define SYS_XCLK_CORE1 (1 << 8) 1473 #define SYS_XRST_CORE1 (1 << 8) 1474 #define SYS_XCLK_CORE2 (1 << 9) 1475 #define SYS_XRST_CORE2 (1 << 9) 1476 #define SYS_XCLK_CORE3 (1 << 10) 1477 #define SYS_XRST_CORE3 (1 << 10) 1478 #define SYS_XCLK_DBG (1 << 11) 1479 #define SYS_XRST_DBG (1 << 11) 1480 #define SYS_XCLK_SCU (1 << 12) 1481 #define SYS_XRST_SCU (1 << 12) 1482 #define SYS_XCLK_DISPLAYX (1 << 13) 1483 #define SYS_XRST_DISPLAYX (1 << 13) 1484 #define SYS_XCLK_DISPLAYH (1 << 14) 1485 #define SYS_XRST_DISPLAYH (1 << 14) 1486 #define SYS_XCLK_CSI (1 << 15) 1487 #define SYS_XRST_CSI (1 << 15) 1488 #define SYS_XCLK_DSI (1 << 16) 1489 #define SYS_XRST_DSI (1 << 16) 1490 #define SYS_XCLK_PSRAM1GMX (1 << 17) 1491 #define SYS_XRST_PSRAM1GMX (1 << 17) 1492 #define SYS_XCLK_GPV_MAIN (1 << 18) 1493 #define SYS_XRST_GPV_MAIN (1 << 18) 1494 #define SYS_XCLK_GPV_PSRAM1G (1 << 19) 1495 #define SYS_XRST_GPV_PSRAM1G (1 << 19) 1496 1497 // A7 APB Clocks: 1498 #define SYS_APCLK_BOOTREG (1 << 0) 1499 #define SYS_APRST_BOOTREG (1 << 0) 1500 #define SYS_APCLK_WDT (1 << 1) 1501 #define SYS_APRST_WDT (1 << 1) 1502 #define SYS_APCLK_TIMER0 (1 << 2) 1503 #define SYS_APRST_TIMER0 (1 << 2) 1504 #define SYS_APCLK_TIMER1 (1 << 3) 1505 #define SYS_APRST_TIMER1 (1 << 3) 1506 #define SYS_APCLK_TQ (1 << 4) 1507 #define SYS_APRST_TQ (1 << 4) 1508 #define SYS_APCLK_TSGEN (1 << 5) 1509 #define SYS_APRST_TSGEN (1 << 5) 1510 #define SYS_APCLK_TSGENRD (1 << 6) 1511 #define SYS_APRST_TSGENRD (1 << 6) 1512 #define SYS_APCLK_DAP (1 << 7) 1513 #define SYS_APRST_DAP (1 << 7) 1514 #define SYS_APCLK_DISPLAY (1 << 8) 1515 #define SYS_APRST_DISPLAY (1 << 8) 1516 #define SYS_APCLK_CSI (1 << 9) 1517 #define SYS_APRST_CSI (1 << 9) 1518 1519 #endif 1520 1521