1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_SMIX_H 10 #define HPM_SMIX_H 11 12 typedef struct { 13 __R uint32_t DMAC_ID; /* 0x0: DMAC_ID Register */ 14 __RW uint32_t DMAC_TC_ST; /* 0x4: Transfer Complete Status */ 15 __RW uint32_t DMAC_ABRT_ST; /* 0x8: Transfer Abort Status */ 16 __RW uint32_t DMAC_ERR_ST; /* 0xC: Transfer Error Status */ 17 __R uint8_t RESERVED0[16]; /* 0x10 - 0x1F: Reserved */ 18 __RW uint32_t DMAC_CTRL; /* 0x20: Control Register */ 19 __W uint32_t DMAC_ABRT_CMD; /* 0x24: Abort Command Register */ 20 __R uint8_t RESERVED1[12]; /* 0x28 - 0x33: Reserved */ 21 __RW uint32_t DMAC_CHEN; /* 0x34: Channel Enable Register */ 22 __R uint8_t RESERVED2[8]; /* 0x38 - 0x3F: Reserved */ 23 struct { 24 __RW uint32_t CTL; /* 0x40: Channel N Control Register */ 25 __RW uint32_t BURST_COUNT; /* 0x44: Channel N Source Total Beats Register */ 26 __RW uint32_t SRCADDR; /* 0x48: Channel N Source Register */ 27 __R uint8_t RESERVED0[4]; /* 0x4C - 0x4F: Reserved */ 28 __RW uint32_t DSTADDR; /* 0x50: Channel N Destination Register */ 29 __R uint8_t RESERVED1[4]; /* 0x54 - 0x57: Reserved */ 30 __RW uint32_t LLP; /* 0x58: Channel N Linked List Pointer Register */ 31 __R uint8_t RESERVED2[4]; /* 0x5C - 0x5F: Reserved */ 32 } DMA_CH[26]; 33 __R uint8_t RESERVED3[1152]; /* 0x380 - 0x7FF: Reserved */ 34 __RW uint32_t CALSAT_ST; /* 0x800: SMIX Cal Saturation Status Register */ 35 __RW uint32_t FDOT_DONE_ST; /* 0x804: SMIX Fade-Out Done Status Register */ 36 __R uint32_t DATA_ST; /* 0x808: SMIX Data Status Register */ 37 __R uint8_t RESERVED4[52]; /* 0x80C - 0x83F: Reserved */ 38 struct { 39 __RW uint32_t CTRL; /* 0x840: SMIX Dstination N Control Register */ 40 __RW uint32_t GAIN; /* 0x844: SMIX Dstination N Gain Register */ 41 __RW uint32_t BUFSIZE; /* 0x848: SMIX Dstination N Max Index Register */ 42 __RW uint32_t FADEIN; /* 0x84C: SMIX Dstination N Fade-In Configuration Register */ 43 __RW uint32_t FADEOUT; /* 0x850: SMIX Dstination N Fade-Out Configuration Register */ 44 __R uint32_t ST; /* 0x854: SMIX Dstination N Status Register */ 45 __R uint32_t DATA; /* 0x858: SMIX Dstination N Data Out Register */ 46 __R uint8_t RESERVED0[4]; /* 0x85C - 0x85F: Reserved */ 47 __RW uint32_t SOURCE_EN; /* 0x860: SMIX Dstination N Source Enable Register */ 48 __RW uint32_t SOURCE_ACT; /* 0x864: SMIX Dstination N Source Activation Register */ 49 __RW uint32_t SOURCE_DEACT; /* 0x868: SMIX Dstination N Source De-Activation Register */ 50 __RW uint32_t SOURCE_FADEIN_CTRL; /* 0x86C: SMIX Dstination N Source Fade-in Control Register */ 51 __R uint32_t DEACT_ST; /* 0x870: SMIX Dstination N Source Deactivation Status Register */ 52 __RW uint32_t SOURCE_MFADEOUT_CTRL; /* 0x874: SMIX Dstination N Source Manual Fade-out Control Register */ 53 __R uint8_t RESERVED1[8]; /* 0x878 - 0x87F: Reserved */ 54 } DST_CH[2]; 55 __R uint8_t RESERVED5[64]; /* 0x8C0 - 0x8FF: Reserved */ 56 struct { 57 __RW uint32_t CTRL; /* 0x900: SMIX Source N Control Register */ 58 __RW uint32_t GAIN; /* 0x904: SMIX Source N Gain Register */ 59 __RW uint32_t FADEIN; /* 0x908: SMIX Source N Fade-in Control Register */ 60 __RW uint32_t FADEOUT; /* 0x90C: SMIX Source N Fade-out Control Register */ 61 __RW uint32_t BUFSIZE; /* 0x910: SMIX Source N Buffer Size Register */ 62 __RW uint32_t ST; /* 0x914: SMIX Source N Status Register */ 63 __W uint32_t DATA; /* 0x918: SMIX Source N Data Input Register */ 64 __R uint8_t RESERVED0[4]; /* 0x91C - 0x91F: Reserved */ 65 } SOURCE_CH[14]; 66 } SMIX_Type; 67 68 69 /* Bitfield definition for register: DMAC_ID */ 70 /* 71 * REV (RO) 72 * 73 * Revision 74 */ 75 #define SMIX_DMAC_ID_REV_MASK (0x7FFFFUL) 76 #define SMIX_DMAC_ID_REV_SHIFT (0U) 77 #define SMIX_DMAC_ID_REV_GET(x) (((uint32_t)(x) & SMIX_DMAC_ID_REV_MASK) >> SMIX_DMAC_ID_REV_SHIFT) 78 79 /* Bitfield definition for register: DMAC_TC_ST */ 80 /* 81 * CH (W1C) 82 * 83 * The terminal count status is set when a channel transfer finishes without abort or error events 84 */ 85 #define SMIX_DMAC_TC_ST_CH_MASK (0x3FFFFFFUL) 86 #define SMIX_DMAC_TC_ST_CH_SHIFT (0U) 87 #define SMIX_DMAC_TC_ST_CH_SET(x) (((uint32_t)(x) << SMIX_DMAC_TC_ST_CH_SHIFT) & SMIX_DMAC_TC_ST_CH_MASK) 88 #define SMIX_DMAC_TC_ST_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_TC_ST_CH_MASK) >> SMIX_DMAC_TC_ST_CH_SHIFT) 89 90 /* Bitfield definition for register: DMAC_ABRT_ST */ 91 /* 92 * CH (W1C) 93 * 94 * The abort status is set when a channel transfer is aborted 95 */ 96 #define SMIX_DMAC_ABRT_ST_CH_MASK (0x3FFFFFFUL) 97 #define SMIX_DMAC_ABRT_ST_CH_SHIFT (0U) 98 #define SMIX_DMAC_ABRT_ST_CH_SET(x) (((uint32_t)(x) << SMIX_DMAC_ABRT_ST_CH_SHIFT) & SMIX_DMAC_ABRT_ST_CH_MASK) 99 #define SMIX_DMAC_ABRT_ST_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_ABRT_ST_CH_MASK) >> SMIX_DMAC_ABRT_ST_CH_SHIFT) 100 101 /* Bitfield definition for register: DMAC_ERR_ST */ 102 /* 103 * CH (W1C) 104 * 105 * The error status is set when a channel transfer encounters the following error events: 106 * . Bus error 107 * . Unaligned address 108 * . Unaligned transfer width 109 * . Reserved configuration 110 */ 111 #define SMIX_DMAC_ERR_ST_CH_MASK (0x3FFFFFFUL) 112 #define SMIX_DMAC_ERR_ST_CH_SHIFT (0U) 113 #define SMIX_DMAC_ERR_ST_CH_SET(x) (((uint32_t)(x) << SMIX_DMAC_ERR_ST_CH_SHIFT) & SMIX_DMAC_ERR_ST_CH_MASK) 114 #define SMIX_DMAC_ERR_ST_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_ERR_ST_CH_MASK) >> SMIX_DMAC_ERR_ST_CH_SHIFT) 115 116 /* Bitfield definition for register: DMAC_CTRL */ 117 /* 118 * SRST (RW) 119 * 120 * Software Reset 121 */ 122 #define SMIX_DMAC_CTRL_SRST_MASK (0x1U) 123 #define SMIX_DMAC_CTRL_SRST_SHIFT (0U) 124 #define SMIX_DMAC_CTRL_SRST_SET(x) (((uint32_t)(x) << SMIX_DMAC_CTRL_SRST_SHIFT) & SMIX_DMAC_CTRL_SRST_MASK) 125 #define SMIX_DMAC_CTRL_SRST_GET(x) (((uint32_t)(x) & SMIX_DMAC_CTRL_SRST_MASK) >> SMIX_DMAC_CTRL_SRST_SHIFT) 126 127 /* Bitfield definition for register: DMAC_ABRT_CMD */ 128 /* 129 * CH (WO) 130 * 131 * Write 1 to force the corresponding channel into abort status 132 */ 133 #define SMIX_DMAC_ABRT_CMD_CH_MASK (0x3FFFFFFUL) 134 #define SMIX_DMAC_ABRT_CMD_CH_SHIFT (0U) 135 #define SMIX_DMAC_ABRT_CMD_CH_SET(x) (((uint32_t)(x) << SMIX_DMAC_ABRT_CMD_CH_SHIFT) & SMIX_DMAC_ABRT_CMD_CH_MASK) 136 #define SMIX_DMAC_ABRT_CMD_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_ABRT_CMD_CH_MASK) >> SMIX_DMAC_ABRT_CMD_CH_SHIFT) 137 138 /* Bitfield definition for register: DMAC_CHEN */ 139 /* 140 * CH (RO) 141 * 142 * Write 1 to enable the corresponding channel 143 */ 144 #define SMIX_DMAC_CHEN_CH_MASK (0x3FFFFFFUL) 145 #define SMIX_DMAC_CHEN_CH_SHIFT (0U) 146 #define SMIX_DMAC_CHEN_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_CHEN_CH_MASK) >> SMIX_DMAC_CHEN_CH_SHIFT) 147 148 /* Bitfield definition for register of struct array DMA_CH: CTL */ 149 /* 150 * SRCREQSEL (RW) 151 * 152 * Source DMA request select. Select the request/ack handshake pair that the source device is connected to. 153 */ 154 #define SMIX_DMA_CH_CTL_SRCREQSEL_MASK (0x7C000000UL) 155 #define SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT (26U) 156 #define SMIX_DMA_CH_CTL_SRCREQSEL_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT) & SMIX_DMA_CH_CTL_SRCREQSEL_MASK) 157 #define SMIX_DMA_CH_CTL_SRCREQSEL_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCREQSEL_MASK) >> SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT) 158 159 /* 160 * DSTREQSEL (RW) 161 * 162 * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. 163 */ 164 #define SMIX_DMA_CH_CTL_DSTREQSEL_MASK (0x3E00000UL) 165 #define SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT (21U) 166 #define SMIX_DMA_CH_CTL_DSTREQSEL_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT) & SMIX_DMA_CH_CTL_DSTREQSEL_MASK) 167 #define SMIX_DMA_CH_CTL_DSTREQSEL_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTREQSEL_MASK) >> SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT) 168 169 /* 170 * PRIORITY (RW) 171 * 172 * 0x0: Lower priority 173 * 0x1: Higher priority 174 */ 175 #define SMIX_DMA_CH_CTL_PRIORITY_MASK (0x80000UL) 176 #define SMIX_DMA_CH_CTL_PRIORITY_SHIFT (19U) 177 #define SMIX_DMA_CH_CTL_PRIORITY_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_PRIORITY_SHIFT) & SMIX_DMA_CH_CTL_PRIORITY_MASK) 178 #define SMIX_DMA_CH_CTL_PRIORITY_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_PRIORITY_MASK) >> SMIX_DMA_CH_CTL_PRIORITY_SHIFT) 179 180 /* 181 * SRCBURSTSIZE (RW) 182 * 183 * 0x0: 1 beat per transfer 184 * 0x1: 2 beats per transfer 185 * 0x2: 4 beats per transfer 186 * 0x3: 8 beats per transfer 187 * 0x4: 16 beats per transfer 188 * 0x5: 32 beats per transfer 189 * 0x6: 64 beats per transfer 190 * 0x7: 128 beats per transfer 191 */ 192 #define SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK (0x78000UL) 193 #define SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT (15U) 194 #define SMIX_DMA_CH_CTL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT) & SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK) 195 #define SMIX_DMA_CH_CTL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK) >> SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT) 196 197 /* 198 * SRCWIDTH (RW) 199 * 200 * Source Transfer Beat Size: 201 * 0x0: Byte transfer 202 * 0x1: Half-word transfer 203 * 0x2: Word transfer 204 */ 205 #define SMIX_DMA_CH_CTL_SRCWIDTH_MASK (0x6000U) 206 #define SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT (13U) 207 #define SMIX_DMA_CH_CTL_SRCWIDTH_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT) & SMIX_DMA_CH_CTL_SRCWIDTH_MASK) 208 #define SMIX_DMA_CH_CTL_SRCWIDTH_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCWIDTH_MASK) >> SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT) 209 210 /* 211 * DSTWIDTH (RW) 212 * 213 * Destination Transfer Beat Size: 214 * 0x0: Byte transfer 215 * 0x1: Half-word transfer 216 * 0x2: Word transfer 217 */ 218 #define SMIX_DMA_CH_CTL_DSTWIDTH_MASK (0x1800U) 219 #define SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT (11U) 220 #define SMIX_DMA_CH_CTL_DSTWIDTH_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT) & SMIX_DMA_CH_CTL_DSTWIDTH_MASK) 221 #define SMIX_DMA_CH_CTL_DSTWIDTH_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTWIDTH_MASK) >> SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT) 222 223 /* 224 * SRCMODE (RW) 225 * 226 * DMA Source handshake mode 227 * 0x0: Normal mode 228 * 0x1: Handshake mode 229 */ 230 #define SMIX_DMA_CH_CTL_SRCMODE_MASK (0x400U) 231 #define SMIX_DMA_CH_CTL_SRCMODE_SHIFT (10U) 232 #define SMIX_DMA_CH_CTL_SRCMODE_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCMODE_SHIFT) & SMIX_DMA_CH_CTL_SRCMODE_MASK) 233 #define SMIX_DMA_CH_CTL_SRCMODE_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCMODE_MASK) >> SMIX_DMA_CH_CTL_SRCMODE_SHIFT) 234 235 /* 236 * DSTMODE (RW) 237 * 238 * DMA Destination handshake mode 239 * 0x0: Normal mode 240 * 0x1: Handshake mode 241 */ 242 #define SMIX_DMA_CH_CTL_DSTMODE_MASK (0x200U) 243 #define SMIX_DMA_CH_CTL_DSTMODE_SHIFT (9U) 244 #define SMIX_DMA_CH_CTL_DSTMODE_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTMODE_SHIFT) & SMIX_DMA_CH_CTL_DSTMODE_MASK) 245 #define SMIX_DMA_CH_CTL_DSTMODE_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTMODE_MASK) >> SMIX_DMA_CH_CTL_DSTMODE_SHIFT) 246 247 /* 248 * SRCADDRCTRL (RW) 249 * 250 * 0x0: Increment address 251 * 0x1: Decrement address 252 * 0x2: Fixed address 253 * 0x3: Reserved, setting the field with this value triggers an error exception 254 */ 255 #define SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK (0x180U) 256 #define SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT (7U) 257 #define SMIX_DMA_CH_CTL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT) & SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK) 258 #define SMIX_DMA_CH_CTL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK) >> SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT) 259 260 /* 261 * DSTADDRCTRL (RW) 262 * 263 * 0x0: Increment address 264 * 0x1: Decrement address 265 * 0x2: Fixed address 266 * 0x3: Reserved, setting the field with this value triggers an error exception 267 */ 268 #define SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK (0x60U) 269 #define SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT (5U) 270 #define SMIX_DMA_CH_CTL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT) & SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK) 271 #define SMIX_DMA_CH_CTL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK) >> SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT) 272 273 /* 274 * ABRT_INT_EN (RW) 275 * 276 * Abort interrupt enable 277 */ 278 #define SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK (0x8U) 279 #define SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT (3U) 280 #define SMIX_DMA_CH_CTL_ABRT_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK) 281 #define SMIX_DMA_CH_CTL_ABRT_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK) >> SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT) 282 283 /* 284 * ERR_INT_EN (RW) 285 * 286 * Err interrupt enable 287 */ 288 #define SMIX_DMA_CH_CTL_ERR_INT_EN_MASK (0x4U) 289 #define SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT (2U) 290 #define SMIX_DMA_CH_CTL_ERR_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_ERR_INT_EN_MASK) 291 #define SMIX_DMA_CH_CTL_ERR_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_ERR_INT_EN_MASK) >> SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT) 292 293 /* 294 * TC_INT_EN (RW) 295 * 296 * TC interrupt enable 297 */ 298 #define SMIX_DMA_CH_CTL_TC_INT_EN_MASK (0x2U) 299 #define SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT (1U) 300 #define SMIX_DMA_CH_CTL_TC_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_TC_INT_EN_MASK) 301 #define SMIX_DMA_CH_CTL_TC_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_TC_INT_EN_MASK) >> SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT) 302 303 /* 304 * EN (RW) 305 * 306 * channel enable bit 307 */ 308 #define SMIX_DMA_CH_CTL_EN_MASK (0x1U) 309 #define SMIX_DMA_CH_CTL_EN_SHIFT (0U) 310 #define SMIX_DMA_CH_CTL_EN_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_EN_SHIFT) & SMIX_DMA_CH_CTL_EN_MASK) 311 #define SMIX_DMA_CH_CTL_EN_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_EN_MASK) >> SMIX_DMA_CH_CTL_EN_SHIFT) 312 313 /* Bitfield definition for register of struct array DMA_CH: BURST_COUNT */ 314 /* 315 * NUM (RW) 316 * 317 * the total number of source beats 318 */ 319 #define SMIX_DMA_CH_BURST_COUNT_NUM_MASK (0xFFFFFFFFUL) 320 #define SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT (0U) 321 #define SMIX_DMA_CH_BURST_COUNT_NUM_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT) & SMIX_DMA_CH_BURST_COUNT_NUM_MASK) 322 #define SMIX_DMA_CH_BURST_COUNT_NUM_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_BURST_COUNT_NUM_MASK) >> SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT) 323 324 /* Bitfield definition for register of struct array DMA_CH: SRCADDR */ 325 /* 326 * PTR (RW) 327 * 328 * source address 329 */ 330 #define SMIX_DMA_CH_SRCADDR_PTR_MASK (0xFFFFFFFFUL) 331 #define SMIX_DMA_CH_SRCADDR_PTR_SHIFT (0U) 332 #define SMIX_DMA_CH_SRCADDR_PTR_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_SRCADDR_PTR_SHIFT) & SMIX_DMA_CH_SRCADDR_PTR_MASK) 333 #define SMIX_DMA_CH_SRCADDR_PTR_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_SRCADDR_PTR_MASK) >> SMIX_DMA_CH_SRCADDR_PTR_SHIFT) 334 335 /* Bitfield definition for register of struct array DMA_CH: DSTADDR */ 336 /* 337 * PTR (RW) 338 * 339 * destination address 340 */ 341 #define SMIX_DMA_CH_DSTADDR_PTR_MASK (0xFFFFFFFFUL) 342 #define SMIX_DMA_CH_DSTADDR_PTR_SHIFT (0U) 343 #define SMIX_DMA_CH_DSTADDR_PTR_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_DSTADDR_PTR_SHIFT) & SMIX_DMA_CH_DSTADDR_PTR_MASK) 344 #define SMIX_DMA_CH_DSTADDR_PTR_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_DSTADDR_PTR_MASK) >> SMIX_DMA_CH_DSTADDR_PTR_SHIFT) 345 346 /* Bitfield definition for register of struct array DMA_CH: LLP */ 347 /* 348 * PTR (RW) 349 * 350 * the address pointer for the linked list descriptor 351 */ 352 #define SMIX_DMA_CH_LLP_PTR_MASK (0xFFFFFFFFUL) 353 #define SMIX_DMA_CH_LLP_PTR_SHIFT (0U) 354 #define SMIX_DMA_CH_LLP_PTR_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_LLP_PTR_SHIFT) & SMIX_DMA_CH_LLP_PTR_MASK) 355 #define SMIX_DMA_CH_LLP_PTR_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_LLP_PTR_MASK) >> SMIX_DMA_CH_LLP_PTR_SHIFT) 356 357 /* Bitfield definition for register: CALSAT_ST */ 358 /* 359 * DST (W1C) 360 * 361 * DST CAL_SAT_ERR. W1C 362 */ 363 #define SMIX_CALSAT_ST_DST_MASK (0xC0000000UL) 364 #define SMIX_CALSAT_ST_DST_SHIFT (30U) 365 #define SMIX_CALSAT_ST_DST_SET(x) (((uint32_t)(x) << SMIX_CALSAT_ST_DST_SHIFT) & SMIX_CALSAT_ST_DST_MASK) 366 #define SMIX_CALSAT_ST_DST_GET(x) (((uint32_t)(x) & SMIX_CALSAT_ST_DST_MASK) >> SMIX_CALSAT_ST_DST_SHIFT) 367 368 /* 369 * SRC (W1C) 370 * 371 * SRC CAL_SAT_ERR. W1C 372 */ 373 #define SMIX_CALSAT_ST_SRC_MASK (0x3FFFU) 374 #define SMIX_CALSAT_ST_SRC_SHIFT (0U) 375 #define SMIX_CALSAT_ST_SRC_SET(x) (((uint32_t)(x) << SMIX_CALSAT_ST_SRC_SHIFT) & SMIX_CALSAT_ST_SRC_MASK) 376 #define SMIX_CALSAT_ST_SRC_GET(x) (((uint32_t)(x) & SMIX_CALSAT_ST_SRC_MASK) >> SMIX_CALSAT_ST_SRC_SHIFT) 377 378 /* Bitfield definition for register: FDOT_DONE_ST */ 379 /* 380 * DST (W1C) 381 * 382 * DST fadeout done. W1C 383 */ 384 #define SMIX_FDOT_DONE_ST_DST_MASK (0xC0000000UL) 385 #define SMIX_FDOT_DONE_ST_DST_SHIFT (30U) 386 #define SMIX_FDOT_DONE_ST_DST_SET(x) (((uint32_t)(x) << SMIX_FDOT_DONE_ST_DST_SHIFT) & SMIX_FDOT_DONE_ST_DST_MASK) 387 #define SMIX_FDOT_DONE_ST_DST_GET(x) (((uint32_t)(x) & SMIX_FDOT_DONE_ST_DST_MASK) >> SMIX_FDOT_DONE_ST_DST_SHIFT) 388 389 /* 390 * SRC (W1C) 391 * 392 * SRC fadeout done. W1C 393 */ 394 #define SMIX_FDOT_DONE_ST_SRC_MASK (0x3FFFU) 395 #define SMIX_FDOT_DONE_ST_SRC_SHIFT (0U) 396 #define SMIX_FDOT_DONE_ST_SRC_SET(x) (((uint32_t)(x) << SMIX_FDOT_DONE_ST_SRC_SHIFT) & SMIX_FDOT_DONE_ST_SRC_MASK) 397 #define SMIX_FDOT_DONE_ST_SRC_GET(x) (((uint32_t)(x) & SMIX_FDOT_DONE_ST_SRC_MASK) >> SMIX_FDOT_DONE_ST_SRC_SHIFT) 398 399 /* Bitfield definition for register: DATA_ST */ 400 /* 401 * DST_DA (RO) 402 * 403 * DST data available 404 */ 405 #define SMIX_DATA_ST_DST_DA_MASK (0xC0000000UL) 406 #define SMIX_DATA_ST_DST_DA_SHIFT (30U) 407 #define SMIX_DATA_ST_DST_DA_GET(x) (((uint32_t)(x) & SMIX_DATA_ST_DST_DA_MASK) >> SMIX_DATA_ST_DST_DA_SHIFT) 408 409 /* 410 * DST_UNDL (RO) 411 * 412 * DST data underflow 413 */ 414 #define SMIX_DATA_ST_DST_UNDL_MASK (0x30000000UL) 415 #define SMIX_DATA_ST_DST_UNDL_SHIFT (28U) 416 #define SMIX_DATA_ST_DST_UNDL_GET(x) (((uint32_t)(x) & SMIX_DATA_ST_DST_UNDL_MASK) >> SMIX_DATA_ST_DST_UNDL_SHIFT) 417 418 /* 419 * SRC_DN (RO) 420 * 421 * SRC data needed 422 */ 423 #define SMIX_DATA_ST_SRC_DN_MASK (0x3FFFU) 424 #define SMIX_DATA_ST_SRC_DN_SHIFT (0U) 425 #define SMIX_DATA_ST_SRC_DN_GET(x) (((uint32_t)(x) & SMIX_DATA_ST_SRC_DN_MASK) >> SMIX_DATA_ST_SRC_DN_SHIFT) 426 427 /* Bitfield definition for register of struct array DST_CH: CTRL */ 428 /* 429 * DATA_UNFL_IE (RW) 430 * 431 * Data Underflow Error IntEn 432 */ 433 #define SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK (0x100000UL) 434 #define SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT (20U) 435 #define SMIX_DST_CH_CTRL_DATA_UNFL_IE_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT) & SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK) 436 #define SMIX_DST_CH_CTRL_DATA_UNFL_IE_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK) >> SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT) 437 438 /* 439 * THRSH (RW) 440 * 441 * FIFO threshold for DMA or Int. >= will generate req. Must be greater or equal than 8. The read burst of DMA should make the fillings in the buffer be greater than 4. 442 */ 443 #define SMIX_DST_CH_CTRL_THRSH_MASK (0xFF000UL) 444 #define SMIX_DST_CH_CTRL_THRSH_SHIFT (12U) 445 #define SMIX_DST_CH_CTRL_THRSH_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_THRSH_SHIFT) & SMIX_DST_CH_CTRL_THRSH_MASK) 446 #define SMIX_DST_CH_CTRL_THRSH_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_THRSH_MASK) >> SMIX_DST_CH_CTRL_THRSH_SHIFT) 447 448 /* 449 * CALSAT_INT_EN (RW) 450 * 451 * Cal Saturation IntEn 452 */ 453 #define SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK (0x800U) 454 #define SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT (11U) 455 #define SMIX_DST_CH_CTRL_CALSAT_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT) & SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK) 456 #define SMIX_DST_CH_CTRL_CALSAT_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK) >> SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT) 457 458 /* 459 * DA_INT_EN (RW) 460 * 461 * Data Available IntEn 462 */ 463 #define SMIX_DST_CH_CTRL_DA_INT_EN_MASK (0x400U) 464 #define SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT (10U) 465 #define SMIX_DST_CH_CTRL_DA_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT) & SMIX_DST_CH_CTRL_DA_INT_EN_MASK) 466 #define SMIX_DST_CH_CTRL_DA_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DA_INT_EN_MASK) >> SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT) 467 468 /* 469 * ADEACTFADEOUT_EN (RW) 470 * 471 * AutoDeactAfterFadeOut_En: 472 * Asserted to enter de-activated mode after fade-out done 473 */ 474 #define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK (0x200U) 475 #define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT (9U) 476 #define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT) & SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK) 477 #define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK) >> SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT) 478 479 /* 480 * FADEOUT_DONE_IE (RW) 481 * 482 * Fade-Out interrupt enable 483 */ 484 #define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK (0x100U) 485 #define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT (8U) 486 #define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT) & SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK) 487 #define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK) >> SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT) 488 489 /* 490 * DST_DEACT (RW) 491 * 492 * de-activate the destination channel 493 */ 494 #define SMIX_DST_CH_CTRL_DST_DEACT_MASK (0x80U) 495 #define SMIX_DST_CH_CTRL_DST_DEACT_SHIFT (7U) 496 #define SMIX_DST_CH_CTRL_DST_DEACT_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_DEACT_SHIFT) & SMIX_DST_CH_CTRL_DST_DEACT_MASK) 497 #define SMIX_DST_CH_CTRL_DST_DEACT_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_DEACT_MASK) >> SMIX_DST_CH_CTRL_DST_DEACT_SHIFT) 498 499 /* 500 * DST_ACT (RW) 501 * 502 * activate the destination channel 503 */ 504 #define SMIX_DST_CH_CTRL_DST_ACT_MASK (0x40U) 505 #define SMIX_DST_CH_CTRL_DST_ACT_SHIFT (6U) 506 #define SMIX_DST_CH_CTRL_DST_ACT_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_ACT_SHIFT) & SMIX_DST_CH_CTRL_DST_ACT_MASK) 507 #define SMIX_DST_CH_CTRL_DST_ACT_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_ACT_MASK) >> SMIX_DST_CH_CTRL_DST_ACT_SHIFT) 508 509 /* 510 * DSTFADOUT_MEN (RW) 511 * 512 * Manual FadeOut_Ctrl for destionation. Auto clear. 513 */ 514 #define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK (0x20U) 515 #define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT (5U) 516 #define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK) 517 #define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK) >> SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT) 518 519 /* 520 * DSTFADOUT_AEN (RW) 521 * 522 * Automatically FadeOut_Ctrl for destionation. Only effective after DST_AFADEOUT is assigned a non-zero value 523 */ 524 #define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK (0x10U) 525 #define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT (4U) 526 #define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK) 527 #define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK) >> SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT) 528 529 /* 530 * DSTFADIN_EN (RW) 531 * 532 * FadeIn_Ctrl for destionation. Auto clear. 533 */ 534 #define SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK (0x8U) 535 #define SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT (3U) 536 #define SMIX_DST_CH_CTRL_DSTFADIN_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK) 537 #define SMIX_DST_CH_CTRL_DSTFADIN_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK) >> SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT) 538 539 /* 540 * DST_EN (RW) 541 * 542 * Dst enabled. When disabled, clear the FIFO pointers. 543 */ 544 #define SMIX_DST_CH_CTRL_DST_EN_MASK (0x4U) 545 #define SMIX_DST_CH_CTRL_DST_EN_SHIFT (2U) 546 #define SMIX_DST_CH_CTRL_DST_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_EN_SHIFT) & SMIX_DST_CH_CTRL_DST_EN_MASK) 547 #define SMIX_DST_CH_CTRL_DST_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_EN_MASK) >> SMIX_DST_CH_CTRL_DST_EN_SHIFT) 548 549 /* 550 * SOFTRST (RW) 551 * 552 * Soft reset 553 */ 554 #define SMIX_DST_CH_CTRL_SOFTRST_MASK (0x2U) 555 #define SMIX_DST_CH_CTRL_SOFTRST_SHIFT (1U) 556 #define SMIX_DST_CH_CTRL_SOFTRST_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_SOFTRST_SHIFT) & SMIX_DST_CH_CTRL_SOFTRST_MASK) 557 #define SMIX_DST_CH_CTRL_SOFTRST_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_SOFTRST_MASK) >> SMIX_DST_CH_CTRL_SOFTRST_SHIFT) 558 559 /* 560 * MIXER_EN (RW) 561 * 562 * mixer function enable. 563 */ 564 #define SMIX_DST_CH_CTRL_MIXER_EN_MASK (0x1U) 565 #define SMIX_DST_CH_CTRL_MIXER_EN_SHIFT (0U) 566 #define SMIX_DST_CH_CTRL_MIXER_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_MIXER_EN_SHIFT) & SMIX_DST_CH_CTRL_MIXER_EN_MASK) 567 #define SMIX_DST_CH_CTRL_MIXER_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_MIXER_EN_MASK) >> SMIX_DST_CH_CTRL_MIXER_EN_SHIFT) 568 569 /* Bitfield definition for register of struct array DST_CH: GAIN */ 570 /* 571 * VAL (RW) 572 * 573 * Unsigned Int, with 12 fractional bits. . The top 3 bits are for shift. Same as SHFT_CTR[2:0] 574 */ 575 #define SMIX_DST_CH_GAIN_VAL_MASK (0x7FFFU) 576 #define SMIX_DST_CH_GAIN_VAL_SHIFT (0U) 577 #define SMIX_DST_CH_GAIN_VAL_SET(x) (((uint32_t)(x) << SMIX_DST_CH_GAIN_VAL_SHIFT) & SMIX_DST_CH_GAIN_VAL_MASK) 578 #define SMIX_DST_CH_GAIN_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_GAIN_VAL_MASK) >> SMIX_DST_CH_GAIN_VAL_SHIFT) 579 580 /* Bitfield definition for register of struct array DST_CH: BUFSIZE */ 581 /* 582 * MAX_IDX (RW) 583 * 584 * The total length of the dst stream -1. If zero, means there is no end of the stream. 585 */ 586 #define SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK (0xFFFFFFFFUL) 587 #define SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT (0U) 588 #define SMIX_DST_CH_BUFSIZE_MAX_IDX_SET(x) (((uint32_t)(x) << SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT) & SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK) 589 #define SMIX_DST_CH_BUFSIZE_MAX_IDX_GET(x) (((uint32_t)(x) & SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK) >> SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT) 590 591 /* Bitfield definition for register of struct array DST_CH: FADEIN */ 592 /* 593 * DELTA (RW) 594 * 595 * Fade-in delta for linear fading in from 0 to 1 (about at most 20s for 48kHz sampled sound) 596 * (Using only top 14 bits for mul) 597 */ 598 #define SMIX_DST_CH_FADEIN_DELTA_MASK (0xFFFFFUL) 599 #define SMIX_DST_CH_FADEIN_DELTA_SHIFT (0U) 600 #define SMIX_DST_CH_FADEIN_DELTA_SET(x) (((uint32_t)(x) << SMIX_DST_CH_FADEIN_DELTA_SHIFT) & SMIX_DST_CH_FADEIN_DELTA_MASK) 601 #define SMIX_DST_CH_FADEIN_DELTA_GET(x) (((uint32_t)(x) & SMIX_DST_CH_FADEIN_DELTA_MASK) >> SMIX_DST_CH_FADEIN_DELTA_SHIFT) 602 603 /* Bitfield definition for register of struct array DST_CH: FADEOUT */ 604 /* 605 * DELTA (RW) 606 * 607 * Fade out in 2^DELTA samples. Now DELTA can be at most 14。 608 */ 609 #define SMIX_DST_CH_FADEOUT_DELTA_MASK (0xFFFFFUL) 610 #define SMIX_DST_CH_FADEOUT_DELTA_SHIFT (0U) 611 #define SMIX_DST_CH_FADEOUT_DELTA_SET(x) (((uint32_t)(x) << SMIX_DST_CH_FADEOUT_DELTA_SHIFT) & SMIX_DST_CH_FADEOUT_DELTA_MASK) 612 #define SMIX_DST_CH_FADEOUT_DELTA_GET(x) (((uint32_t)(x) & SMIX_DST_CH_FADEOUT_DELTA_MASK) >> SMIX_DST_CH_FADEOUT_DELTA_SHIFT) 613 614 /* Bitfield definition for register of struct array DST_CH: ST */ 615 /* 616 * FIFO_FILLINGS (RO) 617 * 618 * destination channel output FIFO fillings 619 */ 620 #define SMIX_DST_CH_ST_FIFO_FILLINGS_MASK (0x7FC0U) 621 #define SMIX_DST_CH_ST_FIFO_FILLINGS_SHIFT (6U) 622 #define SMIX_DST_CH_ST_FIFO_FILLINGS_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_FIFO_FILLINGS_MASK) >> SMIX_DST_CH_ST_FIFO_FILLINGS_SHIFT) 623 624 /* 625 * FDOUT_DONE (RO) 626 * 627 * Fade-Out Done. W1C 628 */ 629 #define SMIX_DST_CH_ST_FDOUT_DONE_MASK (0x20U) 630 #define SMIX_DST_CH_ST_FDOUT_DONE_SHIFT (5U) 631 #define SMIX_DST_CH_ST_FDOUT_DONE_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_FDOUT_DONE_MASK) >> SMIX_DST_CH_ST_FDOUT_DONE_SHIFT) 632 633 /* 634 * CALSAT (RO) 635 * 636 * Saturate Error Found. W1C 637 */ 638 #define SMIX_DST_CH_ST_CALSAT_MASK (0x10U) 639 #define SMIX_DST_CH_ST_CALSAT_SHIFT (4U) 640 #define SMIX_DST_CH_ST_CALSAT_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_CALSAT_MASK) >> SMIX_DST_CH_ST_CALSAT_SHIFT) 641 642 /* 643 * DA (RO) 644 * 645 * Data Available 646 */ 647 #define SMIX_DST_CH_ST_DA_MASK (0x8U) 648 #define SMIX_DST_CH_ST_DA_SHIFT (3U) 649 #define SMIX_DST_CH_ST_DA_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_DA_MASK) >> SMIX_DST_CH_ST_DA_SHIFT) 650 651 /* 652 * MODE (RO) 653 * 654 * The modes are: 655 * Mode 0: Disabled: after reset. Program the registers, and DSTn_CTRL [DST_EN] to enter Mode 1. 656 * Mode 1: Enabled and not-activated. wait for DSTn_CTRL [DSTFADIN_EN] or DSTn_CTRL [DST_ACT], jump to Mode 3 or Mode 4 based on whether Fade-in enabled. 657 * Mode 3: Enabled and activated and fade-in in progress: Can not be fade out. Will send data to DMA. Jump to Mode 4 after fadin op done. 658 * Mode 4: Enabled and activated and done fade-in, no fade-out yet: Can be fade out. Will send data to DMA. 659 * Mode 5: Enabled and activated and fade-out in progress: After faded out OP. Will send data to DMA. Will transfer to mode 6 or mode 7 depending on the DSTn_CTRL [ADeactFadeOut_En] cfg 660 * Mode 6: Enabled and activated and faded-out: faded out is done. Will send data to DMA. Will transfer to mode 7 if manual deactivated. 661 * Mode 7: Enabled and De-activated: If configured to enter this mode, after auto or manuallly fade-out, or after manual de-activated. Won't send data to DMA. Won't gen data avail signals. Intf register can be programmed. Will change to Mode 3 or Mode 4 after manual ACT or Fade-in CMD. Will transfer to Mode 0 if DSTn_CTRL [DST_EN] is assigned 0. To support a new stream or, to continue the old stream after a pause. 662 */ 663 #define SMIX_DST_CH_ST_MODE_MASK (0x7U) 664 #define SMIX_DST_CH_ST_MODE_SHIFT (0U) 665 #define SMIX_DST_CH_ST_MODE_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_MODE_MASK) >> SMIX_DST_CH_ST_MODE_SHIFT) 666 667 /* Bitfield definition for register of struct array DST_CH: DATA */ 668 /* 669 * VAL (RO) 670 * 671 * Output data buffer 672 */ 673 #define SMIX_DST_CH_DATA_VAL_MASK (0xFFFFFFFFUL) 674 #define SMIX_DST_CH_DATA_VAL_SHIFT (0U) 675 #define SMIX_DST_CH_DATA_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_DATA_VAL_MASK) >> SMIX_DST_CH_DATA_VAL_SHIFT) 676 677 /* Bitfield definition for register of struct array DST_CH: SOURCE_EN */ 678 /* 679 * VAL (RW) 680 * 681 * After enabled, Data needed req will be asserted. DMA can feed in data. The channel will join in the sum operation of mixer operation. 682 */ 683 #define SMIX_DST_CH_SOURCE_EN_VAL_MASK (0xFFU) 684 #define SMIX_DST_CH_SOURCE_EN_VAL_SHIFT (0U) 685 #define SMIX_DST_CH_SOURCE_EN_VAL_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_EN_VAL_SHIFT) & SMIX_DST_CH_SOURCE_EN_VAL_MASK) 686 #define SMIX_DST_CH_SOURCE_EN_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_EN_VAL_MASK) >> SMIX_DST_CH_SOURCE_EN_VAL_SHIFT) 687 688 /* Bitfield definition for register of struct array DST_CH: SOURCE_ACT */ 689 /* 690 * VAL (WO) 691 * 692 * Manually Activate the channel 693 */ 694 #define SMIX_DST_CH_SOURCE_ACT_VAL_MASK (0xFFU) 695 #define SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT (0U) 696 #define SMIX_DST_CH_SOURCE_ACT_VAL_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT) & SMIX_DST_CH_SOURCE_ACT_VAL_MASK) 697 #define SMIX_DST_CH_SOURCE_ACT_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_ACT_VAL_MASK) >> SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT) 698 699 /* Bitfield definition for register of struct array DST_CH: SOURCE_DEACT */ 700 /* 701 * VAL (WO) 702 * 703 * Manually DeActivate the channel 704 */ 705 #define SMIX_DST_CH_SOURCE_DEACT_VAL_MASK (0xFFU) 706 #define SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT (0U) 707 #define SMIX_DST_CH_SOURCE_DEACT_VAL_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT) & SMIX_DST_CH_SOURCE_DEACT_VAL_MASK) 708 #define SMIX_DST_CH_SOURCE_DEACT_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_DEACT_VAL_MASK) >> SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT) 709 710 /* Bitfield definition for register of struct array DST_CH: SOURCE_FADEIN_CTRL */ 711 /* 712 * AOP (RW) 713 * 714 * Asserted to start fade-in operation. When the amplification factors are stable, auto clear. 715 */ 716 #define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK (0xFFU) 717 #define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT (0U) 718 #define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT) & SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK) 719 #define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK) >> SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT) 720 721 /* Bitfield definition for register of struct array DST_CH: DEACT_ST */ 722 /* 723 * DST_DEACT (RO) 724 * 725 * Asserted when in de-active mode 726 */ 727 #define SMIX_DST_CH_DEACT_ST_DST_DEACT_MASK (0x80000000UL) 728 #define SMIX_DST_CH_DEACT_ST_DST_DEACT_SHIFT (31U) 729 #define SMIX_DST_CH_DEACT_ST_DST_DEACT_GET(x) (((uint32_t)(x) & SMIX_DST_CH_DEACT_ST_DST_DEACT_MASK) >> SMIX_DST_CH_DEACT_ST_DST_DEACT_SHIFT) 730 731 /* 732 * SRC_DEACT_ST (RO) 733 * 734 * Asserted when in de-active mode 735 */ 736 #define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_MASK (0xFFU) 737 #define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_SHIFT (0U) 738 #define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_GET(x) (((uint32_t)(x) & SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_MASK) >> SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_SHIFT) 739 740 /* Bitfield definition for register of struct array DST_CH: SOURCE_MFADEOUT_CTRL */ 741 /* 742 * OP (RW) 743 * 744 * Asserted to start fade-out operation. When the amplification factors are stable, auto clear. 745 */ 746 #define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK (0xFFU) 747 #define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT (0U) 748 #define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT) & SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK) 749 #define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK) >> SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT) 750 751 /* Bitfield definition for register of struct array SOURCE_CH: CTRL */ 752 /* 753 * FIFO_RESET (RW) 754 * 755 * Asserted to reset FIFO pointer. Cleared to exit reset state. 756 */ 757 #define SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK (0x200000UL) 758 #define SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT (21U) 759 #define SMIX_SOURCE_CH_CTRL_FIFO_RESET_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT) & SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK) 760 #define SMIX_SOURCE_CH_CTRL_FIFO_RESET_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK) >> SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT) 761 762 /* 763 * THRSH (RW) 764 * 765 * FIFO threshold for DMA or Int. <= will generate req. Must be greater or equal than 8. This threshold is also used to trgger the internal FIR operation. To avoid the reading and writing to the same address in the memory block, the threshold should greater than 4. 766 */ 767 #define SMIX_SOURCE_CH_CTRL_THRSH_MASK (0x1FE000UL) 768 #define SMIX_SOURCE_CH_CTRL_THRSH_SHIFT (13U) 769 #define SMIX_SOURCE_CH_CTRL_THRSH_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_THRSH_SHIFT) & SMIX_SOURCE_CH_CTRL_THRSH_MASK) 770 #define SMIX_SOURCE_CH_CTRL_THRSH_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_THRSH_MASK) >> SMIX_SOURCE_CH_CTRL_THRSH_SHIFT) 771 772 /* 773 * CALSAT_INT_EN (RW) 774 * 775 * Cal Saturation IntEn 776 */ 777 #define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK (0x1000U) 778 #define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT (12U) 779 #define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK) 780 #define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT) 781 782 /* 783 * DN_INT_EN (RW) 784 * 785 * Data Needed IntEn 786 */ 787 #define SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK (0x800U) 788 #define SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT (11U) 789 #define SMIX_SOURCE_CH_CTRL_DN_INT_EN_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK) 790 #define SMIX_SOURCE_CH_CTRL_DN_INT_EN_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT) 791 792 /* 793 * SHFT_CTRL (RW) 794 * 795 * Shift operation after FIR 796 * 0: no shift (when no upsampling or up-sampling-by-2 or up-sampling-by-3) 797 * 1: left-shift-by-1 (when up-sampling-by-4 or up-sampling-by-6) 798 * 2: left-shift-by-1 (when up-sampling-by-8 or up-sampling-by-12) 799 * 7: /2 (when rate /2) 800 * Other n: shift-left-by-n, but not suggested to be used. 801 */ 802 #define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK (0x700U) 803 #define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT (8U) 804 #define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT) & SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK) 805 #define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK) >> SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT) 806 807 /* 808 * AUTODEACTAFTERFADEOUT_EN (RW) 809 * 810 * Asserted to enter de-activated mode after fade-out done 811 */ 812 #define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK (0x80U) 813 #define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT (7U) 814 #define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK) 815 #define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT) 816 817 /* 818 * FADEOUT_DONE_IE (RW) 819 * 820 * Fade-Out interrupt enable 821 */ 822 #define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK (0x40U) 823 #define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT (6U) 824 #define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT) & SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK) 825 #define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK) >> SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT) 826 827 /* 828 * RATECONV (RW) 829 * 830 * 0: no rate conversion 831 * 1: up-conversion x2 832 * 2: up-conversion x3 833 * 3: up-conversion x4 834 * 4: up-conversion x6 835 * 5: up-conversion x8 836 * 6: up-conversion x12 837 * 7: down-conversion /2 838 */ 839 #define SMIX_SOURCE_CH_CTRL_RATECONV_MASK (0x7U) 840 #define SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT (0U) 841 #define SMIX_SOURCE_CH_CTRL_RATECONV_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT) & SMIX_SOURCE_CH_CTRL_RATECONV_MASK) 842 #define SMIX_SOURCE_CH_CTRL_RATECONV_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_RATECONV_MASK) >> SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT) 843 844 /* Bitfield definition for register of struct array SOURCE_CH: GAIN */ 845 /* 846 * VAL (RW) 847 * 848 * Unsigned Int, with 12 fractional bits. The top 3 bits are for shift. Same as SHFT_CTR[2:0]. 849 */ 850 #define SMIX_SOURCE_CH_GAIN_VAL_MASK (0x7FFFU) 851 #define SMIX_SOURCE_CH_GAIN_VAL_SHIFT (0U) 852 #define SMIX_SOURCE_CH_GAIN_VAL_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_GAIN_VAL_SHIFT) & SMIX_SOURCE_CH_GAIN_VAL_MASK) 853 #define SMIX_SOURCE_CH_GAIN_VAL_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_GAIN_VAL_MASK) >> SMIX_SOURCE_CH_GAIN_VAL_SHIFT) 854 855 /* Bitfield definition for register of struct array SOURCE_CH: FADEIN */ 856 /* 857 * DELTA (RW) 858 * 859 * Fade -in confg. 860 */ 861 #define SMIX_SOURCE_CH_FADEIN_DELTA_MASK (0xFFFFFUL) 862 #define SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT (0U) 863 #define SMIX_SOURCE_CH_FADEIN_DELTA_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT) & SMIX_SOURCE_CH_FADEIN_DELTA_MASK) 864 #define SMIX_SOURCE_CH_FADEIN_DELTA_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_FADEIN_DELTA_MASK) >> SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT) 865 866 /* Bitfield definition for register of struct array SOURCE_CH: FADEOUT */ 867 /* 868 * DELTA (RW) 869 * 870 * Fade out in 2^DELTA samples. Now DELTA can be at most 14。 871 */ 872 #define SMIX_SOURCE_CH_FADEOUT_DELTA_MASK (0xFFFFFUL) 873 #define SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT (0U) 874 #define SMIX_SOURCE_CH_FADEOUT_DELTA_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT) & SMIX_SOURCE_CH_FADEOUT_DELTA_MASK) 875 #define SMIX_SOURCE_CH_FADEOUT_DELTA_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_FADEOUT_DELTA_MASK) >> SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT) 876 877 /* Bitfield definition for register of struct array SOURCE_CH: BUFSIZE */ 878 /* 879 * MAXIDX (RW) 880 * 881 * unit as 16-bits per sample. Zero means no length limit. = Act Len-1. 882 * The actual length is the up_rate*(input_data_length-4). 883 * If the filter processing is down-sampling, the value of up_rate above is 1. 884 * If the filter processing is up-sampling, the value of up_rate above is the up-sampling rate. 885 */ 886 #define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK (0xFFFFFFFFUL) 887 #define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT (0U) 888 #define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT) & SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK) 889 #define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK) >> SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT) 890 891 /* Bitfield definition for register of struct array SOURCE_CH: ST */ 892 /* 893 * FIFO_FILLINGS (RO) 894 * 895 * The fillings of input FIFO. 896 */ 897 #define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_MASK (0x7FC00UL) 898 #define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_SHIFT (10U) 899 #define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FIFO_FILLINGS_MASK) >> SMIX_SOURCE_CH_ST_FIFO_FILLINGS_SHIFT) 900 901 /* 902 * FDOUT_DONE (W1C) 903 * 904 * Fade-Out Done. W1C 905 */ 906 #define SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK (0x200U) 907 #define SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT (9U) 908 #define SMIX_SOURCE_CH_ST_FDOUT_DONE_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT) & SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK) 909 #define SMIX_SOURCE_CH_ST_FDOUT_DONE_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK) >> SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT) 910 911 /* 912 * CALSAT (W1C) 913 * 914 * Calculation saturation status. W1C 915 */ 916 #define SMIX_SOURCE_CH_ST_CALSAT_MASK (0x100U) 917 #define SMIX_SOURCE_CH_ST_CALSAT_SHIFT (8U) 918 #define SMIX_SOURCE_CH_ST_CALSAT_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_ST_CALSAT_SHIFT) & SMIX_SOURCE_CH_ST_CALSAT_MASK) 919 #define SMIX_SOURCE_CH_ST_CALSAT_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_CALSAT_MASK) >> SMIX_SOURCE_CH_ST_CALSAT_SHIFT) 920 921 /* 922 * DN (RO) 923 * 924 * Data needed flag 925 */ 926 #define SMIX_SOURCE_CH_ST_DN_MASK (0x80U) 927 #define SMIX_SOURCE_CH_ST_DN_SHIFT (7U) 928 #define SMIX_SOURCE_CH_ST_DN_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_DN_MASK) >> SMIX_SOURCE_CH_ST_DN_SHIFT) 929 930 /* 931 * FIRPHASE (RO) 932 * 933 * the poly phase counter 934 */ 935 #define SMIX_SOURCE_CH_ST_FIRPHASE_MASK (0x78U) 936 #define SMIX_SOURCE_CH_ST_FIRPHASE_SHIFT (3U) 937 #define SMIX_SOURCE_CH_ST_FIRPHASE_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FIRPHASE_MASK) >> SMIX_SOURCE_CH_ST_FIRPHASE_SHIFT) 938 939 /* 940 * MODE (RO) 941 * 942 * The modes are: 943 * Mode 0: Disabled: after reset. Program the registers, and DSTx_SRC_EN[n] to enter Mode 1. 944 * Mode 1: Enabled but not activated: After Enabled. Data needed signal can send out, can receive DMA data. Will enter Mode 2 after manual ACT or Fade-in CMD 945 * Mode 2: Enabled and activated and buffer feed-in in progress: Can not be fade out. Will consume data from DMA. If not enter due to Fade-in CMD, will enter Mode 4, else enter Mode 3. This mode is used to make the channel in MIX only after initial data are ready, thus will not stall mix operation due to the lackness of data of this channel omly. 946 * Mode 3: Enabled and activated and fade-in in progress: Can not be fade out. Will consume data from DMA. 947 * Mode 4: Enabled and activated and done fade-in, no fade-out yet: Can be fade out. Will consume data from DMA. 948 * Mode 5: Enabled and activated and fade-out in progress: After faded out done. Will consume data from DMA. Will transfer to mode 6 or mode 7 depending on the SRCn_CTRL[AutoDeactAfterFadeOut_En] cfg 949 * Mode 6: Enabled and activated and faded-out: faded out is done. Will consume data from DMA. Will transfer to mode 7 if manual deactivated. 950 * Mode 7: Enabled and De-activated: If configured to enter this mode, after auto or manuallly fade-out, or after manual de-activated. Won't consume data from DMA. Won't gen data needed signals. Intf register can be programmed. Will change to Mode 2 after manual ACT or Fade-in CMD. Will transfer to Mode 0 if DSTx_SRC_EN[n] is assigned 0. To support a new stream or, to continue the old stream after a pause. 951 */ 952 #define SMIX_SOURCE_CH_ST_MODE_MASK (0x7U) 953 #define SMIX_SOURCE_CH_ST_MODE_SHIFT (0U) 954 #define SMIX_SOURCE_CH_ST_MODE_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_MODE_MASK) >> SMIX_SOURCE_CH_ST_MODE_SHIFT) 955 956 /* Bitfield definition for register of struct array SOURCE_CH: DATA */ 957 /* 958 * VAL (WO) 959 * 960 * Data input register 961 */ 962 #define SMIX_SOURCE_CH_DATA_VAL_MASK (0xFFFFFFFFUL) 963 #define SMIX_SOURCE_CH_DATA_VAL_SHIFT (0U) 964 #define SMIX_SOURCE_CH_DATA_VAL_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_DATA_VAL_SHIFT) & SMIX_SOURCE_CH_DATA_VAL_MASK) 965 #define SMIX_SOURCE_CH_DATA_VAL_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_DATA_VAL_MASK) >> SMIX_SOURCE_CH_DATA_VAL_SHIFT) 966 967 968 969 /* DMA_CH register group index macro definition */ 970 #define SMIX_DMA_CH_0 (0UL) 971 #define SMIX_DMA_CH_1 (1UL) 972 #define SMIX_DMA_CH_2 (2UL) 973 #define SMIX_DMA_CH_3 (3UL) 974 #define SMIX_DMA_CH_4 (4UL) 975 #define SMIX_DMA_CH_5 (5UL) 976 #define SMIX_DMA_CH_6 (6UL) 977 #define SMIX_DMA_CH_7 (7UL) 978 #define SMIX_DMA_CH_8 (8UL) 979 #define SMIX_DMA_CH_9 (9UL) 980 #define SMIX_DMA_CH_10 (10UL) 981 #define SMIX_DMA_CH_11 (11UL) 982 #define SMIX_DMA_CH_12 (12UL) 983 #define SMIX_DMA_CH_13 (13UL) 984 #define SMIX_DMA_CH_14 (14UL) 985 #define SMIX_DMA_CH_15 (15UL) 986 #define SMIX_DMA_CH_16 (16UL) 987 #define SMIX_DMA_CH_17 (17UL) 988 #define SMIX_DMA_CH_18 (18UL) 989 #define SMIX_DMA_CH_19 (19UL) 990 #define SMIX_DMA_CH_20 (20UL) 991 #define SMIX_DMA_CH_21 (21UL) 992 #define SMIX_DMA_CH_22 (22UL) 993 #define SMIX_DMA_CH_23 (23UL) 994 #define SMIX_DMA_CH_24 (24UL) 995 #define SMIX_DMA_CH_25 (25UL) 996 997 /* DST_CH register group index macro definition */ 998 #define SMIX_DST_CH_0 (0UL) 999 #define SMIX_DST_CH_1 (1UL) 1000 1001 /* SOURCE_CH register group index macro definition */ 1002 #define SMIX_SOURCE_CH_0 (0UL) 1003 #define SMIX_SOURCE_CH_1 (1UL) 1004 #define SMIX_SOURCE_CH_2 (2UL) 1005 #define SMIX_SOURCE_CH_3 (3UL) 1006 #define SMIX_SOURCE_CH_4 (4UL) 1007 #define SMIX_SOURCE_CH_5 (5UL) 1008 #define SMIX_SOURCE_CH_6 (6UL) 1009 #define SMIX_SOURCE_CH_7 (7UL) 1010 #define SMIX_SOURCE_CH_8 (8UL) 1011 #define SMIX_SOURCE_CH_9 (9UL) 1012 #define SMIX_SOURCE_CH_10 (10UL) 1013 #define SMIX_SOURCE_CH_11 (11UL) 1014 #define SMIX_SOURCE_CH_12 (12UL) 1015 #define SMIX_SOURCE_CH_13 (13UL) 1016 1017 1018 #endif /* HPM_SMIX_H */ 1019