1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_SPI_H 10 #define HPM_SPI_H 11 12 typedef struct { 13 __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ 14 __RW uint32_t WR_TRANS_CNT; /* 0x4: Transfer count for write data */ 15 __RW uint32_t RD_TRANS_CNT; /* 0x8: Transfer count for read data */ 16 __R uint8_t RESERVED1[4]; /* 0xC - 0xF: Reserved */ 17 __RW uint32_t TRANSFMT; /* 0x10: Transfer Format Register */ 18 __RW uint32_t DIRECTIO; /* 0x14: Direct IO Control Register */ 19 __R uint8_t RESERVED2[8]; /* 0x18 - 0x1F: Reserved */ 20 __RW uint32_t TRANSCTRL; /* 0x20: Transfer Control Register */ 21 __RW uint32_t CMD; /* 0x24: Command Register */ 22 __RW uint32_t ADDR; /* 0x28: Address Register */ 23 __RW uint32_t DATA; /* 0x2C: Data Register */ 24 __RW uint32_t CTRL; /* 0x30: Control Register */ 25 __R uint32_t STATUS; /* 0x34: Status Register */ 26 __RW uint32_t INTREN; /* 0x38: Interrupt Enable Register */ 27 __W uint32_t INTRST; /* 0x3C: Interrupt Status Register */ 28 __RW uint32_t TIMING; /* 0x40: Interface Timing Register */ 29 __R uint8_t RESERVED3[28]; /* 0x44 - 0x5F: Reserved */ 30 __RW uint32_t SLVST; /* 0x60: Slave Status Register */ 31 __R uint32_t SLVDATACNT; /* 0x64: Slave Data Count Register */ 32 __R uint32_t SLVDATAWCNT; /* 0x68: WCnt */ 33 __R uint32_t SLVDATARCNT; /* 0x6C: RCnt */ 34 __R uint8_t RESERVED4[12]; /* 0x70 - 0x7B: Reserved */ 35 __R uint32_t CONFIG; /* 0x7C: Configuration Register */ 36 } SPI_Type; 37 38 39 /* Bitfield definition for register: WR_TRANS_CNT */ 40 /* 41 * WRTRANCNT (RW) 42 * 43 * Transfer count for write data 44 * WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). 45 * WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. 46 * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. 47 * For TransMode 0, WrTranCnt must be equal to RdTranCnt. 48 */ 49 #define SPI_WR_TRANS_CNT_WRTRANCNT_MASK (0xFFFFFFFFUL) 50 #define SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT (0U) 51 #define SPI_WR_TRANS_CNT_WRTRANCNT_SET(x) (((uint32_t)(x) << SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT) & SPI_WR_TRANS_CNT_WRTRANCNT_MASK) 52 #define SPI_WR_TRANS_CNT_WRTRANCNT_GET(x) (((uint32_t)(x) & SPI_WR_TRANS_CNT_WRTRANCNT_MASK) >> SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT) 53 54 /* Bitfield definition for register: RD_TRANS_CNT */ 55 /* 56 * RDTRANCNT (RW) 57 * 58 * Transfer count for read data 59 * RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). 60 * RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. 61 * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. 62 * For TransMode 0, WrTranCnt must equal RdTranCnt. 63 */ 64 #define SPI_RD_TRANS_CNT_RDTRANCNT_MASK (0xFFFFFFFFUL) 65 #define SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT (0U) 66 #define SPI_RD_TRANS_CNT_RDTRANCNT_SET(x) (((uint32_t)(x) << SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT) & SPI_RD_TRANS_CNT_RDTRANCNT_MASK) 67 #define SPI_RD_TRANS_CNT_RDTRANCNT_GET(x) (((uint32_t)(x) & SPI_RD_TRANS_CNT_RDTRANCNT_MASK) >> SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT) 68 69 /* Bitfield definition for register: TRANSFMT */ 70 /* 71 * ADDRLEN (RW) 72 * 73 * Address length in bytes 74 * 0x0: 1 byte 75 * 0x1: 2 bytes 76 * 0x2: 3 bytes 77 * 0x3: 4 bytes 78 */ 79 #define SPI_TRANSFMT_ADDRLEN_MASK (0x30000UL) 80 #define SPI_TRANSFMT_ADDRLEN_SHIFT (16U) 81 #define SPI_TRANSFMT_ADDRLEN_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_ADDRLEN_SHIFT) & SPI_TRANSFMT_ADDRLEN_MASK) 82 #define SPI_TRANSFMT_ADDRLEN_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_ADDRLEN_MASK) >> SPI_TRANSFMT_ADDRLEN_SHIFT) 83 84 /* 85 * DATALEN (RW) 86 * 87 * The length of each data unit in bits 88 * The actual bit number of a data unit is (DataLen + 1) 89 */ 90 #define SPI_TRANSFMT_DATALEN_MASK (0x1F00U) 91 #define SPI_TRANSFMT_DATALEN_SHIFT (8U) 92 #define SPI_TRANSFMT_DATALEN_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_DATALEN_SHIFT) & SPI_TRANSFMT_DATALEN_MASK) 93 #define SPI_TRANSFMT_DATALEN_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_DATALEN_MASK) >> SPI_TRANSFMT_DATALEN_SHIFT) 94 95 /* 96 * DATAMERGE (RW) 97 * 98 * Enable Data Merge mode, which does automatic data split on write and data coalescing on read. 99 * This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. 100 * When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. 101 */ 102 #define SPI_TRANSFMT_DATAMERGE_MASK (0x80U) 103 #define SPI_TRANSFMT_DATAMERGE_SHIFT (7U) 104 #define SPI_TRANSFMT_DATAMERGE_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_DATAMERGE_SHIFT) & SPI_TRANSFMT_DATAMERGE_MASK) 105 #define SPI_TRANSFMT_DATAMERGE_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_DATAMERGE_MASK) >> SPI_TRANSFMT_DATAMERGE_SHIFT) 106 107 /* 108 * MOSIBIDIR (RW) 109 * 110 * Bi-directional MOSI in regular (single) mode 111 * 0x0: MOSI is uni-directional signal in regular mode. 112 * 0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two 113 */ 114 #define SPI_TRANSFMT_MOSIBIDIR_MASK (0x10U) 115 #define SPI_TRANSFMT_MOSIBIDIR_SHIFT (4U) 116 #define SPI_TRANSFMT_MOSIBIDIR_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_MOSIBIDIR_SHIFT) & SPI_TRANSFMT_MOSIBIDIR_MASK) 117 #define SPI_TRANSFMT_MOSIBIDIR_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_MOSIBIDIR_MASK) >> SPI_TRANSFMT_MOSIBIDIR_SHIFT) 118 119 /* 120 * LSB (RW) 121 * 122 * Transfer data with the least significant bit first 123 * 0x0: Most significant bit first 124 * 0x1: Least significant bit first 125 */ 126 #define SPI_TRANSFMT_LSB_MASK (0x8U) 127 #define SPI_TRANSFMT_LSB_SHIFT (3U) 128 #define SPI_TRANSFMT_LSB_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_LSB_SHIFT) & SPI_TRANSFMT_LSB_MASK) 129 #define SPI_TRANSFMT_LSB_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_LSB_MASK) >> SPI_TRANSFMT_LSB_SHIFT) 130 131 /* 132 * SLVMODE (RW) 133 * 134 * SPI Master/Slave mode selection 135 * 0x0: Master mode 136 * 0x1: Slave mode 137 */ 138 #define SPI_TRANSFMT_SLVMODE_MASK (0x4U) 139 #define SPI_TRANSFMT_SLVMODE_SHIFT (2U) 140 #define SPI_TRANSFMT_SLVMODE_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_SLVMODE_SHIFT) & SPI_TRANSFMT_SLVMODE_MASK) 141 #define SPI_TRANSFMT_SLVMODE_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_SLVMODE_MASK) >> SPI_TRANSFMT_SLVMODE_SHIFT) 142 143 /* 144 * CPOL (RW) 145 * 146 * SPI Clock Polarity 147 * 0x0: SCLK is LOW in the idle states 148 * 0x1: SCLK is HIGH in the idle states 149 */ 150 #define SPI_TRANSFMT_CPOL_MASK (0x2U) 151 #define SPI_TRANSFMT_CPOL_SHIFT (1U) 152 #define SPI_TRANSFMT_CPOL_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPOL_SHIFT) & SPI_TRANSFMT_CPOL_MASK) 153 #define SPI_TRANSFMT_CPOL_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPOL_MASK) >> SPI_TRANSFMT_CPOL_SHIFT) 154 155 /* 156 * CPHA (RW) 157 * 158 * SPI Clock Phase 159 * 0x0: Sampling data at odd SCLK edges 160 * 0x1: Sampling data at even SCLK edges 161 */ 162 #define SPI_TRANSFMT_CPHA_MASK (0x1U) 163 #define SPI_TRANSFMT_CPHA_SHIFT (0U) 164 #define SPI_TRANSFMT_CPHA_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPHA_SHIFT) & SPI_TRANSFMT_CPHA_MASK) 165 #define SPI_TRANSFMT_CPHA_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPHA_MASK) >> SPI_TRANSFMT_CPHA_SHIFT) 166 167 /* Bitfield definition for register: DIRECTIO */ 168 /* 169 * DIRECTIOEN (RW) 170 * 171 * Enable Direct IO 172 * 0x0: Disable 173 * 0x1: Enable 174 */ 175 #define SPI_DIRECTIO_DIRECTIOEN_MASK (0x1000000UL) 176 #define SPI_DIRECTIO_DIRECTIOEN_SHIFT (24U) 177 #define SPI_DIRECTIO_DIRECTIOEN_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_DIRECTIOEN_SHIFT) & SPI_DIRECTIO_DIRECTIOEN_MASK) 178 #define SPI_DIRECTIO_DIRECTIOEN_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_DIRECTIOEN_MASK) >> SPI_DIRECTIO_DIRECTIOEN_SHIFT) 179 180 /* 181 * HOLD_OE (RW) 182 * 183 * Output enable for the SPI Flash hold signal 184 */ 185 #define SPI_DIRECTIO_HOLD_OE_MASK (0x200000UL) 186 #define SPI_DIRECTIO_HOLD_OE_SHIFT (21U) 187 #define SPI_DIRECTIO_HOLD_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_HOLD_OE_SHIFT) & SPI_DIRECTIO_HOLD_OE_MASK) 188 #define SPI_DIRECTIO_HOLD_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_OE_MASK) >> SPI_DIRECTIO_HOLD_OE_SHIFT) 189 190 /* 191 * WP_OE (RW) 192 * 193 * Output enable for the SPI Flash write protect signal 194 */ 195 #define SPI_DIRECTIO_WP_OE_MASK (0x100000UL) 196 #define SPI_DIRECTIO_WP_OE_SHIFT (20U) 197 #define SPI_DIRECTIO_WP_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_WP_OE_SHIFT) & SPI_DIRECTIO_WP_OE_MASK) 198 #define SPI_DIRECTIO_WP_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_OE_MASK) >> SPI_DIRECTIO_WP_OE_SHIFT) 199 200 /* 201 * MISO_OE (RW) 202 * 203 * Output enable fo the SPI MISO signal 204 */ 205 #define SPI_DIRECTIO_MISO_OE_MASK (0x80000UL) 206 #define SPI_DIRECTIO_MISO_OE_SHIFT (19U) 207 #define SPI_DIRECTIO_MISO_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MISO_OE_SHIFT) & SPI_DIRECTIO_MISO_OE_MASK) 208 #define SPI_DIRECTIO_MISO_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_OE_MASK) >> SPI_DIRECTIO_MISO_OE_SHIFT) 209 210 /* 211 * MOSI_OE (RW) 212 * 213 * Output enable for the SPI MOSI signal 214 */ 215 #define SPI_DIRECTIO_MOSI_OE_MASK (0x40000UL) 216 #define SPI_DIRECTIO_MOSI_OE_SHIFT (18U) 217 #define SPI_DIRECTIO_MOSI_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MOSI_OE_SHIFT) & SPI_DIRECTIO_MOSI_OE_MASK) 218 #define SPI_DIRECTIO_MOSI_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_OE_MASK) >> SPI_DIRECTIO_MOSI_OE_SHIFT) 219 220 /* 221 * SCLK_OE (RW) 222 * 223 * Output enable for the SPI SCLK signal 224 */ 225 #define SPI_DIRECTIO_SCLK_OE_MASK (0x20000UL) 226 #define SPI_DIRECTIO_SCLK_OE_SHIFT (17U) 227 #define SPI_DIRECTIO_SCLK_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_SCLK_OE_SHIFT) & SPI_DIRECTIO_SCLK_OE_MASK) 228 #define SPI_DIRECTIO_SCLK_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_OE_MASK) >> SPI_DIRECTIO_SCLK_OE_SHIFT) 229 230 /* 231 * CS_OE (RW) 232 * 233 * Output enable for SPI CS (chip select) signal 234 */ 235 #define SPI_DIRECTIO_CS_OE_MASK (0x10000UL) 236 #define SPI_DIRECTIO_CS_OE_SHIFT (16U) 237 #define SPI_DIRECTIO_CS_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_CS_OE_SHIFT) & SPI_DIRECTIO_CS_OE_MASK) 238 #define SPI_DIRECTIO_CS_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_OE_MASK) >> SPI_DIRECTIO_CS_OE_SHIFT) 239 240 /* 241 * HOLD_O (RW) 242 * 243 * Output value for the SPI Flash hold signal 244 */ 245 #define SPI_DIRECTIO_HOLD_O_MASK (0x2000U) 246 #define SPI_DIRECTIO_HOLD_O_SHIFT (13U) 247 #define SPI_DIRECTIO_HOLD_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_HOLD_O_SHIFT) & SPI_DIRECTIO_HOLD_O_MASK) 248 #define SPI_DIRECTIO_HOLD_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_O_MASK) >> SPI_DIRECTIO_HOLD_O_SHIFT) 249 250 /* 251 * WP_O (RW) 252 * 253 * Output value for the SPI Flash write protect signal 254 */ 255 #define SPI_DIRECTIO_WP_O_MASK (0x1000U) 256 #define SPI_DIRECTIO_WP_O_SHIFT (12U) 257 #define SPI_DIRECTIO_WP_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_WP_O_SHIFT) & SPI_DIRECTIO_WP_O_MASK) 258 #define SPI_DIRECTIO_WP_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_O_MASK) >> SPI_DIRECTIO_WP_O_SHIFT) 259 260 /* 261 * MISO_O (RW) 262 * 263 * Output value for the SPI MISO signal 264 */ 265 #define SPI_DIRECTIO_MISO_O_MASK (0x800U) 266 #define SPI_DIRECTIO_MISO_O_SHIFT (11U) 267 #define SPI_DIRECTIO_MISO_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MISO_O_SHIFT) & SPI_DIRECTIO_MISO_O_MASK) 268 #define SPI_DIRECTIO_MISO_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_O_MASK) >> SPI_DIRECTIO_MISO_O_SHIFT) 269 270 /* 271 * MOSI_O (RW) 272 * 273 * Output value for the SPI MOSI signal 274 */ 275 #define SPI_DIRECTIO_MOSI_O_MASK (0x400U) 276 #define SPI_DIRECTIO_MOSI_O_SHIFT (10U) 277 #define SPI_DIRECTIO_MOSI_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MOSI_O_SHIFT) & SPI_DIRECTIO_MOSI_O_MASK) 278 #define SPI_DIRECTIO_MOSI_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_O_MASK) >> SPI_DIRECTIO_MOSI_O_SHIFT) 279 280 /* 281 * SCLK_O (RW) 282 * 283 * Output value for the SPI SCLK signal 284 */ 285 #define SPI_DIRECTIO_SCLK_O_MASK (0x200U) 286 #define SPI_DIRECTIO_SCLK_O_SHIFT (9U) 287 #define SPI_DIRECTIO_SCLK_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_SCLK_O_SHIFT) & SPI_DIRECTIO_SCLK_O_MASK) 288 #define SPI_DIRECTIO_SCLK_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_O_MASK) >> SPI_DIRECTIO_SCLK_O_SHIFT) 289 290 /* 291 * CS_O (RW) 292 * 293 * Output value for the SPI CS (chip select) signal 294 */ 295 #define SPI_DIRECTIO_CS_O_MASK (0x100U) 296 #define SPI_DIRECTIO_CS_O_SHIFT (8U) 297 #define SPI_DIRECTIO_CS_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_CS_O_SHIFT) & SPI_DIRECTIO_CS_O_MASK) 298 #define SPI_DIRECTIO_CS_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_O_MASK) >> SPI_DIRECTIO_CS_O_SHIFT) 299 300 /* 301 * HOLD_I (RO) 302 * 303 * Status of the SPI Flash hold signal 304 */ 305 #define SPI_DIRECTIO_HOLD_I_MASK (0x20U) 306 #define SPI_DIRECTIO_HOLD_I_SHIFT (5U) 307 #define SPI_DIRECTIO_HOLD_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_I_MASK) >> SPI_DIRECTIO_HOLD_I_SHIFT) 308 309 /* 310 * WP_I (RO) 311 * 312 * Status of the SPI Flash write protect signal 313 */ 314 #define SPI_DIRECTIO_WP_I_MASK (0x10U) 315 #define SPI_DIRECTIO_WP_I_SHIFT (4U) 316 #define SPI_DIRECTIO_WP_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_I_MASK) >> SPI_DIRECTIO_WP_I_SHIFT) 317 318 /* 319 * MISO_I (RO) 320 * 321 * Status of the SPI MISO signal 322 */ 323 #define SPI_DIRECTIO_MISO_I_MASK (0x8U) 324 #define SPI_DIRECTIO_MISO_I_SHIFT (3U) 325 #define SPI_DIRECTIO_MISO_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_I_MASK) >> SPI_DIRECTIO_MISO_I_SHIFT) 326 327 /* 328 * MOSI_I (RO) 329 * 330 * Status of the SPI MOSI signal 331 */ 332 #define SPI_DIRECTIO_MOSI_I_MASK (0x4U) 333 #define SPI_DIRECTIO_MOSI_I_SHIFT (2U) 334 #define SPI_DIRECTIO_MOSI_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_I_MASK) >> SPI_DIRECTIO_MOSI_I_SHIFT) 335 336 /* 337 * SCLK_I (RO) 338 * 339 * Status of the SPI SCLK signal 340 */ 341 #define SPI_DIRECTIO_SCLK_I_MASK (0x2U) 342 #define SPI_DIRECTIO_SCLK_I_SHIFT (1U) 343 #define SPI_DIRECTIO_SCLK_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_I_MASK) >> SPI_DIRECTIO_SCLK_I_SHIFT) 344 345 /* 346 * CS_I (RO) 347 * 348 * Status of the SPI CS (chip select) signal 349 */ 350 #define SPI_DIRECTIO_CS_I_MASK (0x1U) 351 #define SPI_DIRECTIO_CS_I_SHIFT (0U) 352 #define SPI_DIRECTIO_CS_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_I_MASK) >> SPI_DIRECTIO_CS_I_SHIFT) 353 354 /* Bitfield definition for register: TRANSCTRL */ 355 /* 356 * SLVDATAONLY (RW) 357 * 358 * Data-only mode (slave mode only) 359 * 0x0: Disable the data-only mode 360 * 0x1: Enable the data-only mode 361 * Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. 362 */ 363 #define SPI_TRANSCTRL_SLVDATAONLY_MASK (0x80000000UL) 364 #define SPI_TRANSCTRL_SLVDATAONLY_SHIFT (31U) 365 #define SPI_TRANSCTRL_SLVDATAONLY_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_SLVDATAONLY_SHIFT) & SPI_TRANSCTRL_SLVDATAONLY_MASK) 366 #define SPI_TRANSCTRL_SLVDATAONLY_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_SLVDATAONLY_MASK) >> SPI_TRANSCTRL_SLVDATAONLY_SHIFT) 367 368 /* 369 * CMDEN (RW) 370 * 371 * SPI command phase enable (Master mode only) 372 * 0x0: Disable the command phase 373 * 0x1: Enable the command phase 374 */ 375 #define SPI_TRANSCTRL_CMDEN_MASK (0x40000000UL) 376 #define SPI_TRANSCTRL_CMDEN_SHIFT (30U) 377 #define SPI_TRANSCTRL_CMDEN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_CMDEN_SHIFT) & SPI_TRANSCTRL_CMDEN_MASK) 378 #define SPI_TRANSCTRL_CMDEN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_CMDEN_MASK) >> SPI_TRANSCTRL_CMDEN_SHIFT) 379 380 /* 381 * ADDREN (RW) 382 * 383 * SPI address phase enable (Master mode only) 384 * 0x0: Disable the address phase 385 * 0x1: Enable the address phase 386 */ 387 #define SPI_TRANSCTRL_ADDREN_MASK (0x20000000UL) 388 #define SPI_TRANSCTRL_ADDREN_SHIFT (29U) 389 #define SPI_TRANSCTRL_ADDREN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_ADDREN_SHIFT) & SPI_TRANSCTRL_ADDREN_MASK) 390 #define SPI_TRANSCTRL_ADDREN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_ADDREN_MASK) >> SPI_TRANSCTRL_ADDREN_SHIFT) 391 392 /* 393 * ADDRFMT (RW) 394 * 395 * SPI address phase format (Master mode only) 396 * 0x0: Address phase is the regular (single) mode 397 * 0x1: The format of the address phase is the same as the data phase (DualQuad). 398 */ 399 #define SPI_TRANSCTRL_ADDRFMT_MASK (0x10000000UL) 400 #define SPI_TRANSCTRL_ADDRFMT_SHIFT (28U) 401 #define SPI_TRANSCTRL_ADDRFMT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_ADDRFMT_SHIFT) & SPI_TRANSCTRL_ADDRFMT_MASK) 402 #define SPI_TRANSCTRL_ADDRFMT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_ADDRFMT_MASK) >> SPI_TRANSCTRL_ADDRFMT_SHIFT) 403 404 /* 405 * TRANSMODE (RW) 406 * 407 * Transfer mode 408 * The transfer sequence could be 409 * 0x0: Write and read at the same time 410 * 0x1: Write only 411 * 0x2: Read only 412 * 0x3: Write, Read 413 * 0x4: Read, Write 414 * 0x5: Write, Dummy, Read 415 * 0x6: Read, Dummy, Write 416 * 0x7: None Data (must enable CmdEn or AddrEn in master mode) 417 * 0x8: Dummy, Write 418 * 0x9: Dummy, Read 419 * 0xa~0xf: Reserved 420 */ 421 #define SPI_TRANSCTRL_TRANSMODE_MASK (0xF000000UL) 422 #define SPI_TRANSCTRL_TRANSMODE_SHIFT (24U) 423 #define SPI_TRANSCTRL_TRANSMODE_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TRANSMODE_SHIFT) & SPI_TRANSCTRL_TRANSMODE_MASK) 424 #define SPI_TRANSCTRL_TRANSMODE_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TRANSMODE_MASK) >> SPI_TRANSCTRL_TRANSMODE_SHIFT) 425 426 /* 427 * DUALQUAD (RW) 428 * 429 * SPI data phase format 430 * 0x0: Regular (Single) mode 431 * 0x1: Dual I/O mode 432 * 0x2: Quad I/O mode 433 * 0x3: Reserved 434 */ 435 #define SPI_TRANSCTRL_DUALQUAD_MASK (0xC00000UL) 436 #define SPI_TRANSCTRL_DUALQUAD_SHIFT (22U) 437 #define SPI_TRANSCTRL_DUALQUAD_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_DUALQUAD_SHIFT) & SPI_TRANSCTRL_DUALQUAD_MASK) 438 #define SPI_TRANSCTRL_DUALQUAD_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_DUALQUAD_MASK) >> SPI_TRANSCTRL_DUALQUAD_SHIFT) 439 440 /* 441 * TOKENEN (RW) 442 * 443 * Token transfer enable (Master mode only) 444 * Append an one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. 445 * 0x0: Disable the one-byte special token 446 * 0x1: Enable the one-byte special token 447 */ 448 #define SPI_TRANSCTRL_TOKENEN_MASK (0x200000UL) 449 #define SPI_TRANSCTRL_TOKENEN_SHIFT (21U) 450 #define SPI_TRANSCTRL_TOKENEN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TOKENEN_SHIFT) & SPI_TRANSCTRL_TOKENEN_MASK) 451 #define SPI_TRANSCTRL_TOKENEN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TOKENEN_MASK) >> SPI_TRANSCTRL_TOKENEN_SHIFT) 452 453 /* 454 * WRTRANCNT (RW) 455 * 456 * Transfer count for write data 457 * WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). 458 * WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. 459 * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. 460 * For TransMode 0, WrTranCnt must be equal to RdTranCnt. 461 */ 462 #define SPI_TRANSCTRL_WRTRANCNT_MASK (0x1FF000UL) 463 #define SPI_TRANSCTRL_WRTRANCNT_SHIFT (12U) 464 #define SPI_TRANSCTRL_WRTRANCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_WRTRANCNT_SHIFT) & SPI_TRANSCTRL_WRTRANCNT_MASK) 465 #define SPI_TRANSCTRL_WRTRANCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_WRTRANCNT_MASK) >> SPI_TRANSCTRL_WRTRANCNT_SHIFT) 466 467 /* 468 * TOKENVALUE (RW) 469 * 470 * Token value (Master mode only) 471 * The value of the one-byte special token following the address phase for SPI read transfers. 472 * 0x0: token value = 0x00 473 * 0x1: token value = 0x69 474 */ 475 #define SPI_TRANSCTRL_TOKENVALUE_MASK (0x800U) 476 #define SPI_TRANSCTRL_TOKENVALUE_SHIFT (11U) 477 #define SPI_TRANSCTRL_TOKENVALUE_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TOKENVALUE_SHIFT) & SPI_TRANSCTRL_TOKENVALUE_MASK) 478 #define SPI_TRANSCTRL_TOKENVALUE_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TOKENVALUE_MASK) >> SPI_TRANSCTRL_TOKENVALUE_SHIFT) 479 480 /* 481 * DUMMYCNT (RW) 482 * 483 * Dummy data count. The actual dummy count is (DummyCnt +1). 484 * The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) 485 * The Data pins are put into the high impedance during the dummy data phase. 486 * DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. 487 */ 488 #define SPI_TRANSCTRL_DUMMYCNT_MASK (0x600U) 489 #define SPI_TRANSCTRL_DUMMYCNT_SHIFT (9U) 490 #define SPI_TRANSCTRL_DUMMYCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_DUMMYCNT_SHIFT) & SPI_TRANSCTRL_DUMMYCNT_MASK) 491 #define SPI_TRANSCTRL_DUMMYCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_DUMMYCNT_MASK) >> SPI_TRANSCTRL_DUMMYCNT_SHIFT) 492 493 /* 494 * RDTRANCNT (RW) 495 * 496 * Transfer count for read data 497 * RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). 498 * RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. 499 * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. 500 * For TransMode 0, WrTranCnt must equal RdTranCnt. 501 */ 502 #define SPI_TRANSCTRL_RDTRANCNT_MASK (0x1FFU) 503 #define SPI_TRANSCTRL_RDTRANCNT_SHIFT (0U) 504 #define SPI_TRANSCTRL_RDTRANCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_RDTRANCNT_SHIFT) & SPI_TRANSCTRL_RDTRANCNT_MASK) 505 #define SPI_TRANSCTRL_RDTRANCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_RDTRANCNT_MASK) >> SPI_TRANSCTRL_RDTRANCNT_SHIFT) 506 507 /* Bitfield definition for register: CMD */ 508 /* 509 * CMD (RW) 510 * 511 * SPI Command 512 */ 513 #define SPI_CMD_CMD_MASK (0xFFU) 514 #define SPI_CMD_CMD_SHIFT (0U) 515 #define SPI_CMD_CMD_SET(x) (((uint32_t)(x) << SPI_CMD_CMD_SHIFT) & SPI_CMD_CMD_MASK) 516 #define SPI_CMD_CMD_GET(x) (((uint32_t)(x) & SPI_CMD_CMD_MASK) >> SPI_CMD_CMD_SHIFT) 517 518 /* Bitfield definition for register: ADDR */ 519 /* 520 * ADDR (RW) 521 * 522 * SPI Address 523 * (Master mode only) 524 */ 525 #define SPI_ADDR_ADDR_MASK (0xFFFFFFFFUL) 526 #define SPI_ADDR_ADDR_SHIFT (0U) 527 #define SPI_ADDR_ADDR_SET(x) (((uint32_t)(x) << SPI_ADDR_ADDR_SHIFT) & SPI_ADDR_ADDR_MASK) 528 #define SPI_ADDR_ADDR_GET(x) (((uint32_t)(x) & SPI_ADDR_ADDR_MASK) >> SPI_ADDR_ADDR_SHIFT) 529 530 /* Bitfield definition for register: DATA */ 531 /* 532 * DATA (RW) 533 * 534 * Data to transmit or the received data 535 * For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. 536 * For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. 537 * The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. 538 * If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. 539 */ 540 #define SPI_DATA_DATA_MASK (0xFFFFFFFFUL) 541 #define SPI_DATA_DATA_SHIFT (0U) 542 #define SPI_DATA_DATA_SET(x) (((uint32_t)(x) << SPI_DATA_DATA_SHIFT) & SPI_DATA_DATA_MASK) 543 #define SPI_DATA_DATA_GET(x) (((uint32_t)(x) & SPI_DATA_DATA_MASK) >> SPI_DATA_DATA_SHIFT) 544 545 /* Bitfield definition for register: CTRL */ 546 /* 547 * CS_EN (RW) 548 * 549 */ 550 #define SPI_CTRL_CS_EN_MASK (0xF000000UL) 551 #define SPI_CTRL_CS_EN_SHIFT (24U) 552 #define SPI_CTRL_CS_EN_SET(x) (((uint32_t)(x) << SPI_CTRL_CS_EN_SHIFT) & SPI_CTRL_CS_EN_MASK) 553 #define SPI_CTRL_CS_EN_GET(x) (((uint32_t)(x) & SPI_CTRL_CS_EN_MASK) >> SPI_CTRL_CS_EN_SHIFT) 554 555 /* 556 * TXTHRES (RW) 557 * 558 * Transmit (TX) FIFO Threshold 559 * The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. 560 */ 561 #define SPI_CTRL_TXTHRES_MASK (0xFF0000UL) 562 #define SPI_CTRL_TXTHRES_SHIFT (16U) 563 #define SPI_CTRL_TXTHRES_SET(x) (((uint32_t)(x) << SPI_CTRL_TXTHRES_SHIFT) & SPI_CTRL_TXTHRES_MASK) 564 #define SPI_CTRL_TXTHRES_GET(x) (((uint32_t)(x) & SPI_CTRL_TXTHRES_MASK) >> SPI_CTRL_TXTHRES_SHIFT) 565 566 /* 567 * RXTHRES (RW) 568 * 569 * Receive (RX) FIFO Threshold 570 * The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. 571 */ 572 #define SPI_CTRL_RXTHRES_MASK (0xFF00U) 573 #define SPI_CTRL_RXTHRES_SHIFT (8U) 574 #define SPI_CTRL_RXTHRES_SET(x) (((uint32_t)(x) << SPI_CTRL_RXTHRES_SHIFT) & SPI_CTRL_RXTHRES_MASK) 575 #define SPI_CTRL_RXTHRES_GET(x) (((uint32_t)(x) & SPI_CTRL_RXTHRES_MASK) >> SPI_CTRL_RXTHRES_SHIFT) 576 577 /* 578 * TXDMAEN (RW) 579 * 580 * TX DMA enable 581 */ 582 #define SPI_CTRL_TXDMAEN_MASK (0x10U) 583 #define SPI_CTRL_TXDMAEN_SHIFT (4U) 584 #define SPI_CTRL_TXDMAEN_SET(x) (((uint32_t)(x) << SPI_CTRL_TXDMAEN_SHIFT) & SPI_CTRL_TXDMAEN_MASK) 585 #define SPI_CTRL_TXDMAEN_GET(x) (((uint32_t)(x) & SPI_CTRL_TXDMAEN_MASK) >> SPI_CTRL_TXDMAEN_SHIFT) 586 587 /* 588 * RXDMAEN (RW) 589 * 590 * RX DMA enable 591 */ 592 #define SPI_CTRL_RXDMAEN_MASK (0x8U) 593 #define SPI_CTRL_RXDMAEN_SHIFT (3U) 594 #define SPI_CTRL_RXDMAEN_SET(x) (((uint32_t)(x) << SPI_CTRL_RXDMAEN_SHIFT) & SPI_CTRL_RXDMAEN_MASK) 595 #define SPI_CTRL_RXDMAEN_GET(x) (((uint32_t)(x) & SPI_CTRL_RXDMAEN_MASK) >> SPI_CTRL_RXDMAEN_SHIFT) 596 597 /* 598 * TXFIFORST (RW) 599 * 600 * Transmit FIFO reset 601 * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. 602 */ 603 #define SPI_CTRL_TXFIFORST_MASK (0x4U) 604 #define SPI_CTRL_TXFIFORST_SHIFT (2U) 605 #define SPI_CTRL_TXFIFORST_SET(x) (((uint32_t)(x) << SPI_CTRL_TXFIFORST_SHIFT) & SPI_CTRL_TXFIFORST_MASK) 606 #define SPI_CTRL_TXFIFORST_GET(x) (((uint32_t)(x) & SPI_CTRL_TXFIFORST_MASK) >> SPI_CTRL_TXFIFORST_SHIFT) 607 608 /* 609 * RXFIFORST (RW) 610 * 611 * Receive FIFO reset 612 * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. 613 */ 614 #define SPI_CTRL_RXFIFORST_MASK (0x2U) 615 #define SPI_CTRL_RXFIFORST_SHIFT (1U) 616 #define SPI_CTRL_RXFIFORST_SET(x) (((uint32_t)(x) << SPI_CTRL_RXFIFORST_SHIFT) & SPI_CTRL_RXFIFORST_MASK) 617 #define SPI_CTRL_RXFIFORST_GET(x) (((uint32_t)(x) & SPI_CTRL_RXFIFORST_MASK) >> SPI_CTRL_RXFIFORST_SHIFT) 618 619 /* 620 * SPIRST (RW) 621 * 622 * SPI reset 623 * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. 624 */ 625 #define SPI_CTRL_SPIRST_MASK (0x1U) 626 #define SPI_CTRL_SPIRST_SHIFT (0U) 627 #define SPI_CTRL_SPIRST_SET(x) (((uint32_t)(x) << SPI_CTRL_SPIRST_SHIFT) & SPI_CTRL_SPIRST_MASK) 628 #define SPI_CTRL_SPIRST_GET(x) (((uint32_t)(x) & SPI_CTRL_SPIRST_MASK) >> SPI_CTRL_SPIRST_SHIFT) 629 630 /* Bitfield definition for register: STATUS */ 631 /* 632 * TXNUM_7_6 (RO) 633 * 634 * Number of valid entries in the Transmit FIFO 635 */ 636 #define SPI_STATUS_TXNUM_7_6_MASK (0x30000000UL) 637 #define SPI_STATUS_TXNUM_7_6_SHIFT (28U) 638 #define SPI_STATUS_TXNUM_7_6_GET(x) (((uint32_t)(x) & SPI_STATUS_TXNUM_7_6_MASK) >> SPI_STATUS_TXNUM_7_6_SHIFT) 639 640 /* 641 * RXNUM_7_6 (RO) 642 * 643 * Number of valid entries in the Receive FIFO 644 */ 645 #define SPI_STATUS_RXNUM_7_6_MASK (0x3000000UL) 646 #define SPI_STATUS_RXNUM_7_6_SHIFT (24U) 647 #define SPI_STATUS_RXNUM_7_6_GET(x) (((uint32_t)(x) & SPI_STATUS_RXNUM_7_6_MASK) >> SPI_STATUS_RXNUM_7_6_SHIFT) 648 649 /* 650 * TXFULL (RO) 651 * 652 * Transmit FIFO Full flag 653 */ 654 #define SPI_STATUS_TXFULL_MASK (0x800000UL) 655 #define SPI_STATUS_TXFULL_SHIFT (23U) 656 #define SPI_STATUS_TXFULL_GET(x) (((uint32_t)(x) & SPI_STATUS_TXFULL_MASK) >> SPI_STATUS_TXFULL_SHIFT) 657 658 /* 659 * TXEMPTY (RO) 660 * 661 * Transmit FIFO Empty flag 662 */ 663 #define SPI_STATUS_TXEMPTY_MASK (0x400000UL) 664 #define SPI_STATUS_TXEMPTY_SHIFT (22U) 665 #define SPI_STATUS_TXEMPTY_GET(x) (((uint32_t)(x) & SPI_STATUS_TXEMPTY_MASK) >> SPI_STATUS_TXEMPTY_SHIFT) 666 667 /* 668 * TXNUM_5_0 (RO) 669 * 670 * Number of valid entries in the Transmit FIFO 671 */ 672 #define SPI_STATUS_TXNUM_5_0_MASK (0x3F0000UL) 673 #define SPI_STATUS_TXNUM_5_0_SHIFT (16U) 674 #define SPI_STATUS_TXNUM_5_0_GET(x) (((uint32_t)(x) & SPI_STATUS_TXNUM_5_0_MASK) >> SPI_STATUS_TXNUM_5_0_SHIFT) 675 676 /* 677 * RXFULL (RO) 678 * 679 * Receive FIFO Full flag 680 */ 681 #define SPI_STATUS_RXFULL_MASK (0x8000U) 682 #define SPI_STATUS_RXFULL_SHIFT (15U) 683 #define SPI_STATUS_RXFULL_GET(x) (((uint32_t)(x) & SPI_STATUS_RXFULL_MASK) >> SPI_STATUS_RXFULL_SHIFT) 684 685 /* 686 * RXEMPTY (RO) 687 * 688 * Receive FIFO Empty flag 689 */ 690 #define SPI_STATUS_RXEMPTY_MASK (0x4000U) 691 #define SPI_STATUS_RXEMPTY_SHIFT (14U) 692 #define SPI_STATUS_RXEMPTY_GET(x) (((uint32_t)(x) & SPI_STATUS_RXEMPTY_MASK) >> SPI_STATUS_RXEMPTY_SHIFT) 693 694 /* 695 * RXNUM_5_0 (RO) 696 * 697 * Number of valid entries in the Receive FIFO 698 */ 699 #define SPI_STATUS_RXNUM_5_0_MASK (0x3F00U) 700 #define SPI_STATUS_RXNUM_5_0_SHIFT (8U) 701 #define SPI_STATUS_RXNUM_5_0_GET(x) (((uint32_t)(x) & SPI_STATUS_RXNUM_5_0_MASK) >> SPI_STATUS_RXNUM_5_0_SHIFT) 702 703 /* 704 * SPIACTIVE (RO) 705 * 706 * SPI register programming is in progress. 707 * In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. 708 * In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. 709 * Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. 710 * Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. 711 */ 712 #define SPI_STATUS_SPIACTIVE_MASK (0x1U) 713 #define SPI_STATUS_SPIACTIVE_SHIFT (0U) 714 #define SPI_STATUS_SPIACTIVE_GET(x) (((uint32_t)(x) & SPI_STATUS_SPIACTIVE_MASK) >> SPI_STATUS_SPIACTIVE_SHIFT) 715 716 /* Bitfield definition for register: INTREN */ 717 /* 718 * SLVCMDEN (RW) 719 * 720 * Enable the Slave Command Interrupt. 721 * Control whether interrupts are triggered whenever slave commands are received. 722 * (Slave mode only) 723 */ 724 #define SPI_INTREN_SLVCMDEN_MASK (0x20U) 725 #define SPI_INTREN_SLVCMDEN_SHIFT (5U) 726 #define SPI_INTREN_SLVCMDEN_SET(x) (((uint32_t)(x) << SPI_INTREN_SLVCMDEN_SHIFT) & SPI_INTREN_SLVCMDEN_MASK) 727 #define SPI_INTREN_SLVCMDEN_GET(x) (((uint32_t)(x) & SPI_INTREN_SLVCMDEN_MASK) >> SPI_INTREN_SLVCMDEN_SHIFT) 728 729 /* 730 * ENDINTEN (RW) 731 * 732 * Enable the End of SPI Transfer interrupt. 733 * Control whether interrupts are triggered when SPI transfers end. 734 * (In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) 735 */ 736 #define SPI_INTREN_ENDINTEN_MASK (0x10U) 737 #define SPI_INTREN_ENDINTEN_SHIFT (4U) 738 #define SPI_INTREN_ENDINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_ENDINTEN_SHIFT) & SPI_INTREN_ENDINTEN_MASK) 739 #define SPI_INTREN_ENDINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_ENDINTEN_MASK) >> SPI_INTREN_ENDINTEN_SHIFT) 740 741 /* 742 * TXFIFOINTEN (RW) 743 * 744 * Enable the SPI Transmit FIFO Threshold interrupt. 745 * Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. 746 */ 747 #define SPI_INTREN_TXFIFOINTEN_MASK (0x8U) 748 #define SPI_INTREN_TXFIFOINTEN_SHIFT (3U) 749 #define SPI_INTREN_TXFIFOINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_TXFIFOINTEN_SHIFT) & SPI_INTREN_TXFIFOINTEN_MASK) 750 #define SPI_INTREN_TXFIFOINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_TXFIFOINTEN_MASK) >> SPI_INTREN_TXFIFOINTEN_SHIFT) 751 752 /* 753 * RXFIFOINTEN (RW) 754 * 755 * Enable the SPI Receive FIFO Threshold interrupt. 756 * Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. 757 */ 758 #define SPI_INTREN_RXFIFOINTEN_MASK (0x4U) 759 #define SPI_INTREN_RXFIFOINTEN_SHIFT (2U) 760 #define SPI_INTREN_RXFIFOINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_RXFIFOINTEN_SHIFT) & SPI_INTREN_RXFIFOINTEN_MASK) 761 #define SPI_INTREN_RXFIFOINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_RXFIFOINTEN_MASK) >> SPI_INTREN_RXFIFOINTEN_SHIFT) 762 763 /* 764 * TXFIFOURINTEN (RW) 765 * 766 * Enable the SPI Transmit FIFO Underrun interrupt. 767 * Control whether interrupts are triggered when the Transmit FIFO run out of data. 768 * (Slave mode only) 769 */ 770 #define SPI_INTREN_TXFIFOURINTEN_MASK (0x2U) 771 #define SPI_INTREN_TXFIFOURINTEN_SHIFT (1U) 772 #define SPI_INTREN_TXFIFOURINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_TXFIFOURINTEN_SHIFT) & SPI_INTREN_TXFIFOURINTEN_MASK) 773 #define SPI_INTREN_TXFIFOURINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_TXFIFOURINTEN_MASK) >> SPI_INTREN_TXFIFOURINTEN_SHIFT) 774 775 /* 776 * RXFIFOORINTEN (RW) 777 * 778 * Enable the SPI Receive FIFO Overrun interrupt. 779 * Control whether interrupts are triggered when the Receive FIFO overflows. 780 * (Slave mode only) 781 */ 782 #define SPI_INTREN_RXFIFOORINTEN_MASK (0x1U) 783 #define SPI_INTREN_RXFIFOORINTEN_SHIFT (0U) 784 #define SPI_INTREN_RXFIFOORINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_RXFIFOORINTEN_SHIFT) & SPI_INTREN_RXFIFOORINTEN_MASK) 785 #define SPI_INTREN_RXFIFOORINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_RXFIFOORINTEN_MASK) >> SPI_INTREN_RXFIFOORINTEN_SHIFT) 786 787 /* Bitfield definition for register: INTRST */ 788 /* 789 * SLVCMDINT (W1C) 790 * 791 * Slave Command Interrupt. 792 * This bit is set when Slave Command interrupts occur. 793 * (Slave mode only) 794 */ 795 #define SPI_INTRST_SLVCMDINT_MASK (0x20U) 796 #define SPI_INTRST_SLVCMDINT_SHIFT (5U) 797 #define SPI_INTRST_SLVCMDINT_SET(x) (((uint32_t)(x) << SPI_INTRST_SLVCMDINT_SHIFT) & SPI_INTRST_SLVCMDINT_MASK) 798 #define SPI_INTRST_SLVCMDINT_GET(x) (((uint32_t)(x) & SPI_INTRST_SLVCMDINT_MASK) >> SPI_INTRST_SLVCMDINT_SHIFT) 799 800 /* 801 * ENDINT (W1C) 802 * 803 * End of SPI Transfer interrupt. 804 * This bit is set when End of SPI Transfer interrupts occur. 805 */ 806 #define SPI_INTRST_ENDINT_MASK (0x10U) 807 #define SPI_INTRST_ENDINT_SHIFT (4U) 808 #define SPI_INTRST_ENDINT_SET(x) (((uint32_t)(x) << SPI_INTRST_ENDINT_SHIFT) & SPI_INTRST_ENDINT_MASK) 809 #define SPI_INTRST_ENDINT_GET(x) (((uint32_t)(x) & SPI_INTRST_ENDINT_MASK) >> SPI_INTRST_ENDINT_SHIFT) 810 811 /* 812 * TXFIFOINT (W1C) 813 * 814 * TX FIFO Threshold interrupt. 815 * This bit is set when TX FIFO Threshold interrupts occur. 816 */ 817 #define SPI_INTRST_TXFIFOINT_MASK (0x8U) 818 #define SPI_INTRST_TXFIFOINT_SHIFT (3U) 819 #define SPI_INTRST_TXFIFOINT_SET(x) (((uint32_t)(x) << SPI_INTRST_TXFIFOINT_SHIFT) & SPI_INTRST_TXFIFOINT_MASK) 820 #define SPI_INTRST_TXFIFOINT_GET(x) (((uint32_t)(x) & SPI_INTRST_TXFIFOINT_MASK) >> SPI_INTRST_TXFIFOINT_SHIFT) 821 822 /* 823 * RXFIFOINT (W1C) 824 * 825 * RX FIFO Threshold interrupt. 826 * This bit is set when RX FIFO Threshold interrupts occur. 827 */ 828 #define SPI_INTRST_RXFIFOINT_MASK (0x4U) 829 #define SPI_INTRST_RXFIFOINT_SHIFT (2U) 830 #define SPI_INTRST_RXFIFOINT_SET(x) (((uint32_t)(x) << SPI_INTRST_RXFIFOINT_SHIFT) & SPI_INTRST_RXFIFOINT_MASK) 831 #define SPI_INTRST_RXFIFOINT_GET(x) (((uint32_t)(x) & SPI_INTRST_RXFIFOINT_MASK) >> SPI_INTRST_RXFIFOINT_SHIFT) 832 833 /* 834 * TXFIFOURINT (W1C) 835 * 836 * TX FIFO Underrun interrupt. 837 * This bit is set when TX FIFO Underrun interrupts occur. 838 * (Slave mode only) 839 */ 840 #define SPI_INTRST_TXFIFOURINT_MASK (0x2U) 841 #define SPI_INTRST_TXFIFOURINT_SHIFT (1U) 842 #define SPI_INTRST_TXFIFOURINT_SET(x) (((uint32_t)(x) << SPI_INTRST_TXFIFOURINT_SHIFT) & SPI_INTRST_TXFIFOURINT_MASK) 843 #define SPI_INTRST_TXFIFOURINT_GET(x) (((uint32_t)(x) & SPI_INTRST_TXFIFOURINT_MASK) >> SPI_INTRST_TXFIFOURINT_SHIFT) 844 845 /* 846 * RXFIFOORINT (W1C) 847 * 848 * RX FIFO Overrun interrupt. 849 * This bit is set when RX FIFO Overrun interrupts occur. 850 * (Slave mode only) 851 */ 852 #define SPI_INTRST_RXFIFOORINT_MASK (0x1U) 853 #define SPI_INTRST_RXFIFOORINT_SHIFT (0U) 854 #define SPI_INTRST_RXFIFOORINT_SET(x) (((uint32_t)(x) << SPI_INTRST_RXFIFOORINT_SHIFT) & SPI_INTRST_RXFIFOORINT_MASK) 855 #define SPI_INTRST_RXFIFOORINT_GET(x) (((uint32_t)(x) & SPI_INTRST_RXFIFOORINT_MASK) >> SPI_INTRST_RXFIFOORINT_SHIFT) 856 857 /* Bitfield definition for register: TIMING */ 858 /* 859 * CS2SCLK (RW) 860 * 861 * The minimum time between the edges of SPI CS and the edges of SCLK. 862 * SCLK_period * (CS2SCLK + 1) / 2 863 */ 864 #define SPI_TIMING_CS2SCLK_MASK (0x3000U) 865 #define SPI_TIMING_CS2SCLK_SHIFT (12U) 866 #define SPI_TIMING_CS2SCLK_SET(x) (((uint32_t)(x) << SPI_TIMING_CS2SCLK_SHIFT) & SPI_TIMING_CS2SCLK_MASK) 867 #define SPI_TIMING_CS2SCLK_GET(x) (((uint32_t)(x) & SPI_TIMING_CS2SCLK_MASK) >> SPI_TIMING_CS2SCLK_SHIFT) 868 869 /* 870 * CSHT (RW) 871 * 872 * The minimum time that SPI CS should stay HIGH. 873 * SCLK_period * (CSHT + 1) / 2 874 */ 875 #define SPI_TIMING_CSHT_MASK (0xF00U) 876 #define SPI_TIMING_CSHT_SHIFT (8U) 877 #define SPI_TIMING_CSHT_SET(x) (((uint32_t)(x) << SPI_TIMING_CSHT_SHIFT) & SPI_TIMING_CSHT_MASK) 878 #define SPI_TIMING_CSHT_GET(x) (((uint32_t)(x) & SPI_TIMING_CSHT_MASK) >> SPI_TIMING_CSHT_SHIFT) 879 880 /* 881 * SCLK_DIV (RW) 882 * 883 * The clock frequency ratio between the clock source and SPI interface SCLK. 884 * SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) 885 * The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. 886 */ 887 #define SPI_TIMING_SCLK_DIV_MASK (0xFFU) 888 #define SPI_TIMING_SCLK_DIV_SHIFT (0U) 889 #define SPI_TIMING_SCLK_DIV_SET(x) (((uint32_t)(x) << SPI_TIMING_SCLK_DIV_SHIFT) & SPI_TIMING_SCLK_DIV_MASK) 890 #define SPI_TIMING_SCLK_DIV_GET(x) (((uint32_t)(x) & SPI_TIMING_SCLK_DIV_MASK) >> SPI_TIMING_SCLK_DIV_SHIFT) 891 892 /* Bitfield definition for register: SLVST */ 893 /* 894 * UNDERRUN (W1C) 895 * 896 * Data underrun occurs in the last transaction 897 */ 898 #define SPI_SLVST_UNDERRUN_MASK (0x40000UL) 899 #define SPI_SLVST_UNDERRUN_SHIFT (18U) 900 #define SPI_SLVST_UNDERRUN_SET(x) (((uint32_t)(x) << SPI_SLVST_UNDERRUN_SHIFT) & SPI_SLVST_UNDERRUN_MASK) 901 #define SPI_SLVST_UNDERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_UNDERRUN_MASK) >> SPI_SLVST_UNDERRUN_SHIFT) 902 903 /* 904 * OVERRUN (RW) 905 * 906 * Data overrun occurs in the last transaction 907 */ 908 #define SPI_SLVST_OVERRUN_MASK (0x20000UL) 909 #define SPI_SLVST_OVERRUN_SHIFT (17U) 910 #define SPI_SLVST_OVERRUN_SET(x) (((uint32_t)(x) << SPI_SLVST_OVERRUN_SHIFT) & SPI_SLVST_OVERRUN_MASK) 911 #define SPI_SLVST_OVERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_OVERRUN_MASK) >> SPI_SLVST_OVERRUN_SHIFT) 912 913 /* 914 * READY (RW) 915 * 916 * Set this bit to indicate that the ATCSPI200 is ready for data transaction. 917 * When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. 918 */ 919 #define SPI_SLVST_READY_MASK (0x10000UL) 920 #define SPI_SLVST_READY_SHIFT (16U) 921 #define SPI_SLVST_READY_SET(x) (((uint32_t)(x) << SPI_SLVST_READY_SHIFT) & SPI_SLVST_READY_MASK) 922 #define SPI_SLVST_READY_GET(x) (((uint32_t)(x) & SPI_SLVST_READY_MASK) >> SPI_SLVST_READY_SHIFT) 923 924 /* 925 * USR_STATUS (RW) 926 * 927 * User defined status flags 928 */ 929 #define SPI_SLVST_USR_STATUS_MASK (0xFFFFU) 930 #define SPI_SLVST_USR_STATUS_SHIFT (0U) 931 #define SPI_SLVST_USR_STATUS_SET(x) (((uint32_t)(x) << SPI_SLVST_USR_STATUS_SHIFT) & SPI_SLVST_USR_STATUS_MASK) 932 #define SPI_SLVST_USR_STATUS_GET(x) (((uint32_t)(x) & SPI_SLVST_USR_STATUS_MASK) >> SPI_SLVST_USR_STATUS_SHIFT) 933 934 /* Bitfield definition for register: SLVDATACNT */ 935 /* 936 * WCNT (RO) 937 * 938 * Slave transmitted data count 939 */ 940 #define SPI_SLVDATACNT_WCNT_MASK (0x3FF0000UL) 941 #define SPI_SLVDATACNT_WCNT_SHIFT (16U) 942 #define SPI_SLVDATACNT_WCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_WCNT_MASK) >> SPI_SLVDATACNT_WCNT_SHIFT) 943 944 /* 945 * RCNT (RO) 946 * 947 * Slave received data count 948 */ 949 #define SPI_SLVDATACNT_RCNT_MASK (0x3FFU) 950 #define SPI_SLVDATACNT_RCNT_SHIFT (0U) 951 #define SPI_SLVDATACNT_RCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_RCNT_MASK) >> SPI_SLVDATACNT_RCNT_SHIFT) 952 953 /* Bitfield definition for register: SLVDATAWCNT */ 954 /* 955 * VAL (RO) 956 * 957 */ 958 #define SPI_SLVDATAWCNT_VAL_MASK (0xFFFFFFFFUL) 959 #define SPI_SLVDATAWCNT_VAL_SHIFT (0U) 960 #define SPI_SLVDATAWCNT_VAL_GET(x) (((uint32_t)(x) & SPI_SLVDATAWCNT_VAL_MASK) >> SPI_SLVDATAWCNT_VAL_SHIFT) 961 962 /* Bitfield definition for register: SLVDATARCNT */ 963 /* 964 * VAL (RO) 965 * 966 */ 967 #define SPI_SLVDATARCNT_VAL_MASK (0xFFFFFFFFUL) 968 #define SPI_SLVDATARCNT_VAL_SHIFT (0U) 969 #define SPI_SLVDATARCNT_VAL_GET(x) (((uint32_t)(x) & SPI_SLVDATARCNT_VAL_MASK) >> SPI_SLVDATARCNT_VAL_SHIFT) 970 971 /* Bitfield definition for register: CONFIG */ 972 /* 973 * SLAVE (RO) 974 * 975 * Support for SPI Slave mode 976 */ 977 #define SPI_CONFIG_SLAVE_MASK (0x4000U) 978 #define SPI_CONFIG_SLAVE_SHIFT (14U) 979 #define SPI_CONFIG_SLAVE_GET(x) (((uint32_t)(x) & SPI_CONFIG_SLAVE_MASK) >> SPI_CONFIG_SLAVE_SHIFT) 980 981 /* 982 * QUADSPI (RO) 983 * 984 * Support for Quad I/O SPI 985 */ 986 #define SPI_CONFIG_QUADSPI_MASK (0x200U) 987 #define SPI_CONFIG_QUADSPI_SHIFT (9U) 988 #define SPI_CONFIG_QUADSPI_GET(x) (((uint32_t)(x) & SPI_CONFIG_QUADSPI_MASK) >> SPI_CONFIG_QUADSPI_SHIFT) 989 990 /* 991 * DUALSPI (RO) 992 * 993 * Support for Dual I/O SPI 994 */ 995 #define SPI_CONFIG_DUALSPI_MASK (0x100U) 996 #define SPI_CONFIG_DUALSPI_SHIFT (8U) 997 #define SPI_CONFIG_DUALSPI_GET(x) (((uint32_t)(x) & SPI_CONFIG_DUALSPI_MASK) >> SPI_CONFIG_DUALSPI_SHIFT) 998 999 /* 1000 * TXFIFOSIZE (RO) 1001 * 1002 * Depth of TX FIFO 1003 * 0x0: 2 words 1004 * 0x1: 4 words 1005 * 0x2: 8 words 1006 * 0x3: 16 words 1007 * 0x4: 32 words 1008 * 0x5: 64 words 1009 * 0x6: 128 words 1010 */ 1011 #define SPI_CONFIG_TXFIFOSIZE_MASK (0xF0U) 1012 #define SPI_CONFIG_TXFIFOSIZE_SHIFT (4U) 1013 #define SPI_CONFIG_TXFIFOSIZE_GET(x) (((uint32_t)(x) & SPI_CONFIG_TXFIFOSIZE_MASK) >> SPI_CONFIG_TXFIFOSIZE_SHIFT) 1014 1015 /* 1016 * RXFIFOSIZE (RO) 1017 * 1018 * Depth of RX FIFO 1019 * 0x0: 2 words 1020 * 0x1: 4 words 1021 * 0x2: 8 words 1022 * 0x3: 16 words 1023 * 0x4: 32 words 1024 * 0x5: 64 words 1025 * 0x6: 128 words 1026 */ 1027 #define SPI_CONFIG_RXFIFOSIZE_MASK (0xFU) 1028 #define SPI_CONFIG_RXFIFOSIZE_SHIFT (0U) 1029 #define SPI_CONFIG_RXFIFOSIZE_GET(x) (((uint32_t)(x) & SPI_CONFIG_RXFIFOSIZE_MASK) >> SPI_CONFIG_RXFIFOSIZE_SHIFT) 1030 1031 1032 1033 1034 #endif /* HPM_SPI_H */ 1035