1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _RTW_MP_C_
16 #include <drv_types.h>
17 #ifdef PLATFORM_FREEBSD
18 #include <sys/unistd.h> /* for RFHIGHPID */
19 #endif
20
21 #include "../hal/phydm/phydm_precomp.h"
22 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)
23 #include <rtw_bt_mp.h>
24 #endif
25
26 #ifdef CONFIG_MP_VHT_HW_TX_MODE
27 #define CEILING_POS(X) ((X - (int)(X)) > 0 ? (int)(X + 1) : (int)(X))
28 #define CEILING_NEG(X) ((X - (int)(X)) < 0 ? (int)(X - 1) : (int)(X))
29 #define ceil(X) (((X) > 0) ? CEILING_POS(X) : CEILING_NEG(X))
30
rtfloor(float x)31 int rtfloor(float x)
32 {
33 int i = x - 2;
34 while
35 (++i <= x - 1)
36 ;
37 return i;
38 }
39 #endif
40
41 #ifdef CONFIG_MP_INCLUDED
read_macreg(_adapter * padapter,u32 addr,u32 sz)42 u32 read_macreg(_adapter *padapter, u32 addr, u32 sz)
43 {
44 u32 val = 0;
45
46 switch (sz) {
47 case 1:
48 val = rtw_read8(padapter, addr);
49 break;
50 case 2:
51 val = rtw_read16(padapter, addr);
52 break;
53 case 4:
54 val = rtw_read32(padapter, addr);
55 break;
56 default:
57 val = 0xffffffff;
58 break;
59 }
60
61 return val;
62
63 }
64
write_macreg(_adapter * padapter,u32 addr,u32 val,u32 sz)65 void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz)
66 {
67 switch (sz) {
68 case 1:
69 rtw_write8(padapter, addr, (u8)val);
70 break;
71 case 2:
72 rtw_write16(padapter, addr, (u16)val);
73 break;
74 case 4:
75 rtw_write32(padapter, addr, val);
76 break;
77 default:
78 break;
79 }
80
81 }
82
read_bbreg(_adapter * padapter,u32 addr,u32 bitmask)83 u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask)
84 {
85 return rtw_hal_read_bbreg(padapter, addr, bitmask);
86 }
87
write_bbreg(_adapter * padapter,u32 addr,u32 bitmask,u32 val)88 void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val)
89 {
90 rtw_hal_write_bbreg(padapter, addr, bitmask, val);
91 }
92
_read_rfreg(PADAPTER padapter,u8 rfpath,u32 addr,u32 bitmask)93 u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask)
94 {
95 return rtw_hal_read_rfreg(padapter, rfpath, addr, bitmask);
96 }
97
_write_rfreg(PADAPTER padapter,u8 rfpath,u32 addr,u32 bitmask,u32 val)98 void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val)
99 {
100 rtw_hal_write_rfreg(padapter, rfpath, addr, bitmask, val);
101 }
102
read_rfreg(PADAPTER padapter,u8 rfpath,u32 addr)103 u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr)
104 {
105 return _read_rfreg(padapter, rfpath, addr, bRFRegOffsetMask);
106 }
107
write_rfreg(PADAPTER padapter,u8 rfpath,u32 addr,u32 val)108 void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val)
109 {
110 _write_rfreg(padapter, rfpath, addr, bRFRegOffsetMask, val);
111 }
112
_init_mp_priv_(struct mp_priv * pmp_priv)113 static void _init_mp_priv_(struct mp_priv *pmp_priv)
114 {
115 WLAN_BSSID_EX *pnetwork;
116
117 _rtw_memset(pmp_priv, 0, sizeof(struct mp_priv));
118
119 pmp_priv->mode = MP_OFF;
120
121 pmp_priv->channel = 1;
122 pmp_priv->bandwidth = CHANNEL_WIDTH_20;
123 pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
124 pmp_priv->rateidx = RATE_1M;
125 pmp_priv->txpoweridx = 0x2A;
126 pmp_priv->txpower_dbm_offset = 0;
127
128 pmp_priv->antenna_tx = ANTENNA_A;
129 pmp_priv->antenna_rx = ANTENNA_AB;
130
131 pmp_priv->check_mp_pkt = 0;
132
133 pmp_priv->tx_pktcount = 0;
134
135 pmp_priv->rx_bssidpktcount = 0;
136 pmp_priv->rx_pktcount = 0;
137 pmp_priv->rx_crcerrpktcount = 0;
138
139 pmp_priv->network_macaddr[0] = 0x00;
140 pmp_priv->network_macaddr[1] = 0xE0;
141 pmp_priv->network_macaddr[2] = 0x4C;
142 pmp_priv->network_macaddr[3] = 0x87;
143 pmp_priv->network_macaddr[4] = 0x66;
144 pmp_priv->network_macaddr[5] = 0x55;
145
146 pmp_priv->bSetRxBssid = _FALSE;
147 pmp_priv->bRTWSmbCfg = _FALSE;
148 pmp_priv->bloopback = _FALSE;
149
150 pmp_priv->bloadefusemap = _FALSE;
151 pmp_priv->brx_filter_beacon = _FALSE;
152 pmp_priv->mplink_brx = _FALSE;
153
154 pnetwork = &pmp_priv->mp_network.network;
155 _rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN);
156
157 pnetwork->Ssid.SsidLength = 8;
158 _rtw_memcpy(pnetwork->Ssid.Ssid, "mp_871x", pnetwork->Ssid.SsidLength);
159
160 pmp_priv->tx.payload = MP_TX_Payload_default_random;
161 #ifdef CONFIG_80211N_HT
162 pmp_priv->tx.attrib.ht_en = 1;
163 #endif
164
165 pmp_priv->mpt_ctx.mpt_rate_index = 1;
166
167 }
168
169
mp_init_xmit_attrib(struct mp_tx * pmptx,PADAPTER padapter)170 static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter)
171 {
172 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
173
174 struct pkt_attrib *pattrib;
175
176 /* init xmitframe attribute */
177 pattrib = &pmptx->attrib;
178 _rtw_memset(pattrib, 0, sizeof(struct pkt_attrib));
179 _rtw_memset(pmptx->desc, 0, TXDESC_SIZE);
180
181 pattrib->ether_type = 0x8712;
182 #if 0
183 _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
184 _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
185 #endif
186 _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);
187
188 /* pattrib->dhcp_pkt = 0;
189 * pattrib->pktlen = 0; */
190 pattrib->ack_policy = 0;
191 /* pattrib->pkt_hdrlen = ETH_HLEN; */
192 pattrib->hdrlen = WLAN_HDR_A3_LEN;
193 pattrib->subtype = WIFI_DATA;
194 pattrib->priority = 0;
195 pattrib->qsel = pattrib->priority;
196 /* do_queue_select(padapter, pattrib); */
197 pattrib->nr_frags = 1;
198 pattrib->encrypt = 0;
199 pattrib->bswenc = _FALSE;
200 pattrib->qos_en = _FALSE;
201
202 pattrib->pktlen = 1500;
203
204 if (pHalData->rf_type == RF_2T2R)
205 pattrib->raid = RATEID_IDX_BGN_40M_2SS;
206 else
207 pattrib->raid = RATEID_IDX_BGN_40M_1SS;
208
209 #ifdef CONFIG_80211AC_VHT
210 if (pHalData->rf_type == RF_1T1R)
211 pattrib->raid = RATEID_IDX_VHT_1SS;
212 else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
213 pattrib->raid = RATEID_IDX_VHT_2SS;
214 else if (pHalData->rf_type == RF_3T3R)
215 pattrib->raid = RATEID_IDX_VHT_3SS;
216 else
217 pattrib->raid = RATEID_IDX_BGN_40M_1SS;
218 #endif
219 }
220
init_mp_priv(PADAPTER padapter)221 s32 init_mp_priv(PADAPTER padapter)
222 {
223 struct mp_priv *pmppriv = &padapter->mppriv;
224 PHAL_DATA_TYPE pHalData;
225
226 pHalData = GET_HAL_DATA(padapter);
227
228 _init_mp_priv_(pmppriv);
229 pmppriv->papdater = padapter;
230 if (IS_HARDWARE_TYPE_8822C(padapter))
231 pmppriv->mp_dm = 1;/* default enable dpk tracking */
232 else
233 pmppriv->mp_dm = 0;
234
235 pmppriv->tx.stop = 1;
236 pmppriv->bSetTxPower = 0; /*for manually set tx power*/
237 pmppriv->bTxBufCkFail = _FALSE;
238 pmppriv->pktInterval = 0;
239 pmppriv->pktLength = 1000;
240 pmppriv->bprocess_mp_mode = _FALSE;
241 pmppriv->efuse_update_file= _FALSE;
242 pmppriv->efuse_update_on = _FALSE;
243
244 mp_init_xmit_attrib(&pmppriv->tx, padapter);
245
246 switch (GET_HAL_RFPATH(padapter)) {
247 case RF_1T1R:
248 pmppriv->antenna_tx = ANTENNA_A;
249 pmppriv->antenna_rx = ANTENNA_A;
250 break;
251 case RF_1T2R:
252 default:
253 pmppriv->antenna_tx = ANTENNA_A;
254 pmppriv->antenna_rx = ANTENNA_AB;
255 break;
256 case RF_2T2R:
257 pmppriv->antenna_tx = ANTENNA_AB;
258 pmppriv->antenna_rx = ANTENNA_AB;
259 break;
260 case RF_2T4R:
261 pmppriv->antenna_tx = ANTENNA_BC;
262 pmppriv->antenna_rx = ANTENNA_ABCD;
263 break;
264 }
265
266 pHalData->AntennaRxPath = pmppriv->antenna_rx;
267 pHalData->antenna_tx_path = pmppriv->antenna_tx;
268
269 return _SUCCESS;
270 }
271
free_mp_priv(struct mp_priv * pmp_priv)272 void free_mp_priv(struct mp_priv *pmp_priv)
273 {
274 if (pmp_priv->pallocated_mp_xmitframe_buf) {
275 rtw_mfree(pmp_priv->pallocated_mp_xmitframe_buf, 0);
276 pmp_priv->pallocated_mp_xmitframe_buf = NULL;
277 }
278 pmp_priv->pmp_xmtframe_buf = NULL;
279 }
280
281 #if 0
282 static void PHY_IQCalibrate_default(
283 PADAPTER pAdapter,
284 BOOLEAN bReCovery
285 )
286 {
287 RTW_INFO("%s\n", __func__);
288 }
289
290 static void PHY_LCCalibrate_default(
291 PADAPTER pAdapter
292 )
293 {
294 RTW_INFO("%s\n", __func__);
295 }
296
297 static void PHY_SetRFPathSwitch_default(
298 PADAPTER pAdapter,
299 BOOLEAN bMain
300 )
301 {
302 RTW_INFO("%s\n", __func__);
303 }
304 #endif
305
mpt_InitHWConfig(PADAPTER Adapter)306 void mpt_InitHWConfig(PADAPTER Adapter)
307 {
308 PHAL_DATA_TYPE hal;
309
310 hal = GET_HAL_DATA(Adapter);
311
312 if (IS_HARDWARE_TYPE_8723B(Adapter)) {
313 /* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */
314 /* TODO: A better solution is configure it according EFUSE during the run-time. */
315
316 phy_set_mac_reg(Adapter, 0x64, BIT20, 0x0); /* 0x66[4]=0 */
317 phy_set_mac_reg(Adapter, 0x64, BIT24, 0x0); /* 0x66[8]=0 */
318 phy_set_mac_reg(Adapter, 0x40, BIT4, 0x0); /* 0x40[4]=0 */
319 phy_set_mac_reg(Adapter, 0x40, BIT3, 0x1); /* 0x40[3]=1 */
320 phy_set_mac_reg(Adapter, 0x4C, BIT24, 0x1); /* 0x4C[24:23]=10 */
321 phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /* 0x4C[24:23]=10 */
322 phy_set_bb_reg(Adapter, 0x944, BIT1 | BIT0, 0x3); /* 0x944[1:0]=11 */
323 phy_set_bb_reg(Adapter, 0x930, bMaskByte0, 0x77);/* 0x930[7:0]=77 */
324 phy_set_mac_reg(Adapter, 0x38, BIT11, 0x1);/* 0x38[11]=1 */
325
326 /* TODO: <20130206, Kordan> The default setting is wrong, hard-coded here. */
327 phy_set_mac_reg(Adapter, 0x778, 0x3, 0x3); /* Turn off hardware PTA control (Asked by Scott) */
328 phy_set_mac_reg(Adapter, 0x64, bMaskDWord, 0x36000000);/* Fix BT S0/S1 */
329 phy_set_mac_reg(Adapter, 0x948, bMaskDWord, 0x0); /* Fix BT can't Tx */
330
331 /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou) */
332 phy_set_bb_reg(Adapter, 0xA00, BIT8, 0x0); /*0xA01[0] = 0*/
333 } else if (IS_HARDWARE_TYPE_8821(Adapter)) {
334 /* <20131121, VincentL> Add for 8821AU DPDT setting and fix switching antenna issue (Asked by Rock)
335 <20131122, VincentL> Enable for all 8821A/8811AU (Asked by Alex)*/
336 phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /*0x4C[23:22]=01*/
337 phy_set_mac_reg(Adapter, 0x4C, BIT22, 0x1); /*0x4C[23:22]=01*/
338 } else if (IS_HARDWARE_TYPE_8188ES(Adapter))
339 phy_set_mac_reg(Adapter, 0x4C , BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/
340 #ifdef CONFIG_RTL8814A
341 else if (IS_HARDWARE_TYPE_8814A(Adapter))
342 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000);
343 #endif
344
345 #ifdef CONFIG_RTL8812A
346 else if (IS_HARDWARE_TYPE_8812(Adapter)) {
347 rtw_write32(Adapter, 0x520, rtw_read32(Adapter, 0x520) | 0x8000);
348 rtw_write32(Adapter, 0x524, rtw_read32(Adapter, 0x524) & (~0x800));
349 }
350 #endif
351
352
353 #ifdef CONFIG_RTL8822B
354 else if (IS_HARDWARE_TYPE_8822B(Adapter)) {
355 u32 tmp_reg = 0;
356
357 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8822B, 0x2000);
358 /* fixed wifi can't 2.4g tx suggest by Szuyitasi 20160504 */
359 phy_set_bb_reg(Adapter, 0x70, bMaskByte3, 0x0e);
360 RTW_INFO(" 0x73 = 0x%x\n", phy_query_bb_reg(Adapter, 0x70, bMaskByte3));
361 phy_set_bb_reg(Adapter, 0x1704, bMaskDWord, 0x0000ff00);
362 RTW_INFO(" 0x1704 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1704, bMaskDWord));
363 phy_set_bb_reg(Adapter, 0x1700, bMaskDWord, 0xc00f0038);
364 RTW_INFO(" 0x1700 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1700, bMaskDWord));
365 }
366 #endif /* CONFIG_RTL8822B */
367 #ifdef CONFIG_RTL8821C
368 else if (IS_HARDWARE_TYPE_8821C(Adapter))
369 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8821C, 0x2000);
370 #endif /* CONFIG_RTL8821C */
371 #if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
372 else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
373 if (IS_A_CUT(hal->version_id) || IS_B_CUT(hal->version_id)) {
374 RTW_INFO("%s() Active large power detection\n", __func__);
375 phy_active_large_power_detection_8188f(&(GET_HAL_DATA(Adapter)->odmpriv));
376 }
377 }
378 #endif
379 #if defined(CONFIG_RTL8822C)
380 else if( IS_HARDWARE_TYPE_8822C(Adapter)) {
381 rtw_write16(Adapter, REG_RXFLTMAP1_8822C, 0x2000);
382 /* 0x7D8[31] : time out enable when cca is not assert
383 0x60D[7:0] : time out value (Unit : us)*/
384 rtw_write8(Adapter, 0x7db, 0xc0);
385 RTW_INFO(" 0x7d8 = 0x%x\n", rtw_read8(Adapter, 0x7d8));
386 rtw_write8(Adapter, 0x60d, 0x0c);
387 RTW_INFO(" 0x60d = 0x%x\n", rtw_read8(Adapter, 0x60d));
388 phy_set_bb_reg(Adapter, 0x1c44, BIT10, 0x1);
389 RTW_INFO(" 0x1c44 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1c44, bMaskDWord));
390 }
391 #endif
392 #if defined(CONFIG_RTL8814B)
393 else if(IS_HARDWARE_TYPE_8814B(Adapter))
394 {
395 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814B, 0x2000);
396 }
397 #endif
398 #if defined(CONFIG_RTL8723F)
399 /* todo: 8723F not verify yet */
400 else if (IS_HARDWARE_TYPE_8723F(Adapter)) {
401 /* 8723F mac is similar with 8723D,
402 * but can't find 8723D here.
403 */
404 }
405 #endif
406 }
407
PHY_IQCalibrate(PADAPTER padapter,u8 bReCovery)408 static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery)
409 {
410 halrf_iqk_trigger(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery);
411 }
412
PHY_LCCalibrate(PADAPTER padapter)413 static void PHY_LCCalibrate(PADAPTER padapter)
414 {
415 halrf_lck_trigger(&(GET_HAL_DATA(padapter)->odmpriv));
416 }
417
PHY_QueryRFPathSwitch(PADAPTER padapter)418 static u8 PHY_QueryRFPathSwitch(PADAPTER padapter)
419 {
420 u8 bmain = 0;
421 /*
422 if (IS_HARDWARE_TYPE_8723B(padapter)) {
423 #ifdef CONFIG_RTL8723B
424 bmain = PHY_QueryRFPathSwitch_8723B(padapter);
425 #endif
426 } else if (IS_HARDWARE_TYPE_8188E(padapter)) {
427 #ifdef CONFIG_RTL8188E
428 bmain = PHY_QueryRFPathSwitch_8188E(padapter);
429 #endif
430 } else if (IS_HARDWARE_TYPE_8814A(padapter)) {
431 #ifdef CONFIG_RTL8814A
432 bmain = PHY_QueryRFPathSwitch_8814A(padapter);
433 #endif
434 } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
435 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
436 bmain = PHY_QueryRFPathSwitch_8812A(padapter);
437 #endif
438 } else if (IS_HARDWARE_TYPE_8192E(padapter)) {
439 #ifdef CONFIG_RTL8192E
440 bmain = PHY_QueryRFPathSwitch_8192E(padapter);
441 #endif
442 } else if (IS_HARDWARE_TYPE_8703B(padapter)) {
443 #ifdef CONFIG_RTL8703B
444 bmain = PHY_QueryRFPathSwitch_8703B(padapter);
445 #endif
446 } else if (IS_HARDWARE_TYPE_8188F(padapter)) {
447 #ifdef CONFIG_RTL8188F
448 bmain = PHY_QueryRFPathSwitch_8188F(padapter);
449 #endif
450 } else if (IS_HARDWARE_TYPE_8188GTV(padapter)) {
451 #ifdef CONFIG_RTL8188GTV
452 bmain = PHY_QueryRFPathSwitch_8188GTV(padapter);
453 #endif
454 } else if (IS_HARDWARE_TYPE_8822B(padapter)) {
455 #ifdef CONFIG_RTL8822B
456 bmain = PHY_QueryRFPathSwitch_8822B(padapter);
457 #endif
458 } else if (IS_HARDWARE_TYPE_8723D(padapter)) {
459 #ifdef CONFIG_RTL8723D
460 bmain = PHY_QueryRFPathSwitch_8723D(padapter);
461 #endif
462 } else
463 */
464
465 if (IS_HARDWARE_TYPE_8821C(padapter)) {
466 #ifdef CONFIG_RTL8821C
467 bmain = phy_query_rf_path_switch_8821c(padapter);
468 #endif
469 }
470
471 return bmain;
472 }
473
PHY_SetRFPathSwitch(PADAPTER padapter,BOOLEAN bMain)474 static void PHY_SetRFPathSwitch(PADAPTER padapter , BOOLEAN bMain) {
475
476 PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
477 struct dm_struct *phydm = &hal->odmpriv;
478
479 if (IS_HARDWARE_TYPE_8723B(padapter)) {
480 #ifdef CONFIG_RTL8723B
481 phy_set_rf_path_switch_8723b(phydm, bMain);
482 #endif
483 } else if (IS_HARDWARE_TYPE_8188E(padapter)) {
484 #ifdef CONFIG_RTL8188E
485 phy_set_rf_path_switch_8188e(phydm, bMain);
486 #endif
487 } else if (IS_HARDWARE_TYPE_8814A(padapter)) {
488 #ifdef CONFIG_RTL8814A
489 phy_set_rf_path_switch_8814a(phydm, bMain);
490 #endif
491 } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
492 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
493 phy_set_rf_path_switch_8812a(phydm, bMain);
494 #endif
495 } else if (IS_HARDWARE_TYPE_8192E(padapter)) {
496 #ifdef CONFIG_RTL8192E
497 phy_set_rf_path_switch_8192e(phydm, bMain);
498 #endif
499 } else if (IS_HARDWARE_TYPE_8703B(padapter)) {
500 #ifdef CONFIG_RTL8703B
501 phy_set_rf_path_switch_8703b(phydm, bMain);
502 #endif
503 } else if (IS_HARDWARE_TYPE_8188F(padapter) || IS_HARDWARE_TYPE_8188GTV(padapter)) {
504 #if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
505 phy_set_rf_path_switch_8188f(phydm, bMain);
506 #endif
507 } else if (IS_HARDWARE_TYPE_8192F(padapter)) {
508 #ifdef CONFIG_RTL8192F
509 phy_set_rf_path_switch_8192f(padapter, bMain);
510 #endif
511 } else if (IS_HARDWARE_TYPE_8822B(padapter)) {
512 #ifdef CONFIG_RTL8822B
513 phy_set_rf_path_switch_8822b(phydm, bMain);
514 #endif
515 } else if (IS_HARDWARE_TYPE_8723D(padapter)) {
516 #ifdef CONFIG_RTL8723D
517 phy_set_rf_path_switch_8723d(phydm, bMain);
518 #endif
519 } else if (IS_HARDWARE_TYPE_8821C(padapter)) {
520 #ifdef CONFIG_RTL8821C
521 phy_set_rf_path_switch_8821c(phydm, bMain);
522 #endif
523 } else if (IS_HARDWARE_TYPE_8822C(padapter)) {
524 #ifdef CONFIG_RTL8822C
525 phy_set_rf_path_switch_8822c(phydm, bMain);
526 #endif
527 } else if (IS_HARDWARE_TYPE_8814B(padapter)) {
528 #ifdef CONFIG_RTL8814B
529 /* phy_set_rf_path_switch_8814b(phydm, bMain); */
530 #endif
531 } else if (IS_HARDWARE_TYPE_8723F(padapter)) {
532 #ifdef CONFIG_RTL8723F
533 phy_set_rf_path_switch_8723f(phydm, bMain);
534 #endif
535 }
536 }
537
538
phy_switch_rf_path_set(PADAPTER padapter,u8 * prf_set_State)539 static void phy_switch_rf_path_set(PADAPTER padapter , u8 *prf_set_State) {
540 #ifdef CONFIG_RTL8821C
541 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
542 struct dm_struct *p_dm = &pHalData->odmpriv;
543
544 if (IS_HARDWARE_TYPE_8821C(padapter)) {
545 config_phydm_set_ant_path(p_dm, *prf_set_State, p_dm->current_ant_num_8821c);
546 /* Do IQK when switching to BTG/WLG, requested by RF Binson */
547 if (*prf_set_State == SWITCH_TO_BTG || *prf_set_State == SWITCH_TO_WLG)
548 PHY_IQCalibrate(padapter, FALSE);
549 }
550 #endif
551
552 }
553
554
555 #ifdef CONFIG_ANTENNA_DIVERSITY
rtw_mp_set_antdiv(PADAPTER padapter,BOOLEAN bMain)556 u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain)
557 {
558 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
559 u8 cur_ant, change_ant;
560
561 if (!pHalData->AntDivCfg)
562 return _FALSE;
563 /*rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);*/
564 change_ant = (bMain == MAIN_ANT) ? MAIN_ANT : AUX_ANT;
565
566 RTW_INFO("%s: config %s\n", __func__, (bMain == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
567 rtw_antenna_select_cmd(padapter, change_ant, _FALSE);
568
569 return _TRUE;
570 }
571 #endif
572
573 s32
MPT_InitializeAdapter(PADAPTER pAdapter,u8 Channel)574 MPT_InitializeAdapter(
575 PADAPTER pAdapter,
576 u8 Channel
577 )
578 {
579 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
580 s32 rtStatus = _SUCCESS;
581 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
582 u32 ledsetting;
583
584 pMptCtx->bMptDrvUnload = _FALSE;
585 pMptCtx->bMassProdTest = _FALSE;
586 pMptCtx->bMptIndexEven = _TRUE; /* default gain index is -6.0db */
587 pMptCtx->h2cReqNum = 0x0;
588 /* init for BT MP */
589 #if defined(CONFIG_RTL8723B)
590 pMptCtx->bMPh2c_timeout = _FALSE;
591 pMptCtx->MptH2cRspEvent = _FALSE;
592 pMptCtx->MptBtC2hEvent = _FALSE;
593 _rtw_init_sema(&pMptCtx->MPh2c_Sema, 0);
594 rtw_init_timer(&pMptCtx->MPh2c_timeout_timer, pAdapter, MPh2c_timeout_handle, pAdapter);
595 #endif
596
597 mpt_InitHWConfig(pAdapter);
598
599 #ifdef CONFIG_RTL8723B
600 rtl8723b_InitAntenna_Selection(pAdapter);
601 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
602
603 /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou)*/
604 phy_set_bb_reg(pAdapter, 0xA00, BIT8, 0x0);
605 PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /*default use Main*/
606
607 if (pHalData->PackageType == PACKAGE_DEFAULT)
608 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
609 else
610 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6F10E);
611
612 }
613 /*set ant to wifi side in mp mode*/
614 rtw_write16(pAdapter, 0x870, 0x300);
615 rtw_write16(pAdapter, 0x860, 0x110);
616 #endif
617
618 pMptCtx->bMptWorkItemInProgress = _FALSE;
619 pMptCtx->CurrMptAct = NULL;
620 pMptCtx->mpt_rf_path = RF_PATH_A;
621 /* ------------------------------------------------------------------------- */
622 /* Don't accept any packets */
623 rtw_write32(pAdapter, REG_RCR, 0);
624
625 /* ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); */
626 /* rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS); */
627
628 /* rtw_write32(pAdapter, REG_LEDCFG0, 0x08080); */
629 ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
630
631
632 PHY_LCCalibrate(pAdapter);
633 PHY_IQCalibrate(pAdapter, _FALSE);
634 /* dm_check_txpowertracking(&pHalData->odmpriv); */ /* trigger thermal meter */
635
636 PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /* default use Main */
637
638 pMptCtx->backup0xc50 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
639 pMptCtx->backup0xc58 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
640 pMptCtx->backup0xc30 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
641 pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
642 pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
643 #ifdef CONFIG_RTL8188E
644 rtw_write32(pAdapter, REG_MACID_NO_LINK_0, 0x0);
645 rtw_write32(pAdapter, REG_MACID_NO_LINK_1, 0x0);
646 #endif
647 #ifdef CONFIG_RTL8814A
648 if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
649 pHalData->BackUp_IG_REG_4_Chnl_Section[0] = (u8)phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
650 pHalData->BackUp_IG_REG_4_Chnl_Section[1] = (u8)phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
651 pHalData->BackUp_IG_REG_4_Chnl_Section[2] = (u8)phy_query_bb_reg(pAdapter, rC_IGI_Jaguar2, bMaskByte0);
652 pHalData->BackUp_IG_REG_4_Chnl_Section[3] = (u8)phy_query_bb_reg(pAdapter, rD_IGI_Jaguar2, bMaskByte0);
653 }
654 #endif
655 return rtStatus;
656 }
657
658 /*-----------------------------------------------------------------------------
659 * Function: MPT_DeInitAdapter()
660 *
661 * Overview: Extra DeInitialization for Mass Production Test.
662 *
663 * Input: PADAPTER pAdapter
664 *
665 * Output: NONE
666 *
667 * Return: NONE
668 *
669 * Revised History:
670 * When Who Remark
671 * 05/08/2007 MHC Create Version 0.
672 * 05/18/2007 MHC Add normal driver MPHalt code.
673 *
674 *---------------------------------------------------------------------------*/
675 void
MPT_DeInitAdapter(PADAPTER pAdapter)676 MPT_DeInitAdapter(
677 PADAPTER pAdapter
678 )
679 {
680 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
681
682 pMptCtx->bMptDrvUnload = _TRUE;
683 #if defined(CONFIG_RTL8723B)
684 _rtw_free_sema(&(pMptCtx->MPh2c_Sema));
685 _cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);
686 #endif
687 #if defined(CONFIG_RTL8723B)
688 phy_set_bb_reg(pAdapter, 0xA01, BIT0, 1); /* /suggestion by jerry for MP Rx. */
689 #endif
690 #if 0 /* for Windows */
691 PlatformFreeWorkItem(&(pMptCtx->MptWorkItem));
692
693 while (pMptCtx->bMptWorkItemInProgress) {
694 if (NdisWaitEvent(&(pMptCtx->MptWorkItemEvent), 50))
695 break;
696 }
697 NdisFreeSpinLock(&(pMptCtx->MptWorkItemSpinLock));
698 #endif
699 }
700
mpt_ProStartTest(PADAPTER padapter)701 static u8 mpt_ProStartTest(PADAPTER padapter)
702 {
703 PMPT_CONTEXT pMptCtx = &padapter->mppriv.mpt_ctx;
704
705 pMptCtx->bMassProdTest = _TRUE;
706 pMptCtx->is_start_cont_tx = _FALSE;
707 pMptCtx->bCckContTx = _FALSE;
708 pMptCtx->bOfdmContTx = _FALSE;
709 pMptCtx->bSingleCarrier = _FALSE;
710 pMptCtx->is_carrier_suppression = _FALSE;
711 pMptCtx->is_single_tone = _FALSE;
712 pMptCtx->HWTxmode = PACKETS_TX;
713
714 return _SUCCESS;
715 }
716
717 /*
718 * General use
719 */
SetPowerTracking(PADAPTER padapter,u8 enable)720 s32 SetPowerTracking(PADAPTER padapter, u8 enable)
721 {
722
723 hal_mpt_SetPowerTracking(padapter, enable);
724 return 0;
725 }
726
GetPowerTracking(PADAPTER padapter,u8 * enable)727 void GetPowerTracking(PADAPTER padapter, u8 *enable)
728 {
729 hal_mpt_GetPowerTracking(padapter, enable);
730 }
731
rtw_mp_trigger_iqk(PADAPTER padapter)732 void rtw_mp_trigger_iqk(PADAPTER padapter)
733 {
734 PHY_IQCalibrate(padapter, _FALSE);
735 }
736
rtw_mp_trigger_lck(PADAPTER padapter)737 void rtw_mp_trigger_lck(PADAPTER padapter)
738 {
739 PHY_LCCalibrate(padapter);
740 }
741
rtw_mp_trigger_dpk(PADAPTER padapter)742 void rtw_mp_trigger_dpk(PADAPTER padapter)
743 {
744 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
745 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
746
747 halrf_dpk_trigger(pDM_Odm);
748 }
749
init_mp_data(PADAPTER padapter)750 static void init_mp_data(PADAPTER padapter)
751 {
752 u8 v8;
753 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
754 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
755
756 /*disable BCN*/
757 #ifdef CONFIG_PROTSEL_PORT
758 rtw_hal_hw_port_disable(padapter);
759 #else
760 v8 = rtw_read8(padapter, REG_BCN_CTRL);
761 v8 &= ~EN_BCN_FUNCTION;
762 rtw_write8(padapter, REG_BCN_CTRL, v8);
763 #endif
764
765 pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
766 }
767
768
MPT_PwrCtlDM(PADAPTER padapter,u32 trk_type)769 void MPT_PwrCtlDM(PADAPTER padapter, u32 trk_type)
770 {
771 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
772 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
773 u32 rf_ability;
774
775 padapter->mppriv.tssitrk_on = trk_type == 3;
776
777 if (trk_type == 0) { /* thermal PwrTrk off*/
778 struct txpwrtrack_cfg c;
779 u8 chnl = 0 ;
780
781 RTW_INFO("in Thermal tracking off\n");
782 rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) & ~HAL_RF_TX_PWR_TRACK;
783 halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);
784 halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_POWER_TRACK_CONTROL, trk_type);
785 halrf_set_pwr_track(pDM_Odm, FALSE);
786 pDM_Odm->rf_calibrate_info.txpowertrack_control = trk_type;
787 if (IS_HARDWARE_TYPE_8822C(padapter))
788 padapter->mppriv.mp_dm = 1; /* default enable dpk tracking */
789 else
790 padapter->mppriv.mp_dm = 0;
791
792 _rtw_memset(&c, 0, sizeof(struct txpwrtrack_cfg));
793 configure_txpower_track(pDM_Odm, &c);
794 odm_clear_txpowertracking_state(pDM_Odm);
795 if (*c.odm_tx_pwr_track_set_pwr) {
796 if (pDM_Odm->support_ic_type == ODM_RTL8188F)
797 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);
798 else if (pDM_Odm->support_ic_type == ODM_RTL8723D) {
799 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);
800 SetTxPower(padapter);
801 } else if (pDM_Odm->support_ic_type == ODM_RTL8192F) {
802 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);
803 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_B, chnl);
804 } else {
805 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);
806 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_B, chnl);
807 }
808 }
809 return ;
810 }
811
812 rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) | HAL_RF_TX_PWR_TRACK;
813 halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);
814 halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_POWER_TRACK_CONTROL, trk_type);
815 if (trk_type == 1 || trk_type == 3) /* Thermal PwrTrk ON , TSSI PwrTrk ON */
816 halrf_set_pwr_track(pDM_Odm, TRUE);
817 else
818 halrf_set_pwr_track(pDM_Odm, false);/* TSSI K */
819 pDM_Odm->rf_calibrate_info.txpowertrack_control = trk_type;
820 padapter->mppriv.mp_dm = 1;
821
822 }
823
824
mp_join(PADAPTER padapter,u8 mode)825 u32 mp_join(PADAPTER padapter, u8 mode)
826 {
827 WLAN_BSSID_EX bssid;
828 struct sta_info *psta;
829 u32 length;
830 _irqL irqL;
831 s32 res = _SUCCESS;
832
833 struct mp_priv *pmppriv = &padapter->mppriv;
834 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
835 struct wlan_network *tgt_network = &pmlmepriv->cur_network;
836 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
837 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
838 WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
839
840 /* 1. initialize a new WLAN_BSSID_EX */
841 _rtw_memset(&bssid, 0, sizeof(WLAN_BSSID_EX));
842 RTW_INFO("%s ,pmppriv->network_macaddr=%x %x %x %x %x %x\n", __func__,
843 pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],
844 pmppriv->network_macaddr[5]);
845 _rtw_memcpy(bssid.MacAddress, pmppriv->network_macaddr, ETH_ALEN);
846
847 if (mode == WIFI_FW_ADHOC_STATE) {
848 bssid.Ssid.SsidLength = strlen("mp_pseudo_adhoc");
849 _rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_adhoc", bssid.Ssid.SsidLength);
850 bssid.InfrastructureMode = Ndis802_11IBSS;
851 bssid.IELength = 0;
852 bssid.Configuration.DSConfig = pmppriv->channel;
853
854 } else if (mode == WIFI_FW_STATION_STATE) {
855 bssid.Ssid.SsidLength = strlen("mp_pseudo_STATION");
856 _rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_STATION", bssid.Ssid.SsidLength);
857 bssid.InfrastructureMode = Ndis802_11Infrastructure;
858 bssid.IELength = 0;
859 }
860
861 length = get_WLAN_BSSID_EX_sz(&bssid);
862 if (length % 4)
863 bssid.Length = ((length >> 2) + 1) << 2; /* round up to multiple of 4 bytes. */
864 else
865 bssid.Length = length;
866
867 _enter_critical_bh(&pmlmepriv->lock, &irqL);
868
869 if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
870 goto end_of_mp_start_test;
871
872 /* init mp_start_test status */
873 if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
874 rtw_disassoc_cmd(padapter, 500, 0);
875 rtw_indicate_disconnect(padapter, 0, _FALSE);
876 rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
877 }
878 pmppriv->prev_fw_state = get_fwstate(pmlmepriv);
879 /*pmlmepriv->fw_state = WIFI_MP_STATE;*/
880 init_fwstate(pmlmepriv, WIFI_MP_STATE);
881
882 set_fwstate(pmlmepriv, WIFI_UNDER_LINKING);
883
884 /* 3 2. create a new psta for mp driver */
885 /* clear psta in the cur_network, if any */
886 psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
887 if (psta)
888 rtw_free_stainfo(padapter, psta);
889
890 psta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress);
891 if (psta == NULL) {
892 /*pmlmepriv->fw_state = pmppriv->prev_fw_state;*/
893 init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
894 res = _FAIL;
895 goto end_of_mp_start_test;
896 }
897 if (mode == WIFI_FW_ADHOC_STATE)
898 set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
899 else
900 set_fwstate(pmlmepriv, WIFI_STATION_STATE);
901 /* 3 3. join psudo AdHoc */
902 tgt_network->join_res = 1;
903 tgt_network->aid = psta->cmn.aid = 1;
904
905 _rtw_memcpy(&padapter->registrypriv.dev_network, &bssid, length);
906 rtw_update_registrypriv_dev_network(padapter);
907 _rtw_memcpy(&tgt_network->network, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
908 _rtw_memcpy(pnetwork, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
909
910 rtw_indicate_connect(padapter);
911 _clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
912 set_fwstate(pmlmepriv, WIFI_ASOC_STATE);
913
914 end_of_mp_start_test:
915
916 _exit_critical_bh(&pmlmepriv->lock, &irqL);
917
918 if (1) { /* (res == _SUCCESS) */
919 /* set MSR to WIFI_FW_ADHOC_STATE */
920 if (mode == WIFI_FW_ADHOC_STATE) {
921 /* set msr to WIFI_FW_ADHOC_STATE */
922 pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
923 Set_MSR(padapter, (pmlmeinfo->state & 0x3));
924 rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress);
925 rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);
926 pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
927 } else {
928 Set_MSR(padapter, WIFI_FW_STATION_STATE);
929
930 RTW_INFO("%s , pmppriv->network_macaddr =%x %x %x %x %x %x\n", __func__,
931 pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],
932 pmppriv->network_macaddr[5]);
933
934 rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmppriv->network_macaddr);
935 }
936 }
937
938 return res;
939 }
940 /* This function initializes the DUT to the MP test mode */
mp_start_test(PADAPTER padapter)941 s32 mp_start_test(PADAPTER padapter)
942 {
943 struct mp_priv *pmppriv = &padapter->mppriv;
944 #ifdef CONFIG_PCI_HCI
945 PHAL_DATA_TYPE hal;
946 #endif
947 s32 res = _SUCCESS;
948
949 padapter->registrypriv.mp_mode = 1;
950
951 init_mp_data(padapter);
952 #ifdef CONFIG_RTL8814A
953 rtl8814_InitHalDm(padapter);
954 #endif /* CONFIG_RTL8814A */
955 #ifdef CONFIG_RTL8812A
956 rtl8812_InitHalDm(padapter);
957 #endif /* CONFIG_RTL8812A */
958 #ifdef CONFIG_RTL8723B
959 rtl8723b_InitHalDm(padapter);
960 #endif /* CONFIG_RTL8723B */
961 #ifdef CONFIG_RTL8703B
962 rtl8703b_InitHalDm(padapter);
963 #endif /* CONFIG_RTL8703B */
964 #ifdef CONFIG_RTL8192E
965 rtl8192e_InitHalDm(padapter);
966 #endif
967 #ifdef CONFIG_RTL8188F
968 rtl8188f_InitHalDm(padapter);
969 #endif
970 #ifdef CONFIG_RTL8188GTV
971 rtl8188gtv_InitHalDm(padapter);
972 #endif
973 #ifdef CONFIG_RTL8188E
974 rtl8188e_InitHalDm(padapter);
975 #endif
976 #ifdef CONFIG_RTL8723D
977 rtl8723d_InitHalDm(padapter);
978 #endif /* CONFIG_RTL8723D */
979
980 #ifdef CONFIG_PCI_HCI
981 hal = GET_HAL_DATA(padapter);
982 hal->pci_backdoor_ctrl = 0;
983 rtw_pci_aspm_config(padapter);
984 #endif
985
986
987 /* 3 0. update mp_priv */
988 switch (GET_HAL_RFPATH(padapter)) {
989 case RF_1T1R:
990 pmppriv->antenna_tx = ANTENNA_A;
991 pmppriv->antenna_rx = ANTENNA_A;
992 break;
993 case RF_1T2R:
994 default:
995 pmppriv->antenna_tx = ANTENNA_A;
996 pmppriv->antenna_rx = ANTENNA_AB;
997 break;
998 case RF_2T2R:
999 pmppriv->antenna_tx = ANTENNA_AB;
1000 pmppriv->antenna_rx = ANTENNA_AB;
1001 break;
1002 case RF_2T4R:
1003 pmppriv->antenna_tx = ANTENNA_AB;
1004 pmppriv->antenna_rx = ANTENNA_ABCD;
1005 break;
1006 }
1007
1008 mpt_ProStartTest(padapter);
1009
1010 mp_join(padapter, WIFI_FW_ADHOC_STATE);
1011
1012 return res;
1013 }
1014 /* ------------------------------------------------------------------------------
1015 * This function change the DUT from the MP test mode into normal mode */
mp_stop_test(PADAPTER padapter)1016 void mp_stop_test(PADAPTER padapter)
1017 {
1018 struct mp_priv *pmppriv = &padapter->mppriv;
1019 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
1020 struct wlan_network *tgt_network = &pmlmepriv->cur_network;
1021 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
1022 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1023 struct sta_info *psta;
1024 #ifdef CONFIG_PCI_HCI
1025 struct registry_priv *registry_par = &padapter->registrypriv;
1026 PHAL_DATA_TYPE hal;
1027 #endif
1028
1029 _irqL irqL;
1030
1031 if (pmppriv->mode == MP_ON) {
1032 pmppriv->bSetTxPower = 0;
1033 _enter_critical_bh(&pmlmepriv->lock, &irqL);
1034 if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)
1035 goto end_of_mp_stop_test;
1036
1037 /* 3 1. disconnect psudo AdHoc */
1038 rtw_indicate_disconnect(padapter, 0, _FALSE);
1039
1040 /* 3 2. clear psta used in mp test mode.
1041 * rtw_free_assoc_resources(padapter, _TRUE); */
1042 psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
1043 if (psta)
1044 rtw_free_stainfo(padapter, psta);
1045
1046 /* 3 3. return to normal state (default:station mode) */
1047 /*pmlmepriv->fw_state = pmppriv->prev_fw_state; */ /* WIFI_STATION_STATE;*/
1048 init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
1049
1050 /* flush the cur_network */
1051 _rtw_memset(tgt_network, 0, sizeof(struct wlan_network));
1052
1053 _clr_fwstate_(pmlmepriv, WIFI_MP_STATE);
1054
1055 pmlmeinfo->state = WIFI_FW_NULL_STATE;
1056
1057 end_of_mp_stop_test:
1058
1059 _exit_critical_bh(&pmlmepriv->lock, &irqL);
1060
1061 #ifdef CONFIG_PCI_HCI
1062 hal = GET_HAL_DATA(padapter);
1063 hal->pci_backdoor_ctrl = registry_par->pci_aspm_config;
1064 rtw_pci_aspm_config(padapter);
1065 #endif
1066
1067 #ifdef CONFIG_RTL8812A
1068 rtl8812_InitHalDm(padapter);
1069 #endif
1070 #ifdef CONFIG_RTL8723B
1071 rtl8723b_InitHalDm(padapter);
1072 #endif
1073 #ifdef CONFIG_RTL8703B
1074 rtl8703b_InitHalDm(padapter);
1075 #endif
1076 #ifdef CONFIG_RTL8192E
1077 rtl8192e_InitHalDm(padapter);
1078 #endif
1079 #ifdef CONFIG_RTL8188F
1080 rtl8188f_InitHalDm(padapter);
1081 #endif
1082 #ifdef CONFIG_RTL8188GTV
1083 rtl8188gtv_InitHalDm(padapter);
1084 #endif
1085 #ifdef CONFIG_RTL8723D
1086 rtl8723d_InitHalDm(padapter);
1087 #endif
1088 }
1089 }
1090 /*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
1091 #if 0
1092 /* #ifdef CONFIG_USB_HCI */
1093 static void mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Channel, u8 BandWidthID)
1094 {
1095 u8 eRFPath;
1096 u32 rfReg0x26;
1097 struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
1098
1099
1100 if (RateIdx < MPT_RATE_6M) /* CCK rate,for 88cu */
1101 rfReg0x26 = 0xf400;
1102 else if ((RateIdx >= MPT_RATE_6M) && (RateIdx <= MPT_RATE_54M)) {/* OFDM rate,for 88cu */
1103 if ((4 == Channel) || (8 == Channel) || (12 == Channel))
1104 rfReg0x26 = 0xf000;
1105 else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
1106 rfReg0x26 = 0xf400;
1107 else
1108 rfReg0x26 = 0x4f200;
1109 } else if ((RateIdx >= MPT_RATE_MCS0) && (RateIdx <= MPT_RATE_MCS15)) {
1110 /* MCS 20M ,for 88cu */ /* MCS40M rate,for 88cu */
1111
1112 if (CHANNEL_WIDTH_20 == BandWidthID) {
1113 if ((4 == Channel) || (8 == Channel))
1114 rfReg0x26 = 0xf000;
1115 else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
1116 rfReg0x26 = 0xf400;
1117 else
1118 rfReg0x26 = 0x4f200;
1119 } else {
1120 if ((4 == Channel) || (8 == Channel))
1121 rfReg0x26 = 0xf000;
1122 else if ((5 == Channel) || (7 == Channel))
1123 rfReg0x26 = 0xf400;
1124 else
1125 rfReg0x26 = 0x4f200;
1126 }
1127 }
1128
1129 for (eRFPath = 0; eRFPath < hal_spec->rf_reg_path_num; eRFPath++)
1130 write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26);
1131 }
1132 #endif
1133 /*-----------------------------------------------------------------------------
1134 * Function: mpt_SwitchRfSetting
1135 *
1136 * Overview: Change RF Setting when we siwthc channel/rate/BW for MP.
1137 *
1138 * Input: PADAPTER pAdapter
1139 *
1140 * Output: NONE
1141 *
1142 * Return: NONE
1143 *
1144 * Revised History:
1145 * When Who Remark
1146 * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series.
1147 * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3.
1148 *
1149 *---------------------------------------------------------------------------*/
1150 #if 0
1151 static void mpt_SwitchRfSetting(PADAPTER pAdapter)
1152 {
1153 hal_mpt_SwitchRfSetting(pAdapter);
1154 }
1155
1156 /*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
1157 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
1158 static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
1159 {
1160 hal_mpt_CCKTxPowerAdjust(Adapter, bInCH14);
1161 }
1162 #endif
1163
1164 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
1165
1166 /*
1167 * SetChannel
1168 * Description
1169 * Use H2C command to change channel,
1170 * not only modify rf register, but also other setting need to be done.
1171 */
SetChannel(PADAPTER pAdapter)1172 void SetChannel(PADAPTER pAdapter)
1173 {
1174 hal_mpt_SetChannel(pAdapter);
1175 }
1176
1177 /*
1178 * Notice
1179 * Switch bandwitdth may change center frequency(channel)
1180 */
SetBandwidth(PADAPTER pAdapter)1181 void SetBandwidth(PADAPTER pAdapter)
1182 {
1183 hal_mpt_SetBandwidth(pAdapter);
1184
1185 }
1186
SetAntenna(PADAPTER pAdapter)1187 void SetAntenna(PADAPTER pAdapter)
1188 {
1189 hal_mpt_SetAntenna(pAdapter);
1190 }
1191
SetTxPower(PADAPTER pAdapter)1192 int SetTxPower(PADAPTER pAdapter)
1193 {
1194
1195 hal_mpt_SetTxPower(pAdapter);
1196 return _TRUE;
1197 }
1198
SetTxAGCOffset(PADAPTER pAdapter,u32 ulTxAGCOffset)1199 void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)
1200 {
1201 u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
1202
1203 TxAGCOffset_B = (ulTxAGCOffset & 0x000000ff);
1204 TxAGCOffset_C = ((ulTxAGCOffset & 0x0000ff00) >> 8);
1205 TxAGCOffset_D = ((ulTxAGCOffset & 0x00ff0000) >> 16);
1206
1207 tmpAGC = (TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B);
1208 write_bbreg(pAdapter, rFPGA0_TxGainStage,
1209 (bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC);
1210 }
1211
SetDataRate(PADAPTER pAdapter)1212 void SetDataRate(PADAPTER pAdapter)
1213 {
1214 hal_mpt_SetDataRate(pAdapter);
1215 }
1216
MP_PHY_SetRFPathSwitch(PADAPTER pAdapter,BOOLEAN bMain)1217 void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain)
1218 {
1219
1220 PHY_SetRFPathSwitch(pAdapter, bMain);
1221
1222 }
1223
mp_phy_switch_rf_path_set(PADAPTER pAdapter,u8 * pstate)1224 void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate)
1225 {
1226
1227 phy_switch_rf_path_set(pAdapter, pstate);
1228
1229 }
1230
MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter)1231 u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter)
1232 {
1233 return PHY_QueryRFPathSwitch(pAdapter);
1234 }
1235
SetThermalMeter(PADAPTER pAdapter,u8 target_ther)1236 s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1237 {
1238 return hal_mpt_SetThermalMeter(pAdapter, target_ther);
1239 }
1240
1241 #if 0
1242 static void TriggerRFThermalMeter(PADAPTER pAdapter)
1243 {
1244 hal_mpt_TriggerRFThermalMeter(pAdapter);
1245 }
1246
1247 static u8 ReadRFThermalMeter(PADAPTER pAdapter)
1248 {
1249 return hal_mpt_ReadRFThermalMeter(pAdapter);
1250 }
1251 #endif
1252
GetThermalMeter(PADAPTER pAdapter,u8 rfpath,u8 * value)1253 void GetThermalMeter(PADAPTER pAdapter, u8 rfpath ,u8 *value)
1254 {
1255 hal_mpt_GetThermalMeter(pAdapter, rfpath, value);
1256 }
1257
SetSingleCarrierTx(PADAPTER pAdapter,u8 bStart)1258 void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1259 {
1260 PhySetTxPowerLevel(pAdapter);
1261 hal_mpt_SetSingleCarrierTx(pAdapter, bStart);
1262 }
1263
SetSingleToneTx(PADAPTER pAdapter,u8 bStart)1264 void SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1265 {
1266 PhySetTxPowerLevel(pAdapter);
1267 hal_mpt_SetSingleToneTx(pAdapter, bStart);
1268 }
1269
SetCarrierSuppressionTx(PADAPTER pAdapter,u8 bStart)1270 void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
1271 {
1272 PhySetTxPowerLevel(pAdapter);
1273 hal_mpt_SetCarrierSuppressionTx(pAdapter, bStart);
1274 }
1275
SetContinuousTx(PADAPTER pAdapter,u8 bStart)1276 void SetContinuousTx(PADAPTER pAdapter, u8 bStart)
1277 {
1278 PhySetTxPowerLevel(pAdapter);
1279 hal_mpt_SetContinuousTx(pAdapter, bStart);
1280 }
1281
1282
PhySetTxPowerLevel(PADAPTER pAdapter)1283 void PhySetTxPowerLevel(PADAPTER pAdapter)
1284 {
1285 struct mp_priv *pmp_priv = &pAdapter->mppriv;
1286
1287
1288 if (pmp_priv->bSetTxPower == 0) /* for NO manually set power index */
1289 rtw_hal_set_tx_power_level(pAdapter, pmp_priv->channel);
1290 }
1291
1292 /* ------------------------------------------------------------------------------ */
dump_mpframe(PADAPTER padapter,struct xmit_frame * pmpframe)1293 static void dump_mpframe(PADAPTER padapter, struct xmit_frame *pmpframe)
1294 {
1295 rtw_hal_mgnt_xmit(padapter, pmpframe);
1296 }
1297
alloc_mp_xmitframe(struct xmit_priv * pxmitpriv)1298 static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv)
1299 {
1300 struct xmit_frame *pmpframe;
1301 struct xmit_buf *pxmitbuf;
1302
1303 pmpframe = rtw_alloc_xmitframe(pxmitpriv, 0);
1304 if (pmpframe == NULL)
1305 return NULL;
1306
1307 pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
1308 if (pxmitbuf == NULL) {
1309 rtw_free_xmitframe(pxmitpriv, pmpframe);
1310 return NULL;
1311 }
1312
1313 pmpframe->frame_tag = MP_FRAMETAG;
1314
1315 pmpframe->pxmitbuf = pxmitbuf;
1316
1317 pmpframe->buf_addr = pxmitbuf->pbuf;
1318
1319 pxmitbuf->priv_data = pmpframe;
1320
1321 return pmpframe;
1322
1323 }
1324
1325 #ifdef CONFIG_PCI_HCI
check_nic_enough_desc(_adapter * padapter,struct pkt_attrib * pattrib)1326 static u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib)
1327 {
1328 u32 prio;
1329 struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
1330 struct rtw_tx_ring *ring;
1331
1332 switch (pattrib->qsel) {
1333 case 0:
1334 case 3:
1335 prio = BE_QUEUE_INX;
1336 break;
1337 case 1:
1338 case 2:
1339 prio = BK_QUEUE_INX;
1340 break;
1341 case 4:
1342 case 5:
1343 prio = VI_QUEUE_INX;
1344 break;
1345 case 6:
1346 case 7:
1347 prio = VO_QUEUE_INX;
1348 break;
1349 default:
1350 prio = BE_QUEUE_INX;
1351 break;
1352 }
1353
1354 ring = &pxmitpriv->tx_ring[prio];
1355
1356 /*
1357 * for now we reserve two free descriptor as a safety boundary
1358 * between the tail and the head
1359 */
1360 if ((ring->entries - ring->qlen) >= 2)
1361 return _TRUE;
1362 else
1363 return _FALSE;
1364 }
1365 #endif
1366
mp_xmit_packet_thread(thread_context context)1367 static thread_return mp_xmit_packet_thread(thread_context context)
1368 {
1369 struct xmit_frame *pxmitframe;
1370 struct mp_tx *pmptx;
1371 struct mp_priv *pmp_priv;
1372 struct xmit_priv *pxmitpriv;
1373 PADAPTER padapter;
1374
1375 pmp_priv = (struct mp_priv *)context;
1376 pmptx = &pmp_priv->tx;
1377 padapter = pmp_priv->papdater;
1378 pxmitpriv = &(padapter->xmitpriv);
1379
1380 thread_enter("RTW_MP_THREAD");
1381
1382 RTW_INFO("%s:pkTx Start\n", __func__);
1383 while (1) {
1384 pxmitframe = alloc_mp_xmitframe(pxmitpriv);
1385 #ifdef CONFIG_PCI_HCI
1386 if(check_nic_enough_desc(padapter, &pmptx->attrib) == _FALSE) {
1387 rtw_usleep_os(1000);
1388 continue;
1389 }
1390 #endif
1391 if (pxmitframe == NULL) {
1392 if (pmptx->stop ||
1393 RTW_CANNOT_RUN(padapter))
1394 goto exit;
1395 else {
1396 rtw_usleep_os(10);
1397 continue;
1398 }
1399 }
1400 _rtw_memcpy((u8 *)(pxmitframe->buf_addr + TXDESC_OFFSET), pmptx->buf, pmptx->write_size);
1401 _rtw_memcpy(&(pxmitframe->attrib), &(pmptx->attrib), sizeof(struct pkt_attrib));
1402
1403
1404 rtw_usleep_os(padapter->mppriv.pktInterval);
1405 dump_mpframe(padapter, pxmitframe);
1406
1407 pmptx->sended++;
1408 pmp_priv->tx_pktcount++;
1409
1410 if (pmptx->stop ||
1411 RTW_CANNOT_RUN(padapter))
1412 goto exit;
1413 if ((pmptx->count != 0) &&
1414 (pmptx->count == pmptx->sended))
1415 goto exit;
1416
1417 flush_signals_thread();
1418 }
1419
1420 exit:
1421 /* RTW_INFO("%s:pkTx Exit\n", __func__); */
1422 rtw_mfree(pmptx->pallocated_buf, pmptx->buf_size);
1423 pmptx->pallocated_buf = NULL;
1424 pmptx->stop = 1;
1425
1426 thread_exit(NULL);
1427 return 0;
1428 }
1429
fill_txdesc_for_mp(PADAPTER padapter,u8 * ptxdesc)1430 void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc)
1431 {
1432 struct mp_priv *pmp_priv = &padapter->mppriv;
1433 _rtw_memcpy(ptxdesc, pmp_priv->tx.desc, TXDESC_SIZE);
1434 }
1435
1436 #if defined(CONFIG_RTL8188E)
fill_tx_desc_8188e(PADAPTER padapter)1437 void fill_tx_desc_8188e(PADAPTER padapter)
1438 {
1439 struct mp_priv *pmp_priv = &padapter->mppriv;
1440 struct tx_desc *desc = (struct tx_desc *)&(pmp_priv->tx.desc);
1441 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1442 u32 pkt_size = pattrib->last_txcmdsz;
1443 s32 bmcast = IS_MCAST(pattrib->ra);
1444 /* offset 0 */
1445 #if !defined(CONFIG_RTL8188E_SDIO) && !defined(CONFIG_PCI_HCI)
1446 desc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
1447 desc->txdw0 |= cpu_to_le32(pkt_size & 0x0000FFFF); /* packet size */
1448 desc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00FF0000); /* 32 bytes for TX Desc */
1449 if (bmcast)
1450 desc->txdw0 |= cpu_to_le32(BMC); /* broadcast packet */
1451
1452 desc->txdw1 |= cpu_to_le32((0x01 << 26) & 0xff000000);
1453 #endif
1454
1455 desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x3F); /* CAM_ID(MAC_ID) */
1456 desc->txdw1 |= cpu_to_le32((pattrib->qsel << QSEL_SHT) & 0x00001F00); /* Queue Select, TID */
1457 desc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000); /* Rate Adaptive ID */
1458 /* offset 8 */
1459 /* desc->txdw2 |= cpu_to_le32(AGG_BK); */ /* AGG BK */
1460
1461 desc->txdw3 |= cpu_to_le32((pattrib->seqnum << 16) & 0x0fff0000);
1462 desc->txdw4 |= cpu_to_le32(HW_SSN);
1463
1464 desc->txdw4 |= cpu_to_le32(USERATE);
1465 desc->txdw4 |= cpu_to_le32(DISDATAFB);
1466
1467 if (pmp_priv->preamble) {
1468 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1469 desc->txdw4 |= cpu_to_le32(DATA_SHORT); /* CCK Short Preamble */
1470 }
1471
1472 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1473 desc->txdw4 |= cpu_to_le32(DATA_BW);
1474
1475 /* offset 20 */
1476 desc->txdw5 |= cpu_to_le32(pmp_priv->rateidx & 0x0000001F);
1477
1478 if (pmp_priv->preamble) {
1479 if (HwRateToMPTRate(pmp_priv->rateidx) > MPT_RATE_54M)
1480 desc->txdw5 |= cpu_to_le32(SGI); /* MCS Short Guard Interval */
1481 }
1482
1483 desc->txdw5 |= cpu_to_le32(RTY_LMT_EN); /* retry limit enable */
1484 desc->txdw5 |= cpu_to_le32(0x00180000); /* DATA/RTS Rate Fallback Limit */
1485
1486
1487 }
1488 #endif
1489
1490 #if defined(CONFIG_RTL8814A)
fill_tx_desc_8814a(PADAPTER padapter)1491 void fill_tx_desc_8814a(PADAPTER padapter)
1492 {
1493 struct mp_priv *pmp_priv = &padapter->mppriv;
1494 u8 *pDesc = (u8 *)&(pmp_priv->tx.desc);
1495 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1496
1497 u32 pkt_size = pattrib->last_txcmdsz;
1498 s32 bmcast = IS_MCAST(pattrib->ra);
1499 u8 offset;
1500
1501 /* SET_TX_DESC_FIRST_SEG_8814A(pDesc, 1); */
1502 SET_TX_DESC_LAST_SEG_8814A(pDesc, 1);
1503 /* SET_TX_DESC_OWN_(pDesc, 1); */
1504
1505 SET_TX_DESC_PKT_SIZE_8814A(pDesc, pkt_size);
1506
1507 offset = TXDESC_SIZE + OFFSET_SZ;
1508
1509 SET_TX_DESC_OFFSET_8814A(pDesc, offset);
1510 #if defined(CONFIG_PCI_HCI)
1511 SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 0); /* 8814AE pkt_offset is 0 */
1512 #else
1513 SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 1);
1514 #endif
1515
1516 if (bmcast)
1517 SET_TX_DESC_BMC_8814A(pDesc, 1);
1518
1519 SET_TX_DESC_MACID_8814A(pDesc, pattrib->mac_id);
1520 SET_TX_DESC_RATE_ID_8814A(pDesc, pattrib->raid);
1521
1522 /* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */
1523 SET_TX_DESC_QUEUE_SEL_8814A(pDesc, pattrib->qsel);
1524 /* SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); */
1525
1526 if (pmp_priv->preamble)
1527 SET_TX_DESC_DATA_SHORT_8814A(pDesc, 1);
1528
1529 if (!pattrib->qos_en) {
1530 SET_TX_DESC_HWSEQ_EN_8814A(pDesc, 1); /* Hw set sequence number */
1531 } else
1532 SET_TX_DESC_SEQ_8814A(pDesc, pattrib->seqnum);
1533
1534 if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
1535 SET_TX_DESC_DATA_BW_8814A(pDesc, pmp_priv->bandwidth);
1536 else {
1537 RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
1538 SET_TX_DESC_DATA_BW_8814A(pDesc, CHANNEL_WIDTH_20);
1539 }
1540
1541 SET_TX_DESC_DISABLE_FB_8814A(pDesc, 1);
1542 SET_TX_DESC_USE_RATE_8814A(pDesc, 1);
1543 SET_TX_DESC_TX_RATE_8814A(pDesc, pmp_priv->rateidx);
1544
1545 }
1546 #endif
1547
1548 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
fill_tx_desc_8812a(PADAPTER padapter)1549 void fill_tx_desc_8812a(PADAPTER padapter)
1550 {
1551 struct mp_priv *pmp_priv = &padapter->mppriv;
1552 u8 *pDesc = (u8 *)&(pmp_priv->tx.desc);
1553 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1554
1555 u32 pkt_size = pattrib->last_txcmdsz;
1556 s32 bmcast = IS_MCAST(pattrib->ra);
1557 u8 data_rate, pwr_status, offset;
1558
1559 SET_TX_DESC_FIRST_SEG_8812(pDesc, 1);
1560 SET_TX_DESC_LAST_SEG_8812(pDesc, 1);
1561 SET_TX_DESC_OWN_8812(pDesc, 1);
1562
1563 SET_TX_DESC_PKT_SIZE_8812(pDesc, pkt_size);
1564
1565 offset = TXDESC_SIZE + OFFSET_SZ;
1566
1567 SET_TX_DESC_OFFSET_8812(pDesc, offset);
1568
1569 #if defined(CONFIG_PCI_HCI)
1570 SET_TX_DESC_PKT_OFFSET_8812(pDesc, 0);
1571 #else
1572 SET_TX_DESC_PKT_OFFSET_8812(pDesc, 1);
1573 #endif
1574 if (bmcast)
1575 SET_TX_DESC_BMC_8812(pDesc, 1);
1576
1577 SET_TX_DESC_MACID_8812(pDesc, pattrib->mac_id);
1578 SET_TX_DESC_RATE_ID_8812(pDesc, pattrib->raid);
1579
1580 /* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */
1581 SET_TX_DESC_QUEUE_SEL_8812(pDesc, pattrib->qsel);
1582 /* SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); */
1583
1584 if (!pattrib->qos_en) {
1585 SET_TX_DESC_HWSEQ_EN_8812(pDesc, 1); /* Hw set sequence number */
1586 } else
1587 SET_TX_DESC_SEQ_8812(pDesc, pattrib->seqnum);
1588
1589 if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
1590 SET_TX_DESC_DATA_BW_8812(pDesc, pmp_priv->bandwidth);
1591 else {
1592 RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
1593 SET_TX_DESC_DATA_BW_8812(pDesc, CHANNEL_WIDTH_20);
1594 }
1595
1596 SET_TX_DESC_DISABLE_FB_8812(pDesc, 1);
1597 SET_TX_DESC_USE_RATE_8812(pDesc, 1);
1598 SET_TX_DESC_TX_RATE_8812(pDesc, pmp_priv->rateidx);
1599
1600 }
1601 #endif
1602 #if defined(CONFIG_RTL8192E)
fill_tx_desc_8192e(PADAPTER padapter)1603 void fill_tx_desc_8192e(PADAPTER padapter)
1604 {
1605 struct mp_priv *pmp_priv = &padapter->mppriv;
1606 u8 *pDesc = (u8 *)&(pmp_priv->tx.desc);
1607 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1608
1609 u32 pkt_size = pattrib->last_txcmdsz;
1610 s32 bmcast = IS_MCAST(pattrib->ra);
1611 u8 data_rate, pwr_status, offset;
1612
1613
1614 SET_TX_DESC_PKT_SIZE_92E(pDesc, pkt_size);
1615
1616 offset = TXDESC_SIZE + OFFSET_SZ;
1617
1618 SET_TX_DESC_OFFSET_92E(pDesc, offset);
1619 #if defined(CONFIG_PCI_HCI) /* 8192EE */
1620
1621 SET_TX_DESC_PKT_OFFSET_92E(pDesc, 0); /* 8192EE pkt_offset is 0 */
1622 #else /* 8192EU 8192ES */
1623 SET_TX_DESC_PKT_OFFSET_92E(pDesc, 1);
1624 #endif
1625
1626 if (bmcast)
1627 SET_TX_DESC_BMC_92E(pDesc, 1);
1628
1629 SET_TX_DESC_MACID_92E(pDesc, pattrib->mac_id);
1630 SET_TX_DESC_RATE_ID_92E(pDesc, pattrib->raid);
1631
1632
1633 SET_TX_DESC_QUEUE_SEL_92E(pDesc, pattrib->qsel);
1634 /* SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); */
1635
1636 if (!pattrib->qos_en) {
1637 SET_TX_DESC_EN_HWSEQ_92E(pDesc, 1);/* Hw set sequence number */
1638 SET_TX_DESC_HWSEQ_SEL_92E(pDesc, pattrib->hw_ssn_sel);
1639 } else
1640 SET_TX_DESC_SEQ_92E(pDesc, pattrib->seqnum);
1641
1642 if ((pmp_priv->bandwidth == CHANNEL_WIDTH_20) || (pmp_priv->bandwidth == CHANNEL_WIDTH_40))
1643 SET_TX_DESC_DATA_BW_92E(pDesc, pmp_priv->bandwidth);
1644 else {
1645 RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
1646 SET_TX_DESC_DATA_BW_92E(pDesc, CHANNEL_WIDTH_20);
1647 }
1648
1649 /* SET_TX_DESC_DATA_SC_92E(pDesc, SCMapping_92E(padapter,pattrib)); */
1650
1651 SET_TX_DESC_DISABLE_FB_92E(pDesc, 1);
1652 SET_TX_DESC_USE_RATE_92E(pDesc, 1);
1653 SET_TX_DESC_TX_RATE_92E(pDesc, pmp_priv->rateidx);
1654
1655 }
1656 #endif
1657
1658 #if defined(CONFIG_RTL8723B)
fill_tx_desc_8723b(PADAPTER padapter)1659 void fill_tx_desc_8723b(PADAPTER padapter)
1660 {
1661 struct mp_priv *pmp_priv = &padapter->mppriv;
1662 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1663 u8 *ptxdesc = pmp_priv->tx.desc;
1664
1665 SET_TX_DESC_AGG_BREAK_8723B(ptxdesc, 1);
1666 SET_TX_DESC_MACID_8723B(ptxdesc, pattrib->mac_id);
1667 SET_TX_DESC_QUEUE_SEL_8723B(ptxdesc, pattrib->qsel);
1668
1669 SET_TX_DESC_RATE_ID_8723B(ptxdesc, pattrib->raid);
1670 SET_TX_DESC_SEQ_8723B(ptxdesc, pattrib->seqnum);
1671 SET_TX_DESC_HWSEQ_EN_8723B(ptxdesc, 1);
1672 SET_TX_DESC_USE_RATE_8723B(ptxdesc, 1);
1673 SET_TX_DESC_DISABLE_FB_8723B(ptxdesc, 1);
1674
1675 if (pmp_priv->preamble) {
1676 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1677 SET_TX_DESC_DATA_SHORT_8723B(ptxdesc, 1);
1678 }
1679
1680 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1681 SET_TX_DESC_DATA_BW_8723B(ptxdesc, 1);
1682
1683 SET_TX_DESC_TX_RATE_8723B(ptxdesc, pmp_priv->rateidx);
1684
1685 SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(ptxdesc, 0x1F);
1686 SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(ptxdesc, 0xF);
1687 }
1688 #endif
1689
1690 #if defined(CONFIG_RTL8703B)
fill_tx_desc_8703b(PADAPTER padapter)1691 void fill_tx_desc_8703b(PADAPTER padapter)
1692 {
1693 struct mp_priv *pmp_priv = &padapter->mppriv;
1694 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1695 u8 *ptxdesc = pmp_priv->tx.desc;
1696
1697 SET_TX_DESC_AGG_BREAK_8703B(ptxdesc, 1);
1698 SET_TX_DESC_MACID_8703B(ptxdesc, pattrib->mac_id);
1699 SET_TX_DESC_QUEUE_SEL_8703B(ptxdesc, pattrib->qsel);
1700
1701 SET_TX_DESC_RATE_ID_8703B(ptxdesc, pattrib->raid);
1702 SET_TX_DESC_SEQ_8703B(ptxdesc, pattrib->seqnum);
1703 SET_TX_DESC_HWSEQ_EN_8703B(ptxdesc, 1);
1704 SET_TX_DESC_USE_RATE_8703B(ptxdesc, 1);
1705 SET_TX_DESC_DISABLE_FB_8703B(ptxdesc, 1);
1706
1707 if (pmp_priv->preamble) {
1708 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1709 SET_TX_DESC_DATA_SHORT_8703B(ptxdesc, 1);
1710 }
1711
1712 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1713 SET_TX_DESC_DATA_BW_8703B(ptxdesc, 1);
1714
1715 SET_TX_DESC_TX_RATE_8703B(ptxdesc, pmp_priv->rateidx);
1716
1717 SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(ptxdesc, 0x1F);
1718 SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(ptxdesc, 0xF);
1719 }
1720 #endif
1721
1722 #if defined(CONFIG_RTL8188F)
fill_tx_desc_8188f(PADAPTER padapter)1723 void fill_tx_desc_8188f(PADAPTER padapter)
1724 {
1725 struct mp_priv *pmp_priv = &padapter->mppriv;
1726 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1727 u8 *ptxdesc = pmp_priv->tx.desc;
1728
1729 SET_TX_DESC_AGG_BREAK_8188F(ptxdesc, 1);
1730 SET_TX_DESC_MACID_8188F(ptxdesc, pattrib->mac_id);
1731 SET_TX_DESC_QUEUE_SEL_8188F(ptxdesc, pattrib->qsel);
1732
1733 SET_TX_DESC_RATE_ID_8188F(ptxdesc, pattrib->raid);
1734 SET_TX_DESC_SEQ_8188F(ptxdesc, pattrib->seqnum);
1735 SET_TX_DESC_HWSEQ_EN_8188F(ptxdesc, 1);
1736 SET_TX_DESC_USE_RATE_8188F(ptxdesc, 1);
1737 SET_TX_DESC_DISABLE_FB_8188F(ptxdesc, 1);
1738
1739 if (pmp_priv->preamble)
1740 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1741 SET_TX_DESC_DATA_SHORT_8188F(ptxdesc, 1);
1742
1743 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1744 SET_TX_DESC_DATA_BW_8188F(ptxdesc, 1);
1745
1746 SET_TX_DESC_TX_RATE_8188F(ptxdesc, pmp_priv->rateidx);
1747
1748 SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(ptxdesc, 0x1F);
1749 SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(ptxdesc, 0xF);
1750 }
1751 #endif
1752
1753 #if defined(CONFIG_RTL8188GTV)
fill_tx_desc_8188gtv(PADAPTER padapter)1754 void fill_tx_desc_8188gtv(PADAPTER padapter)
1755 {
1756 struct mp_priv *pmp_priv = &padapter->mppriv;
1757 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1758 u8 *ptxdesc = pmp_priv->tx.desc;
1759
1760 SET_TX_DESC_AGG_BREAK_8188GTV(ptxdesc, 1);
1761 SET_TX_DESC_MACID_8188GTV(ptxdesc, pattrib->mac_id);
1762 SET_TX_DESC_QUEUE_SEL_8188GTV(ptxdesc, pattrib->qsel);
1763
1764 SET_TX_DESC_RATE_ID_8188GTV(ptxdesc, pattrib->raid);
1765 SET_TX_DESC_SEQ_8188GTV(ptxdesc, pattrib->seqnum);
1766 SET_TX_DESC_HWSEQ_EN_8188GTV(ptxdesc, 1);
1767 SET_TX_DESC_USE_RATE_8188GTV(ptxdesc, 1);
1768 SET_TX_DESC_DISABLE_FB_8188GTV(ptxdesc, 1);
1769
1770 if (pmp_priv->preamble)
1771 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1772 SET_TX_DESC_DATA_SHORT_8188GTV(ptxdesc, 1);
1773
1774 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1775 SET_TX_DESC_DATA_BW_8188GTV(ptxdesc, 1);
1776
1777 SET_TX_DESC_TX_RATE_8188GTV(ptxdesc, pmp_priv->rateidx);
1778
1779 SET_TX_DESC_DATA_RATE_FB_LIMIT_8188GTV(ptxdesc, 0x1F);
1780 SET_TX_DESC_RTS_RATE_FB_LIMIT_8188GTV(ptxdesc, 0xF);
1781 }
1782 #endif
1783
1784 #if defined(CONFIG_RTL8723D)
fill_tx_desc_8723d(PADAPTER padapter)1785 void fill_tx_desc_8723d(PADAPTER padapter)
1786 {
1787 struct mp_priv *pmp_priv = &padapter->mppriv;
1788 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1789 u8 *ptxdesc = pmp_priv->tx.desc;
1790
1791 SET_TX_DESC_BK_8723D(ptxdesc, 1);
1792 SET_TX_DESC_MACID_8723D(ptxdesc, pattrib->mac_id);
1793 SET_TX_DESC_QUEUE_SEL_8723D(ptxdesc, pattrib->qsel);
1794
1795 SET_TX_DESC_RATE_ID_8723D(ptxdesc, pattrib->raid);
1796 SET_TX_DESC_SEQ_8723D(ptxdesc, pattrib->seqnum);
1797 SET_TX_DESC_HWSEQ_EN_8723D(ptxdesc, 1);
1798 SET_TX_DESC_USE_RATE_8723D(ptxdesc, 1);
1799 SET_TX_DESC_DISABLE_FB_8723D(ptxdesc, 1);
1800
1801 if (pmp_priv->preamble) {
1802 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1803 SET_TX_DESC_DATA_SHORT_8723D(ptxdesc, 1);
1804 }
1805
1806 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1807 SET_TX_DESC_DATA_BW_8723D(ptxdesc, 1);
1808
1809 SET_TX_DESC_TX_RATE_8723D(ptxdesc, pmp_priv->rateidx);
1810
1811 SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(ptxdesc, 0x1F);
1812 SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(ptxdesc, 0xF);
1813 }
1814 #endif
1815
1816 #if defined(CONFIG_RTL8710B)
fill_tx_desc_8710b(PADAPTER padapter)1817 void fill_tx_desc_8710b(PADAPTER padapter)
1818 {
1819 struct mp_priv *pmp_priv = &padapter->mppriv;
1820 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1821 u8 *ptxdesc = pmp_priv->tx.desc;
1822
1823 SET_TX_DESC_BK_8710B(ptxdesc, 1);
1824 SET_TX_DESC_MACID_8710B(ptxdesc, pattrib->mac_id);
1825 SET_TX_DESC_QUEUE_SEL_8710B(ptxdesc, pattrib->qsel);
1826
1827 SET_TX_DESC_RATE_ID_8710B(ptxdesc, pattrib->raid);
1828 SET_TX_DESC_SEQ_8710B(ptxdesc, pattrib->seqnum);
1829 SET_TX_DESC_HWSEQ_EN_8710B(ptxdesc, 1);
1830 SET_TX_DESC_USE_RATE_8710B(ptxdesc, 1);
1831 SET_TX_DESC_DISABLE_FB_8710B(ptxdesc, 1);
1832
1833 if (pmp_priv->preamble) {
1834 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1835 SET_TX_DESC_DATA_SHORT_8710B(ptxdesc, 1);
1836 }
1837
1838 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1839 SET_TX_DESC_DATA_BW_8710B(ptxdesc, 1);
1840
1841 SET_TX_DESC_TX_RATE_8710B(ptxdesc, pmp_priv->rateidx);
1842
1843 SET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(ptxdesc, 0x1F);
1844 SET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(ptxdesc, 0xF);
1845 }
1846 #endif
1847
1848 #if defined(CONFIG_RTL8192F)
fill_tx_desc_8192f(PADAPTER padapter)1849 void fill_tx_desc_8192f(PADAPTER padapter)
1850 {
1851 struct mp_priv *pmp_priv = &padapter->mppriv;
1852 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1853 u8 *ptxdesc = pmp_priv->tx.desc;
1854
1855 SET_TX_DESC_BK_8192F(ptxdesc, 1);
1856 SET_TX_DESC_MACID_8192F(ptxdesc, pattrib->mac_id);
1857 SET_TX_DESC_QUEUE_SEL_8192F(ptxdesc, pattrib->qsel);
1858
1859 SET_TX_DESC_RATE_ID_8192F(ptxdesc, pattrib->raid);
1860 SET_TX_DESC_SEQ_8192F(ptxdesc, pattrib->seqnum);
1861 SET_TX_DESC_HWSEQ_EN_8192F(ptxdesc, 1);
1862 SET_TX_DESC_USE_RATE_8192F(ptxdesc, 1);
1863 SET_TX_DESC_DISABLE_FB_8192F(ptxdesc, 1);
1864
1865 if (pmp_priv->preamble) {
1866 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1867 SET_TX_DESC_DATA_SHORT_8192F(ptxdesc, 1);
1868 }
1869
1870 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1871 SET_TX_DESC_DATA_BW_8192F(ptxdesc, 1);
1872
1873 SET_TX_DESC_TX_RATE_8192F(ptxdesc, pmp_priv->rateidx);
1874
1875 SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(ptxdesc, 0x1F);
1876 SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(ptxdesc, 0xF);
1877 }
1878
1879 #endif
Rtw_MPSetMacTxEDCA(PADAPTER padapter)1880 static void Rtw_MPSetMacTxEDCA(PADAPTER padapter)
1881 {
1882
1883 rtw_write32(padapter, 0x508 , 0x00a422); /* Disable EDCA BE Txop for MP pkt tx adjust Packet interval */
1884 /* RTW_INFO("%s:write 0x508~~~~~~ 0x%x\n", __func__,rtw_read32(padapter, 0x508)); */
1885 phy_set_mac_reg(padapter, 0x458 , bMaskDWord , 0x0);
1886 /*RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" ,__func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));*/
1887 phy_set_mac_reg(padapter, 0x460 , bMaskLWord , 0x0); /* fast EDCA queue packet interval & time out value*/
1888 /*phy_set_mac_reg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C);*/
1889 /*phy_set_mac_reg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C);*/
1890 /*phy_set_mac_reg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C);*/
1891 RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" , __func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));
1892
1893 }
1894
SetPacketTx(PADAPTER padapter)1895 void SetPacketTx(PADAPTER padapter)
1896 {
1897 u8 *ptr, *pkt_start, *pkt_end;
1898 u32 pkt_size = 0, i = 0, idx = 0, tmp_idx = 0;
1899 struct rtw_ieee80211_hdr *hdr;
1900 u8 payload;
1901 s32 bmcast;
1902 struct pkt_attrib *pattrib;
1903 struct mp_priv *pmp_priv;
1904
1905 pmp_priv = &padapter->mppriv;
1906
1907 if (pmp_priv->tx.stop)
1908 return;
1909 pmp_priv->tx.sended = 0;
1910 pmp_priv->tx.stop = 0;
1911 pmp_priv->tx_pktcount = 0;
1912
1913 /* 3 1. update_attrib() */
1914 pattrib = &pmp_priv->tx.attrib;
1915 _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
1916 _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
1917 _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
1918 bmcast = IS_MCAST(pattrib->ra);
1919 if (bmcast)
1920 pattrib->psta = rtw_get_bcmc_stainfo(padapter);
1921 else
1922 pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
1923
1924 if (pattrib->psta == NULL) {
1925 RTW_INFO("%s:psta = NULL !!\n", __func__);
1926 return;
1927 }
1928
1929 pattrib->mac_id = pattrib->psta->cmn.mac_id;
1930 pattrib->mbssid = 0;
1931
1932 pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;
1933
1934 /* 3 2. allocate xmit buffer */
1935 pkt_size = pattrib->last_txcmdsz;
1936
1937 if (pmp_priv->tx.pallocated_buf)
1938 rtw_mfree(pmp_priv->tx.pallocated_buf, pmp_priv->tx.buf_size);
1939 pmp_priv->tx.write_size = pkt_size;
1940 pmp_priv->tx.buf_size = pkt_size + XMITBUF_ALIGN_SZ;
1941 pmp_priv->tx.pallocated_buf = rtw_zmalloc(pmp_priv->tx.buf_size);
1942 if (pmp_priv->tx.pallocated_buf == NULL) {
1943 RTW_INFO("%s: malloc(%d) fail!!\n", __func__, pmp_priv->tx.buf_size);
1944 return;
1945 }
1946 pmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), XMITBUF_ALIGN_SZ);
1947 ptr = pmp_priv->tx.buf;
1948
1949 _rtw_memset(pmp_priv->tx.desc, 0, TXDESC_SIZE);
1950 pkt_start = ptr;
1951 pkt_end = pkt_start + pkt_size;
1952
1953 /* 3 3. init TX descriptor */
1954 #if defined(CONFIG_RTL8188E)
1955 if (IS_HARDWARE_TYPE_8188E(padapter))
1956 fill_tx_desc_8188e(padapter);
1957 #endif
1958
1959 #if defined(CONFIG_RTL8814A)
1960 if (IS_HARDWARE_TYPE_8814A(padapter))
1961 fill_tx_desc_8814a(padapter);
1962 #endif /* defined(CONFIG_RTL8814A) */
1963
1964 #if defined(CONFIG_RTL8822B)
1965 if (IS_HARDWARE_TYPE_8822B(padapter))
1966 rtl8822b_prepare_mp_txdesc(padapter, pmp_priv);
1967 #endif /* CONFIG_RTL8822B */
1968
1969 #if defined(CONFIG_RTL8822C)
1970 if (IS_HARDWARE_TYPE_8822C(padapter))
1971 rtl8822c_prepare_mp_txdesc(padapter, pmp_priv);
1972 #endif /* CONFIG_RTL8822C */
1973
1974 #if defined(CONFIG_RTL8821C)
1975 if (IS_HARDWARE_TYPE_8821C(padapter))
1976 rtl8821c_prepare_mp_txdesc(padapter, pmp_priv);
1977 #endif /* CONFIG_RTL8821C */
1978
1979 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1980 if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter))
1981 fill_tx_desc_8812a(padapter);
1982 #endif
1983
1984 #if defined(CONFIG_RTL8192E)
1985 if (IS_HARDWARE_TYPE_8192E(padapter))
1986 fill_tx_desc_8192e(padapter);
1987 #endif
1988 #if defined(CONFIG_RTL8723B)
1989 if (IS_HARDWARE_TYPE_8723B(padapter))
1990 fill_tx_desc_8723b(padapter);
1991 #endif
1992 #if defined(CONFIG_RTL8703B)
1993 if (IS_HARDWARE_TYPE_8703B(padapter))
1994 fill_tx_desc_8703b(padapter);
1995 #endif
1996
1997 #if defined(CONFIG_RTL8188F)
1998 if (IS_HARDWARE_TYPE_8188F(padapter))
1999 fill_tx_desc_8188f(padapter);
2000 #endif
2001
2002 #if defined(CONFIG_RTL8188GTV)
2003 if (IS_HARDWARE_TYPE_8188GTV(padapter))
2004 fill_tx_desc_8188gtv(padapter);
2005 #endif
2006
2007 #if defined(CONFIG_RTL8723D)
2008 if (IS_HARDWARE_TYPE_8723D(padapter))
2009 fill_tx_desc_8723d(padapter);
2010 #endif
2011 #if defined(CONFIG_RTL8192F)
2012 if (IS_HARDWARE_TYPE_8192F(padapter))
2013 fill_tx_desc_8192f(padapter);
2014 #endif
2015
2016 #if defined(CONFIG_RTL8710B)
2017 if (IS_HARDWARE_TYPE_8710B(padapter))
2018 fill_tx_desc_8710b(padapter);
2019 #endif
2020
2021 #if defined(CONFIG_RTL8814B)
2022 if (IS_HARDWARE_TYPE_8814B(padapter))
2023 rtl8814b_prepare_mp_txdesc(padapter, pmp_priv);
2024 #endif /* CONFIG_RTL8814B */
2025
2026 #if defined(CONFIG_RTL8723F)
2027 if (IS_HARDWARE_TYPE_8723F(padapter))
2028 rtl8723f_prepare_mp_txdesc(padapter, pmp_priv);
2029 #endif /* CONFIG_RTL8723F */
2030
2031 /* 3 4. make wlan header, make_wlanhdr() */
2032 hdr = (struct rtw_ieee80211_hdr *)pkt_start;
2033 set_frame_sub_type(&hdr->frame_ctl, pattrib->subtype);
2034
2035 _rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */
2036 _rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */
2037 _rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */
2038
2039 /* 3 5. make payload */
2040 ptr = pkt_start + pattrib->hdrlen;
2041
2042 if (pmp_priv->mplink_btx == _TRUE) {
2043 _rtw_memcpy(ptr, pmp_priv->mplink_buf, pkt_end - ptr);
2044 } else {
2045 switch (pmp_priv->tx.payload) {
2046 case MP_TX_Payload_00:
2047 RTW_INFO("MP packet tx 0x00 payload!\n");
2048 payload = 0x00;
2049 _rtw_memset(ptr, 0x00, pkt_end - ptr);
2050 break;
2051 case MP_TX_Payload_5a:
2052 RTW_INFO("MP packet tx 0x5a payload!\n");
2053 payload = 0x5a;
2054 _rtw_memset(ptr, 0x5a, pkt_end - ptr);
2055 break;
2056 case MP_TX_Payload_a5:
2057 RTW_INFO("MP packet tx 0xa5 payload!\n");
2058 payload = 0xa5;
2059 _rtw_memset(ptr, 0xa5, pkt_end - ptr);
2060 break;
2061 case MP_TX_Payload_ff:
2062 RTW_INFO("MP packet tx 0xff payload!\n");
2063 payload = 0xff;
2064 _rtw_memset(ptr, 0xff, pkt_end - ptr);
2065 break;
2066 case MP_TX_Payload_prbs9:
2067 RTW_INFO("MP packet tx PRBS9 payload!\n");
2068 while (idx <= pkt_end - ptr) {
2069 int start = 0x02;
2070 int a = start;
2071
2072 for (i = 0;; i++) {
2073 int newbit = (((a >> 8) ^ (a >> 4)) & 1);
2074 a = ((a << 1) | newbit) & 0x1ff;
2075 RTW_DBG("%x ", a);
2076 ptr[idx + i] = a;
2077
2078 if (a == start) {
2079 RTW_INFO("payload repetition period is %d , end %d\n", i , idx);
2080 tmp_idx += i;
2081 break;
2082 }
2083 if (idx + i >= (pkt_end - ptr)) {
2084 tmp_idx += (idx + i);
2085 RTW_INFO(" repetition period payload end curr ptr %d\n", idx + i);
2086 break;
2087 }
2088 }
2089 idx = tmp_idx;
2090 }
2091 break;
2092 case MP_TX_Payload_default_random:
2093 RTW_INFO("MP packet tx default random payload!\n");
2094 for (i = 0; i < pkt_end - ptr; i++)
2095 ptr[i] = rtw_random32() % 0xFF;
2096 break;
2097 default:
2098 RTW_INFO("Config payload type default use 0x%x\n!", pmp_priv->tx.payload);
2099 _rtw_memset(ptr, pmp_priv->tx.payload, pkt_end - ptr);
2100 break;
2101 }
2102 }
2103 /* 3 6. start thread */
2104 #ifdef PLATFORM_LINUX
2105 pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD");
2106 if (IS_ERR(pmp_priv->tx.PktTxThread)) {
2107 RTW_ERR("Create PktTx Thread Fail !!!!!\n");
2108 pmp_priv->tx.PktTxThread = NULL;
2109 }
2110 #endif
2111 #ifdef PLATFORM_FREEBSD
2112 {
2113 struct proc *p;
2114 struct thread *td;
2115 pmp_priv->tx.PktTxThread = kproc_kthread_add(mp_xmit_packet_thread, pmp_priv,
2116 &p, &td, RFHIGHPID, 0, "MPXmitThread", "MPXmitThread");
2117
2118 if (pmp_priv->tx.PktTxThread < 0)
2119 RTW_INFO("Create PktTx Thread Fail !!!!!\n");
2120 }
2121 #endif
2122
2123 Rtw_MPSetMacTxEDCA(padapter);
2124 return;
2125 }
2126
SetPacketRx(PADAPTER pAdapter,u8 bStartRx,u8 bAB)2127 void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB)
2128 {
2129 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
2130 struct mp_priv *pmppriv = &pAdapter->mppriv;
2131
2132
2133 if (bStartRx) {
2134 #ifdef CONFIG_RTL8723B
2135 phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x3); /* Power on adc (in RX_WAIT_CCA state) */
2136 write_bbreg(pAdapter, 0xa01, BIT0, bDisable);/* improve Rx performance by jerry */
2137 #endif
2138 pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AMF | RCR_HTC_LOC_CTRL;
2139 pHalData->ReceiveConfig |= RCR_ACRC32;
2140 pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
2141
2142 if (pmppriv->bSetRxBssid == _TRUE) {
2143 RTW_INFO("%s: pmppriv->network_macaddr=" MAC_FMT "\n", __func__,
2144 MAC_ARG(pmppriv->network_macaddr));
2145 pHalData->ReceiveConfig = 0;
2146 pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN |RCR_APM | RCR_AM | RCR_AB |RCR_AMF;
2147 pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF;
2148
2149 #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
2150 /* todo: 8723F */
2151 write_bbreg(pAdapter, 0x550, BIT3, bEnable);
2152 #endif
2153 rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFEF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
2154 pmppriv->brx_filter_beacon = _TRUE;
2155
2156 } else {
2157 pHalData->ReceiveConfig |= RCR_ADF;
2158 /* Accept all data frames */
2159 rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF);
2160 }
2161
2162 if (bAB)
2163 pHalData->ReceiveConfig |= RCR_AB;
2164 } else {
2165 #ifdef CONFIG_RTL8723B
2166 phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x00); /* Power off adc (in RX_WAIT_CCA state)*/
2167 write_bbreg(pAdapter, 0xa01, BIT0, bEnable);/* improve Rx performance by jerry */
2168 #endif
2169 pHalData->ReceiveConfig = 0;
2170 rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFFF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
2171 }
2172
2173 rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);
2174 }
2175
ResetPhyRxPktCount(PADAPTER pAdapter)2176 void ResetPhyRxPktCount(PADAPTER pAdapter)
2177 {
2178 u32 i, phyrx_set = 0;
2179
2180 for (i = 0; i <= 0xF; i++) {
2181 phyrx_set = 0;
2182 phyrx_set |= _RXERR_RPT_SEL(i); /* select */
2183 phyrx_set |= RXERR_RPT_RST; /* set counter to zero */
2184 rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
2185 }
2186 }
2187
GetPhyRxPktCounts(PADAPTER pAdapter,u32 selbit)2188 static u32 GetPhyRxPktCounts(PADAPTER pAdapter, u32 selbit)
2189 {
2190 /* selection */
2191 u32 phyrx_set = 0, count = 0;
2192
2193 phyrx_set = _RXERR_RPT_SEL(selbit & 0xF);
2194 rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
2195
2196 /* Read packet count */
2197 count = rtw_read32(pAdapter, REG_RXERR_RPT) & RXERR_COUNTER_MASK;
2198
2199 return count;
2200 }
2201
GetPhyRxPktReceived(PADAPTER pAdapter)2202 u32 GetPhyRxPktReceived(PADAPTER pAdapter)
2203 {
2204 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
2205
2206 OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_OK);
2207 CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_OK);
2208 HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_OK);
2209
2210 return OFDM_cnt + CCK_cnt + HT_cnt;
2211 }
2212
GetPhyRxPktCRC32Error(PADAPTER pAdapter)2213 u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter)
2214 {
2215 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
2216
2217 OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_FAIL);
2218 CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_FAIL);
2219 HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_FAIL);
2220
2221 return OFDM_cnt + CCK_cnt + HT_cnt;
2222 }
2223
2224 struct psd_init_regs {
2225 /* 3 wire */
2226 int reg_88c;
2227 int reg_c00;
2228 int reg_e00;
2229 int reg_1800;
2230 int reg_1a00;
2231 /* cck */
2232 int reg_800;
2233 int reg_808;
2234 };
2235
rtw_mp_psd_init(PADAPTER padapter,struct psd_init_regs * regs)2236 static int rtw_mp_psd_init(PADAPTER padapter, struct psd_init_regs *regs)
2237 {
2238 HAL_DATA_TYPE *phal_data = GET_HAL_DATA(padapter);
2239
2240 switch (phal_data->rf_type) {
2241 /* 1R */
2242 case RF_1T1R:
2243 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2244 /* 11AC 1R PSD Setting 3wire & cck off */
2245 regs->reg_c00 = rtw_read32(padapter, 0xC00);
2246 phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
2247 regs->reg_808 = rtw_read32(padapter, 0x808);
2248 phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
2249 } else {
2250 /* 11N 3-wire off 1 */
2251 regs->reg_88c = rtw_read32(padapter, 0x88C);
2252 phy_set_bb_reg(padapter, 0x88C, 0x300000, 0x3);
2253 /* 11N CCK off */
2254 regs->reg_800 = rtw_read32(padapter, 0x800);
2255 phy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0);
2256 }
2257 break;
2258
2259 /* 2R */
2260 case RF_1T2R:
2261 case RF_2T2R:
2262 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2263 /* 11AC 2R PSD Setting 3wire & cck off */
2264 regs->reg_c00 = rtw_read32(padapter, 0xC00);
2265 regs->reg_e00 = rtw_read32(padapter, 0xE00);
2266 phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
2267 phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
2268 regs->reg_808 = rtw_read32(padapter, 0x808);
2269 phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
2270 } else {
2271 /* 11N 3-wire off 2 */
2272 regs->reg_88c = rtw_read32(padapter, 0x88C);
2273 phy_set_bb_reg(padapter, 0x88C, 0xF00000, 0xF);
2274 /* 11N CCK off */
2275 regs->reg_800 = rtw_read32(padapter, 0x800);
2276 phy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0);
2277 }
2278 break;
2279
2280 /* 3R */
2281 case RF_2T3R:
2282 case RF_3T3R:
2283 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2284 /* 11AC 3R PSD Setting 3wire & cck off */
2285 regs->reg_c00 = rtw_read32(padapter, 0xC00);
2286 regs->reg_e00 = rtw_read32(padapter, 0xE00);
2287 regs->reg_1800 = rtw_read32(padapter, 0x1800);
2288 phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
2289 phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
2290 phy_set_bb_reg(padapter, 0x1800, 0x3, 0x00);
2291 regs->reg_808 = rtw_read32(padapter, 0x808);
2292 phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
2293 } else {
2294 RTW_ERR("%s: 11n don't support 3R\n", __func__);
2295 return -1;
2296 }
2297 break;
2298
2299 /* 4R */
2300 case RF_2T4R:
2301 case RF_3T4R:
2302 case RF_4T4R:
2303 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2304 /* 11AC 4R PSD Setting 3wire & cck off */
2305 regs->reg_c00 = rtw_read32(padapter, 0xC00);
2306 regs->reg_e00 = rtw_read32(padapter, 0xE00);
2307 regs->reg_1800 = rtw_read32(padapter, 0x1800);
2308 regs->reg_1a00 = rtw_read32(padapter, 0x1A00);
2309 phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
2310 phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
2311 phy_set_bb_reg(padapter, 0x1800, 0x3, 0x00);
2312 phy_set_bb_reg(padapter, 0x1A00, 0x3, 0x00);
2313 regs->reg_808 = rtw_read32(padapter, 0x808);
2314 phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
2315 } else {
2316 RTW_ERR("%s: 11n don't support 4R\n", __func__);
2317 return -1;
2318 }
2319 break;
2320
2321 default:
2322 RTW_ERR("%s: unknown %d rf type\n", __func__, phal_data->rf_type);
2323 return -1;
2324 }
2325
2326 /* Set PSD points, 0=128, 1=256, 2=512, 3=1024 */
2327 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC))
2328 phy_set_bb_reg(padapter, 0x910, 0xC000, 3);
2329 else
2330 phy_set_bb_reg(padapter, 0x808, 0xC000, 3);
2331
2332 RTW_INFO("%s: set %d rf type done\n", __func__, phal_data->rf_type);
2333 return 0;
2334 }
2335
rtw_mp_psd_close(PADAPTER padapter,struct psd_init_regs * regs)2336 static int rtw_mp_psd_close(PADAPTER padapter, struct psd_init_regs *regs)
2337 {
2338 HAL_DATA_TYPE *phal_data = GET_HAL_DATA(padapter);
2339
2340
2341 if (!hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2342 /* 11n 3wire restore */
2343 rtw_write32(padapter, 0x88C, regs->reg_88c);
2344 /* 11n cck restore */
2345 rtw_write32(padapter, 0x800, regs->reg_800);
2346 RTW_INFO("%s: restore %d rf type\n", __func__, phal_data->rf_type);
2347 return 0;
2348 }
2349
2350 /* 11ac 3wire restore */
2351 switch (phal_data->rf_type) {
2352 case RF_1T1R:
2353 rtw_write32(padapter, 0xC00, regs->reg_c00);
2354 break;
2355 case RF_1T2R:
2356 case RF_2T2R:
2357 rtw_write32(padapter, 0xC00, regs->reg_c00);
2358 rtw_write32(padapter, 0xE00, regs->reg_e00);
2359 break;
2360 case RF_2T3R:
2361 case RF_3T3R:
2362 rtw_write32(padapter, 0xC00, regs->reg_c00);
2363 rtw_write32(padapter, 0xE00, regs->reg_e00);
2364 rtw_write32(padapter, 0x1800, regs->reg_1800);
2365 break;
2366 case RF_2T4R:
2367 case RF_3T4R:
2368 case RF_4T4R:
2369 rtw_write32(padapter, 0xC00, regs->reg_c00);
2370 rtw_write32(padapter, 0xE00, regs->reg_e00);
2371 rtw_write32(padapter, 0x1800, regs->reg_1800);
2372 rtw_write32(padapter, 0x1A00, regs->reg_1a00);
2373 break;
2374 default:
2375 RTW_WARN("%s: unknown %d rf type\n", __func__, phal_data->rf_type);
2376 break;
2377 }
2378
2379 /* 11ac cck restore */
2380 rtw_write32(padapter, 0x808, regs->reg_808);
2381 RTW_INFO("%s: restore %d rf type done\n", __func__, phal_data->rf_type);
2382 return 0;
2383 }
2384
2385 /* reg 0x808[9:0]: FFT data x
2386 * reg 0x808[22]: 0 --> 1 to get 1 FFT data y
2387 * reg 0x8B4[15:0]: FFT data y report */
rtw_GetPSDData(PADAPTER pAdapter,u32 point)2388 static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point)
2389 {
2390 u32 psd_val = 0;
2391
2392 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) \
2393 || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
2394
2395 u16 psd_reg = 0x910;
2396 u16 psd_regL = 0xF44;
2397 #else
2398 u16 psd_reg = 0x808;
2399 u16 psd_regL = 0x8B4;
2400 #endif
2401
2402 psd_val = rtw_read32(pAdapter, psd_reg);
2403
2404 psd_val &= 0xFFBFFC00;
2405 psd_val |= point;
2406
2407 rtw_write32(pAdapter, psd_reg, psd_val);
2408 rtw_mdelay_os(1);
2409 psd_val |= 0x00400000;
2410
2411 rtw_write32(pAdapter, psd_reg, psd_val);
2412 rtw_mdelay_os(1);
2413
2414 psd_val = rtw_read32(pAdapter, psd_regL);
2415 #if defined(CONFIG_RTL8821C)
2416 psd_val = (psd_val & 0x00FFFFFF) / 32;
2417 #else
2418 psd_val &= 0x0000FFFF;
2419 #endif
2420
2421 return psd_val;
2422 }
2423
2424 /*
2425 * pts start_point_min stop_point_max
2426 * 128 64 64 + 128 = 192
2427 * 256 128 128 + 256 = 384
2428 * 512 256 256 + 512 = 768
2429 * 1024 512 512 + 1024 = 1536
2430 *
2431 */
mp_query_psd(PADAPTER pAdapter,u8 * data)2432 u32 mp_query_psd(PADAPTER pAdapter, u8 *data)
2433 {
2434 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2435 struct dm_struct *p_dm = adapter_to_phydm(pAdapter);
2436
2437 u32 i, psd_pts = 0, psd_start = 0, psd_stop = 0;
2438 u32 psd_data = 0;
2439 struct psd_init_regs regs = {};
2440 int psd_analysis = 0;
2441 char *pdata = NULL;
2442
2443
2444 #ifdef PLATFORM_LINUX
2445 if (!netif_running(pAdapter->pnetdev)) {
2446 return 0;
2447 }
2448 #endif
2449
2450 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
2451 return 0;
2452 }
2453
2454 if (strlen(data) == 0) { /* default value */
2455 psd_pts = 128;
2456 psd_start = 64;
2457 psd_stop = 128;
2458 } else if (strncmp(data, "analysis,", 9) == 0) {
2459 if (rtw_mp_psd_init(pAdapter, ®s) != 0)
2460 return 0;
2461 psd_analysis = 1;
2462 sscanf(data + 9, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
2463 } else
2464 sscanf(data, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
2465
2466 data[0] = '\0';
2467 pdata = data;
2468
2469 if (psd_stop > 1920 || psd_stop < 1) {
2470 rtw_warn_on(1);
2471 psd_stop = 1920;
2472 }
2473
2474 if (IS_HARDWARE_TYPE_8822C(pAdapter) || IS_HARDWARE_TYPE_8723F(pAdapter)) {
2475 u32 *psdbuf = rtw_zmalloc(sizeof(u32)*256);
2476
2477 if (psdbuf == NULL) {
2478 RTW_INFO("%s: psd buf malloc fail!!\n", __func__);
2479 return 0;
2480 }
2481
2482 halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_POINT, psd_pts);
2483 halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_START_POINT, psd_start);
2484 halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_STOP_POINT, psd_stop);
2485 halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_AVERAGE, 0x20000);
2486
2487 halrf_psd_init(p_dm);
2488 #ifdef CONFIG_LONG_DELAY_ISSUE
2489 rtw_msleep_os(100);
2490 #else
2491 rtw_mdelay_os(10);
2492 #endif
2493 halrf_psd_query(p_dm, psdbuf, 256);
2494
2495 i = 0;
2496 while (i < 256) {
2497 pdata += sprintf(pdata, "%x ", (psdbuf[i]));
2498 i++;
2499 }
2500
2501 if (psdbuf)
2502 rtw_mfree(psdbuf, sizeof(u32)*256);
2503
2504 } else {
2505 i = psd_start;
2506
2507 while (i < psd_stop) {
2508 if (i >= psd_pts)
2509 psd_data = rtw_GetPSDData(pAdapter, i - psd_pts);
2510 else
2511 psd_data = rtw_GetPSDData(pAdapter, i);
2512
2513 pdata += sprintf(pdata, "%x ", psd_data);
2514 i++;
2515 }
2516
2517 }
2518
2519 #ifdef CONFIG_LONG_DELAY_ISSUE
2520 rtw_msleep_os(100);
2521 #else
2522 rtw_mdelay_os(100);
2523 #endif
2524
2525 if (psd_analysis)
2526 rtw_mp_psd_close(pAdapter, ®s);
2527
2528 return strlen(data) + 1;
2529 }
2530
2531
2532 #if 0
2533 void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv)
2534 {
2535 int i, res;
2536 _adapter *padapter = pxmitpriv->adapter;
2537 struct xmit_frame *pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;
2538 struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
2539
2540 u32 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
2541 u32 num_xmit_extbuf = NR_XMIT_EXTBUFF;
2542 if (padapter->registrypriv.mp_mode == 0) {
2543 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
2544 num_xmit_extbuf = NR_XMIT_EXTBUFF;
2545 } else {
2546 max_xmit_extbuf_size = 6000;
2547 num_xmit_extbuf = 8;
2548 }
2549
2550 pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
2551 for (i = 0; i < num_xmit_extbuf; i++) {
2552 rtw_os_xmit_resource_free(padapter, pxmitbuf, (max_xmit_extbuf_size + XMITBUF_ALIGN_SZ), _FALSE);
2553
2554 pxmitbuf++;
2555 }
2556
2557 if (pxmitpriv->pallocated_xmit_extbuf)
2558 rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
2559
2560 if (padapter->registrypriv.mp_mode == 0) {
2561 max_xmit_extbuf_size = 6000;
2562 num_xmit_extbuf = 8;
2563 } else {
2564 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
2565 num_xmit_extbuf = NR_XMIT_EXTBUFF;
2566 }
2567
2568 /* Init xmit extension buff */
2569 _rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue);
2570
2571 pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
2572
2573 if (pxmitpriv->pallocated_xmit_extbuf == NULL) {
2574 res = _FAIL;
2575 goto exit;
2576 }
2577
2578 pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4);
2579
2580 pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
2581
2582 for (i = 0; i < num_xmit_extbuf; i++) {
2583 _rtw_init_listhead(&pxmitbuf->list);
2584
2585 pxmitbuf->priv_data = NULL;
2586 pxmitbuf->padapter = padapter;
2587 pxmitbuf->buf_tag = XMITBUF_MGNT;
2588
2589 res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, max_xmit_extbuf_size + XMITBUF_ALIGN_SZ, _TRUE);
2590 if (res == _FAIL) {
2591 res = _FAIL;
2592 goto exit;
2593 }
2594
2595 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
2596 pxmitbuf->phead = pxmitbuf->pbuf;
2597 pxmitbuf->pend = pxmitbuf->pbuf + max_xmit_extbuf_size;
2598 pxmitbuf->len = 0;
2599 pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
2600 #endif
2601
2602 rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue));
2603 #ifdef DBG_XMIT_BUF_EXT
2604 pxmitbuf->no = i;
2605 #endif
2606 pxmitbuf++;
2607
2608 }
2609
2610 pxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf;
2611
2612 exit:
2613 ;
2614 }
2615 #endif
2616
2617 u8
mpt_to_mgnt_rate(u32 MptRateIdx)2618 mpt_to_mgnt_rate(
2619 u32 MptRateIdx
2620 )
2621 {
2622 /* Mapped to MGN_XXX defined in MgntGen.h */
2623 switch (MptRateIdx) {
2624 /* CCK rate. */
2625 case MPT_RATE_1M:
2626 return MGN_1M;
2627 case MPT_RATE_2M:
2628 return MGN_2M;
2629 case MPT_RATE_55M:
2630 return MGN_5_5M;
2631 case MPT_RATE_11M:
2632 return MGN_11M;
2633
2634 /* OFDM rate. */
2635 case MPT_RATE_6M:
2636 return MGN_6M;
2637 case MPT_RATE_9M:
2638 return MGN_9M;
2639 case MPT_RATE_12M:
2640 return MGN_12M;
2641 case MPT_RATE_18M:
2642 return MGN_18M;
2643 case MPT_RATE_24M:
2644 return MGN_24M;
2645 case MPT_RATE_36M:
2646 return MGN_36M;
2647 case MPT_RATE_48M:
2648 return MGN_48M;
2649 case MPT_RATE_54M:
2650 return MGN_54M;
2651
2652 /* HT rate. */
2653 case MPT_RATE_MCS0:
2654 return MGN_MCS0;
2655 case MPT_RATE_MCS1:
2656 return MGN_MCS1;
2657 case MPT_RATE_MCS2:
2658 return MGN_MCS2;
2659 case MPT_RATE_MCS3:
2660 return MGN_MCS3;
2661 case MPT_RATE_MCS4:
2662 return MGN_MCS4;
2663 case MPT_RATE_MCS5:
2664 return MGN_MCS5;
2665 case MPT_RATE_MCS6:
2666 return MGN_MCS6;
2667 case MPT_RATE_MCS7:
2668 return MGN_MCS7;
2669 case MPT_RATE_MCS8:
2670 return MGN_MCS8;
2671 case MPT_RATE_MCS9:
2672 return MGN_MCS9;
2673 case MPT_RATE_MCS10:
2674 return MGN_MCS10;
2675 case MPT_RATE_MCS11:
2676 return MGN_MCS11;
2677 case MPT_RATE_MCS12:
2678 return MGN_MCS12;
2679 case MPT_RATE_MCS13:
2680 return MGN_MCS13;
2681 case MPT_RATE_MCS14:
2682 return MGN_MCS14;
2683 case MPT_RATE_MCS15:
2684 return MGN_MCS15;
2685 case MPT_RATE_MCS16:
2686 return MGN_MCS16;
2687 case MPT_RATE_MCS17:
2688 return MGN_MCS17;
2689 case MPT_RATE_MCS18:
2690 return MGN_MCS18;
2691 case MPT_RATE_MCS19:
2692 return MGN_MCS19;
2693 case MPT_RATE_MCS20:
2694 return MGN_MCS20;
2695 case MPT_RATE_MCS21:
2696 return MGN_MCS21;
2697 case MPT_RATE_MCS22:
2698 return MGN_MCS22;
2699 case MPT_RATE_MCS23:
2700 return MGN_MCS23;
2701 case MPT_RATE_MCS24:
2702 return MGN_MCS24;
2703 case MPT_RATE_MCS25:
2704 return MGN_MCS25;
2705 case MPT_RATE_MCS26:
2706 return MGN_MCS26;
2707 case MPT_RATE_MCS27:
2708 return MGN_MCS27;
2709 case MPT_RATE_MCS28:
2710 return MGN_MCS28;
2711 case MPT_RATE_MCS29:
2712 return MGN_MCS29;
2713 case MPT_RATE_MCS30:
2714 return MGN_MCS30;
2715 case MPT_RATE_MCS31:
2716 return MGN_MCS31;
2717
2718 /* VHT rate. */
2719 case MPT_RATE_VHT1SS_MCS0:
2720 return MGN_VHT1SS_MCS0;
2721 case MPT_RATE_VHT1SS_MCS1:
2722 return MGN_VHT1SS_MCS1;
2723 case MPT_RATE_VHT1SS_MCS2:
2724 return MGN_VHT1SS_MCS2;
2725 case MPT_RATE_VHT1SS_MCS3:
2726 return MGN_VHT1SS_MCS3;
2727 case MPT_RATE_VHT1SS_MCS4:
2728 return MGN_VHT1SS_MCS4;
2729 case MPT_RATE_VHT1SS_MCS5:
2730 return MGN_VHT1SS_MCS5;
2731 case MPT_RATE_VHT1SS_MCS6:
2732 return MGN_VHT1SS_MCS6;
2733 case MPT_RATE_VHT1SS_MCS7:
2734 return MGN_VHT1SS_MCS7;
2735 case MPT_RATE_VHT1SS_MCS8:
2736 return MGN_VHT1SS_MCS8;
2737 case MPT_RATE_VHT1SS_MCS9:
2738 return MGN_VHT1SS_MCS9;
2739 case MPT_RATE_VHT2SS_MCS0:
2740 return MGN_VHT2SS_MCS0;
2741 case MPT_RATE_VHT2SS_MCS1:
2742 return MGN_VHT2SS_MCS1;
2743 case MPT_RATE_VHT2SS_MCS2:
2744 return MGN_VHT2SS_MCS2;
2745 case MPT_RATE_VHT2SS_MCS3:
2746 return MGN_VHT2SS_MCS3;
2747 case MPT_RATE_VHT2SS_MCS4:
2748 return MGN_VHT2SS_MCS4;
2749 case MPT_RATE_VHT2SS_MCS5:
2750 return MGN_VHT2SS_MCS5;
2751 case MPT_RATE_VHT2SS_MCS6:
2752 return MGN_VHT2SS_MCS6;
2753 case MPT_RATE_VHT2SS_MCS7:
2754 return MGN_VHT2SS_MCS7;
2755 case MPT_RATE_VHT2SS_MCS8:
2756 return MGN_VHT2SS_MCS8;
2757 case MPT_RATE_VHT2SS_MCS9:
2758 return MGN_VHT2SS_MCS9;
2759 case MPT_RATE_VHT3SS_MCS0:
2760 return MGN_VHT3SS_MCS0;
2761 case MPT_RATE_VHT3SS_MCS1:
2762 return MGN_VHT3SS_MCS1;
2763 case MPT_RATE_VHT3SS_MCS2:
2764 return MGN_VHT3SS_MCS2;
2765 case MPT_RATE_VHT3SS_MCS3:
2766 return MGN_VHT3SS_MCS3;
2767 case MPT_RATE_VHT3SS_MCS4:
2768 return MGN_VHT3SS_MCS4;
2769 case MPT_RATE_VHT3SS_MCS5:
2770 return MGN_VHT3SS_MCS5;
2771 case MPT_RATE_VHT3SS_MCS6:
2772 return MGN_VHT3SS_MCS6;
2773 case MPT_RATE_VHT3SS_MCS7:
2774 return MGN_VHT3SS_MCS7;
2775 case MPT_RATE_VHT3SS_MCS8:
2776 return MGN_VHT3SS_MCS8;
2777 case MPT_RATE_VHT3SS_MCS9:
2778 return MGN_VHT3SS_MCS9;
2779 case MPT_RATE_VHT4SS_MCS0:
2780 return MGN_VHT4SS_MCS0;
2781 case MPT_RATE_VHT4SS_MCS1:
2782 return MGN_VHT4SS_MCS1;
2783 case MPT_RATE_VHT4SS_MCS2:
2784 return MGN_VHT4SS_MCS2;
2785 case MPT_RATE_VHT4SS_MCS3:
2786 return MGN_VHT4SS_MCS3;
2787 case MPT_RATE_VHT4SS_MCS4:
2788 return MGN_VHT4SS_MCS4;
2789 case MPT_RATE_VHT4SS_MCS5:
2790 return MGN_VHT4SS_MCS5;
2791 case MPT_RATE_VHT4SS_MCS6:
2792 return MGN_VHT4SS_MCS6;
2793 case MPT_RATE_VHT4SS_MCS7:
2794 return MGN_VHT4SS_MCS7;
2795 case MPT_RATE_VHT4SS_MCS8:
2796 return MGN_VHT4SS_MCS8;
2797 case MPT_RATE_VHT4SS_MCS9:
2798 return MGN_VHT4SS_MCS9;
2799
2800 case MPT_RATE_LAST: /* fully automatiMGN_VHT2SS_MCS1; */
2801 default:
2802 RTW_INFO("<===mpt_to_mgnt_rate(), Invalid Rate: %d!!\n", MptRateIdx);
2803 return 0x0;
2804 }
2805 }
2806
2807
HwRateToMPTRate(u8 rate)2808 u8 HwRateToMPTRate(u8 rate)
2809 {
2810 u8 ret_rate = MGN_1M;
2811
2812 switch (rate) {
2813 case DESC_RATE1M:
2814 ret_rate = MPT_RATE_1M;
2815 break;
2816 case DESC_RATE2M:
2817 ret_rate = MPT_RATE_2M;
2818 break;
2819 case DESC_RATE5_5M:
2820 ret_rate = MPT_RATE_55M;
2821 break;
2822 case DESC_RATE11M:
2823 ret_rate = MPT_RATE_11M;
2824 break;
2825 case DESC_RATE6M:
2826 ret_rate = MPT_RATE_6M;
2827 break;
2828 case DESC_RATE9M:
2829 ret_rate = MPT_RATE_9M;
2830 break;
2831 case DESC_RATE12M:
2832 ret_rate = MPT_RATE_12M;
2833 break;
2834 case DESC_RATE18M:
2835 ret_rate = MPT_RATE_18M;
2836 break;
2837 case DESC_RATE24M:
2838 ret_rate = MPT_RATE_24M;
2839 break;
2840 case DESC_RATE36M:
2841 ret_rate = MPT_RATE_36M;
2842 break;
2843 case DESC_RATE48M:
2844 ret_rate = MPT_RATE_48M;
2845 break;
2846 case DESC_RATE54M:
2847 ret_rate = MPT_RATE_54M;
2848 break;
2849 case DESC_RATEMCS0:
2850 ret_rate = MPT_RATE_MCS0;
2851 break;
2852 case DESC_RATEMCS1:
2853 ret_rate = MPT_RATE_MCS1;
2854 break;
2855 case DESC_RATEMCS2:
2856 ret_rate = MPT_RATE_MCS2;
2857 break;
2858 case DESC_RATEMCS3:
2859 ret_rate = MPT_RATE_MCS3;
2860 break;
2861 case DESC_RATEMCS4:
2862 ret_rate = MPT_RATE_MCS4;
2863 break;
2864 case DESC_RATEMCS5:
2865 ret_rate = MPT_RATE_MCS5;
2866 break;
2867 case DESC_RATEMCS6:
2868 ret_rate = MPT_RATE_MCS6;
2869 break;
2870 case DESC_RATEMCS7:
2871 ret_rate = MPT_RATE_MCS7;
2872 break;
2873 case DESC_RATEMCS8:
2874 ret_rate = MPT_RATE_MCS8;
2875 break;
2876 case DESC_RATEMCS9:
2877 ret_rate = MPT_RATE_MCS9;
2878 break;
2879 case DESC_RATEMCS10:
2880 ret_rate = MPT_RATE_MCS10;
2881 break;
2882 case DESC_RATEMCS11:
2883 ret_rate = MPT_RATE_MCS11;
2884 break;
2885 case DESC_RATEMCS12:
2886 ret_rate = MPT_RATE_MCS12;
2887 break;
2888 case DESC_RATEMCS13:
2889 ret_rate = MPT_RATE_MCS13;
2890 break;
2891 case DESC_RATEMCS14:
2892 ret_rate = MPT_RATE_MCS14;
2893 break;
2894 case DESC_RATEMCS15:
2895 ret_rate = MPT_RATE_MCS15;
2896 break;
2897 case DESC_RATEMCS16:
2898 ret_rate = MPT_RATE_MCS16;
2899 break;
2900 case DESC_RATEMCS17:
2901 ret_rate = MPT_RATE_MCS17;
2902 break;
2903 case DESC_RATEMCS18:
2904 ret_rate = MPT_RATE_MCS18;
2905 break;
2906 case DESC_RATEMCS19:
2907 ret_rate = MPT_RATE_MCS19;
2908 break;
2909 case DESC_RATEMCS20:
2910 ret_rate = MPT_RATE_MCS20;
2911 break;
2912 case DESC_RATEMCS21:
2913 ret_rate = MPT_RATE_MCS21;
2914 break;
2915 case DESC_RATEMCS22:
2916 ret_rate = MPT_RATE_MCS22;
2917 break;
2918 case DESC_RATEMCS23:
2919 ret_rate = MPT_RATE_MCS23;
2920 break;
2921 case DESC_RATEMCS24:
2922 ret_rate = MPT_RATE_MCS24;
2923 break;
2924 case DESC_RATEMCS25:
2925 ret_rate = MPT_RATE_MCS25;
2926 break;
2927 case DESC_RATEMCS26:
2928 ret_rate = MPT_RATE_MCS26;
2929 break;
2930 case DESC_RATEMCS27:
2931 ret_rate = MPT_RATE_MCS27;
2932 break;
2933 case DESC_RATEMCS28:
2934 ret_rate = MPT_RATE_MCS28;
2935 break;
2936 case DESC_RATEMCS29:
2937 ret_rate = MPT_RATE_MCS29;
2938 break;
2939 case DESC_RATEMCS30:
2940 ret_rate = MPT_RATE_MCS30;
2941 break;
2942 case DESC_RATEMCS31:
2943 ret_rate = MPT_RATE_MCS31;
2944 break;
2945 case DESC_RATEVHTSS1MCS0:
2946 ret_rate = MPT_RATE_VHT1SS_MCS0;
2947 break;
2948 case DESC_RATEVHTSS1MCS1:
2949 ret_rate = MPT_RATE_VHT1SS_MCS1;
2950 break;
2951 case DESC_RATEVHTSS1MCS2:
2952 ret_rate = MPT_RATE_VHT1SS_MCS2;
2953 break;
2954 case DESC_RATEVHTSS1MCS3:
2955 ret_rate = MPT_RATE_VHT1SS_MCS3;
2956 break;
2957 case DESC_RATEVHTSS1MCS4:
2958 ret_rate = MPT_RATE_VHT1SS_MCS4;
2959 break;
2960 case DESC_RATEVHTSS1MCS5:
2961 ret_rate = MPT_RATE_VHT1SS_MCS5;
2962 break;
2963 case DESC_RATEVHTSS1MCS6:
2964 ret_rate = MPT_RATE_VHT1SS_MCS6;
2965 break;
2966 case DESC_RATEVHTSS1MCS7:
2967 ret_rate = MPT_RATE_VHT1SS_MCS7;
2968 break;
2969 case DESC_RATEVHTSS1MCS8:
2970 ret_rate = MPT_RATE_VHT1SS_MCS8;
2971 break;
2972 case DESC_RATEVHTSS1MCS9:
2973 ret_rate = MPT_RATE_VHT1SS_MCS9;
2974 break;
2975 case DESC_RATEVHTSS2MCS0:
2976 ret_rate = MPT_RATE_VHT2SS_MCS0;
2977 break;
2978 case DESC_RATEVHTSS2MCS1:
2979 ret_rate = MPT_RATE_VHT2SS_MCS1;
2980 break;
2981 case DESC_RATEVHTSS2MCS2:
2982 ret_rate = MPT_RATE_VHT2SS_MCS2;
2983 break;
2984 case DESC_RATEVHTSS2MCS3:
2985 ret_rate = MPT_RATE_VHT2SS_MCS3;
2986 break;
2987 case DESC_RATEVHTSS2MCS4:
2988 ret_rate = MPT_RATE_VHT2SS_MCS4;
2989 break;
2990 case DESC_RATEVHTSS2MCS5:
2991 ret_rate = MPT_RATE_VHT2SS_MCS5;
2992 break;
2993 case DESC_RATEVHTSS2MCS6:
2994 ret_rate = MPT_RATE_VHT2SS_MCS6;
2995 break;
2996 case DESC_RATEVHTSS2MCS7:
2997 ret_rate = MPT_RATE_VHT2SS_MCS7;
2998 break;
2999 case DESC_RATEVHTSS2MCS8:
3000 ret_rate = MPT_RATE_VHT2SS_MCS8;
3001 break;
3002 case DESC_RATEVHTSS2MCS9:
3003 ret_rate = MPT_RATE_VHT2SS_MCS9;
3004 break;
3005 case DESC_RATEVHTSS3MCS0:
3006 ret_rate = MPT_RATE_VHT3SS_MCS0;
3007 break;
3008 case DESC_RATEVHTSS3MCS1:
3009 ret_rate = MPT_RATE_VHT3SS_MCS1;
3010 break;
3011 case DESC_RATEVHTSS3MCS2:
3012 ret_rate = MPT_RATE_VHT3SS_MCS2;
3013 break;
3014 case DESC_RATEVHTSS3MCS3:
3015 ret_rate = MPT_RATE_VHT3SS_MCS3;
3016 break;
3017 case DESC_RATEVHTSS3MCS4:
3018 ret_rate = MPT_RATE_VHT3SS_MCS4;
3019 break;
3020 case DESC_RATEVHTSS3MCS5:
3021 ret_rate = MPT_RATE_VHT3SS_MCS5;
3022 break;
3023 case DESC_RATEVHTSS3MCS6:
3024 ret_rate = MPT_RATE_VHT3SS_MCS6;
3025 break;
3026 case DESC_RATEVHTSS3MCS7:
3027 ret_rate = MPT_RATE_VHT3SS_MCS7;
3028 break;
3029 case DESC_RATEVHTSS3MCS8:
3030 ret_rate = MPT_RATE_VHT3SS_MCS8;
3031 break;
3032 case DESC_RATEVHTSS3MCS9:
3033 ret_rate = MPT_RATE_VHT3SS_MCS9;
3034 break;
3035 case DESC_RATEVHTSS4MCS0:
3036 ret_rate = MPT_RATE_VHT4SS_MCS0;
3037 break;
3038 case DESC_RATEVHTSS4MCS1:
3039 ret_rate = MPT_RATE_VHT4SS_MCS1;
3040 break;
3041 case DESC_RATEVHTSS4MCS2:
3042 ret_rate = MPT_RATE_VHT4SS_MCS2;
3043 break;
3044 case DESC_RATEVHTSS4MCS3:
3045 ret_rate = MPT_RATE_VHT4SS_MCS3;
3046 break;
3047 case DESC_RATEVHTSS4MCS4:
3048 ret_rate = MPT_RATE_VHT4SS_MCS4;
3049 break;
3050 case DESC_RATEVHTSS4MCS5:
3051 ret_rate = MPT_RATE_VHT4SS_MCS5;
3052 break;
3053 case DESC_RATEVHTSS4MCS6:
3054 ret_rate = MPT_RATE_VHT4SS_MCS6;
3055 break;
3056 case DESC_RATEVHTSS4MCS7:
3057 ret_rate = MPT_RATE_VHT4SS_MCS7;
3058 break;
3059 case DESC_RATEVHTSS4MCS8:
3060 ret_rate = MPT_RATE_VHT4SS_MCS8;
3061 break;
3062 case DESC_RATEVHTSS4MCS9:
3063 ret_rate = MPT_RATE_VHT4SS_MCS9;
3064 break;
3065
3066 default:
3067 RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate);
3068 break;
3069 }
3070 return ret_rate;
3071 }
3072
rtw_mpRateParseFunc(PADAPTER pAdapter,u8 * targetStr)3073 u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr)
3074 {
3075 u16 i = 0;
3076 u8 *rateindex_Array[] = { "1M", "2M", "5.5M", "11M", "6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M",
3077 "HTMCS0", "HTMCS1", "HTMCS2", "HTMCS3", "HTMCS4", "HTMCS5", "HTMCS6", "HTMCS7",
3078 "HTMCS8", "HTMCS9", "HTMCS10", "HTMCS11", "HTMCS12", "HTMCS13", "HTMCS14", "HTMCS15",
3079 "HTMCS16", "HTMCS17", "HTMCS18", "HTMCS19", "HTMCS20", "HTMCS21", "HTMCS22", "HTMCS23",
3080 "HTMCS24", "HTMCS25", "HTMCS26", "HTMCS27", "HTMCS28", "HTMCS29", "HTMCS30", "HTMCS31",
3081 "VHT1MCS0", "VHT1MCS1", "VHT1MCS2", "VHT1MCS3", "VHT1MCS4", "VHT1MCS5", "VHT1MCS6", "VHT1MCS7", "VHT1MCS8", "VHT1MCS9",
3082 "VHT2MCS0", "VHT2MCS1", "VHT2MCS2", "VHT2MCS3", "VHT2MCS4", "VHT2MCS5", "VHT2MCS6", "VHT2MCS7", "VHT2MCS8", "VHT2MCS9",
3083 "VHT3MCS0", "VHT3MCS1", "VHT3MCS2", "VHT3MCS3", "VHT3MCS4", "VHT3MCS5", "VHT3MCS6", "VHT3MCS7", "VHT3MCS8", "VHT3MCS9",
3084 "VHT4MCS0", "VHT4MCS1", "VHT4MCS2", "VHT4MCS3", "VHT4MCS4", "VHT4MCS5", "VHT4MCS6", "VHT4MCS7", "VHT4MCS8", "VHT4MCS9"
3085 };
3086
3087 for (i = 0; i <= 83; i++) {
3088 if (strcmp(targetStr, rateindex_Array[i]) == 0) {
3089 RTW_INFO("%s , index = %d\n", __func__ , i);
3090 return i;
3091 }
3092 }
3093
3094 printk("%s ,please input a Data RATE String as:", __func__);
3095 for (i = 0; i <= 83; i++) {
3096 printk("%s ", rateindex_Array[i]);
3097 if (i % 10 == 0)
3098 printk("\n");
3099 }
3100 return _FAIL;
3101 }
3102
rtw_mp_mode_check(PADAPTER pAdapter)3103 u8 rtw_mp_mode_check(PADAPTER pAdapter)
3104 {
3105 PADAPTER primary_adapter = GET_PRIMARY_ADAPTER(pAdapter);
3106
3107 if (primary_adapter->registrypriv.mp_mode == 1 || primary_adapter->mppriv.bprocess_mp_mode == _TRUE)
3108 return _TRUE;
3109 else
3110 return _FALSE;
3111 }
3112
rtw_is_mp_tssitrk_on(_adapter * adapter)3113 bool rtw_is_mp_tssitrk_on(_adapter *adapter)
3114 {
3115 _adapter *primary_adapter = GET_PRIMARY_ADAPTER(adapter);
3116
3117 return primary_adapter->mppriv.tssitrk_on;
3118 }
3119
mpt_ProQueryCalTxPower(PADAPTER pAdapter,u8 RfPath)3120 u32 mpt_ProQueryCalTxPower(
3121 PADAPTER pAdapter,
3122 u8 RfPath
3123 )
3124 {
3125
3126 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3127 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
3128
3129 u32 TxPower = 1;
3130 struct txpwr_idx_comp tic;
3131 u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
3132 RATE_SECTION rs = mgn_rate_to_rs(mgn_rate);
3133
3134 TxPower = rtw_hal_get_tx_power_index(pAdapter, RfPath, rs, mgn_rate
3135 , pHalData->current_channel_bw, pHalData->current_band_type, pHalData->current_channel, 0, &tic);
3136
3137 dump_tx_power_index_inline(RTW_DBGDUMP, pAdapter, RfPath
3138 , pHalData->current_channel_bw, pHalData->current_channel
3139 , mgn_rate, TxPower, &tic);
3140
3141 pAdapter->mppriv.txpoweridx = (u8)TxPower;
3142 if (RfPath == RF_PATH_A)
3143 pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)TxPower;
3144 else if (RfPath == RF_PATH_B)
3145 pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)TxPower;
3146 else if (RfPath == RF_PATH_C)
3147 pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)TxPower;
3148 else if (RfPath == RF_PATH_D)
3149 pMptCtx->TxPwrLevel[RF_PATH_D] = (u8)TxPower;
3150 hal_mpt_SetTxPower(pAdapter);
3151
3152 return TxPower;
3153 }
3154
mpt_get_tx_power_finalabs_val(PADAPTER padapter,u8 rf_path)3155 u32 mpt_get_tx_power_finalabs_val(PADAPTER padapter, u8 rf_path)
3156 {
3157 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3158 PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx);
3159
3160 u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
3161 u32 powerdbm = 0;
3162
3163 powerdbm = phy_get_tx_power_final_absolute_value(padapter, rf_path, mgn_rate, pHalData->current_channel_bw, pHalData->current_channel);
3164
3165 RTW_INFO("bw=%d, ch=%d, rateid=%d, TSSI Power(dBm):%d\n",
3166 pHalData->current_channel_bw, pHalData->current_channel, mgn_rate ,powerdbm);
3167
3168 return powerdbm;
3169 }
3170
3171 #ifdef CONFIG_MP_VHT_HW_TX_MODE
dump_buf(u8 * buf,u32 len)3172 static inline void dump_buf(u8 *buf, u32 len)
3173 {
3174 u32 i;
3175
3176 RTW_INFO("-----------------Len %d----------------\n", len);
3177 for (i = 0; i < len; i++)
3178 RTW_INFO("%2.2x-", *(buf + i));
3179 RTW_INFO("\n");
3180 }
3181
ByteToBit(u8 * out,bool * in,u8 in_size)3182 void ByteToBit(
3183 u8 *out,
3184 bool *in,
3185 u8 in_size)
3186 {
3187 u8 i = 0, j = 0;
3188
3189 for (i = 0; i < in_size; i++) {
3190 for (j = 0; j < 8; j++) {
3191 if (in[8 * i + j])
3192 out[i] |= (1 << j);
3193 }
3194 }
3195 }
3196
3197
CRC16_generator(bool * out,bool * in,u8 in_size)3198 void CRC16_generator(
3199 bool *out,
3200 bool *in,
3201 u8 in_size
3202 )
3203 {
3204 u8 i = 0;
3205 bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
3206
3207 for (i = 0; i < in_size; i++) {/* take one's complement and bit reverse*/
3208 temp = in[i] ^ reg[15];
3209 reg[15] = reg[14];
3210 reg[14] = reg[13];
3211 reg[13] = reg[12];
3212 reg[12] = reg[11];
3213 reg[11] = reg[10];
3214 reg[10] = reg[9];
3215 reg[9] = reg[8];
3216 reg[8] = reg[7];
3217
3218 reg[7] = reg[6];
3219 reg[6] = reg[5];
3220 reg[5] = reg[4];
3221 reg[4] = reg[3];
3222 reg[3] = reg[2];
3223 reg[2] = reg[1];
3224 reg[1] = reg[0];
3225 reg[12] = reg[12] ^ temp;
3226 reg[5] = reg[5] ^ temp;
3227 reg[0] = temp;
3228 }
3229 for (i = 0; i < 16; i++) /* take one's complement and bit reverse*/
3230 out[i] = 1 - reg[15 - i];
3231 }
3232
3233
3234
3235 /*========================================
3236 SFD SIGNAL SERVICE LENGTH CRC
3237 16 bit 8 bit 8 bit 16 bit 16 bit
3238 ========================================*/
CCK_generator(PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3239 void CCK_generator(
3240 PRT_PMAC_TX_INFO pPMacTxInfo,
3241 PRT_PMAC_PKT_INFO pPMacPktInfo
3242 )
3243 {
3244 double ratio = 0;
3245 bool crc16_in[32] = {0}, crc16_out[16] = {0};
3246 bool LengthExtBit;
3247 double LengthExact;
3248 double LengthPSDU;
3249 u8 i;
3250 u32 PacketLength = pPMacTxInfo->PacketLength;
3251
3252 if (pPMacTxInfo->bSPreamble)
3253 pPMacTxInfo->SFD = 0x05CF;
3254 else
3255 pPMacTxInfo->SFD = 0xF3A0;
3256
3257 switch (pPMacPktInfo->MCS) {
3258 case 0:
3259 pPMacTxInfo->SignalField = 0xA;
3260 ratio = 8;
3261 /*CRC16_in(1,0:7)=[0 1 0 1 0 0 0 0]*/
3262 crc16_in[1] = crc16_in[3] = 1;
3263 break;
3264 case 1:
3265 pPMacTxInfo->SignalField = 0x14;
3266 ratio = 4;
3267 /*CRC16_in(1,0:7)=[0 0 1 0 1 0 0 0];*/
3268 crc16_in[2] = crc16_in[4] = 1;
3269 break;
3270 case 2:
3271 pPMacTxInfo->SignalField = 0x37;
3272 ratio = 8.0 / 5.5;
3273 /*CRC16_in(1,0:7)=[1 1 1 0 1 1 0 0];*/
3274 crc16_in[0] = crc16_in[1] = crc16_in[2] = crc16_in[4] = crc16_in[5] = 1;
3275 break;
3276 case 3:
3277 pPMacTxInfo->SignalField = 0x6E;
3278 ratio = 8.0 / 11.0;
3279 /*CRC16_in(1,0:7)=[0 1 1 1 0 1 1 0];*/
3280 crc16_in[1] = crc16_in[2] = crc16_in[3] = crc16_in[5] = crc16_in[6] = 1;
3281 break;
3282 }
3283
3284 LengthExact = PacketLength * ratio;
3285 LengthPSDU = ceil(LengthExact);
3286
3287 if ((pPMacPktInfo->MCS == 3) &&
3288 ((LengthPSDU - LengthExact) >= 0.727 || (LengthPSDU - LengthExact) <= -0.727))
3289 LengthExtBit = 1;
3290 else
3291 LengthExtBit = 0;
3292
3293
3294 pPMacTxInfo->LENGTH = (u32)LengthPSDU;
3295 /* CRC16_in(1,16:31) = LengthPSDU[0:15]*/
3296 for (i = 0; i < 16; i++)
3297 crc16_in[i + 16] = (pPMacTxInfo->LENGTH >> i) & 0x1;
3298
3299 if (LengthExtBit == 0) {
3300 pPMacTxInfo->ServiceField = 0x0;
3301 /* CRC16_in(1,8:15) = [0 0 0 0 0 0 0 0];*/
3302 } else {
3303 pPMacTxInfo->ServiceField = 0x80;
3304 /*CRC16_in(1,8:15)=[0 0 0 0 0 0 0 1];*/
3305 crc16_in[15] = 1;
3306 }
3307
3308 CRC16_generator(crc16_out, crc16_in, 32);
3309
3310 _rtw_memset(pPMacTxInfo->CRC16, 0, 2);
3311 ByteToBit(pPMacTxInfo->CRC16, crc16_out, 2);
3312
3313 }
3314
3315
PMAC_Get_Pkt_Param(PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3316 void PMAC_Get_Pkt_Param(
3317 PRT_PMAC_TX_INFO pPMacTxInfo,
3318 PRT_PMAC_PKT_INFO pPMacPktInfo)
3319 {
3320
3321 u8 TX_RATE_HEX = 0, MCS = 0;
3322 u8 TX_RATE = pPMacTxInfo->TX_RATE;
3323
3324 /* TX_RATE & Nss */
3325 if (MPT_IS_2SS_RATE(TX_RATE))
3326 pPMacPktInfo->Nss = 2;
3327 else if (MPT_IS_3SS_RATE(TX_RATE))
3328 pPMacPktInfo->Nss = 3;
3329 else if (MPT_IS_4SS_RATE(TX_RATE))
3330 pPMacPktInfo->Nss = 4;
3331 else
3332 pPMacPktInfo->Nss = 1;
3333
3334 RTW_INFO("PMacTxInfo.Nss =%d\n", pPMacPktInfo->Nss);
3335
3336 /* MCS & TX_RATE_HEX*/
3337 if (MPT_IS_CCK_RATE(TX_RATE)) {
3338 switch (TX_RATE) {
3339 case MPT_RATE_1M:
3340 TX_RATE_HEX = MCS = 0;
3341 break;
3342 case MPT_RATE_2M:
3343 TX_RATE_HEX = MCS = 1;
3344 break;
3345 case MPT_RATE_55M:
3346 TX_RATE_HEX = MCS = 2;
3347 break;
3348 case MPT_RATE_11M:
3349 TX_RATE_HEX = MCS = 3;
3350 break;
3351 }
3352 } else if (MPT_IS_OFDM_RATE(TX_RATE)) {
3353 MCS = TX_RATE - MPT_RATE_6M;
3354 TX_RATE_HEX = MCS + 4;
3355 } else if (MPT_IS_HT_RATE(TX_RATE)) {
3356 MCS = TX_RATE - MPT_RATE_MCS0;
3357 TX_RATE_HEX = MCS + 12;
3358 } else if (MPT_IS_VHT_RATE(TX_RATE)) {
3359 TX_RATE_HEX = TX_RATE - MPT_RATE_VHT1SS_MCS0 + 44;
3360
3361 if (MPT_IS_VHT_2S_RATE(TX_RATE))
3362 MCS = TX_RATE - MPT_RATE_VHT2SS_MCS0;
3363 else if (MPT_IS_VHT_3S_RATE(TX_RATE))
3364 MCS = TX_RATE - MPT_RATE_VHT3SS_MCS0;
3365 else if (MPT_IS_VHT_4S_RATE(TX_RATE))
3366 MCS = TX_RATE - MPT_RATE_VHT4SS_MCS0;
3367 else
3368 MCS = TX_RATE - MPT_RATE_VHT1SS_MCS0;
3369 }
3370
3371 pPMacPktInfo->MCS = MCS;
3372 pPMacTxInfo->TX_RATE_HEX = TX_RATE_HEX;
3373
3374 RTW_INFO(" MCS=%d, TX_RATE_HEX =0x%x\n", MCS, pPMacTxInfo->TX_RATE_HEX);
3375 /* mSTBC & Nsts*/
3376 pPMacPktInfo->Nsts = pPMacPktInfo->Nss;
3377 if (pPMacTxInfo->bSTBC) {
3378 if (pPMacPktInfo->Nss == 1) {
3379 pPMacTxInfo->m_STBC = 2;
3380 pPMacPktInfo->Nsts = pPMacPktInfo->Nss * 2;
3381 } else
3382 pPMacTxInfo->m_STBC = 1;
3383 } else
3384 pPMacTxInfo->m_STBC = 1;
3385 }
3386
3387
LDPC_parameter_generator(u32 N_pld_int,u32 N_CBPSS,u32 N_SS,u32 R,u32 m_STBC,u32 N_TCB_int)3388 u32 LDPC_parameter_generator(
3389 u32 N_pld_int,
3390 u32 N_CBPSS,
3391 u32 N_SS,
3392 u32 R,
3393 u32 m_STBC,
3394 u32 N_TCB_int
3395 )
3396 {
3397 double CR = 0.;
3398 double N_pld = (double)N_pld_int;
3399 double N_TCB = (double)N_TCB_int;
3400 double N_CW = 0., N_shrt = 0., N_spcw = 0., N_fshrt = 0.;
3401 double L_LDPC = 0., K_LDPC = 0., L_LDPC_info = 0.;
3402 double N_punc = 0., N_ppcw = 0., N_fpunc = 0., N_rep = 0., N_rpcw = 0., N_frep = 0.;
3403 double R_eff = 0.;
3404 u32 VHTSIGA2B3 = 0;/* extra symbol from VHT-SIG-A2 Bit 3*/
3405
3406 if (R == 0)
3407 CR = 0.5;
3408 else if (R == 1)
3409 CR = 2. / 3.;
3410 else if (R == 2)
3411 CR = 3. / 4.;
3412 else if (R == 3)
3413 CR = 5. / 6.;
3414
3415 if (N_TCB <= 648.) {
3416 N_CW = 1.;
3417 if (N_TCB >= N_pld + 912.*(1. - CR))
3418 L_LDPC = 1296.;
3419 else
3420 L_LDPC = 648.;
3421 } else if (N_TCB <= 1296.) {
3422 N_CW = 1.;
3423 if (N_TCB >= (double)N_pld + 1464.*(1. - CR))
3424 L_LDPC = 1944.;
3425 else
3426 L_LDPC = 1296.;
3427 } else if (N_TCB <= 1944.) {
3428 N_CW = 1.;
3429 L_LDPC = 1944.;
3430 } else if (N_TCB <= 2592.) {
3431 N_CW = 2.;
3432 if (N_TCB >= N_pld + 2916.*(1. - CR))
3433 L_LDPC = 1944.;
3434 else
3435 L_LDPC = 1296.;
3436 } else {
3437 N_CW = ceil(N_pld / 1944. / CR);
3438 L_LDPC = 1944.;
3439 }
3440 /* Number of information bits per CW*/
3441 K_LDPC = L_LDPC * CR;
3442 /* Number of shortening bits max(0, (N_CW * L_LDPC * R) - N_pld)*/
3443 N_shrt = (N_CW * K_LDPC - N_pld) > 0. ? (N_CW * K_LDPC - N_pld) : 0.;
3444 /* Number of shortening bits per CW N_spcw = rtfloor(N_shrt/N_CW)*/
3445 N_spcw = rtfloor(N_shrt / N_CW);
3446 /* The first N_fshrt CWs shorten 1 bit more*/
3447 N_fshrt = (double)((int)N_shrt % (int)N_CW);
3448 /* Number of data bits for the last N_CW-N_fshrt CWs*/
3449 L_LDPC_info = K_LDPC - N_spcw;
3450 /* Number of puncturing bits*/
3451 N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;
3452 if (((N_punc > .1 * N_CW * L_LDPC * (1. - CR)) && (N_shrt < 1.2 * N_punc * CR / (1. - CR))) ||
3453 (N_punc > 0.3 * N_CW * L_LDPC * (1. - CR))) {
3454 /*cout << "*** N_TCB and N_punc are Recomputed ***" << endl;*/
3455 VHTSIGA2B3 = 1;
3456 N_TCB += (double)N_CBPSS * N_SS * m_STBC;
3457 N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;
3458 } else
3459 VHTSIGA2B3 = 0;
3460
3461 return VHTSIGA2B3;
3462 } /* function end of LDPC_parameter_generator */
3463
3464 /*========================================
3465 Data field of PPDU
3466 Get N_sym and SIGA2BB3
3467 ========================================*/
PMAC_Nsym_generator(PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3468 void PMAC_Nsym_generator(
3469 PRT_PMAC_TX_INFO pPMacTxInfo,
3470 PRT_PMAC_PKT_INFO pPMacPktInfo)
3471 {
3472 u32 SIGA2B3 = 0;
3473 u8 TX_RATE = pPMacTxInfo->TX_RATE;
3474
3475 u32 R, R_list[10] = {0, 0, 2, 0, 2, 1, 2, 3, 2, 3};
3476 double CR = 0;
3477 u32 N_SD, N_BPSC_list[10] = {1, 2, 2, 4, 4, 6, 6, 6, 8, 8};
3478 u32 N_BPSC = 0, N_CBPS = 0, N_DBPS = 0, N_ES = 0, N_SYM = 0, N_pld = 0, N_TCB = 0;
3479 int D_R = 0;
3480
3481 RTW_INFO("TX_RATE = %d\n", TX_RATE);
3482 /* N_SD*/
3483 if (pPMacTxInfo->BandWidth == 0)
3484 N_SD = 52;
3485 else if (pPMacTxInfo->BandWidth == 1)
3486 N_SD = 108;
3487 else
3488 N_SD = 234;
3489
3490 if (MPT_IS_HT_RATE(TX_RATE)) {
3491 u8 MCS_temp;
3492
3493 if (pPMacPktInfo->MCS > 23)
3494 MCS_temp = pPMacPktInfo->MCS - 24;
3495 else if (pPMacPktInfo->MCS > 15)
3496 MCS_temp = pPMacPktInfo->MCS - 16;
3497 else if (pPMacPktInfo->MCS > 7)
3498 MCS_temp = pPMacPktInfo->MCS - 8;
3499 else
3500 MCS_temp = pPMacPktInfo->MCS;
3501
3502 R = R_list[MCS_temp];
3503
3504 switch (R) {
3505 case 0:
3506 CR = .5;
3507 break;
3508 case 1:
3509 CR = 2. / 3.;
3510 break;
3511 case 2:
3512 CR = 3. / 4.;
3513 break;
3514 case 3:
3515 CR = 5. / 6.;
3516 break;
3517 }
3518
3519 N_BPSC = N_BPSC_list[MCS_temp];
3520 N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;
3521 N_DBPS = (u32)((double)N_CBPS * CR);
3522
3523 if (pPMacTxInfo->bLDPC == FALSE) {
3524 N_ES = (u32)ceil((double)(N_DBPS * pPMacPktInfo->Nss) / 4. / 300.);
3525 RTW_INFO("N_ES = %d\n", N_ES);
3526
3527 /* N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/
3528 N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) /
3529 (double)(N_DBPS * pPMacTxInfo->m_STBC));
3530
3531 } else {
3532 N_ES = 1;
3533 /* N_pld = length * 8 + 16*/
3534 N_pld = pPMacTxInfo->PacketLength * 8 + 16;
3535 RTW_INFO("N_pld = %d\n", N_pld);
3536 N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(N_pld) /
3537 (double)(N_DBPS * pPMacTxInfo->m_STBC));
3538 RTW_INFO("N_SYM = %d\n", N_SYM);
3539 /* N_avbits = N_CBPS *m_STBC *(N_pld/N_CBPS*R*m_STBC)*/
3540 N_TCB = N_CBPS * N_SYM;
3541 RTW_INFO("N_TCB = %d\n", N_TCB);
3542 SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);
3543 RTW_INFO("SIGA2B3 = %d\n", SIGA2B3);
3544 N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;
3545 RTW_INFO("N_SYM = %d\n", N_SYM);
3546 }
3547 } else if (MPT_IS_VHT_RATE(TX_RATE)) {
3548 R = R_list[pPMacPktInfo->MCS];
3549
3550 switch (R) {
3551 case 0:
3552 CR = .5;
3553 break;
3554 case 1:
3555 CR = 2. / 3.;
3556 break;
3557 case 2:
3558 CR = 3. / 4.;
3559 break;
3560 case 3:
3561 CR = 5. / 6.;
3562 break;
3563 }
3564 N_BPSC = N_BPSC_list[pPMacPktInfo->MCS];
3565 N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;
3566 N_DBPS = (u32)((double)N_CBPS * CR);
3567 if (pPMacTxInfo->bLDPC == FALSE) {
3568 if (pPMacTxInfo->bSGI)
3569 N_ES = (u32)ceil((double)(N_DBPS) / 3.6 / 600.);
3570 else
3571 N_ES = (u32)ceil((double)(N_DBPS) / 4. / 600.);
3572 /* N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/
3573 N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) / (double)(N_DBPS * pPMacTxInfo->m_STBC));
3574 SIGA2B3 = 0;
3575 } else {
3576 N_ES = 1;
3577 /* N_SYM = m_STBC* (8*length+N_service) / (m_STBC*N_DBPS)*/
3578 N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16) / (double)(N_DBPS * pPMacTxInfo->m_STBC));
3579 /* N_avbits = N_sys_init * N_CBPS*/
3580 N_TCB = N_CBPS * N_SYM;
3581 /* N_pld = N_sys_init * N_DBPS*/
3582 N_pld = N_SYM * N_DBPS;
3583 SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);
3584 N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;
3585 }
3586
3587 switch (R) {
3588 case 0:
3589 D_R = 2;
3590 break;
3591 case 1:
3592 D_R = 3;
3593 break;
3594 case 2:
3595 D_R = 4;
3596 break;
3597 case 3:
3598 D_R = 6;
3599 break;
3600 }
3601
3602 if (((N_CBPS / N_ES) % D_R) != 0) {
3603 RTW_INFO("MCS= %d is not supported when Nss=%d and BW= %d !!\n", pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);
3604 return;
3605 }
3606
3607 RTW_INFO("MCS= %d Nss=%d and BW= %d !!\n", pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);
3608 }
3609
3610 pPMacPktInfo->N_sym = N_SYM;
3611 pPMacPktInfo->SIGA2B3 = SIGA2B3;
3612 }
3613
3614 /*========================================
3615 L-SIG Rate R Length P Tail
3616 4b 1b 12b 1b 6b
3617 ========================================*/
3618
L_SIG_generator(u32 N_SYM,PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3619 void L_SIG_generator(
3620 u32 N_SYM, /* Max: 750*/
3621 PRT_PMAC_TX_INFO pPMacTxInfo,
3622 PRT_PMAC_PKT_INFO pPMacPktInfo)
3623 {
3624 u8 sig_bi[24] = {0}; /* 24 BIT*/
3625 u32 mode, LENGTH;
3626 int i;
3627
3628 if (MPT_IS_OFDM_RATE(pPMacTxInfo->TX_RATE)) {
3629 mode = pPMacPktInfo->MCS;
3630 LENGTH = pPMacTxInfo->PacketLength;
3631 } else {
3632 u8 N_LTF;
3633 double T_data;
3634 u32 OFDM_symbol;
3635
3636 mode = 0;
3637
3638 /* Table 20-13 Num of HT-DLTFs request*/
3639 if (pPMacPktInfo->Nsts <= 2)
3640 N_LTF = pPMacPktInfo->Nsts;
3641 else
3642 N_LTF = 4;
3643
3644 if (pPMacTxInfo->bSGI)
3645 T_data = 3.6;
3646 else
3647 T_data = 4.0;
3648
3649 /*(L-SIG, HT-SIG, HT-STF, HT-LTF....HT-LTF, Data)*/
3650 if (MPT_IS_VHT_RATE(pPMacTxInfo->TX_RATE))
3651 OFDM_symbol = (u32)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data + 4) / 4.);
3652 else
3653 OFDM_symbol = (u32)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data) / 4.);
3654
3655 RTW_INFO("%s , OFDM_symbol =%d\n", __func__, OFDM_symbol);
3656 LENGTH = OFDM_symbol * 3 - 3;
3657 RTW_INFO("%s , LENGTH =%d\n", __func__, LENGTH);
3658
3659 }
3660 /* Rate Field*/
3661 switch (mode) {
3662 case 0:
3663 sig_bi[0] = 1;
3664 sig_bi[1] = 1;
3665 sig_bi[2] = 0;
3666 sig_bi[3] = 1;
3667 break;
3668 case 1:
3669 sig_bi[0] = 1;
3670 sig_bi[1] = 1;
3671 sig_bi[2] = 1;
3672 sig_bi[3] = 1;
3673 break;
3674 case 2:
3675 sig_bi[0] = 0;
3676 sig_bi[1] = 1;
3677 sig_bi[2] = 0;
3678 sig_bi[3] = 1;
3679 break;
3680 case 3:
3681 sig_bi[0] = 0;
3682 sig_bi[1] = 1;
3683 sig_bi[2] = 1;
3684 sig_bi[3] = 1;
3685 break;
3686 case 4:
3687 sig_bi[0] = 1;
3688 sig_bi[1] = 0;
3689 sig_bi[2] = 0;
3690 sig_bi[3] = 1;
3691 break;
3692 case 5:
3693 sig_bi[0] = 1;
3694 sig_bi[1] = 0;
3695 sig_bi[2] = 1;
3696 sig_bi[3] = 1;
3697 break;
3698 case 6:
3699 sig_bi[0] = 0;
3700 sig_bi[1] = 0;
3701 sig_bi[2] = 0;
3702 sig_bi[3] = 1;
3703 break;
3704 case 7:
3705 sig_bi[0] = 0;
3706 sig_bi[1] = 0;
3707 sig_bi[2] = 1;
3708 sig_bi[3] = 1;
3709 break;
3710 }
3711 /*Reserved bit*/
3712 sig_bi[4] = 0;
3713
3714 /* Length Field*/
3715 for (i = 0; i < 12; i++)
3716 sig_bi[i + 5] = (LENGTH >> i) & 1;
3717
3718 /* Parity Bit*/
3719 sig_bi[17] = 0;
3720 for (i = 0; i < 17; i++)
3721 sig_bi[17] = sig_bi[17] + sig_bi[i];
3722
3723 sig_bi[17] %= 2;
3724
3725 /* Tail Field*/
3726 for (i = 18; i < 24; i++)
3727 sig_bi[i] = 0;
3728
3729 /* dump_buf(sig_bi,24);*/
3730 _rtw_memset(pPMacTxInfo->LSIG, 0, 3);
3731 ByteToBit(pPMacTxInfo->LSIG, (bool *)sig_bi, 3);
3732 }
3733
3734
CRC8_generator(bool * out,bool * in,u8 in_size)3735 void CRC8_generator(
3736 bool *out,
3737 bool *in,
3738 u8 in_size
3739 )
3740 {
3741 u8 i = 0;
3742 bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1};
3743
3744 for (i = 0; i < in_size; i++) { /* take one's complement and bit reverse*/
3745 temp = in[i] ^ reg[7];
3746 reg[7] = reg[6];
3747 reg[6] = reg[5];
3748 reg[5] = reg[4];
3749 reg[4] = reg[3];
3750 reg[3] = reg[2];
3751 reg[2] = reg[1] ^ temp;
3752 reg[1] = reg[0] ^ temp;
3753 reg[0] = temp;
3754 }
3755 for (i = 0; i < 8; i++)/* take one's complement and bit reverse*/
3756 out[i] = reg[7 - i] ^ 1;
3757 }
3758
3759 /*/================================================================================
3760 HT-SIG1 MCS CW Length 24BIT + 24BIT
3761 7b 1b 16b
3762 HT-SIG2 Smoothing Not sounding Rsvd AGG STBC FEC SGI N_ELTF CRC Tail
3763 1b 1b 1b 1b 2b 1b 1b 2b 8b 6b
3764 ================================================================================*/
HT_SIG_generator(PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3765 void HT_SIG_generator(
3766 PRT_PMAC_TX_INFO pPMacTxInfo,
3767 PRT_PMAC_PKT_INFO pPMacPktInfo
3768 )
3769 {
3770 u32 i;
3771 bool sig_bi[48] = {0}, crc8[8] = {0};
3772 /* MCS Field*/
3773 for (i = 0; i < 7; i++)
3774 sig_bi[i] = (pPMacPktInfo->MCS >> i) & 0x1;
3775 /* Packet BW Setting*/
3776 sig_bi[7] = pPMacTxInfo->BandWidth;
3777 /* HT-Length Field*/
3778 for (i = 0; i < 16; i++)
3779 sig_bi[i + 8] = (pPMacTxInfo->PacketLength >> i) & 0x1;
3780 /* Smoothing; 1->allow smoothing*/
3781 sig_bi[24] = 1;
3782 /*Not Sounding*/
3783 sig_bi[25] = 1 - pPMacTxInfo->NDP_sound;
3784 /*Reserved bit*/
3785 sig_bi[26] = 1;
3786 /*/Aggregate*/
3787 sig_bi[27] = 0;
3788 /*STBC Field*/
3789 if (pPMacTxInfo->bSTBC) {
3790 sig_bi[28] = 1;
3791 sig_bi[29] = 0;
3792 } else {
3793 sig_bi[28] = 0;
3794 sig_bi[29] = 0;
3795 }
3796 /*Advance Coding, 0: BCC, 1: LDPC*/
3797 sig_bi[30] = pPMacTxInfo->bLDPC;
3798 /* Short GI*/
3799 sig_bi[31] = pPMacTxInfo->bSGI;
3800 /* N_ELTFs*/
3801 if (pPMacTxInfo->NDP_sound == FALSE) {
3802 sig_bi[32] = 0;
3803 sig_bi[33] = 0;
3804 } else {
3805 int N_ELTF = pPMacTxInfo->Ntx - pPMacPktInfo->Nss;
3806
3807 for (i = 0; i < 2; i++)
3808 sig_bi[32 + i] = (N_ELTF >> i) % 2;
3809 }
3810 /* CRC-8*/
3811 CRC8_generator(crc8, sig_bi, 34);
3812
3813 for (i = 0; i < 8; i++)
3814 sig_bi[34 + i] = crc8[i];
3815
3816 /*Tail*/
3817 for (i = 42; i < 48; i++)
3818 sig_bi[i] = 0;
3819
3820 _rtw_memset(pPMacTxInfo->HT_SIG, 0, 6);
3821 ByteToBit(pPMacTxInfo->HT_SIG, sig_bi, 6);
3822 }
3823
3824
3825 /*======================================================================================
3826 VHT-SIG-A1
3827 BW Reserved STBC G_ID SU_Nsts P_AID TXOP_PS_NOT_ALLOW Reserved
3828 2b 1b 1b 6b 3b 9b 1b 2b 1b
3829 VHT-SIG-A2
3830 SGI SGI_Nsym SU/MU coding LDPC_Extra SU_NCS Beamformed Reserved CRC Tail
3831 1b 1b 1b 1b 4b 1b 1b 8b 6b
3832 ======================================================================================*/
VHT_SIG_A_generator(PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3833 void VHT_SIG_A_generator(
3834 PRT_PMAC_TX_INFO pPMacTxInfo,
3835 PRT_PMAC_PKT_INFO pPMacPktInfo)
3836 {
3837 u32 i;
3838 bool sig_bi[48], crc8[8];
3839
3840 _rtw_memset(sig_bi, 0, 48);
3841 _rtw_memset(crc8, 0, 8);
3842
3843 /* BW Setting*/
3844 for (i = 0; i < 2; i++)
3845 sig_bi[i] = (pPMacTxInfo->BandWidth >> i) & 0x1;
3846 /* Reserved Bit*/
3847 sig_bi[2] = 1;
3848 /*STBC Field*/
3849 sig_bi[3] = pPMacTxInfo->bSTBC;
3850 /*Group ID: Single User->A value of 0 or 63 indicates an SU PPDU. */
3851 for (i = 0; i < 6; i++)
3852 sig_bi[4 + i] = 0;
3853 /* N_STS/Partial AID*/
3854 for (i = 0; i < 12; i++) {
3855 if (i < 3)
3856 sig_bi[10 + i] = ((pPMacPktInfo->Nsts - 1) >> i) & 0x1;
3857 else
3858 sig_bi[10 + i] = 0;
3859 }
3860 /*TXOP_PS_NOT_ALLPWED*/
3861 sig_bi[22] = 0;
3862 /*Reserved Bits*/
3863 sig_bi[23] = 1;
3864 /*Short GI*/
3865 sig_bi[24] = pPMacTxInfo->bSGI;
3866 if (pPMacTxInfo->bSGI > 0 && (pPMacPktInfo->N_sym % 10) == 9)
3867 sig_bi[25] = 1;
3868 else
3869 sig_bi[25] = 0;
3870 /* SU/MU[0] Coding*/
3871 sig_bi[26] = pPMacTxInfo->bLDPC; /* 0:BCC, 1:LDPC */
3872 sig_bi[27] = pPMacPktInfo->SIGA2B3; /*/ Record Extra OFDM Symols is added or not when LDPC is used*/
3873 /*SU MCS/MU[1-3] Coding*/
3874 for (i = 0; i < 4; i++)
3875 sig_bi[28 + i] = (pPMacPktInfo->MCS >> i) & 0x1;
3876 /*SU Beamform */
3877 sig_bi[32] = 0; /*packet.TXBF_en;*/
3878 /*Reserved Bit*/
3879 sig_bi[33] = 1;
3880 /*CRC-8*/
3881 CRC8_generator(crc8, sig_bi, 34);
3882 for (i = 0; i < 8; i++)
3883 sig_bi[34 + i] = crc8[i];
3884 /*Tail*/
3885 for (i = 42; i < 48; i++)
3886 sig_bi[i] = 0;
3887
3888 _rtw_memset(pPMacTxInfo->VHT_SIG_A, 0, 6);
3889 ByteToBit(pPMacTxInfo->VHT_SIG_A, sig_bi, 6);
3890 }
3891
3892 /*======================================================================================
3893 VHT-SIG-B
3894 Length Resesrved Trail
3895 17/19/21 BIT 3/2/2 BIT 6b
3896 ======================================================================================*/
VHT_SIG_B_generator(PRT_PMAC_TX_INFO pPMacTxInfo)3897 void VHT_SIG_B_generator(
3898 PRT_PMAC_TX_INFO pPMacTxInfo)
3899 {
3900 bool sig_bi[32], crc8_bi[8];
3901 u32 i, len, res, tail = 6, total_len, crc8_in_len;
3902 u32 sigb_len;
3903
3904 _rtw_memset(sig_bi, 0, 32);
3905 _rtw_memset(crc8_bi, 0, 8);
3906
3907 /*Sounding Packet*/
3908 if (pPMacTxInfo->NDP_sound == 1) {
3909 if (pPMacTxInfo->BandWidth == 0) {
3910 bool sigb_temp[26] = {0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};
3911
3912 _rtw_memcpy(sig_bi, sigb_temp, 26);
3913 } else if (pPMacTxInfo->BandWidth == 1) {
3914 bool sigb_temp[27] = {1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0};
3915
3916 _rtw_memcpy(sig_bi, sigb_temp, 27);
3917 } else if (pPMacTxInfo->BandWidth == 2) {
3918 bool sigb_temp[29] = {0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};
3919
3920 _rtw_memcpy(sig_bi, sigb_temp, 29);
3921 }
3922 } else { /* Not NDP Sounding*/
3923 bool *sigb_temp[29] = {0};
3924
3925 if (pPMacTxInfo->BandWidth == 0) {
3926 len = 17;
3927 res = 3;
3928 } else if (pPMacTxInfo->BandWidth == 1) {
3929 len = 19;
3930 res = 2;
3931 } else if (pPMacTxInfo->BandWidth == 2) {
3932 len = 21;
3933 res = 2;
3934 } else {
3935 len = 21;
3936 res = 2;
3937 }
3938 total_len = len + res + tail;
3939 crc8_in_len = len + res;
3940
3941 /*Length Field*/
3942 sigb_len = (pPMacTxInfo->PacketLength + 3) >> 2;
3943
3944 for (i = 0; i < len; i++)
3945 sig_bi[i] = (sigb_len >> i) & 0x1;
3946 /*Reserved Field*/
3947 for (i = 0; i < res; i++)
3948 sig_bi[len + i] = 1;
3949 /* CRC-8*/
3950 CRC8_generator(crc8_bi, sig_bi, crc8_in_len);
3951
3952 /* Tail */
3953 for (i = 0; i < tail; i++)
3954 sig_bi[len + res + i] = 0;
3955 }
3956
3957 _rtw_memset(pPMacTxInfo->VHT_SIG_B, 0, 4);
3958 ByteToBit(pPMacTxInfo->VHT_SIG_B, sig_bi, 4);
3959
3960 pPMacTxInfo->VHT_SIG_B_CRC = 0;
3961 ByteToBit(&(pPMacTxInfo->VHT_SIG_B_CRC), crc8_bi, 1);
3962 }
3963
3964 /*=======================
3965 VHT Delimiter
3966 =======================*/
VHT_Delimiter_generator(PRT_PMAC_TX_INFO pPMacTxInfo)3967 void VHT_Delimiter_generator(
3968 PRT_PMAC_TX_INFO pPMacTxInfo
3969 )
3970 {
3971 bool sig_bi[32] = {0}, crc8[8] = {0};
3972 u32 crc8_in_len = 16;
3973 u32 PacketLength = pPMacTxInfo->PacketLength;
3974 int j;
3975
3976 /* Delimiter[0]: EOF*/
3977 sig_bi[0] = 1;
3978 /* Delimiter[1]: Reserved*/
3979 sig_bi[1] = 0;
3980 /* Delimiter[3:2]: MPDU Length High*/
3981 sig_bi[2] = ((PacketLength - 4) >> 12) % 2;
3982 sig_bi[3] = ((PacketLength - 4) >> 13) % 2;
3983 /* Delimiter[15:4]: MPDU Length Low*/
3984 for (j = 4; j < 16; j++)
3985 sig_bi[j] = ((PacketLength - 4) >> (j - 4)) % 2;
3986 CRC8_generator(crc8, sig_bi, crc8_in_len);
3987 for (j = 16; j < 24; j++) /* Delimiter[23:16]: CRC 8*/
3988 sig_bi[j] = crc8[j - 16];
3989 for (j = 24; j < 32; j++) /* Delimiter[31:24]: Signature ('4E' in Hex, 78 in Dec)*/
3990 sig_bi[j] = (78 >> (j - 24)) % 2;
3991
3992 _rtw_memset(pPMacTxInfo->VHT_Delimiter, 0, 4);
3993 ByteToBit(pPMacTxInfo->VHT_Delimiter, sig_bi, 4);
3994 }
3995
3996 #endif
3997 #endif
3998