1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_PTPC_H 10 #define HPM_PTPC_H 11 12 typedef struct { 13 struct { 14 __RW uint32_t CTRL0; /* 0x0: Control Register 0 */ 15 __RW uint32_t CTRL1; /* 0x4: Control Register 1 */ 16 __R uint32_t TIMEH; /* 0x8: timestamp high */ 17 __R uint32_t TIMEL; /* 0xC: timestamp low */ 18 __RW uint32_t TS_UPDTH; /* 0x10: timestamp update high */ 19 __RW uint32_t TS_UPDTL; /* 0x14: timestamp update low */ 20 __RW uint32_t ADDEND; /* 0x18: */ 21 __RW uint32_t TARH; /* 0x1C: */ 22 __RW uint32_t TARL; /* 0x20: */ 23 __R uint8_t RESERVED0[8]; /* 0x24 - 0x2B: Reserved */ 24 __RW uint32_t PPS_CTRL; /* 0x2C: */ 25 __R uint32_t CAPT_SNAPH; /* 0x30: */ 26 __RW uint32_t CAPT_SNAPL; /* 0x34: */ 27 __R uint8_t RESERVED1[4040]; /* 0x38 - 0xFFF: Reserved */ 28 } PTPC[2]; 29 __RW uint32_t TIME_SEL; /* 0x2000: */ 30 __W uint32_t INT_STS; /* 0x2004: */ 31 __RW uint32_t INT_EN; /* 0x2008: */ 32 __R uint8_t RESERVED0[4084]; /* 0x200C - 0x2FFF: Reserved */ 33 __RW uint32_t PTPC_CAN_TS_SEL; /* 0x3000: */ 34 } PTPC_Type; 35 36 37 /* Bitfield definition for register of struct array PTPC: CTRL0 */ 38 /* 39 * SUBSEC_DIGITAL_ROLLOVER (RW) 40 * 41 * Format for ns counter rollover, 42 * 1-digital, overflow time 1000000000/0x3B9ACA00 43 * 0-binary, overflow time 0x7FFFFFFF 44 */ 45 #define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK (0x200U) 46 #define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT (9U) 47 #define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) 48 #define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) >> PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) 49 50 /* 51 * CAPT_SNAP_KEEP (RW) 52 * 53 * set will keep capture snap till software read capt_snapl. 54 * If this bit is set, software should read capt_snaph first to avoid wrong result. 55 * If this bit is cleared, capture result will be updated at each capture event 56 */ 57 #define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK (0x100U) 58 #define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT (8U) 59 #define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) 60 #define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) 61 62 /* 63 * CAPT_SNAP_POS_EN (RW) 64 * 65 * set will use posege of input capture signal to latch timestamp value 66 */ 67 #define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK (0x80U) 68 #define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT (7U) 69 #define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) 70 #define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) 71 72 /* 73 * CAPT_SNAP_NEG_EN (RW) 74 * 75 */ 76 #define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK (0x40U) 77 #define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT (6U) 78 #define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) 79 #define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) 80 81 /* 82 * COMP_EN (RW) 83 * 84 * set to enable compare, will be cleared by HW when compare event triggered 85 */ 86 #define PTPC_PTPC_CTRL0_COMP_EN_MASK (0x10U) 87 #define PTPC_PTPC_CTRL0_COMP_EN_SHIFT (4U) 88 #define PTPC_PTPC_CTRL0_COMP_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_COMP_EN_SHIFT) & PTPC_PTPC_CTRL0_COMP_EN_MASK) 89 #define PTPC_PTPC_CTRL0_COMP_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_COMP_EN_MASK) >> PTPC_PTPC_CTRL0_COMP_EN_SHIFT) 90 91 /* 92 * UPDATE_TIMER (WO) 93 * 94 * update timer with +/- ts_updt, pulse, clear after set 95 */ 96 #define PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK (0x8U) 97 #define PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT (3U) 98 #define PTPC_PTPC_CTRL0_UPDATE_TIMER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) 99 #define PTPC_PTPC_CTRL0_UPDATE_TIMER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) >> PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) 100 101 /* 102 * INIT_TIMER (WO) 103 * 104 * initial timer with ts_updt, pulse, clear after set 105 */ 106 #define PTPC_PTPC_CTRL0_INIT_TIMER_MASK (0x4U) 107 #define PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT (2U) 108 #define PTPC_PTPC_CTRL0_INIT_TIMER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) 109 #define PTPC_PTPC_CTRL0_INIT_TIMER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) >> PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) 110 111 /* 112 * FINE_COARSE_SEL (RW) 113 * 114 * 0: coarse update, ns counter add ss_incr[7:0] each clk 115 * 1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow 116 */ 117 #define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK (0x2U) 118 #define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT (1U) 119 #define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) 120 #define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) >> PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) 121 122 /* 123 * TIMER_ENABLE (RW) 124 * 125 */ 126 #define PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK (0x1U) 127 #define PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT (0U) 128 #define PTPC_PTPC_CTRL0_TIMER_ENABLE_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) 129 #define PTPC_PTPC_CTRL0_TIMER_ENABLE_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) >> PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) 130 131 /* Bitfield definition for register of struct array PTPC: CTRL1 */ 132 /* 133 * SS_INCR (RW) 134 * 135 * constant value used to add ns counter; 136 * such as for 50MHz timer clock, set it to 8'd20 137 */ 138 #define PTPC_PTPC_CTRL1_SS_INCR_MASK (0xFFU) 139 #define PTPC_PTPC_CTRL1_SS_INCR_SHIFT (0U) 140 #define PTPC_PTPC_CTRL1_SS_INCR_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL1_SS_INCR_SHIFT) & PTPC_PTPC_CTRL1_SS_INCR_MASK) 141 #define PTPC_PTPC_CTRL1_SS_INCR_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL1_SS_INCR_MASK) >> PTPC_PTPC_CTRL1_SS_INCR_SHIFT) 142 143 /* Bitfield definition for register of struct array PTPC: TIMEH */ 144 /* 145 * TIMESTAMP_HIGH (RO) 146 * 147 */ 148 #define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK (0xFFFFFFFFUL) 149 #define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT (0U) 150 #define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK) >> PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT) 151 152 /* Bitfield definition for register of struct array PTPC: TIMEL */ 153 /* 154 * TIMESTAMP_LOW (RO) 155 * 156 */ 157 #define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK (0xFFFFFFFFUL) 158 #define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT (0U) 159 #define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK) >> PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT) 160 161 /* Bitfield definition for register of struct array PTPC: TS_UPDTH */ 162 /* 163 * SEC_UPDATE (RW) 164 * 165 * together with ts_updtl, used to initial or update timestamp 166 */ 167 #define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK (0xFFFFFFFFUL) 168 #define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT (0U) 169 #define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) 170 #define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) 171 172 /* Bitfield definition for register of struct array PTPC: TS_UPDTL */ 173 /* 174 * ADD_SUB (RW) 175 * 176 * 1 for sub; 0 for add, used only at update 177 */ 178 #define PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK (0x80000000UL) 179 #define PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT (31U) 180 #define PTPC_PTPC_TS_UPDTL_ADD_SUB_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) 181 #define PTPC_PTPC_TS_UPDTL_ADD_SUB_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) >> PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) 182 183 /* 184 * NS_UPDATE (RW) 185 * 186 */ 187 #define PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK (0x7FFFFFFFUL) 188 #define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT (0U) 189 #define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) 190 #define PTPC_PTPC_TS_UPDTL_NS_UPDATE_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) 191 192 /* Bitfield definition for register of struct array PTPC: ADDEND */ 193 /* 194 * ADDEND (RW) 195 * 196 * used in fine update mode only 197 */ 198 #define PTPC_PTPC_ADDEND_ADDEND_MASK (0xFFFFFFFFUL) 199 #define PTPC_PTPC_ADDEND_ADDEND_SHIFT (0U) 200 #define PTPC_PTPC_ADDEND_ADDEND_SET(x) (((uint32_t)(x) << PTPC_PTPC_ADDEND_ADDEND_SHIFT) & PTPC_PTPC_ADDEND_ADDEND_MASK) 201 #define PTPC_PTPC_ADDEND_ADDEND_GET(x) (((uint32_t)(x) & PTPC_PTPC_ADDEND_ADDEND_MASK) >> PTPC_PTPC_ADDEND_ADDEND_SHIFT) 202 203 /* Bitfield definition for register of struct array PTPC: TARH */ 204 /* 205 * TARGET_TIME_HIGH (RW) 206 * 207 * used for generate compare signal if enabled 208 */ 209 #define PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK (0xFFFFFFFFUL) 210 #define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT (0U) 211 #define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SET(x) (((uint32_t)(x) << PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) 212 #define PTPC_PTPC_TARH_TARGET_TIME_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) >> PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) 213 214 /* Bitfield definition for register of struct array PTPC: TARL */ 215 /* 216 * TARGET_TIME_LOW (RW) 217 * 218 */ 219 #define PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK (0xFFFFFFFFUL) 220 #define PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT (0U) 221 #define PTPC_PTPC_TARL_TARGET_TIME_LOW_SET(x) (((uint32_t)(x) << PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) 222 #define PTPC_PTPC_TARL_TARGET_TIME_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) >> PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) 223 224 /* Bitfield definition for register of struct array PTPC: PPS_CTRL */ 225 /* 226 * PPS_CTRL (RW) 227 * 228 */ 229 #define PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK (0xFU) 230 #define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT (0U) 231 #define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SET(x) (((uint32_t)(x) << PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) 232 #define PTPC_PTPC_PPS_CTRL_PPS_CTRL_GET(x) (((uint32_t)(x) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) >> PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) 233 234 /* Bitfield definition for register of struct array PTPC: CAPT_SNAPH */ 235 /* 236 * CAPT_SNAP_HIGH (RO) 237 * 238 * take snapshot for input capture signal, at pos or neg or both; 239 * the result can be kept or updated at each event according to cfg0.bit8 240 */ 241 #define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK (0xFFFFFFFFUL) 242 #define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT (0U) 243 #define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK) >> PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT) 244 245 /* Bitfield definition for register of struct array PTPC: CAPT_SNAPL */ 246 /* 247 * CAPT_SNAP_LOW (RW) 248 * 249 */ 250 #define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK (0xFFFFFFFFUL) 251 #define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT (0U) 252 #define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) 253 #define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) >> PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) 254 255 /* Bitfield definition for register: TIME_SEL */ 256 /* 257 * CAN3_TIME_SEL (RW) 258 * 259 */ 260 #define PTPC_TIME_SEL_CAN3_TIME_SEL_MASK (0x8U) 261 #define PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT (3U) 262 #define PTPC_TIME_SEL_CAN3_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) 263 #define PTPC_TIME_SEL_CAN3_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) 264 265 /* 266 * CAN2_TIME_SEL (RW) 267 * 268 */ 269 #define PTPC_TIME_SEL_CAN2_TIME_SEL_MASK (0x4U) 270 #define PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT (2U) 271 #define PTPC_TIME_SEL_CAN2_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) 272 #define PTPC_TIME_SEL_CAN2_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) 273 274 /* 275 * CAN1_TIME_SEL (RW) 276 * 277 */ 278 #define PTPC_TIME_SEL_CAN1_TIME_SEL_MASK (0x2U) 279 #define PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT (1U) 280 #define PTPC_TIME_SEL_CAN1_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) 281 #define PTPC_TIME_SEL_CAN1_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) 282 283 /* 284 * CAN0_TIME_SEL (RW) 285 * 286 * set to use ptpc1 for canx 287 * clr to use ptpc0 for canx 288 */ 289 #define PTPC_TIME_SEL_CAN0_TIME_SEL_MASK (0x1U) 290 #define PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT (0U) 291 #define PTPC_TIME_SEL_CAN0_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) 292 #define PTPC_TIME_SEL_CAN0_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) 293 294 /* Bitfield definition for register: INT_STS */ 295 /* 296 * COMP_INT_STS1 (W1C) 297 * 298 */ 299 #define PTPC_INT_STS_COMP_INT_STS1_MASK (0x40000UL) 300 #define PTPC_INT_STS_COMP_INT_STS1_SHIFT (18U) 301 #define PTPC_INT_STS_COMP_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS1_SHIFT) & PTPC_INT_STS_COMP_INT_STS1_MASK) 302 #define PTPC_INT_STS_COMP_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS1_MASK) >> PTPC_INT_STS_COMP_INT_STS1_SHIFT) 303 304 /* 305 * CAPTURE_INT_STS1 (W1C) 306 * 307 */ 308 #define PTPC_INT_STS_CAPTURE_INT_STS1_MASK (0x20000UL) 309 #define PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT (17U) 310 #define PTPC_INT_STS_CAPTURE_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) 311 #define PTPC_INT_STS_CAPTURE_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) 312 313 /* 314 * PPS_INT_STS1 (W1C) 315 * 316 */ 317 #define PTPC_INT_STS_PPS_INT_STS1_MASK (0x10000UL) 318 #define PTPC_INT_STS_PPS_INT_STS1_SHIFT (16U) 319 #define PTPC_INT_STS_PPS_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS1_SHIFT) & PTPC_INT_STS_PPS_INT_STS1_MASK) 320 #define PTPC_INT_STS_PPS_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS1_MASK) >> PTPC_INT_STS_PPS_INT_STS1_SHIFT) 321 322 /* 323 * COMP_INT_STS0 (W1C) 324 * 325 */ 326 #define PTPC_INT_STS_COMP_INT_STS0_MASK (0x4U) 327 #define PTPC_INT_STS_COMP_INT_STS0_SHIFT (2U) 328 #define PTPC_INT_STS_COMP_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS0_SHIFT) & PTPC_INT_STS_COMP_INT_STS0_MASK) 329 #define PTPC_INT_STS_COMP_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS0_MASK) >> PTPC_INT_STS_COMP_INT_STS0_SHIFT) 330 331 /* 332 * CAPTURE_INT_STS0 (W1C) 333 * 334 */ 335 #define PTPC_INT_STS_CAPTURE_INT_STS0_MASK (0x2U) 336 #define PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT (1U) 337 #define PTPC_INT_STS_CAPTURE_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) 338 #define PTPC_INT_STS_CAPTURE_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) 339 340 /* 341 * PPS_INT_STS0 (W1C) 342 * 343 */ 344 #define PTPC_INT_STS_PPS_INT_STS0_MASK (0x1U) 345 #define PTPC_INT_STS_PPS_INT_STS0_SHIFT (0U) 346 #define PTPC_INT_STS_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS0_SHIFT) & PTPC_INT_STS_PPS_INT_STS0_MASK) 347 #define PTPC_INT_STS_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS0_MASK) >> PTPC_INT_STS_PPS_INT_STS0_SHIFT) 348 349 /* Bitfield definition for register: INT_EN */ 350 /* 351 * COMP_INT_STS1 (RW) 352 * 353 */ 354 #define PTPC_INT_EN_COMP_INT_STS1_MASK (0x40000UL) 355 #define PTPC_INT_EN_COMP_INT_STS1_SHIFT (18U) 356 #define PTPC_INT_EN_COMP_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS1_SHIFT) & PTPC_INT_EN_COMP_INT_STS1_MASK) 357 #define PTPC_INT_EN_COMP_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS1_MASK) >> PTPC_INT_EN_COMP_INT_STS1_SHIFT) 358 359 /* 360 * CAPTURE_INT_STS1 (RW) 361 * 362 */ 363 #define PTPC_INT_EN_CAPTURE_INT_STS1_MASK (0x20000UL) 364 #define PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT (17U) 365 #define PTPC_INT_EN_CAPTURE_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) 366 #define PTPC_INT_EN_CAPTURE_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) 367 368 /* 369 * PPS_INT_STS1 (RW) 370 * 371 */ 372 #define PTPC_INT_EN_PPS_INT_STS1_MASK (0x10000UL) 373 #define PTPC_INT_EN_PPS_INT_STS1_SHIFT (16U) 374 #define PTPC_INT_EN_PPS_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS1_SHIFT) & PTPC_INT_EN_PPS_INT_STS1_MASK) 375 #define PTPC_INT_EN_PPS_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS1_MASK) >> PTPC_INT_EN_PPS_INT_STS1_SHIFT) 376 377 /* 378 * COMP_INT_STS0 (RW) 379 * 380 */ 381 #define PTPC_INT_EN_COMP_INT_STS0_MASK (0x4U) 382 #define PTPC_INT_EN_COMP_INT_STS0_SHIFT (2U) 383 #define PTPC_INT_EN_COMP_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS0_SHIFT) & PTPC_INT_EN_COMP_INT_STS0_MASK) 384 #define PTPC_INT_EN_COMP_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS0_MASK) >> PTPC_INT_EN_COMP_INT_STS0_SHIFT) 385 386 /* 387 * CAPTURE_INT_STS0 (RW) 388 * 389 */ 390 #define PTPC_INT_EN_CAPTURE_INT_STS0_MASK (0x2U) 391 #define PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT (1U) 392 #define PTPC_INT_EN_CAPTURE_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) 393 #define PTPC_INT_EN_CAPTURE_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) 394 395 /* 396 * PPS_INT_STS0 (RW) 397 * 398 */ 399 #define PTPC_INT_EN_PPS_INT_STS0_MASK (0x1U) 400 #define PTPC_INT_EN_PPS_INT_STS0_SHIFT (0U) 401 #define PTPC_INT_EN_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS0_SHIFT) & PTPC_INT_EN_PPS_INT_STS0_MASK) 402 #define PTPC_INT_EN_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS0_MASK) >> PTPC_INT_EN_PPS_INT_STS0_SHIFT) 403 404 /* Bitfield definition for register: PTPC_CAN_TS_SEL */ 405 /* 406 * TSU_TBIN3_SEL (RW) 407 * 408 */ 409 #define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK (0xFC000000UL) 410 #define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT (26U) 411 #define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) 412 #define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) 413 414 /* 415 * TSU_TBIN2_SEL (RW) 416 * 417 */ 418 #define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK (0x3F00000UL) 419 #define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT (20U) 420 #define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) 421 #define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) 422 423 /* 424 * TSU_TBIN1_SEL (RW) 425 * 426 */ 427 #define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK (0xFC000UL) 428 #define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT (14U) 429 #define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) 430 #define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) 431 432 /* 433 * TSU_TBIN0_SEL (RW) 434 * 435 */ 436 #define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK (0x3F00U) 437 #define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT (8U) 438 #define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) 439 #define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) 440 441 442 443 /* PTPC register group index macro definition */ 444 #define PTPC_PTPC_0 (0UL) 445 #define PTPC_PTPC_1 (1UL) 446 447 448 #endif /* HPM_PTPC_H */ 449