1 /* 2 * Copyright (C) 2017 Amlogic, Inc. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * Description: 19 */ 20 21 #ifndef __MACH_MESON8_REG_ADDR_H_ 22 #define __MACH_MESON8_REG_ADDR_H_ 23 #include <linux/amlogic/iomap.h> 24 #define CBUS_REG_ADDR(_r) aml_read_cbus(_r) 25 26 27 #define STB_CBUS_BASE aml_stb_get_base(ID_STB_CBUS_BASE) 28 #define SMARTCARD_REG_BASE aml_stb_get_base(ID_SMARTCARD_REG_BASE) 29 #define ASYNC_FIFO_REG_BASE aml_stb_get_base(ID_ASYNC_FIFO_REG_BASE) 30 #define ASYNC_FIFO1_REG_BASE aml_stb_get_base(ID_ASYNC_FIFO1_REG_BASE) 31 #define ASYNC_FIFO2_REG_BASE aml_stb_get_base(ID_ASYNC_FIFO2_REG_BASE) 32 #define RESET_BASE aml_stb_get_base(ID_RESET_BASE) 33 #define PARSER_SUB_START_PTR_BASE \ 34 aml_stb_get_base(ID_PARSER_SUB_START_PTR_BASE) 35 36 #define HHI_CSI_PHY_CNTL_BASE 0x1000 37 38 #define DEMUX_1_OFFSET 0x00 39 #define DEMUX_2_OFFSET 0x50 40 #define DEMUX_3_OFFSET 0xa0 41 42 43 #define TS_HIU1_CONFIG (STB_CBUS_BASE + 0x4e) 44 #define P_TS_HIU1_CONFIG CBUS_REG_ADDR(TS_HIU1_CONFIG) 45 46 #define TS_TOP_CONFIG1 (STB_CBUS_BASE + 0x4f) 47 #define P_TS_TOP_CONFIG1 CBUS_REG_ADDR(TS_TOP_CONFIG1) 48 49 #define STB_S2P2_CONFIG (STB_CBUS_BASE + 0xef) 50 #define P_STB_S2P2_CONFIG CBUS_REG_ADDR(STB_S2P2_CONFIG) 51 52 #define STB_RECORDER2_CNTL (STB_CBUS_BASE + 0xee) 53 #define P_STB_RECORDER2_CNTL CBUS_REG_ADDR(STB_RECORDER2_CNTL) 54 55 #define STB_TOP_CONFIG (STB_CBUS_BASE + 0xf0) 56 #define P_STB_TOP_CONFIG CBUS_REG_ADDR(STB_TOP_CONFIG) 57 #define TS_TOP_CONFIG (STB_CBUS_BASE + 0xf1) 58 #define P_TS_TOP_CONFIG CBUS_REG_ADDR(TS_TOP_CONFIG) 59 #define TS_FILE_CONFIG (STB_CBUS_BASE + 0xf2) 60 #define P_TS_FILE_CONFIG CBUS_REG_ADDR(TS_FILE_CONFIG) 61 #define TS_PL_PID_INDEX (STB_CBUS_BASE + 0xf3) 62 #define P_TS_PL_PID_INDEX CBUS_REG_ADDR(TS_PL_PID_INDEX) 63 #define TS_PL_PID_DATA (STB_CBUS_BASE + 0xf4) 64 #define P_TS_PL_PID_DATA CBUS_REG_ADDR(TS_PL_PID_DATA) 65 #define COMM_DESC_KEY0 (STB_CBUS_BASE + 0xf5) 66 #define P_COMM_DESC_KEY0 CBUS_REG_ADDR(COMM_DESC_KEY0) 67 #define COMM_DESC_KEY1 (STB_CBUS_BASE + 0xf6) 68 #define P_COMM_DESC_KEY1 CBUS_REG_ADDR(COMM_DESC_KEY1) 69 #define COMM_DESC_KEY_RW (STB_CBUS_BASE + 0xf7) 70 #define P_COMM_DESC_KEY_RW CBUS_REG_ADDR(COMM_DESC_KEY_RW) 71 #define CIPLUS_KEY0 (STB_CBUS_BASE + 0xf8) 72 #define P_CIPLUS_KEY0 CBUS_REG_ADDR(CIPLUS_KEY0) 73 #define CIPLUS_KEY1 (STB_CBUS_BASE + 0xf9) 74 #define P_CIPLUS_KEY1 CBUS_REG_ADDR(CIPLUS_KEY1) 75 #define CIPLUS_KEY2 (STB_CBUS_BASE + 0xfa) 76 #define P_CIPLUS_KEY2 CBUS_REG_ADDR(CIPLUS_KEY2) 77 #define CIPLUS_KEY3 (STB_CBUS_BASE + 0xfb) 78 #define P_CIPLUS_KEY3 CBUS_REG_ADDR(CIPLUS_KEY3) 79 #define CIPLUS_KEY_WR (STB_CBUS_BASE + 0xfc) 80 #define P_CIPLUS_KEY_WR CBUS_REG_ADDR(CIPLUS_KEY_WR) 81 #define CIPLUS_CONFIG (STB_CBUS_BASE + 0xfd) 82 #define P_CIPLUS_CONFIG CBUS_REG_ADDR(CIPLUS_CONFIG) 83 #define CIPLUS_ENDIAN (STB_CBUS_BASE + 0xfe) 84 #define P_CIPLUS_ENDIAN CBUS_REG_ADDR(CIPLUS_ENDIAN) 85 86 #define SMARTCARD_REG0 (SMARTCARD_REG_BASE + 0x0) 87 #define P_SMARTCARD_REG0 CBUS_REG_ADDR(SMARTCARD_REG0) 88 #define SMARTCARD_REG1 (SMARTCARD_REG_BASE + 0x1) 89 #define P_SMARTCARD_REG1 CBUS_REG_ADDR(SMARTCARD_REG1) 90 #define SMARTCARD_REG2 (SMARTCARD_REG_BASE + 0x2) 91 #define P_SMARTCARD_REG2 CBUS_REG_ADDR(SMARTCARD_REG2) 92 #define SMARTCARD_STATUS (SMARTCARD_REG_BASE + 0x3) 93 #define P_SMARTCARD_STATUS CBUS_REG_ADDR(SMARTCARD_STATUS) 94 #define SMARTCARD_INTR (SMARTCARD_REG_BASE + 0x4) 95 #define P_SMARTCARD_INTR CBUS_REG_ADDR(SMARTCARD_INTR) 96 #define SMARTCARD_REG5 (SMARTCARD_REG_BASE + 0x5) 97 #define P_SMARTCARD_REG5 CBUS_REG_ADDR(SMARTCARD_REG5) 98 #define SMARTCARD_REG6 (SMARTCARD_REG_BASE + 0x6) 99 #define P_SMARTCARD_REG6 CBUS_REG_ADDR(SMARTCARD_REG6) 100 #define SMARTCARD_FIFO (SMARTCARD_REG_BASE + 0x7) 101 #define P_SMARTCARD_FIFO CBUS_REG_ADDR(SMARTCARD_FIFO) 102 #define SMARTCARD_REG8 (SMARTCARD_REG_BASE + 0x8) 103 #define P_SMARTCARD_REG8 CBUS_REG_ADDR(SMARTCARD_REG8) 104 105 #define ASYNC_FIFO_REG0 (ASYNC_FIFO_REG_BASE + 0x0) 106 #define P_ASYNC_FIFO_REG0 CBUS_REG_ADDR(ASYNC_FIFO_REG0) 107 #define ASYNC_FIFO_REG1 (ASYNC_FIFO_REG_BASE + 0x1) 108 #define P_ASYNC_FIFO_REG1 CBUS_REG_ADDR(ASYNC_FIFO_REG1) 109 #define ASYNC_FIFO_REG2 (ASYNC_FIFO_REG_BASE + 0x2) 110 #define P_ASYNC_FIFO_REG2 CBUS_REG_ADDR(ASYNC_FIFO_REG2) 111 #define ASYNC_FIFO_REG3 (ASYNC_FIFO_REG_BASE + 0x3) 112 #define P_ASYNC_FIFO_REG3 CBUS_REG_ADDR(ASYNC_FIFO_REG3) 113 #define ASYNC_FIFO_REG4 (ASYNC_FIFO_REG_BASE + 0x4) 114 #define P_ASYNC_FIFO_REG4 CBUS_REG_ADDR(ASYNC_FIFO_REG4) 115 #define ASYNC_FIFO_REG5 (ASYNC_FIFO_REG_BASE + 0x5) 116 #define P_ASYNC_FIFO_REG5 CBUS_REG_ADDR(ASYNC_FIFO_REG5) 117 118 #define ASYNC_FIFO1_REG0 (ASYNC_FIFO1_REG_BASE + 0x0) 119 #define P_ASYNC_FIFO1_REG0 CBUS_REG_ADDR(ASYNC_FIFO1_REG0) 120 #define ASYNC_FIFO1_REG1 (ASYNC_FIFO1_REG_BASE + 0x1) 121 #define P_ASYNC_FIFO1_REG1 CBUS_REG_ADDR(ASYNC_FIFO1_REG1) 122 #define ASYNC_FIFO1_REG2 (ASYNC_FIFO1_REG_BASE + 0x2) 123 #define P_ASYNC_FIFO1_REG2 CBUS_REG_ADDR(ASYNC_FIFO1_REG2) 124 #define ASYNC_FIFO1_REG3 (ASYNC_FIFO1_REG_BASE + 0x3) 125 #define P_ASYNC_FIFO1_REG3 CBUS_REG_ADDR(ASYNC_FIFO1_REG3) 126 #define ASYNC_FIFO1_REG4 (ASYNC_FIFO1_REG_BASE + 0x4) 127 #define P_ASYNC_FIFO1_REG4 CBUS_REG_ADDR(ASYNC_FIFO1_REG4) 128 #define ASYNC_FIFO1_REG5 (ASYNC_FIFO1_REG_BASE + 0x5) 129 #define P_ASYNC_FIFO1_REG5 CBUS_REG_ADDR(ASYNC_FIFO1_REG5) 130 131 132 #define ASYNC_FIFO2_REG0 (ASYNC_FIFO2_REG_BASE + 0x0) 133 #define P_ASYNC_FIFO2_REG0 CBUS_REG_ADDR(ASYNC_FIFO2_REG0) 134 #define ASYNC_FIFO2_REG1 (ASYNC_FIFO2_REG_BASE + 0x1) 135 #define P_ASYNC_FIFO2_REG1 CBUS_REG_ADDR(ASYNC_FIFO2_REG1) 136 #define ASYNC_FIFO2_REG2 (ASYNC_FIFO2_REG_BASE + 0x2) 137 #define P_ASYNC_FIFO2_REG2 CBUS_REG_ADDR(ASYNC_FIFO2_REG2) 138 #define ASYNC_FIFO2_REG3 (ASYNC_FIFO2_REG_BASE + 0x3) 139 #define P_ASYNC_FIFO2_REG3 CBUS_REG_ADDR(ASYNC_FIFO2_REG3) 140 #define ASYNC_FIFO2_REG4 (ASYNC_FIFO2_REG_BASE + 0x4) 141 #define P_ASYNC_FIFO2_REG4 CBUS_REG_ADDR(ASYNC_FIFO2_REG4) 142 #define ASYNC_FIFO2_REG5 (ASYNC_FIFO2_REG_BASE + 0x5) 143 #define P_ASYNC_FIFO2_REG5 CBUS_REG_ADDR(ASYNC_FIFO2_REG5) 144 145 146 #define RESET0_REGISTER (RESET_BASE + 0x1) 147 #define P_RESET0_REGISTER CBUS_REG_ADDR(RESET0_REGISTER) 148 #define RESET1_REGISTER (RESET_BASE + 0x2) 149 #define P_RESET1_REGISTER CBUS_REG_ADDR(RESET1_REGISTER) 150 #define RESET2_REGISTER (RESET_BASE + 0x3) 151 #define P_RESET2_REGISTER CBUS_REG_ADDR(RESET2_REGISTER) 152 #define RESET3_REGISTER (RESET_BASE + 0x4) 153 #define P_RESET3_REGISTER CBUS_REG_ADDR(RESET3_REGISTER) 154 #define RESET4_REGISTER (RESET_BASE + 0x5) 155 #define P_RESET4_REGISTER CBUS_REG_ADDR(RESET4_REGISTER) 156 #define RESET5_REGISTER (RESET_BASE + 0x6) 157 #define P_RESET5_REGISTER CBUS_REG_ADDR(RESET5_REGISTER) 158 #define RESET6_REGISTER (RESET_BASE + 0x7) 159 #define P_RESET6_REGISTER CBUS_REG_ADDR(RESET6_REGISTER) 160 #define RESET7_REGISTER (RESET_BASE + 0x8) 161 #define P_RESET7_REGISTER CBUS_REG_ADDR(RESET7_REGISTER) 162 #define RESET0_MASK (RESET_BASE + 0x10) 163 #define P_RESET0_MASK CBUS_REG_ADDR(RESET0_MASK) 164 #define RESET1_MASK (RESET_BASE + 0x11) 165 #define P_RESET1_MASK CBUS_REG_ADDR(RESET1_MASK) 166 #define RESET2_MASK (RESET_BASE + 0x12) 167 #define P_RESET2_MASK CBUS_REG_ADDR(RESET2_MASK) 168 #define RESET3_MASK (RESET_BASE + 0x13) 169 #define P_RESET3_MASK CBUS_REG_ADDR(RESET3_MASK) 170 #define RESET4_MASK (RESET_BASE + 0x14) 171 #define P_RESET4_MASK CBUS_REG_ADDR(RESET4_MASK) 172 #define RESET5_MASK (RESET_BASE + 0x15) 173 #define P_RESET5_MASK CBUS_REG_ADDR(RESET5_MASK) 174 #define RESET6_MASK (RESET_BASE + 0x16) 175 #define P_RESET6_MASK CBUS_REG_ADDR(RESET6_MASK) 176 #define CRT_MASK (RESET_BASE + 0x17) 177 #define P_CRT_MASK CBUS_REG_ADDR(CRT_MASK) 178 #define RESET7_MASK (RESET_BASE + 0x18) 179 #define P_RESET7_MASK CBUS_REG_ADDR(RESET7_MASK) 180 /*add from M8M2*/ 181 #define P_RESET0_LEVEL CBUS_REG_ADDR(RESET0_LEVEL) 182 #define RESET1_LEVEL (RESET_BASE + 0x21) 183 #define P_RESET1_LEVEL CBUS_REG_ADDR(RESET1_LEVEL) 184 #define RESET2_LEVEL (RESET_BASE + 0x22) 185 #define P_RESET2_LEVEL CBUS_REG_ADDR(RESET2_LEVEL) 186 #define RESET3_LEVEL (RESET_BASE + 0x23) 187 #define P_RESET3_LEVEL CBUS_REG_ADDR(RESET3_LEVEL) 188 #define RESET4_LEVEL (RESET_BASE + 0x24) 189 #define P_RESET4_LEVEL CBUS_REG_ADDR(RESET4_LEVEL) 190 #define RESET5_LEVEL (RESET_BASE + 0x25) 191 #define P_RESET5_LEVEL CBUS_REG_ADDR(RESET5_LEVEL) 192 #define RESET6_LEVEL (RESET_BASE + 0x26) 193 #define P_RESET6_LEVEL CBUS_REG_ADDR(RESET6_LEVEL) 194 #define RESET7_LEVEL (RESET_BASE + 0x27) 195 #define P_RESET7_LEVEL CBUS_REG_ADDR(RESET7_LEVEL) 196 197 /*no set*/ 198 #ifdef MESON_M8_CPU 199 #define HHI_CSI_PHY_CNTL0 (HHI_CSI_PHY_CNTL_BASE + 0xd3) 200 #define P_HHI_CSI_PHY_CNTL0 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL0) 201 #define HHI_CSI_PHY_CNTL1 (HHI_CSI_PHY_CNTL_BASE + 0xd4) 202 #define P_HHI_CSI_PHY_CNTL1 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL1) 203 #define HHI_CSI_PHY_CNTL2 (HHI_CSI_PHY_CNTL_BASE + 0xd5) 204 #define P_HHI_CSI_PHY_CNTL2 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL2) 205 #define HHI_CSI_PHY_CNTL3 (HHI_CSI_PHY_CNTL_BASE + 0xd6) 206 #define P_HHI_CSI_PHY_CNTL3 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL3) 207 #define HHI_CSI_PHY_CNTL4 (HHI_CSI_PHY_CNTL_BASE + 0xd7) 208 #define P_HHI_CSI_PHY_CNTL4 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL4) 209 #endif 210 211 #define PARSER_SUB_START_PTR (PARSER_SUB_START_PTR_BASE + 0x8a) 212 #define P_PARSER_SUB_START_PTR CBUS_REG_ADDR(PARSER_SUB_START_PTR) 213 #define PARSER_SUB_END_PTR (PARSER_SUB_START_PTR_BASE + 0x8b) 214 #define P_PARSER_SUB_END_PTR CBUS_REG_ADDR(PARSER_SUB_END_PTR) 215 #define PARSER_SUB_WP (PARSER_SUB_START_PTR_BASE + 0x8c) 216 #define P_PARSER_SUB_WP CBUS_REG_ADDR(PARSER_SUB_WP) 217 #define PARSER_SUB_RP (PARSER_SUB_START_PTR_BASE + 0x8d) 218 #define P_PARSER_SUB_RP CBUS_REG_ADDR(PARSER_SUB_RP) 219 #define PARSER_SUB_HOLE (PARSER_SUB_START_PTR_BASE + 0x8e) 220 #define P_PARSER_SUB_HOLE CBUS_REG_ADDR(PARSER_SUB_HOLE) 221 222 /*no set*/ 223 #define AO_RTI_GEN_PWR_SLEEP0 ((0x00 << 10) | (0x3a << 2)) 224 #define P_AO_RTI_GEN_PWR_SLEEP0 \ 225 AOBUS_REG_ADDR(AO_RTI_GEN_PWR_SLEEP0) 226 #define AO_RTI_GEN_PWR_ISO0 ((0x00 << 10) | (0x3b << 2)) 227 #define P_AO_RTI_GEN_PWR_ISO0 AOBUS_REG_ADDR(AO_RTI_GEN_PWR_ISO0) 228 229 /**/ 230 #define STB_VERSION (STB_CBUS_BASE + 0x00) 231 #define P_STB_VERSION CBUS_REG_ADDR(STB_VERSION) 232 #define STB_VERSION_2 (STB_CBUS_BASE + 0x50) 233 #define P_STB_VERSION_2 CBUS_REG_ADDR(STB_VERSION_2) 234 #define STB_VERSION_3 (STB_CBUS_BASE + 0xa0) 235 #define P_STB_VERSION_3 CBUS_REG_ADDR(STB_VERSION_3) 236 #define STB_TEST_REG (STB_CBUS_BASE + 0x01) 237 #define P_STB_TEST_REG CBUS_REG_ADDR(STB_TEST_REG) 238 #define STB_TEST_REG_2 (STB_CBUS_BASE + 0x51) 239 #define P_STB_TEST_REG_2 CBUS_REG_ADDR(STB_TEST_REG_2) 240 #define STB_TEST_REG_3 (STB_CBUS_BASE + 0xa1) 241 #define P_STB_TEST_REG_3 CBUS_REG_ADDR(STB_TEST_REG_3) 242 243 #define FEC_INPUT_CONTROL (STB_CBUS_BASE + 0x2) 244 #define P_FEC_INPUT_CONTROL CBUS_REG_ADDR(FEC_INPUT_CONTROL) 245 #define FEC_INPUT_CONTROL_2 (STB_CBUS_BASE + 0x52) 246 #define P_FEC_INPUT_CONTROL_2 CBUS_REG_ADDR(FEC_INPUT_CONTROL_2) 247 #define FEC_INPUT_CONTROL_3 (STB_CBUS_BASE + 0xa2) 248 #define P_FEC_INPUT_CONTROL_3 CBUS_REG_ADDR(FEC_INPUT_CONTROL_3) 249 /*no used*/ 250 #define FEC_INPUT_DATA (STB_CBUS_BASE + 0x03) 251 #define P_FEC_INPUT_DATA CBUS_REG_ADDR(FEC_INPUT_DATA) 252 #define FEC_INPUT_DATA_2 (STB_CBUS_BASE + 0x53) 253 #define P_FEC_INPUT_DATA_2 CBUS_REG_ADDR(FEC_INPUT_DATA_2) 254 #define FEC_INPUT_DATA_3 (STB_CBUS_BASE + 0xa3) 255 #define P_FEC_INPUT_DATA_3 CBUS_REG_ADDR(FEC_INPUT_DATA_3) 256 /*no used end*/ 257 #define DEMUX_CONTROL (STB_CBUS_BASE + 0x04) 258 #define P_DEMUX_CONTROL CBUS_REG_ADDR(DEMUX_CONTROL) 259 #define DEMUX_CONTROL_2 (STB_CBUS_BASE + 0x54) 260 #define P_DEMUX_CONTROL_2 CBUS_REG_ADDR(DEMUX_CONTROL_2) 261 #define DEMUX_CONTROL_3 (STB_CBUS_BASE + 0xa4) 262 #define P_DEMUX_CONTROL_3 CBUS_REG_ADDR(DEMUX_CONTROL_3) 263 /*no used*/ 264 #define FEC_SYNC_BYTE (STB_CBUS_BASE + 0x05) 265 #define P_FEC_SYNC_BYTE CBUS_REG_ADDR(FEC_SYNC_BYTE) 266 #define FEC_SYNC_BYTE_2 (STB_CBUS_BASE + 0x55) 267 #define P_FEC_SYNC_BYTE_2 CBUS_REG_ADDR(FEC_SYNC_BYTE_2) 268 #define FEC_SYNC_BYTE_3 (STB_CBUS_BASE + 0xa5) 269 #define P_FEC_SYNC_BYTE_3 CBUS_REG_ADDR(FEC_SYNC_BYTE_3) 270 /*no used end*/ 271 272 #define FM_WR_DATA (STB_CBUS_BASE + 0x06) 273 #define P_FM_WR_DATA CBUS_REG_ADDR(FM_WR_DATA) 274 #define FM_WR_DATA_2 (STB_CBUS_BASE + 0x56) 275 #define P_FM_WR_DATA_2 CBUS_REG_ADDR(FM_WR_DATA_2) 276 #define FM_WR_DATA_3 (STB_CBUS_BASE + 0xa6) 277 #define P_FM_WR_DATA_3 CBUS_REG_ADDR(FM_WR_DATA_3) 278 #define FM_WR_ADDR (STB_CBUS_BASE + 0x07) 279 #define P_FM_WR_ADDR CBUS_REG_ADDR(FM_WR_ADDR) 280 #define FM_WR_ADDR_2 (STB_CBUS_BASE + 0x57) 281 #define P_FM_WR_ADDR_2 CBUS_REG_ADDR(FM_WR_ADDR_2) 282 #define FM_WR_ADDR_3 (STB_CBUS_BASE + 0xa7) 283 #define P_FM_WR_ADDR_3 CBUS_REG_ADDR(FM_WR_ADDR_3) 284 #define MAX_FM_COMP_ADDR (STB_CBUS_BASE + 0x08) 285 #define P_MAX_FM_COMP_ADDR CBUS_REG_ADDR(MAX_FM_COMP_ADDR) 286 #define MAX_FM_COMP_ADDR_2 (STB_CBUS_BASE + 0x58) 287 #define P_MAX_FM_COMP_ADDR_2 CBUS_REG_ADDR(MAX_FM_COMP_ADDR_2) 288 #define MAX_FM_COMP_ADDR_3 (STB_CBUS_BASE + 0xa8) 289 #define P_MAX_FM_COMP_ADDR_3 CBUS_REG_ADDR(MAX_FM_COMP_ADDR_3) 290 291 #define TS_HEAD_0 (STB_CBUS_BASE + 0x09) 292 #define P_TS_HEAD_0 CBUS_REG_ADDR(TS_HEAD_0) 293 #define TS_HEAD_0_2 (STB_CBUS_BASE + 0x59) 294 #define P_TS_HEAD_0_2 CBUS_REG_ADDR(TS_HEAD_0_2) 295 #define TS_HEAD_0_3 (STB_CBUS_BASE + 0xa9) 296 #define P_TS_HEAD_0_3 CBUS_REG_ADDR(TS_HEAD_0_3) 297 #define TS_HEAD_1 (STB_CBUS_BASE + 0x0a) 298 #define P_TS_HEAD_1 CBUS_REG_ADDR(TS_HEAD_1) 299 #define TS_HEAD_1_2 (STB_CBUS_BASE + 0x5a) 300 #define P_TS_HEAD_1_2 CBUS_REG_ADDR(TS_HEAD_1_2) 301 #define TS_HEAD_1_3 (STB_CBUS_BASE + 0xaa) 302 #define P_TS_HEAD_1_3 CBUS_REG_ADDR(TS_HEAD_1_3) 303 304 #define OM_CMD_STATUS (STB_CBUS_BASE + 0x0b) 305 #define P_OM_CMD_STATUS CBUS_REG_ADDR(OM_CMD_STATUS) 306 #define OM_CMD_STATUS_2 (STB_CBUS_BASE + 0x5b) 307 #define P_OM_CMD_STATUS_2 CBUS_REG_ADDR(OM_CMD_STATUS_2) 308 #define OM_CMD_STATUS_3 (STB_CBUS_BASE + 0xab) 309 #define P_OM_CMD_STATUS_3 CBUS_REG_ADDR(OM_CMD_STATUS_3) 310 311 #define OM_CMD_DATA (STB_CBUS_BASE + 0x0c) 312 #define P_OM_CMD_DATA CBUS_REG_ADDR(OM_CMD_DATA) 313 #define OM_CMD_DATA_2 (STB_CBUS_BASE + 0x5c) 314 #define P_OM_CMD_DATA_2 CBUS_REG_ADDR(OM_CMD_DATA_2) 315 #define OM_CMD_DATA_3 (STB_CBUS_BASE + 0xac) 316 #define P_OM_CMD_DATA_3 CBUS_REG_ADDR(OM_CMD_DATA_3) 317 #define OM_CMD_DATA2 (STB_CBUS_BASE + 0x0d) 318 #define P_OM_CMD_DATA2 CBUS_REG_ADDR(OM_CMD_DATA2) 319 #define OM_CMD_DATA2_2 (STB_CBUS_BASE + 0x5d) 320 #define P_OM_CMD_DATA2_2 CBUS_REG_ADDR(OM_CMD_DATA2_2) 321 #define OM_CMD_DATA2_3 (STB_CBUS_BASE + 0xad) 322 #define P_OM_CMD_DATA2_3 CBUS_REG_ADDR(OM_CMD_DATA2_3) 323 324 #define SEC_BUFF_01_START (STB_CBUS_BASE + 0x0e) 325 #define P_SEC_BUFF_01_START CBUS_REG_ADDR(SEC_BUFF_01_START) 326 #define SEC_BUFF_01_START_2 (STB_CBUS_BASE + 0x5e) 327 #define P_SEC_BUFF_01_START_2 CBUS_REG_ADDR(SEC_BUFF_01_START_2) 328 #define SEC_BUFF_01_START_3 (STB_CBUS_BASE + 0xae) 329 #define P_SEC_BUFF_01_START_3 CBUS_REG_ADDR(SEC_BUFF_01_START_3) 330 #define SEC_BUFF_23_START (STB_CBUS_BASE + 0x0f) 331 #define P_SEC_BUFF_23_START CBUS_REG_ADDR(SEC_BUFF_23_START) 332 #define SEC_BUFF_23_START_2 (STB_CBUS_BASE + 0x5f) 333 #define P_SEC_BUFF_23_START_2 CBUS_REG_ADDR(SEC_BUFF_23_START_2) 334 #define SEC_BUFF_23_START_3 (STB_CBUS_BASE + 0xaf) 335 #define P_SEC_BUFF_23_START_3 CBUS_REG_ADDR(SEC_BUFF_23_START_3) 336 #define SEC_BUFF_SIZE (STB_CBUS_BASE + 0x10) 337 #define P_SEC_BUFF_SIZE CBUS_REG_ADDR(SEC_BUFF_SIZE) 338 #define SEC_BUFF_SIZE_2 (STB_CBUS_BASE + 0x60) 339 #define P_SEC_BUFF_SIZE_2 CBUS_REG_ADDR(SEC_BUFF_SIZE_2) 340 #define SEC_BUFF_SIZE_3 (STB_CBUS_BASE + 0xb0) 341 #define P_SEC_BUFF_SIZE_3 CBUS_REG_ADDR(SEC_BUFF_SIZE_3) 342 #define SEC_BUFF_BUSY (STB_CBUS_BASE + 0x11) 343 #define P_SEC_BUFF_BUSY CBUS_REG_ADDR(SEC_BUFF_BUSY) 344 #define SEC_BUFF_BUSY_2 (STB_CBUS_BASE + 0x61) 345 #define P_SEC_BUFF_BUSY_2 CBUS_REG_ADDR(SEC_BUFF_BUSY_2) 346 #define SEC_BUFF_BUSY_3 (STB_CBUS_BASE + 0xb1) 347 #define P_SEC_BUFF_BUSY_3 CBUS_REG_ADDR(SEC_BUFF_BUSY_3) 348 #define SEC_BUFF_READY (STB_CBUS_BASE + 0x12) 349 #define P_SEC_BUFF_READY CBUS_REG_ADDR(SEC_BUFF_READY) 350 #define SEC_BUFF_READY_2 (STB_CBUS_BASE + 0x62) 351 #define P_SEC_BUFF_READY_2 CBUS_REG_ADDR(SEC_BUFF_READY_2) 352 #define SEC_BUFF_READY_3 (STB_CBUS_BASE + 0xb2) 353 #define P_SEC_BUFF_READY_3 CBUS_REG_ADDR(SEC_BUFF_READY_3) 354 #define SEC_BUFF_NUMBER (STB_CBUS_BASE + 0x13) 355 #define P_SEC_BUFF_NUMBER CBUS_REG_ADDR(SEC_BUFF_NUMBER) 356 #define SEC_BUFF_NUMBER_2 (STB_CBUS_BASE + 0x63) 357 #define P_SEC_BUFF_NUMBER_2 CBUS_REG_ADDR(SEC_BUFF_NUMBER_2) 358 #define SEC_BUFF_NUMBER_3 (STB_CBUS_BASE + 0xb3) 359 #define P_SEC_BUFF_NUMBER_3 CBUS_REG_ADDR(SEC_BUFF_NUMBER_3) 360 361 362 /**no used*/ 363 #define ASSIGN_PID_NUMBER (STB_CBUS_BASE + 0x14) 364 #define P_ASSIGN_PID_NUMBER CBUS_REG_ADDR(ASSIGN_PID_NUMBER) 365 #define ASSIGN_PID_NUMBER_2 (STB_CBUS_BASE + 0x64) 366 #define P_ASSIGN_PID_NUMBER_2 CBUS_REG_ADDR(ASSIGN_PID_NUMBER_2) 367 #define ASSIGN_PID_NUMBER_3 (STB_CBUS_BASE + 0xb4) 368 #define P_ASSIGN_PID_NUMBER_3 CBUS_REG_ADDR(ASSIGN_PID_NUMBER_3) 369 #define VIDEO_STREAM_ID (STB_CBUS_BASE + 0x15) 370 #define P_VIDEO_STREAM_ID CBUS_REG_ADDR(VIDEO_STREAM_ID) 371 #define VIDEO_STREAM_ID_2 (STB_CBUS_BASE + 0x65) 372 #define P_VIDEO_STREAM_ID_2 CBUS_REG_ADDR(VIDEO_STREAM_ID_2) 373 #define VIDEO_STREAM_ID_3 (STB_CBUS_BASE + 0xb5) 374 #define P_VIDEO_STREAM_ID_3 CBUS_REG_ADDR(VIDEO_STREAM_ID_3) 375 #define AUDIO_STREAM_ID (STB_CBUS_BASE + 0x16) 376 #define P_AUDIO_STREAM_ID CBUS_REG_ADDR(AUDIO_STREAM_ID) 377 #define AUDIO_STREAM_ID_2 (STB_CBUS_BASE + 0x66) 378 #define P_AUDIO_STREAM_ID_2 CBUS_REG_ADDR(AUDIO_STREAM_ID_2) 379 #define AUDIO_STREAM_ID_3 (STB_CBUS_BASE + 0xb6) 380 #define P_AUDIO_STREAM_ID_3 CBUS_REG_ADDR(AUDIO_STREAM_ID_3) 381 #define SUB_STREAM_ID (STB_CBUS_BASE + 0x17) 382 #define P_SUB_STREAM_ID CBUS_REG_ADDR(SUB_STREAM_ID) 383 #define SUB_STREAM_ID_2 (STB_CBUS_BASE + 0x67) 384 #define P_SUB_STREAM_ID_2 CBUS_REG_ADDR(SUB_STREAM_ID_2) 385 #define SUB_STREAM_ID_3 (STB_CBUS_BASE + 0xb7) 386 #define P_SUB_STREAM_ID_3 CBUS_REG_ADDR(SUB_STREAM_ID_3) 387 #define OTHER_STREAM_ID (STB_CBUS_BASE + 0x18) 388 #define P_OTHER_STREAM_ID CBUS_REG_ADDR(OTHER_STREAM_ID) 389 #define OTHER_STREAM_ID_2 (STB_CBUS_BASE + 0x68) 390 #define P_OTHER_STREAM_ID_2 CBUS_REG_ADDR(OTHER_STREAM_ID_2) 391 #define OTHER_STREAM_ID_3 (STB_CBUS_BASE + 0xb8) 392 #define P_OTHER_STREAM_ID_3 CBUS_REG_ADDR(OTHER_STREAM_ID_3) 393 #define PCR90K_CTL (STB_CBUS_BASE + 0x19) 394 #define P_PCR90K_CTL CBUS_REG_ADDR(PCR90K_CTL) 395 #define PCR90K_CTL_2 (STB_CBUS_BASE + 0x69) 396 #define P_PCR90K_CTL_2 CBUS_REG_ADDR(PCR90K_CTL_2) 397 #define PCR90K_CTL_3 (STB_CBUS_BASE + 0xb9) 398 #define P_PCR90K_CTL_3 CBUS_REG_ADDR(PCR90K_CTL_3) 399 /*no used end*/ 400 #define PCR_DEMUX (STB_CBUS_BASE + 0x1a) 401 #define P_PCR_DEMUX CBUS_REG_ADDR(PCR_DEMUX) 402 #define PCR_DEMUX_2 (STB_CBUS_BASE + 0x6a) 403 #define P_PCR_DEMUX_2 CBUS_REG_ADDR(PCR_DEMUX_2) 404 #define PCR_DEMUX_3 (STB_CBUS_BASE + 0xba) 405 #define P_PCR_DEMUX_3 CBUS_REG_ADDR(PCR_DEMUX_3) 406 407 #define VIDEO_PTS_DEMUX (STB_CBUS_BASE + 0x1b) 408 #define P_VIDEO_PTS_DEMUX CBUS_REG_ADDR(VIDEO_PTS_DEMUX) 409 #define VIDEO_PTS_DEMUX_2 (STB_CBUS_BASE + 0x6b) 410 #define P_VIDEO_PTS_DEMUX_2 CBUS_REG_ADDR(VIDEO_PTS_DEMUX_2) 411 #define VIDEO_PTS_DEMUX_3 (STB_CBUS_BASE + 0xbb) 412 #define P_VIDEO_PTS_DEMUX_3 CBUS_REG_ADDR(VIDEO_PTS_DEMUX_3) 413 /*no used*/ 414 #define VIDEO_DTS_DEMUX (STB_CBUS_BASE + 0x1c) 415 #define P_VIDEO_DTS_DEMUX CBUS_REG_ADDR(VIDEO_DTS_DEMUX) 416 #define VIDEO_DTS_DEMUX_2 (STB_CBUS_BASE + 0x6c) 417 #define P_VIDEO_DTS_DEMUX_2 CBUS_REG_ADDR(VIDEO_DTS_DEMUX_2) 418 #define VIDEO_DTS_DEMUX_3 (STB_CBUS_BASE + 0xbc) 419 #define P_VIDEO_DTS_DEMUX_3 CBUS_REG_ADDR(VIDEO_DTS_DEMUX_3) 420 /*no used end*/ 421 #define AUDIO_PTS_DEMUX (STB_CBUS_BASE + 0x1d) 422 #define P_AUDIO_PTS_DEMUX CBUS_REG_ADDR(AUDIO_PTS_DEMUX) 423 #define AUDIO_PTS_DEMUX_2 (STB_CBUS_BASE + 0x6d) 424 #define P_AUDIO_PTS_DEMUX_2 CBUS_REG_ADDR(AUDIO_PTS_DEMUX_2) 425 #define AUDIO_PTS_DEMUX_3 (STB_CBUS_BASE + 0xbd) 426 #define P_AUDIO_PTS_DEMUX_3 CBUS_REG_ADDR(AUDIO_PTS_DEMUX_3) 427 /*no used */ 428 #define SUB_PTS_DEMUX (STB_CBUS_BASE + 0x1e) 429 #define P_SUB_PTS_DEMUX CBUS_REG_ADDR(SUB_PTS_DEMUX) 430 #define SUB_PTS_DEMUX_2 (STB_CBUS_BASE + 0x6e) 431 #define P_SUB_PTS_DEMUX_2 CBUS_REG_ADDR(SUB_PTS_DEMUX_2) 432 #define SUB_PTS_DEMUX_3 (STB_CBUS_BASE + 0xbe) 433 #define P_SUB_PTS_DEMUX_3 CBUS_REG_ADDR(SUB_PTS_DEMUX_3) 434 /*no used end*/ 435 #define STB_PTS_DTS_STATUS (STB_CBUS_BASE + 0x1f) 436 #define P_STB_PTS_DTS_STATUS CBUS_REG_ADDR(STB_PTS_DTS_STATUS) 437 #define STB_PTS_DTS_STATUS_2 (STB_CBUS_BASE + 0x6f) 438 #define P_STB_PTS_DTS_STATUS_2 CBUS_REG_ADDR(STB_PTS_DTS_STATUS_2) 439 #define STB_PTS_DTS_STATUS_3 (STB_CBUS_BASE + 0xbf) 440 #define P_STB_PTS_DTS_STATUS_3 CBUS_REG_ADDR(STB_PTS_DTS_STATUS_3) 441 442 /*no use*/ 443 #define STB_DEBUG_INDEX (STB_CBUS_BASE + 0x20) 444 #define P_STB_DEBUG_INDEX CBUS_REG_ADDR(STB_DEBUG_INDEX) 445 #define STB_DEBUG_INDEX_2 (STB_CBUS_BASE + 0x70) 446 #define P_STB_DEBUG_INDEX_2 CBUS_REG_ADDR(STB_DEBUG_INDEX_2) 447 #define STB_DEBUG_INDEX_3 (STB_CBUS_BASE + 0xc0) 448 #define P_STB_DEBUG_INDEX_3 CBUS_REG_ADDR(STB_DEBUG_INDEX_3) 449 #define STB_DEBUG_DATAUT_O (STB_CBUS_BASE + 0x21) 450 #define P_STB_DEBUG_DATAUT_O CBUS_REG_ADDR(STB_DEBUG_DATAUT_O) 451 #define STB_DEBUG_DATAUT_O_2 (STB_CBUS_BASE + 0x71) 452 #define P_STB_DEBUG_DATAUT_O_2 CBUS_REG_ADDR(STB_DEBUG_DATAUT_O_2) 453 #define STB_DEBUG_DATAUT_O_3 (STB_CBUS_BASE + 0xc1) 454 #define P_STB_DEBUG_DATAUT_O_3 CBUS_REG_ADDR(STB_DEBUG_DATAUT_O_3) 455 /*no use end*/ 456 457 #define STBM_CTL_O (STB_CBUS_BASE + 0x22) 458 #define P_STBM_CTL_O CBUS_REG_ADDR(STBM_CTL_O) 459 #define STBM_CTL_O_2 (STB_CBUS_BASE + 0x72) 460 #define P_STBM_CTL_O_2 CBUS_REG_ADDR(STBM_CTL_O_2) 461 #define STBM_CTL_O_3 (STB_CBUS_BASE + 0xc2) 462 #define P_STBM_CTL_O_3 CBUS_REG_ADDR(STBM_CTL_O_3) 463 #define STB_INT_STATUS (STB_CBUS_BASE + 0x23) 464 #define P_STB_INT_STATUS CBUS_REG_ADDR(STB_INT_STATUS) 465 #define STB_INT_STATUS_2 (STB_CBUS_BASE + 0x73) 466 #define P_STB_INT_STATUS_2 CBUS_REG_ADDR(STB_INT_STATUS_2) 467 #define STB_INT_STATUS_3 (STB_CBUS_BASE + 0xc3) 468 #define P_STB_INT_STATUS_3 CBUS_REG_ADDR(STB_INT_STATUS_3) 469 #define DEMUX_ENDIAN (STB_CBUS_BASE + 0x24) 470 #define P_DEMUX_ENDIAN CBUS_REG_ADDR(DEMUX_ENDIAN) 471 #define DEMUX_ENDIAN_2 (STB_CBUS_BASE + 0x74) 472 #define P_DEMUX_ENDIAN_2 CBUS_REG_ADDR(DEMUX_ENDIAN_2) 473 #define DEMUX_ENDIAN_3 (STB_CBUS_BASE + 0xc4) 474 #define P_DEMUX_ENDIAN_3 CBUS_REG_ADDR(DEMUX_ENDIAN_3) 475 #define TS_HIU_CTL (STB_CBUS_BASE + 0x25) 476 #define P_TS_HIU_CTL CBUS_REG_ADDR(TS_HIU_CTL) 477 #define TS_HIU_CTL_2 (STB_CBUS_BASE + 0x75) 478 #define P_TS_HIU_CTL_2 CBUS_REG_ADDR(TS_HIU_CTL_2) 479 #define TS_HIU_CTL_3 (STB_CBUS_BASE + 0xc5) 480 #define P_TS_HIU_CTL_3 CBUS_REG_ADDR(TS_HIU_CTL_3) 481 482 #define SEC_BUFF_BASE (STB_CBUS_BASE + 0x26) 483 #define P_SEC_BUFF_BASE CBUS_REG_ADDR(SEC_BUFF_BASE) 484 #define SEC_BUFF_BASE_2 (STB_CBUS_BASE + 0x76) 485 #define P_SEC_BUFF_BASE_2 CBUS_REG_ADDR(SEC_BUFF_BASE_2) 486 #define SEC_BUFF_BASE_3 (STB_CBUS_BASE + 0xc6) 487 #define P_SEC_BUFF_BASE_3 CBUS_REG_ADDR(SEC_BUFF_BASE_3) 488 #define DEMUX_MEM_REQ_EN (STB_CBUS_BASE + 0x27) 489 #define P_DEMUX_MEM_REQ_EN CBUS_REG_ADDR(DEMUX_MEM_REQ_EN) 490 #define DEMUX_MEM_REQ_EN_2 (STB_CBUS_BASE + 0x77) 491 #define P_DEMUX_MEM_REQ_EN_2 CBUS_REG_ADDR(DEMUX_MEM_REQ_EN_2) 492 #define DEMUX_MEM_REQ_EN_3 (STB_CBUS_BASE + 0xc7) 493 #define P_DEMUX_MEM_REQ_EN_3 CBUS_REG_ADDR(DEMUX_MEM_REQ_EN_3) 494 495 496 /*no use*/ 497 #define VIDEO_PDTS_WR_PTR (STB_CBUS_BASE + 0x28) 498 #define P_VIDEO_PDTS_WR_PTR CBUS_REG_ADDR(VIDEO_PDTS_WR_PTR) 499 #define VIDEO_PDTS_WR_PTR_2 (STB_CBUS_BASE + 0x78) 500 #define P_VIDEO_PDTS_WR_PTR_2 CBUS_REG_ADDR(VIDEO_PDTS_WR_PTR_2) 501 #define VIDEO_PDTS_WR_PTR_3 (STB_CBUS_BASE + 0xc8) 502 #define P_VIDEO_PDTS_WR_PTR_3 CBUS_REG_ADDR(VIDEO_PDTS_WR_PTR_3) 503 #define AUDIO_PDTS_WR_PTR (STB_CBUS_BASE + 0x29) 504 #define P_AUDIO_PDTS_WR_PTR CBUS_REG_ADDR(AUDIO_PDTS_WR_PTR) 505 #define AUDIO_PDTS_WR_PTR_2 (STB_CBUS_BASE + 0x79) 506 #define P_AUDIO_PDTS_WR_PTR_2 CBUS_REG_ADDR(AUDIO_PDTS_WR_PTR_2) 507 #define AUDIO_PDTS_WR_PTR_3 (STB_CBUS_BASE + 0xc9) 508 #define P_AUDIO_PDTS_WR_PTR_3 CBUS_REG_ADDR(AUDIO_PDTS_WR_PTR_3) 509 #define SUB_WR_PTR (STB_CBUS_BASE + 0x2a) 510 #define P_SUB_WR_PTR CBUS_REG_ADDR(SUB_WR_PTR) 511 #define SUB_WR_PTR_2 (STB_CBUS_BASE + 0x7a) 512 #define P_SUB_WR_PTR_2 CBUS_REG_ADDR(SUB_WR_PTR_2) 513 #define SUB_WR_PTR_3 (STB_CBUS_BASE + 0xca) 514 #define P_SUB_WR_PTR_3 CBUS_REG_ADDR(SUB_WR_PTR_3) 515 /*no use*/ 516 517 #define SB_START (STB_CBUS_BASE + 0x2b) 518 #define P_SB_START CBUS_REG_ADDR(SB_START) 519 #define SB_START_2 (STB_CBUS_BASE + 0x7b) 520 #define P_SB_START_2 CBUS_REG_ADDR(SB_START_2) 521 #define SB_START_3 (STB_CBUS_BASE + 0xcb) 522 #define P_SB_START_3 CBUS_REG_ADDR(SB_START_3) 523 #define SB_LAST_ADDR (STB_CBUS_BASE + 0x2c) 524 #define P_SB_LAST_ADDR CBUS_REG_ADDR(SB_LAST_ADDR) 525 #define SB_LAST_ADDR_2 (STB_CBUS_BASE + 0x7c) 526 #define P_SB_LAST_ADDR_2 CBUS_REG_ADDR(SB_LAST_ADDR_2) 527 #define SB_LAST_ADDR_3 (STB_CBUS_BASE + 0xcc) 528 #define P_SB_LAST_ADDR_3 CBUS_REG_ADDR(SB_LAST_ADDR_3) 529 #define SB_PES_WR_PTR (STB_CBUS_BASE + 0x2d) 530 #define P_SB_PES_WR_PTR CBUS_REG_ADDR(SB_PES_WR_PTR) 531 #define SB_PES_WR_PTR_2 (STB_CBUS_BASE + 0x7d) 532 #define P_SB_PES_WR_PTR_2 CBUS_REG_ADDR(SB_PES_WR_PTR_2) 533 #define SB_PES_WR_PTR_3 (STB_CBUS_BASE + 0xcd) 534 #define P_SB_PES_WR_PTR_3 CBUS_REG_ADDR(SB_PES_WR_PTR_3) 535 #define OTHER_WR_PTR (STB_CBUS_BASE + 0x2e) 536 #define P_OTHER_WR_PTR CBUS_REG_ADDR(OTHER_WR_PTR) 537 #define OTHER_WR_PTR_2 (STB_CBUS_BASE + 0x7e) 538 #define P_OTHER_WR_PTR_2 CBUS_REG_ADDR(OTHER_WR_PTR_2) 539 #define OTHER_WR_PTR_3 (STB_CBUS_BASE + 0xce) 540 #define P_OTHER_WR_PTR_3 CBUS_REG_ADDR(OTHER_WR_PTR_3) 541 542 #define OB_START (STB_CBUS_BASE + 0x2f) 543 #define P_OB_START CBUS_REG_ADDR(OB_START) 544 #define OB_START_2 (STB_CBUS_BASE + 0x7f) 545 #define P_OB_START_2 CBUS_REG_ADDR(OB_START_2) 546 #define OB_START_3 (STB_CBUS_BASE + 0xcf) 547 #define P_OB_START_3 CBUS_REG_ADDR(OB_START_3) 548 #define OB_LAST_ADDR (STB_CBUS_BASE + 0x30) 549 #define P_OB_LAST_ADDR CBUS_REG_ADDR(OB_LAST_ADDR) 550 #define OB_LAST_ADDR_2 (STB_CBUS_BASE + 0x80) 551 #define P_OB_LAST_ADDR_2 CBUS_REG_ADDR(OB_LAST_ADDR_2) 552 #define OB_LAST_ADDR_3 (STB_CBUS_BASE + 0xd0) 553 #define P_OB_LAST_ADDR_3 CBUS_REG_ADDR(OB_LAST_ADDR_3) 554 #define OB_PES_WR_PTR (STB_CBUS_BASE + 0x31) 555 #define P_OB_PES_WR_PTR CBUS_REG_ADDR(OB_PES_WR_PTR) 556 #define OB_PES_WR_PTR_2 (STB_CBUS_BASE + 0x81) 557 #define P_OB_PES_WR_PTR_2 CBUS_REG_ADDR(OB_PES_WR_PTR_2) 558 #define OB_PES_WR_PTR_3 (STB_CBUS_BASE + 0xd1) 559 #define P_OB_PES_WR_PTR_3 CBUS_REG_ADDR(OB_PES_WR_PTR_3) 560 #define STB_INT_MASK (STB_CBUS_BASE + 0x32) 561 #define P_STB_INT_MASK CBUS_REG_ADDR(STB_INT_MASK) 562 #define STB_INT_MASK_2 (STB_CBUS_BASE + 0x82) 563 #define P_STB_INT_MASK_2 CBUS_REG_ADDR(STB_INT_MASK_2) 564 #define STB_INT_MASK_3 (STB_CBUS_BASE + 0xd2) 565 #define P_STB_INT_MASK_3 CBUS_REG_ADDR(STB_INT_MASK_3) 566 /*no used */ 567 #define VIDEO_SPLICING_CTL (STB_CBUS_BASE + 0x33) 568 #define P_VIDEO_SPLICING_CTL CBUS_REG_ADDR(VIDEO_SPLICING_CTL) 569 #define VIDEO_SPLICING_CTL_2 (STB_CBUS_BASE + 0x83) 570 #define P_VIDEO_SPLICING_CTL_2 CBUS_REG_ADDR(VIDEO_SPLICING_CTL_2) 571 #define VIDEO_SPLICING_CTL_3 (STB_CBUS_BASE + 0xd3) 572 #define P_VIDEO_SPLICING_CTL_3 CBUS_REG_ADDR(VIDEO_SPLICING_CTL_3) 573 #define AUDIO_SPLICING_CTL (STB_CBUS_BASE + 0x34) 574 #define P_AUDIO_SPLICING_CTL CBUS_REG_ADDR(AUDIO_SPLICING_CTL) 575 #define AUDIO_SPLICING_CTL_2 (STB_CBUS_BASE + 0x84) 576 #define P_AUDIO_SPLICING_CTL_2 CBUS_REG_ADDR(AUDIO_SPLICING_CTL_2) 577 #define AUDIO_SPLICING_CTL_3 (STB_CBUS_BASE + 0xd4) 578 #define P_AUDIO_SPLICING_CTL_3 CBUS_REG_ADDR(AUDIO_SPLICING_CTL_3) 579 #define TS_PACKAGE_BYTE_COUNT (STB_CBUS_BASE + 0x35) 580 #define P_TS_PACKAGE_BYTE_COUNT \ 581 CBUS_REG_ADDR(TS_PACKAGE_BYTE_COUNT) 582 #define TS_PACKAGE_BYTE_COUNT_2 (STB_CBUS_BASE + 0x85) 583 #define P_TS_PACKAGE_BYTE_COUNT_2 \ 584 CBUS_REG_ADDR(TS_PACKAGE_BYTE_COUNT_2) 585 #define TS_PACKAGE_BYTE_COUNT_3 (STB_CBUS_BASE + 0xd5) 586 #define P_TS_PACKAGE_BYTE_COUNT_3 \ 587 CBUS_REG_ADDR(TS_PACKAGE_BYTE_COUNT_3) 588 /*no used end*/ 589 590 #define PES_STRONG_SYNC (STB_CBUS_BASE + 0x36) 591 #define P_PES_STRONG_SYNC CBUS_REG_ADDR(PES_STRONG_SYNC) 592 #define PES_STRONG_SYNC_2 (STB_CBUS_BASE + 0x86) 593 #define P_PES_STRONG_SYNC_2 CBUS_REG_ADDR(PES_STRONG_SYNC_2) 594 #define PES_STRONG_SYNC_3 (STB_CBUS_BASE + 0xd6) 595 #define P_PES_STRONG_SYNC_3 CBUS_REG_ADDR(PES_STRONG_SYNC_3) 596 597 #define OM_DATA_RD_ADDR (STB_CBUS_BASE + 0x37) 598 #define P_OM_DATA_RD_ADDR CBUS_REG_ADDR(OM_DATA_RD_ADDR) 599 #define OM_DATA_RD_ADDR_2 (STB_CBUS_BASE + 0x87) 600 #define P_OM_DATA_RD_ADDR_2 CBUS_REG_ADDR(OM_DATA_RD_ADDR_2) 601 #define OM_DATA_RD_ADDR_3 (STB_CBUS_BASE + 0xd7) 602 #define P_OM_DATA_RD_ADDR_3 CBUS_REG_ADDR(OM_DATA_RD_ADDR_3) 603 #define OM_DATA_RD (STB_CBUS_BASE + 0x38) 604 #define P_OM_DATA_RD CBUS_REG_ADDR(OM_DATA_RD) 605 #define OM_DATA_RD_2 (STB_CBUS_BASE + 0x88) 606 #define P_OM_DATA_RD_2 CBUS_REG_ADDR(OM_DATA_RD_2) 607 #define OM_DATA_RD_3 (STB_CBUS_BASE + 0xd8) 608 #define P_OM_DATA_RD_3 CBUS_REG_ADDR(OM_DATA_RD_3) 609 610 /*no used*/ 611 612 #define SECTION_AUTO_STOP_3 (STB_CBUS_BASE + 0x39) 613 #define P_SECTION_AUTO_STOP_3 CBUS_REG_ADDR(SECTION_AUTO_STOP_3) 614 #define SECTION_AUTO_STOP_3_2 (STB_CBUS_BASE + 0x89) 615 #define P_SECTION_AUTO_STOP_3_2 \ 616 CBUS_REG_ADDR(SECTION_AUTO_STOP_3_2) 617 #define SECTION_AUTO_STOP_3_3 (STB_CBUS_BASE + 0xd9) 618 #define P_SECTION_AUTO_STOP_3_3 \ 619 CBUS_REG_ADDR(SECTION_AUTO_STOP_3_3) 620 #define SECTION_AUTO_STOP_2 (STB_CBUS_BASE + 0x3a) 621 #define P_SECTION_AUTO_STOP_2 \ 622 CBUS_REG_ADDR(SECTION_AUTO_STOP_2) 623 #define SECTION_AUTO_STOP_2_2 (STB_CBUS_BASE + 0x8a) 624 #define P_SECTION_AUTO_STOP_2_2 \ 625 CBUS_REG_ADDR(SECTION_AUTO_STOP_2_2) 626 #define SECTION_AUTO_STOP_2_3 (STB_CBUS_BASE + 0xda) 627 #define P_SECTION_AUTO_STOP_2_3 \ 628 CBUS_REG_ADDR(SECTION_AUTO_STOP_2_3) 629 #define SECTION_AUTO_STOP_1 (STB_CBUS_BASE + 0x3b) 630 #define P_SECTION_AUTO_STOP_1 CBUS_REG_ADDR(SECTION_AUTO_STOP_1) 631 #define SECTION_AUTO_STOP_1_2 (STB_CBUS_BASE + 0x8b) 632 #define P_SECTION_AUTO_STOP_1_2 \ 633 CBUS_REG_ADDR(SECTION_AUTO_STOP_1_2) 634 #define SECTION_AUTO_STOP_1_3 (STB_CBUS_BASE + 0xdb) 635 #define P_SECTION_AUTO_STOP_1_3 \ 636 CBUS_REG_ADDR(SECTION_AUTO_STOP_1_3) 637 #define SECTION_AUTO_STOP_0 (STB_CBUS_BASE + 0x3c) 638 #define P_SECTION_AUTO_STOP_0 \ 639 CBUS_REG_ADDR(SECTION_AUTO_STOP_0) 640 #define SECTION_AUTO_STOP_0_2 (STB_CBUS_BASE + 0x8c) 641 #define P_SECTION_AUTO_STOP_0_2 \ 642 CBUS_REG_ADDR(SECTION_AUTO_STOP_0_2) 643 #define SECTION_AUTO_STOP_0_3 (STB_CBUS_BASE + 0xdc) 644 #define P_SECTION_AUTO_STOP_0_3 \ 645 CBUS_REG_ADDR(SECTION_AUTO_STOP_0_3) 646 647 #define DEMUX_CHANNEL_RESET (STB_CBUS_BASE + 0x3d) 648 #define P_DEMUX_CHANNEL_RESET \ 649 CBUS_REG_ADDR(DEMUX_CHANNEL_RESET) 650 #define DEMUX_CHANNEL_RESET_2 (STB_CBUS_BASE + 0x8d) 651 #define P_DEMUX_CHANNEL_RESET_2 \ 652 CBUS_REG_ADDR(DEMUX_CHANNEL_RESET_2) 653 #define DEMUX_CHANNEL_RESET_3 (STB_CBUS_BASE + 0xdd) 654 #define P_DEMUX_CHANNEL_RESET_3 \ 655 CBUS_REG_ADDR(DEMUX_CHANNEL_RESET_3) 656 /*no use end*/ 657 #define DEMUX_SCRAMBLING_STATE (STB_CBUS_BASE + 0x3e) 658 #define DEMUX_SCRAMBLING_STATE_2 (STB_CBUS_BASE + 0x8e) 659 #define P_DEMUX_SCRAMBLING_STATE_2 \ 660 CBUS_REG_ADDR(DEMUX_SCRAMBLING_STATE_2) 661 #define DEMUX_SCRAMBLING_STATE_3 (STB_CBUS_BASE + 0xde) 662 #define P_DEMUX_SCRAMBLING_STATE_3 \ 663 CBUS_REG_ADDR(DEMUX_SCRAMBLING_STATE_3) 664 #define DEMUX_CHANNEL_ACTIVITY (STB_CBUS_BASE + 0x3f) 665 #define P_DEMUX_CHANNEL_ACTIVITY \ 666 CBUS_REG_ADDR(DEMUX_CHANNEL_ACTIVITY) 667 #define DEMUX_CHANNEL_ACTIVITY_2 (STB_CBUS_BASE + 0x8f) 668 #define P_DEMUX_CHANNEL_ACTIVITY_2 \ 669 CBUS_REG_ADDR(DEMUX_CHANNEL_ACTIVITY_2) 670 #define DEMUX_CHANNEL_ACTIVITY_3 (STB_CBUS_BASE + 0xdf) 671 #define P_DEMUX_CHANNEL_ACTIVITY_3 \ 672 CBUS_REG_ADDR(DEMUX_CHANNEL_ACTIVITY_3) 673 674 /*no use*/ 675 676 #define DEMUX_STAMP_CTL (STB_CBUS_BASE + 0x40) 677 #define P_DEMUX_STAMP_CTL CBUS_REG_ADDR(DEMUX_STAMP_CTL) 678 #define DEMUX_STAMP_CTL_2 (STB_CBUS_BASE + 0x90) 679 #define P_DEMUX_STAMP_CTL_2 \ 680 CBUS_REG_ADDR(DEMUX_STAMP_CTL_2) 681 #define DEMUX_STAMP_CTL_3 (STB_CBUS_BASE + 0xe0) 682 #define P_DEMUX_STAMP_CTL_3 \ 683 CBUS_REG_ADDR(DEMUX_STAMP_CTL_3) 684 #define DEMUX_VIDEO_STAMP_SYNC_0 (STB_CBUS_BASE + 0x41) 685 #define P_DEMUX_VIDEO_STAMP_SYNC_0 \ 686 CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_0) 687 #define DEMUX_VIDEO_STAMP_SYNC_0_2 (STB_CBUS_BASE + 0x91) 688 #define P_DEMUX_VIDEO_STAMP_SYNC_0_2 \ 689 CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_0_2) 690 #define DEMUX_VIDEO_STAMP_SYNC_0_3 (STB_CBUS_BASE + 0xe1) 691 #define P_DEMUX_VIDEO_STAMP_SYNC_0_3 \ 692 CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_0_3) 693 #define DEMUX_VIDEO_STAMP_SYNC_1 (STB_CBUS_BASE + 0x42) 694 #define P_DEMUX_VIDEO_STAMP_SYNC_1 \ 695 CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_1) 696 #define DEMUX_VIDEO_STAMP_SYNC_1_2 (STB_CBUS_BASE + 0x92) 697 #define P_DEMUX_VIDEO_STAMP_SYNC_1_2 \ 698 CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_1_2) 699 #define DEMUX_VIDEO_STAMP_SYNC_1_3 (STB_CBUS_BASE + 0xe2) 700 #define P_DEMUX_VIDEO_STAMP_SYNC_1_3 \ 701 CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_1_3) 702 #define DEMUX_AUDIO_STAMP_SYNC_0 (STB_CBUS_BASE + 0x43) 703 #define P_DEMUX_AUDIO_STAMP_SYNC_0 \ 704 CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_0) 705 #define DEMUX_AUDIO_STAMP_SYNC_0_2 (STB_CBUS_BASE + 0x93) 706 #define P_DEMUX_AUDIO_STAMP_SYNC_0_2 \ 707 CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_0_2) 708 #define DEMUX_AUDIO_STAMP_SYNC_0_3 (STB_CBUS_BASE + 0xe3) 709 #define P_DEMUX_AUDIO_STAMP_SYNC_0_3 \ 710 CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_0_3) 711 #define DEMUX_AUDIO_STAMP_SYNC_1 (STB_CBUS_BASE + 0x44) 712 #define P_DEMUX_AUDIO_STAMP_SYNC_1 \ 713 CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_1) 714 #define DEMUX_AUDIO_STAMP_SYNC_1_2 (STB_CBUS_BASE + 0x94) 715 #define P_DEMUX_AUDIO_STAMP_SYNC_1_2 \ 716 CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_1_2) 717 #define DEMUX_AUDIO_STAMP_SYNC_1_3 (STB_CBUS_BASE + 0xe4) 718 #define P_DEMUX_AUDIO_STAMP_SYNC_1_3 \ 719 CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_1_3) 720 #define DEMUX_SECTION_RESET (STB_CBUS_BASE + 0x45) 721 #define P_DEMUX_SECTION_RESET CBUS_REG_ADDR(DEMUX_SECTION_RESET) 722 #define DEMUX_SECTION_RESET_2 (STB_CBUS_BASE + 0x95) 723 #define P_DEMUX_SECTION_RESET_2 \ 724 CBUS_REG_ADDR(DEMUX_SECTION_RESET_2) 725 #define DEMUX_SECTION_RESET_3 (STB_CBUS_BASE + 0xe5) 726 #define P_DEMUX_SECTION_RESET_3 \ 727 CBUS_REG_ADDR(DEMUX_SECTION_RESET_3) 728 /*no use end*/ 729 730 /*from c_stb_define.h*/ 731 #define COMM_DESC_2_CTL (STB_CBUS_BASE + 0xff) /*0x16ff*/ 732 733 #define STB_OM_CTL \ 734 (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x22) /* 0x1622*/ 735 #define STB_OM_CTL_2 \ 736 (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x22) /* 0x1672*/ 737 #define STB_OM_CTL_3 \ 738 (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x22) /* 0x16c2*/ 739 740 #define DEMUX_INPUT_TIMEOUT_C \ 741 (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x46) /* 0x1646*/ 742 #define DEMUX_INPUT_TIMEOUT_C_2 \ 743 (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x46) /* 0x1696*/ 744 #define DEMUX_INPUT_TIMEOUT_C_3 \ 745 (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x46) /* 0x16e6*/ 746 /* bit[31] - no_match_reset_timeout_disable*/ 747 /* bit[30:0] input_time_out_int_cnt (0 -- means disable) Wr-setting, Rd-count*/ 748 #define DEMUX_INPUT_TIMEOUT \ 749 (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x47) /* 0x1647*/ 750 #define DEMUX_INPUT_TIMEOUT_2 \ 751 (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x47) /* 0x1697*/ 752 #define DEMUX_INPUT_TIMEOUT_3 \ 753 (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x47) /* 0x16e7*/ 754 755 /* bit[31:0] - channel_packet_count_disable*/ 756 #define DEMUX_PACKET_COUNT_C \ 757 (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x48) /* 0x1648*/ 758 #define DEMUX_PACKET_COUNT_C_2 \ 759 (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x48) /* 0x1698*/ 760 #define DEMUX_PACKET_COUNT_C_3 \ 761 (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x48) /* 0x16e8*/ 762 /* bit[31] - no_match_packet_count_disable*/ 763 /* bit[30:0] input_packet_count*/ 764 #define DEMUX_PACKET_COUNT \ 765 (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x49) /* 0x1649*/ 766 #define DEMUX_PACKET_COUNT_2 \ 767 (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x49) /* 0x1699*/ 768 #define DEMUX_PACKET_COUNT_3 \ 769 (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x49) /* 0x16e9*/ 770 771 /* bit[31:0] channel_record_enable*/ 772 #define DEMUX_CHAN_RECORD_EN \ 773 (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4a) /* 0x164a*/ 774 #define DEMUX_CHAN_RECORD_EN_2 \ 775 (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4a) /* 0x169a*/ 776 #define DEMUX_CHAN_RECORD_EN_3 \ 777 (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4a) /* 0x16ea*/ 778 779 /* bit[31:0] channel_process_enable*/ 780 #define DEMUX_CHAN_PROCESS_EN \ 781 (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4b) /* 0x164b*/ 782 #define DEMUX_CHAN_PROCESS_EN_2 \ 783 (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4b) /* 0x169b*/ 784 #define DEMUX_CHAN_PROCESS_EN_3 \ 785 (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4b) /* 0x16eb*/ 786 787 /* bit[31:24] small_sec_size ((n+1) * 256 Bytes)*/ 788 /* bit[23:16] small_sec_rd_ptr */ 789 /* bit[15:8] small_sec_wr_ptr */ 790 /* bit[7:2] reserved*/ 791 /* bit[1] small_sec_wr_ptr_wr_enable*/ 792 /* bit[0] small_section_enable*/ 793 #define DEMUX_SMALL_SEC_CTL \ 794 (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4c) /* 0x164c*/ 795 #define DEMUX_SMALL_SEC_CTL_2 \ 796 (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4c) /* 0x169c*/ 797 #define DEMUX_SMALL_SEC_CTL_3 \ 798 (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4c) /* 0x16ec*/ 799 /* bit[31:0] small_sec_start_addr*/ 800 #define DEMUX_SMALL_SEC_ADDR \ 801 (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4d) /* 0x164d*/ 802 #define DEMUX_SMALL_SEC_ADDR_2 \ 803 (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4d) /* 0x169d*/ 804 #define DEMUX_SMALL_SEC_ADDR_3 \ 805 (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4d) /* 0x16ed*/ 806 807 #endif 808