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1 /*
2  * Allwinner SoCs g2d driver.
3  *
4  * Copyright (C) 2016 Allwinner.
5  *
6  * This file is licensed under the terms of the GNU General Public
7  * License version 2.  This program is licensed "as is" without any
8  * warranty of any kind, whether express or implied.
9  */
10 
11 
12 #ifndef __G2D_MIXER_REGS_H
13 #define __G2D_MIXER_REGS_H
14 
15 /* module base addr */
16 /*
17  *#define G2D_TOP        (0x00000 + G2D_BASE)
18  *#define G2D_MIXER      (0x00100 + G2D_BASE)
19  *#define G2D_BLD        (0x00400 + G2D_BASE)
20  *#define G2D_V0         (0x00800 + G2D_BASE)
21  *#define G2D_UI0        (0x01000 + G2D_BASE)
22  *#define G2D_UI1        (0x01800 + G2D_BASE)
23  *#define G2D_UI2        (0x02000 + G2D_BASE)
24  *#define G2D_WB         (0x03000 + G2D_BASE)
25  *#define G2D_VSU        (0x08000 + G2D_BASE)
26  *#define G2D_ROT        (0x28000 + G2D_BASE)
27  *#define G2D_GSU        (0x30000 + G2D_BASE)
28  */
29 #define G2D_TOP        (0x00000)
30 #define G2D_MIXER      (0x00100)
31 #define G2D_BLD        (0x00400)
32 #define G2D_V0         (0x00800)
33 #define G2D_UI0        (0x01000)
34 #define G2D_UI1        (0x01800)
35 #define G2D_UI2        (0x02000)
36 #define G2D_WB         (0x03000)
37 #define G2D_VSU        (0x08000)
38 #define G2D_ROT        (0x28000)
39 #define G2D_GSU        (0x30000)
40 
41 /* register offset */
42 /* TOP register */
43 #define G2D_SCLK_GATE  (0x00 + G2D_TOP)
44 #define G2D_HCLK_GATE  (0x04 + G2D_TOP)
45 #define G2D_AHB_RESET  (0x08 + G2D_TOP)
46 #define G2D_SCLK_DIV   (0x0C + G2D_TOP)
47 
48 /* MIXER GLB register */
49 #define G2D_MIXER_CTL  (0x00 + G2D_MIXER)
50 #define G2D_MIXER_INT  (0x04 + G2D_MIXER)
51 #define G2D_MIXER_CLK  (0x08 + G2D_MIXER)
52 
53 /* LAY VIDEO register */
54 #define V0_ATTCTL      (0x00 + G2D_V0)
55 #define V0_MBSIZE      (0x04 + G2D_V0)
56 #define V0_COOR        (0x08 + G2D_V0)
57 #define V0_PITCH0      (0x0C + G2D_V0)
58 #define V0_PITCH1      (0x10 + G2D_V0)
59 #define V0_PITCH2      (0x14 + G2D_V0)
60 #define V0_LADD0       (0x18 + G2D_V0)
61 #define V0_LADD1       (0x1C + G2D_V0)
62 #define V0_LADD2       (0x20 + G2D_V0)
63 #define V0_FILLC       (0x24 + G2D_V0)
64 #define V0_HADD        (0x28 + G2D_V0)
65 #define V0_SIZE        (0x2C + G2D_V0)
66 #define V0_HDS_CTL0    (0x30 + G2D_V0)
67 #define V0_HDS_CTL1    (0x34 + G2D_V0)
68 #define V0_VDS_CTL0    (0x38 + G2D_V0)
69 #define V0_VDS_CTL1    (0x3C + G2D_V0)
70 
71 /* LAY0 UI register */
72 #define UI0_ATTR       (0x00 + G2D_UI0)
73 #define UI0_MBSIZE     (0x04 + G2D_UI0)
74 #define UI0_COOR       (0x08 + G2D_UI0)
75 #define UI0_PITCH      (0x0C + G2D_UI0)
76 #define UI0_LADD       (0x10 + G2D_UI0)
77 #define UI0_FILLC      (0x14 + G2D_UI0)
78 #define UI0_HADD       (0x18 + G2D_UI0)
79 #define UI0_SIZE       (0x1C + G2D_UI0)
80 
81 /* LAY1 UI register */
82 #define UI1_ATTR       (0x00 + G2D_UI1)
83 #define UI1_MBSIZE     (0x04 + G2D_UI1)
84 #define UI1_COOR       (0x08 + G2D_UI1)
85 #define UI1_PITCH      (0x0C + G2D_UI1)
86 #define UI1_LADD       (0x10 + G2D_UI1)
87 #define UI1_FILLC      (0x14 + G2D_UI1)
88 #define UI1_HADD       (0x18 + G2D_UI1)
89 #define UI1_SIZE       (0x1C + G2D_UI1)
90 
91 /* LAY2 UI register */
92 #define UI2_ATTR       (0x00 + G2D_UI2)
93 #define UI2_MBSIZE     (0x04 + G2D_UI2)
94 #define UI2_COOR       (0x08 + G2D_UI2)
95 #define UI2_PITCH      (0x0C + G2D_UI2)
96 #define UI2_LADD       (0x10 + G2D_UI2)
97 #define UI2_FILLC      (0x14 + G2D_UI2)
98 #define UI2_HADD       (0x18 + G2D_UI2)
99 #define UI2_SIZE       (0x1C + G2D_UI2)
100 
101 /* VSU register */
102 #define VS_CTRL           (0x000 + G2D_VSU)
103 #define VS_OUT_SIZE       (0x040 + G2D_VSU)
104 #define VS_GLB_ALPHA      (0x044 + G2D_VSU)
105 #define VS_Y_SIZE         (0x080 + G2D_VSU)
106 #define VS_Y_HSTEP        (0x088 + G2D_VSU)
107 #define VS_Y_VSTEP        (0x08C + G2D_VSU)
108 #define VS_Y_HPHASE       (0x090 + G2D_VSU)
109 #define VS_Y_VPHASE0      (0x098 + G2D_VSU)
110 #define VS_C_SIZE         (0x0C0 + G2D_VSU)
111 #define VS_C_HSTEP        (0x0C8 + G2D_VSU)
112 #define VS_C_VSTEP        (0x0CC + G2D_VSU)
113 #define VS_C_HPHASE       (0x0D0 + G2D_VSU)
114 #define VS_C_VPHASE0      (0x0D8 + G2D_VSU)
115 #define VS_Y_HCOEF0       (0x200 + G2D_VSU)
116 #define VS_Y_VCOEF0       (0x300 + G2D_VSU)
117 #define VS_C_HCOEF0       (0x400 + G2D_VSU)
118 
119 /* BLD register */
120 #define BLD_EN_CTL         (0x000 + G2D_BLD)
121 #define BLD_FILLC0         (0x010 + G2D_BLD)
122 #define BLD_FILLC1         (0x014 + G2D_BLD)
123 #define BLD_CH_ISIZE0      (0x020 + G2D_BLD)
124 #define BLD_CH_ISIZE1      (0x024 + G2D_BLD)
125 #define BLD_CH_OFFSET0     (0x030 + G2D_BLD)
126 #define BLD_CH_OFFSET1     (0x034 + G2D_BLD)
127 #define BLD_PREMUL_CTL     (0x040 + G2D_BLD)
128 #define BLD_BK_COLOR       (0x044 + G2D_BLD)
129 #define BLD_SIZE           (0x048 + G2D_BLD)
130 #define BLD_CTL            (0x04C + G2D_BLD)
131 #define BLD_KEY_CTL        (0x050 + G2D_BLD)
132 #define BLD_KEY_CON        (0x054 + G2D_BLD)
133 #define BLD_KEY_MAX        (0x058 + G2D_BLD)
134 #define BLD_KEY_MIN        (0x05C + G2D_BLD)
135 #define BLD_OUT_COLOR      (0x060 + G2D_BLD)
136 #define ROP_CTL            (0x080 + G2D_BLD)
137 #define ROP_INDEX0         (0x084 + G2D_BLD)
138 #define ROP_INDEX1         (0x088 + G2D_BLD)
139 #define BLD_CSC_CTL        (0x100 + G2D_BLD)
140 #define BLD_CSC0_COEF00    (0x110 + G2D_BLD)
141 #define BLD_CSC0_COEF01    (0x114 + G2D_BLD)
142 #define BLD_CSC0_COEF02    (0x118 + G2D_BLD)
143 #define BLD_CSC0_CONST0    (0x11C + G2D_BLD)
144 #define BLD_CSC0_COEF10    (0x120 + G2D_BLD)
145 #define BLD_CSC0_COEF11    (0x124 + G2D_BLD)
146 #define BLD_CSC0_COEF12    (0x128 + G2D_BLD)
147 #define BLD_CSC0_CONST1    (0x12C + G2D_BLD)
148 #define BLD_CSC0_COEF20    (0x130 + G2D_BLD)
149 #define BLD_CSC0_COEF21    (0x134 + G2D_BLD)
150 #define BLD_CSC0_COEF22    (0x138 + G2D_BLD)
151 #define BLD_CSC0_CONST2    (0x13C + G2D_BLD)
152 #define BLD_CSC1_COEF00    (0x140 + G2D_BLD)
153 #define BLD_CSC1_COEF01    (0x144 + G2D_BLD)
154 #define BLD_CSC1_COEF02    (0x148 + G2D_BLD)
155 #define BLD_CSC1_CONST0    (0x14C + G2D_BLD)
156 #define BLD_CSC1_COEF10    (0x150 + G2D_BLD)
157 #define BLD_CSC1_COEF11    (0x154 + G2D_BLD)
158 #define BLD_CSC1_COEF12    (0x158 + G2D_BLD)
159 #define BLD_CSC1_CONST1    (0x15C + G2D_BLD)
160 #define BLD_CSC1_COEF20    (0x160 + G2D_BLD)
161 #define BLD_CSC1_COEF21    (0x164 + G2D_BLD)
162 #define BLD_CSC1_COEF22    (0x168 + G2D_BLD)
163 #define BLD_CSC1_CONST2    (0x16C + G2D_BLD)
164 #define BLD_CSC2_COEF00    (0x170 + G2D_BLD)
165 #define BLD_CSC2_COEF01    (0x174 + G2D_BLD)
166 #define BLD_CSC2_COEF02    (0x178 + G2D_BLD)
167 #define BLD_CSC2_CONST0    (0x17C + G2D_BLD)
168 #define BLD_CSC2_COEF10    (0x180 + G2D_BLD)
169 #define BLD_CSC2_COEF11    (0x184 + G2D_BLD)
170 #define BLD_CSC2_COEF12    (0x188 + G2D_BLD)
171 #define BLD_CSC2_CONST1    (0x18C + G2D_BLD)
172 #define BLD_CSC2_COEF20    (0x190 + G2D_BLD)
173 #define BLD_CSC2_COEF21    (0x194 + G2D_BLD)
174 #define BLD_CSC2_COEF22    (0x198 + G2D_BLD)
175 #define BLD_CSC2_CONST2    (0x19C + G2D_BLD)
176 
177 /* WB register */
178 #define WB_ATT             (0x00 + G2D_WB)
179 #define WB_SIZE            (0x04 + G2D_WB)
180 #define WB_PITCH0          (0x08 + G2D_WB)
181 #define WB_PITCH1          (0x0C + G2D_WB)
182 #define WB_PITCH2          (0x10 + G2D_WB)
183 #define WB_LADD0           (0x14 + G2D_WB)
184 #define WB_HADD0           (0x18 + G2D_WB)
185 #define WB_LADD1           (0x1C + G2D_WB)
186 #define WB_HADD1           (0x20 + G2D_WB)
187 #define WB_LADD2           (0x24 + G2D_WB)
188 #define WB_HADD2           (0x28 + G2D_WB)
189 
190 /* Rotate register */
191 #define ROT_CTL            (0x00 + G2D_ROT)
192 #define ROT_INT            (0x04 + G2D_ROT)
193 #define ROT_TIMEOUT        (0x08 + G2D_ROT)
194 #define ROT_IFMT           (0x20 + G2D_ROT)
195 #define ROT_ISIZE          (0x24 + G2D_ROT)
196 #define ROT_IPITCH0        (0x30 + G2D_ROT)
197 #define ROT_IPITCH1        (0x34 + G2D_ROT)
198 #define ROT_IPITCH2        (0x38 + G2D_ROT)
199 #define ROT_ILADD0         (0x40 + G2D_ROT)
200 #define ROT_IHADD0         (0x44 + G2D_ROT)
201 #define ROT_ILADD1         (0x48 + G2D_ROT)
202 #define ROT_IHADD1         (0x4C + G2D_ROT)
203 #define ROT_ILADD2         (0x50 + G2D_ROT)
204 #define ROT_IHADD2         (0x54 + G2D_ROT)
205 #define ROT_OSIZE          (0x84 + G2D_ROT)
206 #define ROT_OPITCH0        (0x90 + G2D_ROT)
207 #define ROT_OPITCH1        (0x94 + G2D_ROT)
208 #define ROT_OPITCH2        (0x98 + G2D_ROT)
209 #define ROT_OLADD0         (0xA0 + G2D_ROT)
210 #define ROT_OHADD0         (0xA4 + G2D_ROT)
211 #define ROT_OLADD1         (0xA8 + G2D_ROT)
212 #define ROT_OHADD1         (0xAC + G2D_ROT)
213 #define ROT_OLADD2         (0xB0 + G2D_ROT)
214 #define ROT_OHADD2         (0xB4 + G2D_ROT)
215 
216 /* #define write_wvalue(addr, data) m_usbwordwrite32(  addr, data ) */
217 /* #define write_wvalue(addr, v) put_wvalue(addr, v) */
218 /* #define read_wvalue(addr) get_wvalue(addr) */
219 
220 /* byte input */
221 #define get_bvalue(n)	(*((volatile __u8 *)(n)))
222 /* byte output */
223 #define put_bvalue(n, c)	(*((volatile __u8 *)(n)) = (c))
224 /* half word input */
225 #define get_hvalue(n)	(*((volatile __u16 *)(n)))
226 /* half word output */
227 #define put_hvalue(n, c)	(*((volatile __u16 *)(n)) = (c))
228 /* word input */
229 #define get_wvalue(n)	(*((volatile __u32 *)(n)))
230 /* word output */
231 #define put_wvalue(n, c)	(*((volatile __u32 *)(n)) = (c))
232 
233 #endif /*
234  */
235