1 /*
2 * drivers/usb/sunxi_usb/usbc/usbc_dev.c
3 * (C) Copyright 2010-2015
4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
5 * daniel, 2009.09.01
6 *
7 * usb register ops.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 */
15
16 #include "usbc_i.h"
17
18 /**
19 * select the usb transfer type, eg control/iso/interrupt/bulk transfer
20 */
21
__USBC_Dev_TsType_default(void __iomem * usbc_base_addr)22 static void __USBC_Dev_TsType_default(void __iomem *usbc_base_addr)
23 {
24 /* disable all transfer type */
25 USBC_REG_clear_bit_b(USBC_BP_POWER_D_ISO_UPDATE_EN,
26 USBC_REG_PCTL(usbc_base_addr));
27 }
28
__USBC_Dev_TsType_Ctrl(void __iomem * usbc_base_addr)29 static void __USBC_Dev_TsType_Ctrl(void __iomem *usbc_base_addr)
30 {
31 /* --<1>--disable other transfer type */
32 USBC_REG_clear_bit_b(USBC_BP_POWER_D_ISO_UPDATE_EN,
33 USBC_REG_PCTL(usbc_base_addr));
34
35 /* --<2>--select Ctrl type */
36 /* do not need config */
37 }
38
__USBC_Dev_TsType_Iso(void __iomem * usbc_base_addr)39 static void __USBC_Dev_TsType_Iso(void __iomem *usbc_base_addr)
40 {
41 /* --<1>--disable other transfer type */
42 /* do not need config */
43
44 /* --<2>--select Ctrl type */
45 USBC_REG_set_bit_b(USBC_BP_POWER_D_ISO_UPDATE_EN,
46 USBC_REG_PCTL(usbc_base_addr));
47 }
48
__USBC_Dev_TsType_Int(void __iomem * usbc_base_addr)49 static void __USBC_Dev_TsType_Int(void __iomem *usbc_base_addr)
50 {
51 /* --<1>--disable other transfer type */
52 USBC_REG_clear_bit_b(USBC_BP_POWER_D_ISO_UPDATE_EN,
53 USBC_REG_PCTL(usbc_base_addr));
54
55 /* --<2>--select Ctrl type */
56 /* donot need config */
57 }
58
__USBC_Dev_TsType_Bulk(void __iomem * usbc_base_addr)59 static void __USBC_Dev_TsType_Bulk(void __iomem *usbc_base_addr)
60 {
61 /* --<1>--disable other transfer type */
62 USBC_REG_clear_bit_b(USBC_BP_POWER_D_ISO_UPDATE_EN,
63 USBC_REG_PCTL(usbc_base_addr));
64
65 /* --<2>--select Ctrl type */
66 /* donot need config */
67 }
68
69 /**
70 * select the usb speed type, eg high/full/low
71 */
72
__USBC_Dev_TsMode_default(void __iomem * usbc_base_addr)73 static void __USBC_Dev_TsMode_default(void __iomem *usbc_base_addr)
74 {
75 USBC_REG_clear_bit_b(USBC_BP_POWER_D_HIGH_SPEED_EN,
76 USBC_REG_PCTL(usbc_base_addr));
77 }
78
__USBC_Dev_TsMode_Hs(void __iomem * usbc_base_addr)79 static void __USBC_Dev_TsMode_Hs(void __iomem *usbc_base_addr)
80 {
81 USBC_REG_set_bit_b(USBC_BP_POWER_D_HIGH_SPEED_EN,
82 USBC_REG_PCTL(usbc_base_addr));
83 }
84
__USBC_Dev_TsMode_Fs(void __iomem * usbc_base_addr)85 static void __USBC_Dev_TsMode_Fs(void __iomem *usbc_base_addr)
86 {
87 USBC_REG_clear_bit_b(USBC_BP_POWER_D_HIGH_SPEED_EN,
88 USBC_REG_PCTL(usbc_base_addr));
89 }
90
__USBC_Dev_TsMode_Ls(void __iomem * usbc_base_addr)91 static void __USBC_Dev_TsMode_Ls(void __iomem *usbc_base_addr)
92 {
93 /* hw not support ls, so default select fs */
94 __USBC_Dev_TsMode_Fs(usbc_base_addr);
95 }
96
__USBC_Dev_ep0_ConfigEp0_Default(void __iomem * usbc_base_addr)97 static void __USBC_Dev_ep0_ConfigEp0_Default(void __iomem *usbc_base_addr)
98 {
99 USBC_Writew(1<<USBC_BP_CSR0_D_FLUSH_FIFO,
100 USBC_REG_CSR0(usbc_base_addr));
101 }
102
__USBC_Dev_ep0_ConfigEp0(void __iomem * usbc_base_addr)103 static void __USBC_Dev_ep0_ConfigEp0(void __iomem *usbc_base_addr)
104 {
105 USBC_Writew(1<<USBC_BP_CSR0_D_FLUSH_FIFO,
106 USBC_REG_CSR0(usbc_base_addr));
107 }
108
__USBC_Dev_ep0_IsReadDataReady(void __iomem * usbc_base_addr)109 static __u32 __USBC_Dev_ep0_IsReadDataReady(void __iomem *usbc_base_addr)
110 {
111 return USBC_REG_test_bit_w(USBC_BP_CSR0_D_RX_PKT_READY,
112 USBC_REG_CSR0(usbc_base_addr));
113 }
114
__USBC_Dev_ep0_IsWriteDataReady(void __iomem * usbc_base_addr)115 static __u32 __USBC_Dev_ep0_IsWriteDataReady(void __iomem *usbc_base_addr)
116 {
117 return USBC_REG_test_bit_w(USBC_BP_CSR0_D_TX_PKT_READY,
118 USBC_REG_CSR0(usbc_base_addr));
119 }
120
__USBC_Dev_ep0_ReadDataHalf(void __iomem * usbc_base_addr)121 static void __USBC_Dev_ep0_ReadDataHalf(void __iomem *usbc_base_addr)
122 {
123 USBC_Writew(1<<USBC_BP_CSR0_D_SERVICED_RX_PKT_READY,
124 USBC_REG_CSR0(usbc_base_addr));
125 }
126
__USBC_Dev_ep0_ReadDataComplete(void __iomem * usbc_base_addr)127 static void __USBC_Dev_ep0_ReadDataComplete(void __iomem *usbc_base_addr)
128 {
129 USBC_Writew((1<<USBC_BP_CSR0_D_SERVICED_RX_PKT_READY)
130 | (1<<USBC_BP_CSR0_D_DATA_END),
131 USBC_REG_CSR0(usbc_base_addr));
132 }
133
__USBC_Dev_ep0_WriteDataHalf(void __iomem * usbc_base_addr)134 static void __USBC_Dev_ep0_WriteDataHalf(void __iomem *usbc_base_addr)
135 {
136 USBC_Writew(1<<USBC_BP_CSR0_D_TX_PKT_READY,
137 USBC_REG_CSR0(usbc_base_addr));
138 }
139
__USBC_Dev_ep0_WriteDataComplete(void __iomem * usbc_base_addr)140 static void __USBC_Dev_ep0_WriteDataComplete(void __iomem *usbc_base_addr)
141 {
142 USBC_Writew((1<<USBC_BP_CSR0_D_TX_PKT_READY)
143 | (1<<USBC_BP_CSR0_D_DATA_END),
144 USBC_REG_CSR0(usbc_base_addr));
145 }
146
__USBC_Dev_ep0_IsEpStall(void __iomem * usbc_base_addr)147 static __u32 __USBC_Dev_ep0_IsEpStall(void __iomem *usbc_base_addr)
148 {
149 return USBC_REG_test_bit_w(USBC_BP_CSR0_D_SENT_STALL,
150 USBC_REG_CSR0(usbc_base_addr));
151 }
152
__USBC_Dev_ep0_SendStall(void __iomem * usbc_base_addr)153 static void __USBC_Dev_ep0_SendStall(void __iomem *usbc_base_addr)
154 {
155 USBC_REG_set_bit_w(USBC_BP_CSR0_D_SEND_STALL,
156 USBC_REG_CSR0(usbc_base_addr));
157 }
158
__USBC_Dev_ep0_ClearStall(void __iomem * usbc_base_addr)159 static void __USBC_Dev_ep0_ClearStall(void __iomem *usbc_base_addr)
160 {
161 USBC_REG_clear_bit_w(USBC_BP_CSR0_D_SEND_STALL,
162 USBC_REG_CSR0(usbc_base_addr));
163 USBC_REG_clear_bit_w(USBC_BP_CSR0_D_SENT_STALL,
164 USBC_REG_CSR0(usbc_base_addr));
165 }
166
__USBC_Dev_ep0_IsSetupEnd(void __iomem * usbc_base_addr)167 static __u32 __USBC_Dev_ep0_IsSetupEnd(void __iomem *usbc_base_addr)
168 {
169 return USBC_REG_test_bit_w(USBC_BP_CSR0_D_SETUP_END,
170 USBC_REG_CSR0(usbc_base_addr));
171 }
172
__USBC_Dev_ep0_ClearSetupEnd(void __iomem * usbc_base_addr)173 static void __USBC_Dev_ep0_ClearSetupEnd(void __iomem *usbc_base_addr)
174 {
175 USBC_REG_set_bit_w(USBC_BP_CSR0_D_SERVICED_SETUP_END,
176 USBC_REG_CSR0(usbc_base_addr));
177 }
178
__USBC_Dev_Tx_EnableIsoEp(void __iomem * usbc_base_addr)179 static void __USBC_Dev_Tx_EnableIsoEp(void __iomem *usbc_base_addr)
180 {
181 USBC_REG_set_bit_w(USBC_BP_TXCSR_D_ISO,
182 USBC_REG_TXCSR(usbc_base_addr));
183 }
184
__USBC_Dev_Tx_EnableIntEp(void __iomem * usbc_base_addr)185 static void __USBC_Dev_Tx_EnableIntEp(void __iomem *usbc_base_addr)
186 {
187 USBC_REG_clear_bit_w(USBC_BP_TXCSR_D_ISO,
188 USBC_REG_TXCSR(usbc_base_addr));
189 }
190
__USBC_Dev_Tx_EnableBulkEp(void __iomem * usbc_base_addr)191 static void __USBC_Dev_Tx_EnableBulkEp(void __iomem *usbc_base_addr)
192 {
193 USBC_REG_clear_bit_w(USBC_BP_TXCSR_D_ISO,
194 USBC_REG_TXCSR(usbc_base_addr));
195 }
196
__USBC_Dev_Tx_ConfigEp_Default(void __iomem * usbc_base_addr)197 static void __USBC_Dev_Tx_ConfigEp_Default(void __iomem *usbc_base_addr)
198 {
199 /* --<1>--clear tx csr */
200 USBC_Writew(0x00, USBC_REG_TXCSR(usbc_base_addr));
201
202 /* --<2>--clear tx ep max packet */
203 USBC_Writew(0x00, USBC_REG_TXMAXP(usbc_base_addr));
204
205 /* --<3>--config ep transfer type */
206 }
207
__USBC_Dev_Tx_ConfigEp(void __iomem * usbc_base_addr,__u32 ts_type,__u32 is_double_fifo,__u32 ep_MaxPkt)208 static void __USBC_Dev_Tx_ConfigEp(void __iomem *usbc_base_addr,
209 __u32 ts_type, __u32 is_double_fifo, __u32 ep_MaxPkt)
210 {
211 __u16 reg_val = 0;
212 __u16 temp = 0;
213
214 /* --<1>--config tx csr */
215 reg_val = (1 << USBC_BP_TXCSR_D_MODE);
216 reg_val |= (1 << USBC_BP_TXCSR_D_CLEAR_DATA_TOGGLE);
217 reg_val |= (1 << USBC_BP_TXCSR_D_FLUSH_FIFO);
218 USBC_Writew(reg_val, USBC_REG_TXCSR(usbc_base_addr));
219
220 if (is_double_fifo)
221 USBC_Writew(reg_val, USBC_REG_TXCSR(usbc_base_addr));
222
223 /* --<2>--config tx ep max packet */
224 reg_val = USBC_Readw(USBC_REG_TXMAXP(usbc_base_addr));
225 temp = ep_MaxPkt & ((1 << USBC_BP_TXMAXP_PACKET_COUNT) - 1);
226 reg_val |= temp;
227 USBC_Writew(reg_val, USBC_REG_TXMAXP(usbc_base_addr));
228
229 /* --<3>--config ep transfer type */
230 switch (ts_type) {
231 case USBC_TS_TYPE_ISO:
232 __USBC_Dev_Tx_EnableIsoEp(usbc_base_addr);
233 break;
234
235 case USBC_TS_TYPE_INT:
236 __USBC_Dev_Tx_EnableIntEp(usbc_base_addr);
237 break;
238
239 case USBC_TS_TYPE_BULK:
240 __USBC_Dev_Tx_EnableBulkEp(usbc_base_addr);
241 break;
242
243 default:
244 __USBC_Dev_Tx_EnableBulkEp(usbc_base_addr);
245 }
246 }
247
__USBC_Dev_Tx_ConfigEpDma(void __iomem * usbc_base_addr)248 static void __USBC_Dev_Tx_ConfigEpDma(void __iomem *usbc_base_addr)
249 {
250 __u16 ep_csr = 0;
251
252 /* auto_set, tx_mode, dma_tx_en, mode1 */
253 ep_csr = USBC_Readb(USBC_REG_TXCSR(usbc_base_addr) + 1);
254 ep_csr |= (1 << USBC_BP_TXCSR_D_AUTOSET) >> 8;
255 ep_csr |= (1 << USBC_BP_TXCSR_D_MODE) >> 8;
256 ep_csr |= (1 << USBC_BP_TXCSR_D_DMA_REQ_EN) >> 8;
257 ep_csr |= (1 << USBC_BP_TXCSR_D_DMA_REQ_MODE) >> 8;
258 USBC_Writeb(ep_csr, (USBC_REG_TXCSR(usbc_base_addr) + 1));
259 }
260
__USBC_Dev_Tx_ClearEpDma(void __iomem * usbc_base_addr)261 static void __USBC_Dev_Tx_ClearEpDma(void __iomem *usbc_base_addr)
262 {
263 __u16 ep_csr = 0;
264
265 /* auto_set, dma_tx_en, mode1 */
266 ep_csr = USBC_Readb(USBC_REG_TXCSR(usbc_base_addr) + 1);
267 ep_csr &= ~((1 << USBC_BP_TXCSR_D_AUTOSET) >> 8);
268 ep_csr &= ~((1 << USBC_BP_TXCSR_D_DMA_REQ_EN) >> 8);
269 USBC_Writeb(ep_csr, (USBC_REG_TXCSR(usbc_base_addr) + 1));
270
271 /* DMA_REQ_EN and DMA_REQ_MODE cannot be cleared in the same cycle */
272 ep_csr = USBC_Readb(USBC_REG_TXCSR(usbc_base_addr) + 1);
273 ep_csr &= ~((1 << USBC_BP_TXCSR_D_DMA_REQ_MODE) >> 8);
274 USBC_Writeb(ep_csr, (USBC_REG_TXCSR(usbc_base_addr) + 1));
275 }
276
__USBC_Dev_Tx_IsWriteDataReady(void __iomem * usbc_base_addr)277 static __u32 __USBC_Dev_Tx_IsWriteDataReady(void __iomem *usbc_base_addr)
278 {
279 __u32 temp = 0;
280
281 temp = USBC_Readw(USBC_REG_TXCSR(usbc_base_addr));
282 temp &= (1 << USBC_BP_TXCSR_D_TX_READY);
283
284 return temp;
285 }
286
__USBC_Dev_Tx_IsWriteDataReady_FifoEmpty(void __iomem * usbc_base_addr)287 static __u32 __USBC_Dev_Tx_IsWriteDataReady_FifoEmpty(
288 void __iomem *usbc_base_addr)
289 {
290 __u32 temp = 0;
291
292 temp = USBC_Readw(USBC_REG_TXCSR(usbc_base_addr));
293 temp &= (1 << USBC_BP_TXCSR_D_TX_READY)
294 | (1 << USBC_BP_TXCSR_D_FIFO_NOT_EMPTY);
295
296 return temp;
297 }
298
299
__USBC_Dev_Tx_WriteDataHalf(void __iomem * usbc_base_addr)300 static void __USBC_Dev_Tx_WriteDataHalf(void __iomem *usbc_base_addr)
301 {
302 __u16 ep_csr = 0;
303
304 ep_csr = USBC_Readw(USBC_REG_TXCSR(usbc_base_addr));
305 ep_csr |= 1 << USBC_BP_TXCSR_D_TX_READY;
306 ep_csr &= ~(1 << USBC_BP_TXCSR_D_UNDER_RUN);
307 USBC_Writew(ep_csr, USBC_REG_TXCSR(usbc_base_addr));
308 }
309
__USBC_Dev_Tx_WriteDataComplete(void __iomem * usbc_base_addr)310 static void __USBC_Dev_Tx_WriteDataComplete(void __iomem *usbc_base_addr)
311 {
312 __u16 ep_csr = 0;
313
314 ep_csr = USBC_Readw(USBC_REG_TXCSR(usbc_base_addr));
315 ep_csr |= 1 << USBC_BP_TXCSR_D_TX_READY;
316 ep_csr &= ~(1 << USBC_BP_TXCSR_D_UNDER_RUN);
317 USBC_Writew(ep_csr, USBC_REG_TXCSR(usbc_base_addr));
318 }
319
__USBC_Dev_Tx_SendStall(void __iomem * usbc_base_addr)320 static void __USBC_Dev_Tx_SendStall(void __iomem *usbc_base_addr)
321 {
322 /* send stall, and fifo is flushed automatically */
323 USBC_REG_set_bit_w(USBC_BP_TXCSR_D_SEND_STALL,
324 USBC_REG_TXCSR(usbc_base_addr));
325 }
326
__USBC_Dev_Tx_IsEpStall(void __iomem * usbc_base_addr)327 static __u32 __USBC_Dev_Tx_IsEpStall(void __iomem *usbc_base_addr)
328 {
329 return USBC_REG_test_bit_w(USBC_BP_TXCSR_D_SENT_STALL,
330 USBC_REG_TXCSR(usbc_base_addr));
331 }
332
__USBC_Dev_Tx_ClearStall(void __iomem * usbc_base_addr)333 static void __USBC_Dev_Tx_ClearStall(void __iomem *usbc_base_addr)
334 {
335 __u32 reg_val;
336
337 reg_val = USBC_Readw(USBC_REG_TXCSR(usbc_base_addr));
338 reg_val &= ~((1 << USBC_BP_TXCSR_D_SENT_STALL)
339 |(1 << USBC_BP_TXCSR_D_SEND_STALL));
340 USBC_Writew(reg_val, USBC_REG_TXCSR(usbc_base_addr));
341
342 /* clear data toggle */
343 USBC_REG_set_bit_w(USBC_BP_TXCSR_D_CLEAR_DATA_TOGGLE, USBC_REG_TXCSR(usbc_base_addr));
344 }
345
__USBC_Dev_Rx_EnableIsoEp(void __iomem * usbc_base_addr)346 static void __USBC_Dev_Rx_EnableIsoEp(void __iomem *usbc_base_addr)
347 {
348 USBC_REG_set_bit_w(USBC_BP_RXCSR_D_ISO,
349 USBC_REG_RXCSR(usbc_base_addr));
350 }
351
__USBC_Dev_Rx_EnableIntEp(void __iomem * usbc_base_addr)352 static void __USBC_Dev_Rx_EnableIntEp(void __iomem *usbc_base_addr)
353 {
354 USBC_REG_clear_bit_w(USBC_BP_RXCSR_D_ISO,
355 USBC_REG_RXCSR(usbc_base_addr));
356 }
357
__USBC_Dev_Rx_EnableBulkEp(void __iomem * usbc_base_addr)358 static void __USBC_Dev_Rx_EnableBulkEp(void __iomem *usbc_base_addr)
359 {
360 USBC_REG_clear_bit_w(USBC_BP_RXCSR_D_ISO,
361 USBC_REG_RXCSR(usbc_base_addr));
362 }
363
__USBC_Dev_Rx_ConfigEp_Default(void __iomem * usbc_base_addr)364 static void __USBC_Dev_Rx_ConfigEp_Default(void __iomem *usbc_base_addr)
365 {
366 /* --<1>--clear tx csr */
367 USBC_Writew(0x00, USBC_REG_RXCSR(usbc_base_addr));
368
369 /* --<2>--clear tx ep max packet */
370 USBC_Writew(0x00, USBC_REG_RXMAXP(usbc_base_addr));
371
372 /* --<3>--config ep transfer type */
373 }
374
__USBC_Dev_Rx_ConfigEp(void __iomem * usbc_base_addr,__u32 ts_type,__u32 is_double_fifo,__u32 ep_MaxPkt)375 static void __USBC_Dev_Rx_ConfigEp(void __iomem *usbc_base_addr,
376 __u32 ts_type, __u32 is_double_fifo, __u32 ep_MaxPkt)
377 {
378 __u16 reg_val = 0;
379 __u16 temp = 0;
380
381 /* --<1>--config tx csr */
382 USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE)
383 | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO),
384 USBC_REG_RXCSR(usbc_base_addr));
385
386 if (is_double_fifo) {
387 USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE)
388 | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO),
389 USBC_REG_RXCSR(usbc_base_addr));
390 }
391
392 if (ts_type == USBC_TS_TYPE_INT)
393 USBC_Writew(1 << USBC_BP_RXCSR_D_DISABLE_NYET,
394 USBC_REG_RXCSR(usbc_base_addr));
395
396 /* --<2>--config tx ep max packet */
397 reg_val = USBC_Readw(USBC_REG_RXMAXP(usbc_base_addr));
398 temp = ep_MaxPkt & ((1 << USBC_BP_RXMAXP_PACKET_COUNT) - 1);
399 reg_val |= temp;
400 USBC_Writew(reg_val, USBC_REG_RXMAXP(usbc_base_addr));
401
402 /* --<3>--config ep transfer type */
403 switch (ts_type) {
404 case USBC_TS_TYPE_ISO:
405 __USBC_Dev_Rx_EnableIsoEp(usbc_base_addr);
406 break;
407
408 case USBC_TS_TYPE_INT:
409 __USBC_Dev_Rx_EnableIntEp(usbc_base_addr);
410 break;
411
412 case USBC_TS_TYPE_BULK:
413 __USBC_Dev_Rx_EnableBulkEp(usbc_base_addr);
414 break;
415
416 default:
417 __USBC_Dev_Rx_EnableBulkEp(usbc_base_addr);
418 }
419 }
420
__USBC_Dev_Rx_ConfigEpDma(void __iomem * usbc_base_addr)421 static void __USBC_Dev_Rx_ConfigEpDma(void __iomem *usbc_base_addr)
422 {
423 __u16 ep_csr = 0;
424
425 /* auto_clear, dma_rx_en, mode0 */
426 ep_csr = USBC_Readb(USBC_REG_RXCSR(usbc_base_addr) + 1);
427 ep_csr |= ((1 << USBC_BP_RXCSR_D_DMA_REQ_MODE) >> 8);
428 USBC_Writeb(ep_csr, (USBC_REG_RXCSR(usbc_base_addr) + 1));
429
430 ep_csr = USBC_Readb(USBC_REG_RXCSR(usbc_base_addr) + 1);
431 ep_csr |= ((1 << USBC_BP_RXCSR_D_AUTO_CLEAR) >> 8);
432 ep_csr |= ((1 << USBC_BP_RXCSR_D_DMA_REQ_EN) >> 8);
433 USBC_Writeb(ep_csr, (USBC_REG_RXCSR(usbc_base_addr) + 1));
434
435 ep_csr = USBC_Readb(USBC_REG_RXCSR(usbc_base_addr) + 1);
436 ep_csr &= ~((1 << USBC_BP_RXCSR_D_DMA_REQ_MODE) >> 8);
437 USBC_Writeb(ep_csr, (USBC_REG_RXCSR(usbc_base_addr) + 1));
438
439 ep_csr = USBC_Readb(USBC_REG_RXCSR(usbc_base_addr) + 1);
440 ep_csr |= ((1 << USBC_BP_RXCSR_D_DMA_REQ_MODE) >> 8);
441 USBC_Writeb(ep_csr, (USBC_REG_RXCSR(usbc_base_addr) + 1));
442 }
443
__USBC_Dev_Rx_ClearEpDma(void __iomem * usbc_base_addr)444 static void __USBC_Dev_Rx_ClearEpDma(void __iomem *usbc_base_addr)
445 {
446 __u16 ep_csr = 0;
447
448 /* auto_clear, dma_rx_en, mode0 */
449 ep_csr = USBC_Readb(USBC_REG_RXCSR(usbc_base_addr) + 1);
450
451 ep_csr &= ~((1 << USBC_BP_RXCSR_D_AUTO_CLEAR) >> 8);
452 ep_csr &= ~((1 << USBC_BP_RXCSR_D_DMA_REQ_MODE) >> 8);
453 ep_csr &= ~((1 << USBC_BP_RXCSR_D_DMA_REQ_EN) >> 8);
454 USBC_Writeb(ep_csr, (USBC_REG_RXCSR(usbc_base_addr) + 1));
455 }
456
__USBC_Dev_Rx_IsReadDataReady(void __iomem * usbc_base_addr)457 static __u32 __USBC_Dev_Rx_IsReadDataReady(void __iomem *usbc_base_addr)
458 {
459 return USBC_REG_test_bit_w(USBC_BP_RXCSR_D_RX_PKT_READY,
460 USBC_REG_RXCSR(usbc_base_addr));
461 }
462
__USBC_Dev_Rx_ReadDataHalf(void __iomem * usbc_base_addr)463 static void __USBC_Dev_Rx_ReadDataHalf(void __iomem *usbc_base_addr)
464 {
465 __u32 reg_val = 0;
466
467 /* overrun, dataerr is used in iso transfer */
468 reg_val = USBC_Readw(USBC_REG_RXCSR(usbc_base_addr));
469 reg_val &= ~(1 << USBC_BP_RXCSR_D_RX_PKT_READY);
470 reg_val &= ~(1 << USBC_BP_RXCSR_D_OVERRUN);
471 reg_val &= ~(1 << USBC_BP_RXCSR_D_DATA_ERROR);
472 USBC_Writew(reg_val, USBC_REG_RXCSR(usbc_base_addr));
473 }
474
__USBC_Dev_Rx_ReadDataComplete(void __iomem * usbc_base_addr)475 static void __USBC_Dev_Rx_ReadDataComplete(void __iomem *usbc_base_addr)
476 {
477 __u32 reg_val = 0;
478
479 /* overrun, dataerr is used in iso transfer */
480 reg_val = USBC_Readw(USBC_REG_RXCSR(usbc_base_addr));
481 reg_val &= ~(1 << USBC_BP_RXCSR_D_RX_PKT_READY);
482 reg_val &= ~(1 << USBC_BP_RXCSR_D_OVERRUN);
483 reg_val &= ~(1 << USBC_BP_RXCSR_D_DATA_ERROR);
484 USBC_Writew(reg_val, USBC_REG_RXCSR(usbc_base_addr));
485 }
486
__USBC_Dev_Rx_SendStall(void __iomem * usbc_base_addr)487 static void __USBC_Dev_Rx_SendStall(void __iomem *usbc_base_addr)
488 {
489 USBC_REG_set_bit_w(USBC_BP_RXCSR_D_SEND_STALL,
490 USBC_REG_RXCSR(usbc_base_addr));
491 }
492
__USBC_Dev_Rx_IsEpStall(void __iomem * usbc_base_addr)493 static __u32 __USBC_Dev_Rx_IsEpStall(void __iomem *usbc_base_addr)
494 {
495 return USBC_REG_test_bit_w(USBC_BP_RXCSR_D_SENT_STALL,
496 USBC_REG_RXCSR(usbc_base_addr));
497 }
498
__USBC_Dev_Rx_ClearStall(void __iomem * usbc_base_addr)499 static void __USBC_Dev_Rx_ClearStall(void __iomem *usbc_base_addr)
500 {
501 USBC_REG_clear_bit_w(USBC_BP_RXCSR_D_SEND_STALL,
502 USBC_REG_RXCSR(usbc_base_addr));
503 USBC_REG_clear_bit_w(USBC_BP_RXCSR_D_SENT_STALL,
504 USBC_REG_RXCSR(usbc_base_addr));
505
506 /* clear data toggle */
507 USBC_REG_set_bit_w(USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE, USBC_REG_RXCSR(usbc_base_addr));
508 }
509
__USBC_Dev_ClearDma_Trans(void __iomem * usbc_base_addr)510 static void __USBC_Dev_ClearDma_Trans(void __iomem *usbc_base_addr)
511 {
512 /**
513 * in SUN8IW5, SUN8IW6 and later ic, this bit is fix to 1, set when
514 * drv initialize;
515 * in SUN8IW5, SUN8IW6 former ic, we donot use inner dma, so this bit
516 * should be 0.
517 */
518 }
519
__USBC_Dev_ConfigDma_Trans(void __iomem * usbc_base_addr)520 static void __USBC_Dev_ConfigDma_Trans(void __iomem *usbc_base_addr)
521 {
522 /**
523 * in SUN8IW5 and later ic, this bit is fix to 1, set when drv
524 * initialize, so donot set here;
525 * in SUN8IW5 former ic(eg SUN8IW3), we donot use inner dma(use cpu
526 * or outer dma), this bit should be 0, so cannot set here.
527 */
528 }
529
530 /**
531 * clear the address allocated by host for device
532 * @hUSB: handle return by USBC_open_otg, include the key data which USBC need
533 */
USBC_Dev_SetAddress_default(__hdle hUSB)534 void USBC_Dev_SetAddress_default(__hdle hUSB)
535 {
536 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
537
538 if (usbc_otg == NULL)
539 return;
540
541 USBC_Writeb(0x00, USBC_REG_FADDR(usbc_otg->base_addr));
542 }
543 EXPORT_SYMBOL(USBC_Dev_SetAddress_default);
544
545 /**
546 * set the address
547 * @hUSB: handle return by USBC_open_otg, include the key data which USBC need
548 */
USBC_Dev_SetAddress(__hdle hUSB,__u8 address)549 void USBC_Dev_SetAddress(__hdle hUSB, __u8 address)
550 {
551 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
552
553 if (usbc_otg == NULL)
554 return;
555
556 USBC_Writeb(address, USBC_REG_FADDR(usbc_otg->base_addr));
557 }
558 EXPORT_SYMBOL(USBC_Dev_SetAddress);
559
USBC_Dev_QueryTransferMode(__hdle hUSB)560 __u32 USBC_Dev_QueryTransferMode(__hdle hUSB)
561 {
562 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
563
564 if (usbc_otg == NULL)
565 return USBC_TS_MODE_UNKNOWN;
566
567 if (USBC_REG_test_bit_b(USBC_BP_POWER_D_HIGH_SPEED_FLAG,
568 USBC_REG_PCTL(usbc_otg->base_addr)))
569 return USBC_TS_MODE_HS;
570 else
571 return USBC_TS_MODE_FS;
572 }
573 EXPORT_SYMBOL(USBC_Dev_QueryTransferMode);
574
575 /**
576 * config the device's transfer type and speed mode
577 * @hUSB: handle return by USBC_open_otg,
578 * include the key data which USBC need
579 * @ts_type: transfer type
580 * @speed_mode: speed mode
581 */
USBC_Dev_ConfigTransferMode(__hdle hUSB,__u8 ts_type,__u8 speed_mode)582 void USBC_Dev_ConfigTransferMode(__hdle hUSB, __u8 ts_type, __u8 speed_mode)
583 {
584 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
585
586 if (usbc_otg == NULL)
587 return;
588
589 /* --<1>--select the transfer type */
590 /* default bulk transfer */
591 switch (ts_type) {
592 case USBC_TS_TYPE_CTRL:
593 __USBC_Dev_TsType_Ctrl(usbc_otg->base_addr);
594 break;
595
596 case USBC_TS_TYPE_ISO:
597 __USBC_Dev_TsType_Iso(usbc_otg->base_addr);
598 break;
599
600 case USBC_TS_TYPE_INT:
601 __USBC_Dev_TsType_Int(usbc_otg->base_addr);
602 break;
603
604 case USBC_TS_TYPE_BULK:
605 __USBC_Dev_TsType_Bulk(usbc_otg->base_addr);
606 break;
607
608 default:
609 __USBC_Dev_TsType_default(usbc_otg->base_addr);
610 }
611
612 /* --<2>--select the transfer speed */
613 switch (speed_mode) {
614 case USBC_TS_MODE_HS:
615 __USBC_Dev_TsMode_Hs(usbc_otg->base_addr);
616 break;
617
618 case USBC_TS_MODE_FS:
619 __USBC_Dev_TsMode_Fs(usbc_otg->base_addr);
620 break;
621
622 case USBC_TS_MODE_LS:
623 __USBC_Dev_TsMode_Ls(usbc_otg->base_addr);
624 break;
625
626 default:
627 __USBC_Dev_TsMode_default(usbc_otg->base_addr);
628 }
629 }
630 EXPORT_SYMBOL(USBC_Dev_ConfigTransferMode);
631
632 /**
633 * the switch to communicate with PC
634 * @hUSB: handle return by USBC_open_otg,
635 * include the key data which USBC need
636 * @is_on: 1 - open the switch, 0 - close the switch
637 *
638 */
USBC_Dev_ConectSwitch(__hdle hUSB,__u32 is_on)639 void USBC_Dev_ConectSwitch(__hdle hUSB, __u32 is_on)
640 {
641 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
642
643 if (usbc_otg == NULL)
644 return;
645
646 if (is_on == USBC_DEVICE_SWITCH_ON)
647 USBC_REG_set_bit_b(USBC_BP_POWER_D_SOFT_CONNECT,
648 USBC_REG_PCTL(usbc_otg->base_addr));
649 else
650 USBC_REG_clear_bit_b(USBC_BP_POWER_D_SOFT_CONNECT,
651 USBC_REG_PCTL(usbc_otg->base_addr));
652 }
653 EXPORT_SYMBOL(USBC_Dev_ConectSwitch);
654
655 /**
656 * query current device's status, eg reset, resume, suspend, etc.
657 * @hUSB: handle return by USBC_open_otg,
658 * include the key data which USBC need
659 *
660 */
USBC_Dev_QueryPowerStatus(__hdle hUSB)661 __u32 USBC_Dev_QueryPowerStatus(__hdle hUSB)
662 {
663 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
664
665 if (usbc_otg == NULL)
666 return 0;
667
668 return (USBC_Readb(USBC_REG_PCTL(usbc_otg->base_addr)) & 0x0f);
669 }
670 EXPORT_SYMBOL(USBC_Dev_QueryPowerStatus);
671
672 /**
673 * config EP, include double fifo, max packet size, etc.
674 * @hUSB: handle return by USBC_open_otg,
675 * include the key data which USBC need
676 * @ep_type: transfer type
677 * @is_double_fifo: speed mode
678 * @ep_MaxPkt: max packet size
679 *
680 */
USBC_Dev_ConfigEp(__hdle hUSB,__u32 ts_type,__u32 ep_type,__u32 is_double_fifo,__u32 ep_MaxPkt)681 __s32 USBC_Dev_ConfigEp(__hdle hUSB,
682 __u32 ts_type, __u32 ep_type,
683 __u32 is_double_fifo, __u32 ep_MaxPkt)
684 {
685 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
686
687 if (usbc_otg == NULL)
688 return -1;
689
690 switch (ep_type) {
691 case USBC_EP_TYPE_EP0:
692 __USBC_Dev_ep0_ConfigEp0(usbc_otg->base_addr);
693 break;
694
695 case USBC_EP_TYPE_TX:
696 __USBC_Dev_Tx_ConfigEp(usbc_otg->base_addr,
697 ts_type, is_double_fifo, ep_MaxPkt);
698 break;
699
700 case USBC_EP_TYPE_RX:
701 __USBC_Dev_Rx_ConfigEp(usbc_otg->base_addr,
702 ts_type, is_double_fifo, ep_MaxPkt);
703 break;
704
705 default:
706 return -1;
707 }
708
709 return 0;
710 }
711 EXPORT_SYMBOL(USBC_Dev_ConfigEp);
712
713 /**
714 * release all Ep resources, excpet irq
715 * @hUSB: handle return by USBC_open_otg,
716 * include the key data which USBC need
717 * @ep_type: ep type
718 *
719 * return: 0 - success, !0 - failed
720 */
USBC_Dev_ConfigEp_Default(__hdle hUSB,__u32 ep_type)721 __s32 USBC_Dev_ConfigEp_Default(__hdle hUSB, __u32 ep_type)
722 {
723 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
724
725 if (usbc_otg == NULL)
726 return -1;
727
728 switch (ep_type) {
729 case USBC_EP_TYPE_EP0:
730 __USBC_Dev_ep0_ConfigEp0_Default(usbc_otg->base_addr);
731 break;
732
733 case USBC_EP_TYPE_TX:
734 __USBC_Dev_Tx_ConfigEp_Default(usbc_otg->base_addr);
735 break;
736
737 case USBC_EP_TYPE_RX:
738 __USBC_Dev_Rx_ConfigEp_Default(usbc_otg->base_addr);
739 break;
740
741 default:
742 return -1;
743 }
744
745 return 0;
746 }
747 EXPORT_SYMBOL(USBC_Dev_ConfigEp_Default);
748
749 /**
750 * config Ep's dma
751 * @hUSB: handle return by USBC_open_otg,
752 * include the key data which USBC need
753 * @ep_type: ep type
754 *
755 * return: 0 - success, !0 - failed
756 */
USBC_Dev_ConfigEpDma(__hdle hUSB,__u32 ep_type)757 __s32 USBC_Dev_ConfigEpDma(__hdle hUSB, __u32 ep_type)
758 {
759 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
760
761 if (usbc_otg == NULL)
762 return -1;
763
764 switch (ep_type) {
765 case USBC_EP_TYPE_EP0:
766 /* not support */
767 return -1;
768
769 case USBC_EP_TYPE_TX:
770 __USBC_Dev_Tx_ConfigEpDma(usbc_otg->base_addr);
771 __USBC_Dev_ConfigDma_Trans(usbc_otg->base_addr);
772 break;
773
774 case USBC_EP_TYPE_RX:
775 __USBC_Dev_Rx_ConfigEpDma(usbc_otg->base_addr);
776 __USBC_Dev_ConfigDma_Trans(usbc_otg->base_addr);
777 break;
778
779 default:
780 return -1;
781 }
782
783 return 0;
784 }
785 EXPORT_SYMBOL(USBC_Dev_ConfigEpDma);
786
787 /**
788 * clear Ep's dma configuration
789 * @hUSB: handle return by USBC_open_otg,
790 * include the key data which USBC need
791 * @ep_type: ep type
792 *
793 * return: 0 - success, !0 - failed
794 */
USBC_Dev_ClearEpDma(__hdle hUSB,__u32 ep_type)795 __s32 USBC_Dev_ClearEpDma(__hdle hUSB, __u32 ep_type)
796 {
797 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
798
799 if (usbc_otg == NULL)
800 return -1;
801
802 switch (ep_type) {
803 case USBC_EP_TYPE_EP0:
804 /* not support */
805 return -1;
806
807 case USBC_EP_TYPE_TX:
808 __USBC_Dev_Tx_ClearEpDma(usbc_otg->base_addr);
809 __USBC_Dev_ClearDma_Trans(usbc_otg->base_addr);
810 break;
811
812 case USBC_EP_TYPE_RX:
813 __USBC_Dev_Rx_ClearEpDma(usbc_otg->base_addr);
814 __USBC_Dev_ClearDma_Trans(usbc_otg->base_addr);
815 break;
816
817 default:
818 return -1;
819 }
820
821 return 0;
822 }
823 EXPORT_SYMBOL(USBC_Dev_ClearEpDma);
824
825 /**
826 * check if ep is stalled
827 * @hUSB: handle return by USBC_open_otg,
828 * include the key data which USBC need
829 * @ep_type: ep type
830 *
831 * return: 0 - success, !0 - failed
832 */
USBC_Dev_IsEpStall(__hdle hUSB,__u32 ep_type)833 __s32 USBC_Dev_IsEpStall(__hdle hUSB, __u32 ep_type)
834 {
835 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
836
837 if (usbc_otg == NULL)
838 return -1;
839
840 switch (ep_type) {
841 case USBC_EP_TYPE_EP0:
842 __USBC_Dev_ep0_IsEpStall(usbc_otg->base_addr);
843 break;
844
845 case USBC_EP_TYPE_TX:
846 __USBC_Dev_Tx_IsEpStall(usbc_otg->base_addr);
847 break;
848
849 case USBC_EP_TYPE_RX:
850 __USBC_Dev_Rx_IsEpStall(usbc_otg->base_addr);
851 break;
852
853 default:
854 return -1;
855 }
856
857 return 0;
858 }
859 EXPORT_SYMBOL(USBC_Dev_IsEpStall);
860
861 /**
862 * let ep enter stall status
863 * @hUSB: handle return by USBC_open_otg,
864 * include the key data which USBC need
865 * @ep_type: ep type
866 *
867 * return: 0 - success, !0 - failed
868 */
USBC_Dev_EpSendStall(__hdle hUSB,__u32 ep_type)869 __s32 USBC_Dev_EpSendStall(__hdle hUSB, __u32 ep_type)
870 {
871 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
872
873 if (usbc_otg == NULL)
874 return -1;
875
876 switch (ep_type) {
877 case USBC_EP_TYPE_EP0:
878 __USBC_Dev_ep0_SendStall(usbc_otg->base_addr);
879 break;
880
881 case USBC_EP_TYPE_TX:
882 __USBC_Dev_Tx_SendStall(usbc_otg->base_addr);
883 break;
884
885 case USBC_EP_TYPE_RX:
886 __USBC_Dev_Rx_SendStall(usbc_otg->base_addr);
887 break;
888
889 default:
890 return -1;
891 }
892
893 return 0;
894 }
895 EXPORT_SYMBOL(USBC_Dev_EpSendStall);
896
897 /**
898 * clear the ep's stall status
899 * @hUSB: handle return by USBC_open_otg,
900 * include the key data which USBC need
901 * @ep_type: ep type
902 *
903 * return: 0 - success, !0 - failed
904 */
USBC_Dev_EpClearStall(__hdle hUSB,__u32 ep_type)905 __s32 USBC_Dev_EpClearStall(__hdle hUSB, __u32 ep_type)
906 {
907 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
908
909 if (usbc_otg == NULL)
910 return -1;
911
912 switch (ep_type) {
913 case USBC_EP_TYPE_EP0:
914 __USBC_Dev_ep0_ClearStall(usbc_otg->base_addr);
915 break;
916
917 case USBC_EP_TYPE_TX:
918 __USBC_Dev_Tx_ClearStall(usbc_otg->base_addr);
919 break;
920
921 case USBC_EP_TYPE_RX:
922 __USBC_Dev_Rx_ClearStall(usbc_otg->base_addr);
923 break;
924
925 default:
926 return -1;
927 }
928
929 return 0;
930 }
931 EXPORT_SYMBOL(USBC_Dev_EpClearStall);
932
933 /**
934 * check if ep0 is SetupEnd
935 * @hUSB: handle return by USBC_open_otg,
936 * include the key data which USBC need
937 *
938 */
USBC_Dev_Ctrl_IsSetupEnd(__hdle hUSB)939 __u32 USBC_Dev_Ctrl_IsSetupEnd(__hdle hUSB)
940 {
941 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
942
943 if (usbc_otg == NULL)
944 return 0;
945
946 return __USBC_Dev_ep0_IsSetupEnd(usbc_otg->base_addr);
947 }
948 EXPORT_SYMBOL(USBC_Dev_Ctrl_IsSetupEnd);
949
950 /**
951 * clear the ep0's SetupEnd status
952 * @hUSB: handle return by USBC_open_otg,
953 * include the key data which USBC need
954 *
955 */
USBC_Dev_Ctrl_ClearSetupEnd(__hdle hUSB)956 void USBC_Dev_Ctrl_ClearSetupEnd(__hdle hUSB)
957 {
958 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
959
960 if (usbc_otg == NULL)
961 return;
962
963 __USBC_Dev_ep0_ClearSetupEnd(usbc_otg->base_addr);
964 }
965 EXPORT_SYMBOL(USBC_Dev_Ctrl_ClearSetupEnd);
966
__USBC_Dev_WriteDataHalf(void __iomem * usbc_base_addr,__u32 ep_type)967 static __s32 __USBC_Dev_WriteDataHalf(void __iomem *usbc_base_addr,
968 __u32 ep_type)
969 {
970 switch (ep_type) {
971 case USBC_EP_TYPE_EP0:
972 __USBC_Dev_ep0_WriteDataHalf(usbc_base_addr);
973 break;
974
975 case USBC_EP_TYPE_TX:
976 __USBC_Dev_Tx_WriteDataHalf(usbc_base_addr);
977 break;
978
979 case USBC_EP_TYPE_RX:
980 /* not support */
981 return -1;
982
983 default:
984 return -1;
985 }
986
987 return 0;
988 }
989
__USBC_Dev_WriteDataComplete(void __iomem * usbc_base_addr,__u32 ep_type)990 static __s32 __USBC_Dev_WriteDataComplete(void __iomem *usbc_base_addr,
991 __u32 ep_type)
992 {
993 switch (ep_type) {
994 case USBC_EP_TYPE_EP0:
995 __USBC_Dev_ep0_WriteDataComplete(usbc_base_addr);
996 break;
997
998 case USBC_EP_TYPE_TX:
999 __USBC_Dev_Tx_WriteDataComplete(usbc_base_addr);
1000 break;
1001
1002 case USBC_EP_TYPE_RX:
1003 /* not support */
1004 return -1;
1005
1006 default:
1007 return -1;
1008 }
1009
1010 return 0;
1011 }
1012
__USBC_Dev_ReadDataHalf(void __iomem * usbc_base_addr,__u32 ep_type)1013 static __s32 __USBC_Dev_ReadDataHalf(void __iomem *usbc_base_addr,
1014 __u32 ep_type)
1015 {
1016 switch (ep_type) {
1017 case USBC_EP_TYPE_EP0:
1018 __USBC_Dev_ep0_ReadDataHalf(usbc_base_addr);
1019 break;
1020
1021 case USBC_EP_TYPE_TX:
1022 /* not support */
1023 return -1;
1024
1025 case USBC_EP_TYPE_RX:
1026 __USBC_Dev_Rx_ReadDataHalf(usbc_base_addr);
1027 break;
1028
1029 default:
1030 return -1;
1031 }
1032
1033 return 0;
1034 }
1035
__USBC_Dev_ReadDataComplete(void __iomem * usbc_base_addr,__u32 ep_type)1036 static __s32 __USBC_Dev_ReadDataComplete(void __iomem *usbc_base_addr,
1037 __u32 ep_type)
1038 {
1039 switch (ep_type) {
1040 case USBC_EP_TYPE_EP0:
1041 __USBC_Dev_ep0_ReadDataComplete(usbc_base_addr);
1042 break;
1043
1044 case USBC_EP_TYPE_TX:
1045 /* not support */
1046 return -1;
1047
1048 case USBC_EP_TYPE_RX:
1049 __USBC_Dev_Rx_ReadDataComplete(usbc_base_addr);
1050 break;
1051
1052 default:
1053 return -1;
1054 }
1055
1056 return 0;
1057 }
1058
1059 /**
1060 * get the write status, eg write over or not
1061 * @hUSB: handle return by USBC_open_otg,
1062 * include the key data which USBC need
1063 * @ep_type: ep type
1064 * @complete: if all data has been written over.
1065 *
1066 * return: 0 - success, !0 - failed
1067 */
USBC_Dev_WriteDataStatus(__hdle hUSB,__u32 ep_type,__u32 complete)1068 __s32 USBC_Dev_WriteDataStatus(__hdle hUSB,
1069 __u32 ep_type, __u32 complete)
1070 {
1071 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
1072
1073 if (usbc_otg == NULL)
1074 return -1;
1075
1076 if (complete)
1077 return __USBC_Dev_WriteDataComplete(
1078 usbc_otg->base_addr, ep_type);
1079 else
1080 return __USBC_Dev_WriteDataHalf(
1081 usbc_otg->base_addr, ep_type);
1082 }
1083 EXPORT_SYMBOL(USBC_Dev_WriteDataStatus);
1084
1085 /**
1086 * get the read status, eg write over or not
1087 * @hUSB: handle return by USBC_open_otg,
1088 * include the key data which USBC need
1089 * @ep_type: ep type
1090 * @complete: if all data has been read over.
1091 *
1092 * return: 0 - success, !0 - failed
1093 */
USBC_Dev_ReadDataStatus(__hdle hUSB,__u32 ep_type,__u32 complete)1094 __s32 USBC_Dev_ReadDataStatus(__hdle hUSB,
1095 __u32 ep_type, __u32 complete)
1096 {
1097 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
1098
1099 if (usbc_otg == NULL)
1100 return -1;
1101
1102 if (complete)
1103 return __USBC_Dev_ReadDataComplete(
1104 usbc_otg->base_addr, ep_type);
1105 else
1106 return __USBC_Dev_ReadDataHalf(
1107 usbc_otg->base_addr, ep_type);
1108 }
1109 EXPORT_SYMBOL(USBC_Dev_ReadDataStatus);
1110
1111 /**
1112 * check if the data ready for reading
1113 * @hUSB: handle return by USBC_open_otg,
1114 * include the key data which USBC need
1115 * @ep_type: ep type
1116 *
1117 */
USBC_Dev_IsReadDataReady(__hdle hUSB,__u32 ep_type)1118 __u32 USBC_Dev_IsReadDataReady(__hdle hUSB, __u32 ep_type)
1119 {
1120 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
1121
1122 if (usbc_otg == NULL)
1123 return 0;
1124
1125 switch (ep_type) {
1126 case USBC_EP_TYPE_EP0:
1127 return __USBC_Dev_ep0_IsReadDataReady(usbc_otg->base_addr);
1128
1129 case USBC_EP_TYPE_TX:
1130 /* not support */
1131 break;
1132
1133 case USBC_EP_TYPE_RX:
1134 return __USBC_Dev_Rx_IsReadDataReady(usbc_otg->base_addr);
1135
1136 default:
1137 break;
1138 }
1139
1140 return 0;
1141 }
1142 EXPORT_SYMBOL(USBC_Dev_IsReadDataReady);
1143
1144 /**
1145 * check if the data ready for writing
1146 * @hUSB: handle return by USBC_open_otg,
1147 * include the key data which USBC need
1148 * @ep_type: ep type
1149 *
1150 */
USBC_Dev_IsWriteDataReady(__hdle hUSB,__u32 ep_type)1151 __u32 USBC_Dev_IsWriteDataReady(__hdle hUSB, __u32 ep_type)
1152 {
1153 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
1154
1155 if (usbc_otg == NULL)
1156 return 0;
1157
1158 switch (ep_type) {
1159 case USBC_EP_TYPE_EP0:
1160 return __USBC_Dev_ep0_IsWriteDataReady(usbc_otg->base_addr);
1161
1162 case USBC_EP_TYPE_TX:
1163 return __USBC_Dev_Tx_IsWriteDataReady(usbc_otg->base_addr);
1164
1165 case USBC_EP_TYPE_RX:
1166 /* not support */
1167 break;
1168
1169 default:
1170 break;
1171 }
1172
1173 return 0;
1174 }
1175 EXPORT_SYMBOL(USBC_Dev_IsWriteDataReady);
1176
USBC_Dev_IsWriteDataReady_FifoEmpty(__hdle hUSB,__u32 ep_type)1177 __u32 USBC_Dev_IsWriteDataReady_FifoEmpty(__hdle hUSB, __u32 ep_type)
1178 {
1179 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
1180
1181 if (usbc_otg == NULL)
1182 return 0;
1183
1184 switch (ep_type) {
1185 case USBC_EP_TYPE_EP0:
1186 return __USBC_Dev_ep0_IsWriteDataReady(usbc_otg->base_addr);
1187
1188 case USBC_EP_TYPE_TX:
1189 return __USBC_Dev_Tx_IsWriteDataReady_FifoEmpty(
1190 usbc_otg->base_addr);
1191
1192 case USBC_EP_TYPE_RX:
1193 /* not support */
1194 break;
1195
1196 default:
1197 break;
1198 }
1199
1200 return 0;
1201 }
1202
1203
1204
1205 /**
1206 * configure the device's transfer type and speed mode.
1207 * @hUSB: handle return by USBC_open_otg,
1208 * include the key data which USBC need
1209 *
1210 */
USBC_Dev_IsoUpdateEnable(__hdle hUSB)1211 __s32 USBC_Dev_IsoUpdateEnable(__hdle hUSB)
1212 {
1213 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
1214
1215 if (usbc_otg == NULL)
1216 return -1;
1217
1218 __USBC_Dev_TsType_Iso(usbc_otg->base_addr);
1219 return 0;
1220 }
1221 EXPORT_SYMBOL(USBC_Dev_IsoUpdateEnable);
1222
__USBC_Dev_ep0_FlushFifo(void __iomem * usbc_base_addr)1223 static void __USBC_Dev_ep0_FlushFifo(void __iomem *usbc_base_addr)
1224 {
1225 USBC_Writew(1 << USBC_BP_CSR0_D_FLUSH_FIFO,
1226 USBC_REG_CSR0(usbc_base_addr));
1227 }
1228
__USBC_Dev_Tx_FlushFifo(void __iomem * usbc_base_addr)1229 static void __USBC_Dev_Tx_FlushFifo(void __iomem *usbc_base_addr)
1230 {
1231 USBC_Writew((1 << USBC_BP_TXCSR_D_CLEAR_DATA_TOGGLE)
1232 | (1 << USBC_BP_TXCSR_D_FLUSH_FIFO),
1233 USBC_REG_TXCSR(usbc_base_addr));
1234 }
1235
__USBC_Dev_Rx_FlushFifo(void __iomem * usbc_base_addr)1236 static void __USBC_Dev_Rx_FlushFifo(void __iomem *usbc_base_addr)
1237 {
1238 USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE)
1239 | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO),
1240 USBC_REG_RXCSR(usbc_base_addr));
1241 }
1242
USBC_Dev_FlushFifo(__hdle hUSB,__u32 ep_type)1243 void USBC_Dev_FlushFifo(__hdle hUSB, __u32 ep_type)
1244 {
1245 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
1246
1247 if (usbc_otg == NULL)
1248 return;
1249
1250 switch (ep_type) {
1251 case USBC_EP_TYPE_EP0:
1252 __USBC_Dev_ep0_FlushFifo(usbc_otg->base_addr);
1253 break;
1254
1255 case USBC_EP_TYPE_TX:
1256 __USBC_Dev_Tx_FlushFifo(usbc_otg->base_addr);
1257 break;
1258
1259 case USBC_EP_TYPE_RX:
1260 __USBC_Dev_Rx_FlushFifo(usbc_otg->base_addr);
1261 break;
1262
1263 default:
1264 break;
1265 }
1266 }
1267 EXPORT_SYMBOL(USBC_Dev_FlushFifo);
1268
USBC_Phyx_Read(__hdle hUSB)1269 __u32 USBC_Phyx_Read(__hdle hUSB)
1270 {
1271 __u32 reg_value = 0;
1272 __u32 temp = 0;
1273 __u32 ptmp = 0;
1274 __u32 ret = 0;
1275
1276 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
1277
1278 if (usbc_otg == NULL) {
1279 DMSG_PANIC("ERR: usbc_otg is null!");
1280 return -1;
1281 }
1282
1283 reg_value = USBC_Readl(usbc_otg->base_addr + USBC_REG_o_PHYTUNE);
1284 reg_value &= 0xf3f;
1285 ptmp = reg_value;
1286
1287 temp = reg_value >> 8;
1288 ptmp &= ~((0xf << 8) | (0xf << 4));
1289 ptmp <<= 6;
1290 reg_value &= ~((0xf << 8) | (0xf << 0));
1291 ret = reg_value | ptmp | temp;
1292 DMSG_INFO("bit[3:0]VREF = 0x%x; bit[5:4]RISE = 0x%x; bit[7:6]PREEMPAMP = 0x%x; bit[9:8]RES = 0x%x\n",
1293 temp, reg_value >> 4, (ptmp >> 6) & 0x3,
1294 ((ptmp >> 6) & 0xc) >> 2);
1295
1296 return ret;
1297 }
1298 EXPORT_SYMBOL(USBC_Phyx_Read);
1299
1300
USBC_Phyx_Write(__hdle hUSB,__u32 data)1301 void USBC_Phyx_Write(__hdle hUSB, __u32 data)
1302 {
1303 __u32 reg_value = 0;
1304 __u32 temp = 0;
1305 __u32 dtmp = 0;
1306
1307 __usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
1308
1309 if (usbc_otg == NULL)
1310 return;
1311
1312 temp = dtmp = data;
1313 reg_value = USBC_Readl(usbc_otg->base_addr + USBC_REG_o_PHYTUNE);
1314 /*TXVREFTUNE + TXRISETUNE + TXPREEMPAMPTUNE + TXRESTUNE*/
1315 reg_value &= ~((0xf << 8) | (0x3 << 4) | (0xf << 0));
1316 temp &= ~((0xf << 4) | (0x3 << 8) | (0x1 << 10));
1317 reg_value |= temp << 8;
1318 dtmp &= ~((0xf << 6) | (0xf << 0) | (0x1 << 10));
1319 reg_value |= dtmp;
1320 data &= ~((0x3 << 4) | (0xf << 0) | (0x1 << 10));
1321 reg_value |= data >> 6;
1322
1323 USBC_Writel(reg_value, (usbc_otg->base_addr + USBC_REG_o_PHYTUNE));
1324 }
1325 EXPORT_SYMBOL(USBC_Phyx_Write);
1326