1 /* 2 * drivers/usb/sunxi_usb/include/sunxi_usb_bsp.h 3 * (C) Copyright 2010-2015 4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 5 * javen, 2010-12-20, create this file 6 * 7 * register defination. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 */ 15 16 17 #ifndef __SUNXI_USB_BSP_H__ 18 #define __SUNXI_USB_BSP_H__ 19 20 #include <linux/io.h> 21 22 #define USBC_Readb(reg) readb(reg) 23 #define USBC_Readw(reg) readw(reg) 24 #define USBC_Readl(reg) readl(reg) 25 #define USBC_Readq(reg) readq(reg) 26 27 #define USBC_Writeb(value, reg) writeb(value, reg) 28 #define USBC_Writew(value, reg) writew(value, reg) 29 #define USBC_Writel(value, reg) writel(value, reg) 30 #define USBC_Writeq(value, reg) writeq(value, reg) 31 32 #define USBC_REG_test_bit_b(bp, reg) (USBC_Readb(reg) & (1 << (bp))) 33 #define USBC_REG_test_bit_w(bp, reg) (USBC_Readw(reg) & (1 << (bp))) 34 #define USBC_REG_test_bit_l(bp, reg) (USBC_Readl(reg) & (1 << (bp))) 35 36 #define USBC_REG_set_bit_b(bp, reg) (USBC_Writeb((USBC_Readb(reg) \ 37 | (1 << (bp))), (reg))) 38 #define USBC_REG_set_bit_w(bp, reg) (USBC_Writew((USBC_Readw(reg) \ 39 | (1 << (bp))), (reg))) 40 #define USBC_REG_set_bit_l(bp, reg) (USBC_Writel((USBC_Readl(reg) \ 41 | (1 << (bp))), (reg))) 42 #define USBC_REG_clear_bit_b(bp, reg) (USBC_Writeb((USBC_Readb(reg) \ 43 & (~(1 << (bp)))), (reg))) 44 #define USBC_REG_clear_bit_w(bp, reg) (USBC_Writew((USBC_Readw(reg) \ 45 & (~(1 << (bp)))), (reg))) 46 #define USBC_REG_clear_bit_l(bp, reg) (USBC_Writel((USBC_Readl(reg) \ 47 & (~(1 << (bp)))), (reg))) 48 49 /* reg base */ 50 #define USBC0_BASE 0x01c13000 51 #define USBC1_BASE 0x01c14000 52 #define USBC2_BASE 0x01c1E000 53 54 /* reg offset */ 55 #define USBC_REG_o_FADDR 0x0098 56 #define USBC_REG_o_PCTL 0x0040 57 #define USBC_REG_o_INTTx 0x0044 58 #define USBC_REG_o_INTRx 0x0046 59 #define USBC_REG_o_INTTxE 0x0048 60 #define USBC_REG_o_INTRxE 0x004A 61 #define USBC_REG_o_INTUSB 0x004C 62 #define USBC_REG_o_INTUSBE 0x0050 63 #define USBC_REG_o_FRNUM 0x0054 64 #define USBC_REG_o_EPIND 0x0042 65 #define USBC_REG_o_TMCTL 0x007C 66 67 #define USBC_REG_o_TXMAXP 0x0080 68 #define USBC_REG_o_CSR0 0x0082 69 #define USBC_REG_o_TXCSR 0x0082 70 #define USBC_REG_o_RXMAXP 0x0084 71 #define USBC_REG_o_RXCSR 0x0086 72 #define USBC_REG_o_COUNT0 0x0088 73 #define USBC_REG_o_RXCOUNT 0x0088 74 #define USBC_REG_o_EP0TYPE 0x008C 75 #define USBC_REG_o_TXTYPE 0x008C 76 #define USBC_REG_o_NAKLIMIT0 0x008D 77 #define USBC_REG_o_TXINTERVAL 0x008D 78 #define USBC_REG_o_RXTYPE 0x008E 79 #define USBC_REG_o_RXINTERVAL 0x008F 80 81 #define USBC_REG_o_CONFIGDATA 0x00c0 82 83 #define USBC_REG_o_EPFIFO0 0x0000 84 #define USBC_REG_o_EPFIFO1 0x0004 85 #define USBC_REG_o_EPFIFO2 0x0008 86 #define USBC_REG_o_EPFIFO3 0x000C 87 #define USBC_REG_o_EPFIFO4 0x0010 88 #define USBC_REG_o_EPFIFO5 0x0014 89 #define USBC_REG_o_EPFIFOx(n) (0x0000 + (n<<2)) 90 91 #define USBC_REG_o_DEVCTL 0x0041 92 93 #define USBC_REG_o_TXFIFOSZ 0x0090 94 #define USBC_REG_o_RXFIFOSZ 0x0094 95 #define USBC_REG_o_TXFIFOAD 0x0092 96 #define USBC_REG_o_RXFIFOAD 0x0096 97 98 #define USBC_REG_o_VEND0 0x0043 99 #define USBC_REG_o_VEND1 0x007D 100 #define USBC_REG_o_VEND3 0x007E 101 102 #define USBC_REG_o_EPINFO 0x0078 103 #define USBC_REG_o_RAMINFO 0x0079 104 #define USBC_REG_o_LINKINFO 0x007A 105 #define USBC_REG_o_VPLEN 0x007B 106 #define USBC_REG_o_HSEOF 0x007C 107 #define USBC_REG_o_FSEOF 0x007D 108 #define USBC_REG_o_LSEOF 0x007E 109 110 /* new */ 111 #define USBC_REG_o_FADDR0 0x0098 112 #define USBC_REG_o_HADDR0 0x009A 113 #define USBC_REG_o_HPORT0 0x009B 114 #define USBC_REG_o_TXFADDRx 0x0098 115 #define USBC_REG_o_TXHADDRx 0x009A 116 #define USBC_REG_o_TXHPORTx 0x009B 117 #define USBC_REG_o_RXFADDRx 0x009C 118 #define USBC_REG_o_RXHADDRx 0x009E 119 #define USBC_REG_o_RXHPORTx 0x009F 120 121 #define USBC_REG_o_RPCOUNT 0x008A 122 123 /* new */ 124 #define USBC_REG_o_ISCR 0x0400 125 #define USBC_REG_o_PHYCTL 0x0404 126 #define USBC_REG_o_PHYBIST 0x0408 127 #define USBC_REG_o_PHYTUNE 0x0418 128 #define USBC_REG_o_PHYSTATUS 0x0424 129 130 #if defined(CONFIG_ARCH_SUN50I) \ 131 || defined(CONFIG_ARCH_SUN8IW10) \ 132 || defined(CONFIG_ARCH_SUN8IW11) \ 133 || defined(CONFIG_ARCH_SUN8IW12) \ 134 || defined(CONFIG_ARCH_SUN8IW15) \ 135 || defined(CONFIG_ARCH_SUN8IW8) \ 136 || defined(CONFIG_ARCH_SUN8IW7) \ 137 || defined(CONFIG_ARCH_SUN8IW6) \ 138 || defined(CONFIG_ARCH_SUN8IW17) \ 139 || defined(CONFIG_ARCH_SUN8IW18) \ 140 || defined(CONFIG_ARCH_SUN8IW16) \ 141 || defined(CONFIG_ARCH_SUN8IW19) \ 142 || defined(CONFIG_ARCH_SUN8IW20)\ 143 || defined(CONFIG_ARCH_SUN20IW1) 144 #define USBPHYC_REG_o_PHYCTL 0x0410 145 #else 146 #define USBPHYC_REG_o_PHYCTL 0x0404 147 #endif 148 149 /* dma */ 150 #define USBC_REG_o_DMA_INTE 0x0500 151 #define USBC_REG_o_DMA_INTS 0x0504 152 #define USBC_REG_o_DMA_CHAN_CFN(n) (0x0540 + (0x10 * n)) 153 #define USBC_REG_o_DMA_SDRAM_ADD(n) (0x0544 + (0x10 * n)) 154 #define USBC_REG_o_DMA_BC(n) (0x0548 + (0x10 * n)) 155 #define USBC_REG_o_DMA_RESIDUAL_BC(n) (0x054c + (0x10 * n)) 156 157 /* registers */ 158 #define USBC_REG_FADDR(usbc_base_addr) ((usbc_base_addr) \ 159 + USBC_REG_o_FADDR) 160 #define USBC_REG_PCTL(usbc_base_addr) ((usbc_base_addr) \ 161 + USBC_REG_o_PCTL) 162 #define USBC_REG_INTTx(usbc_base_addr) ((usbc_base_addr) \ 163 + USBC_REG_o_INTTx) 164 #define USBC_REG_INTRx(usbc_base_addr) ((usbc_base_addr) \ 165 + USBC_REG_o_INTRx) 166 #define USBC_REG_INTTxE(usbc_base_addr) ((usbc_base_addr) \ 167 + USBC_REG_o_INTTxE) 168 #define USBC_REG_INTRxE(usbc_base_addr) ((usbc_base_addr) \ 169 + USBC_REG_o_INTRxE) 170 #define USBC_REG_INTUSB(usbc_base_addr) ((usbc_base_addr) \ 171 + USBC_REG_o_INTUSB) 172 #define USBC_REG_INTUSBE(usbc_base_addr) ((usbc_base_addr) \ 173 + USBC_REG_o_INTUSBE) 174 #define USBC_REG_FRNUM(usbc_base_addr) ((usbc_base_addr) \ 175 + USBC_REG_o_FRNUM) 176 #define USBC_REG_EPIND(usbc_base_addr) ((usbc_base_addr) \ 177 + USBC_REG_o_EPIND) 178 #define USBC_REG_TMCTL(usbc_base_addr) ((usbc_base_addr) \ 179 + USBC_REG_o_TMCTL) 180 #define USBC_REG_TXMAXP(usbc_base_addr) ((usbc_base_addr) \ 181 + USBC_REG_o_TXMAXP) 182 183 #define USBC_REG_CSR0(usbc_base_addr) ((usbc_base_addr) \ 184 + USBC_REG_o_CSR0) 185 #define USBC_REG_TXCSR(usbc_base_addr) ((usbc_base_addr) \ 186 + USBC_REG_o_TXCSR) 187 188 #define USBC_REG_RXMAXP(usbc_base_addr) ((usbc_base_addr) \ 189 + USBC_REG_o_RXMAXP) 190 #define USBC_REG_RXCSR(usbc_base_addr) ((usbc_base_addr) \ 191 + USBC_REG_o_RXCSR) 192 193 #define USBC_REG_COUNT0(usbc_base_addr) ((usbc_base_addr) \ 194 + USBC_REG_o_COUNT0) 195 #define USBC_REG_RXCOUNT(usbc_base_addr) ((usbc_base_addr) \ 196 + USBC_REG_o_RXCOUNT) 197 198 #define USBC_REG_EP0TYPE(usbc_base_addr) ((usbc_base_addr) \ 199 + USBC_REG_o_EP0TYPE) 200 #define USBC_REG_TXTYPE(usbc_base_addr) ((usbc_base_addr) \ 201 + USBC_REG_o_TXTYPE) 202 203 #define USBC_REG_NAKLIMIT0(usbc_base_addr) ((usbc_base_addr) \ 204 + USBC_REG_o_NAKLIMIT0) 205 #define USBC_REG_TXINTERVAL(usbc_base_addr) ((usbc_base_addr) \ 206 + USBC_REG_o_TXINTERVAL) 207 208 #define USBC_REG_RXTYPE(usbc_base_addr) ((usbc_base_addr) \ 209 + USBC_REG_o_RXTYPE) 210 #define USBC_REG_RXINTERVAL(usbc_base_addr) ((usbc_base_addr) \ 211 + USBC_REG_o_RXINTERVAL) 212 #define USBC_REG_CONFIGDATA(usbc_base_addr) ((usbc_base_addr) \ 213 + USBC_REG_o_CONFIGDATA) 214 #define USBC_REG_EPFIFO0(usbc_base_addr) ((usbc_base_addr) \ 215 + USBC_REG_o_EPFIFO0) 216 #define USBC_REG_EPFIFO1(usbc_base_addr) ((usbc_base_addr) \ 217 + USBC_REG_o_EPFIFO1) 218 #define USBC_REG_EPFIFO2(usbc_base_addr) ((usbc_base_addr) \ 219 + USBC_REG_o_EPFIFO2) 220 #define USBC_REG_EPFIFO3(usbc_base_addr) ((usbc_base_addr) \ 221 + USBC_REG_o_EPFIFO3) 222 #define USBC_REG_EPFIFO4(usbc_base_addr) ((usbc_base_addr) \ 223 + USBC_REG_o_EPFIFO4) 224 #define USBC_REG_EPFIFO5(usbc_base_addr) ((usbc_base_addr) \ 225 + USBC_REG_o_EPFIFO5) 226 #define USBC_REG_EPFIFOx(usbc_base_addr, n) ((usbc_base_addr) \ 227 + USBC_REG_o_EPFIFOx(n)) 228 #define USBC_REG_DEVCTL(usbc_base_addr) ((usbc_base_addr) \ 229 + USBC_REG_o_DEVCTL) 230 #define USBC_REG_TXFIFOSZ(usbc_base_addr) ((usbc_base_addr) \ 231 + USBC_REG_o_TXFIFOSZ) 232 #define USBC_REG_RXFIFOSZ(usbc_base_addr) ((usbc_base_addr) \ 233 + USBC_REG_o_RXFIFOSZ) 234 #define USBC_REG_TXFIFOAD(usbc_base_addr) ((usbc_base_addr) \ 235 + USBC_REG_o_TXFIFOAD) 236 #define USBC_REG_RXFIFOAD(usbc_base_addr) ((usbc_base_addr) \ 237 + USBC_REG_o_RXFIFOAD) 238 #define USBC_REG_VEND0(usbc_base_addr) ((usbc_base_addr) \ 239 + USBC_REG_o_VEND0) 240 #define USBC_REG_VEND1(usbc_base_addr) ((usbc_base_addr) \ 241 + USBC_REG_o_VEND1) 242 #define USBC_REG_EPINFO(usbc_base_addr) ((usbc_base_addr) \ 243 + USBC_REG_o_EPINFO) 244 #define USBC_REG_RAMINFO(usbc_base_addr) ((usbc_base_addr) \ 245 + USBC_REG_o_RAMINFO) 246 #define USBC_REG_LINKINFO(usbc_base_addr) ((usbc_base_addr) \ 247 + USBC_REG_o_LINKINFO) 248 #define USBC_REG_VPLEN(usbc_base_addr) ((usbc_base_addr) \ 249 + USBC_REG_o_VPLEN) 250 #define USBC_REG_HSEOF(usbc_base_addr) ((usbc_base_addr) \ 251 + USBC_REG_o_HSEOF) 252 #define USBC_REG_FSEOF(usbc_base_addr) ((usbc_base_addr) \ 253 + USBC_REG_o_FSEOF) 254 #define USBC_REG_LSEOF(usbc_base_addr) ((usbc_base_addr) \ 255 + USBC_REG_o_LSEOF) 256 257 #define USBC_REG_FADDR0(usbc_base_addr) ((usbc_base_addr) \ 258 + USBC_REG_o_FADDR0) 259 #define USBC_REG_HADDR0(usbc_base_addr) ((usbc_base_addr) \ 260 + USBC_REG_o_HADDR0) 261 #define USBC_REG_HPORT0(usbc_base_addr) ((usbc_base_addr) \ 262 + USBC_REG_o_HPORT0) 263 264 #define USBC_REG_TXFADDRx(usbc_base_addr, n) ((usbc_base_addr) \ 265 + USBC_REG_o_TXFADDRx) 266 #define USBC_REG_TXHADDRx(usbc_base_addr, n) ((usbc_base_addr) \ 267 + USBC_REG_o_TXHADDRx) 268 #define USBC_REG_TXHPORTx(usbc_base_addr, n) ((usbc_base_addr) \ 269 + USBC_REG_o_TXHPORTx) 270 #define USBC_REG_RXFADDRx(usbc_base_addr, n) ((usbc_base_addr) \ 271 + USBC_REG_o_RXFADDRx) 272 #define USBC_REG_RXHADDRx(usbc_base_addr, n) ((usbc_base_addr) \ 273 + USBC_REG_o_RXHADDRx) 274 #define USBC_REG_RXHPORTx(usbc_base_addr, n) ((usbc_base_addr) \ 275 + USBC_REG_o_RXHPORTx) 276 277 #define USBC_REG_RPCOUNTx(usbc_base_addr, n) ((usbc_base_addr) \ 278 + USBC_REG_o_RPCOUNT) 279 280 #define USBC_REG_ISCR(usbc_base_addr) ((usbc_base_addr) \ 281 + USBC_REG_o_ISCR) 282 #define USBC_REG_PHYCTL(usbc_base_addr) ((usbc_base_addr) \ 283 + USBC_REG_o_PHYCTL) 284 #define USBC_REG_PHYBIST(usbc_base_addr) ((usbc_base_addr) \ 285 + USBC_REG_o_PHYBIST) 286 #define USBC_REG_PHYTUNE(usbc_base_addr) ((usbc_base_addr) \ 287 + USBC_REG_o_PHYTUNE) 288 289 #define USBC_REG_RXFADDRx_Ex(usbc_base_addr) ((usbc_base_addr) \ 290 + USBC_REG_o_RXFADDRx) 291 292 /* dma */ 293 #define USBC_REG_DMA_INTE(usbc_base_addr) ((usbc_base_addr) \ 294 + USBC_REG_o_DMA_INTE) 295 #define USBC_REG_DMA_INTS(usbc_base_addr) ((usbc_base_addr) \ 296 + USBC_REG_o_DMA_INTS) 297 #define USBC_REG_DMA_CHAN_CFN(usbc_base_addr, n) \ 298 ((usbc_base_addr) + USBC_REG_o_DMA_CHAN_CFN(n)) 299 #define USBC_REG_DMA_SDRAM_ADD(usbc_base_addr, n) \ 300 ((usbc_base_addr) + USBC_REG_o_DMA_SDRAM_ADD(n)) 301 #define USBC_REG_DMA_BC(usbc_base_addr, n) \ 302 ((usbc_base_addr) + USBC_REG_o_DMA_BC(n)) 303 #define USBC_REG_DMA_RESIDUAL_BC(usbc_base_addr, n) \ 304 ((usbc_base_addr) + USBC_REG_o_DMA_RESIDUAL_BC(n)) 305 306 /* registers extern */ 307 #define USBC_REG_EX_USB_EPFIFOn(usbc_base_addr) \ 308 ((usbc_base_addr) + (0x00 + (n << 2))) 309 #define USBC_REG_EX_USB_GCS(usbc_base_addr) \ 310 ((usbc_base_addr) + 0x0040) 311 #define USBC_REG_EX_USB_EPINTF(usbc_base_addr) \ 312 ((usbc_base_addr) + 0x0044) 313 #define USBC_REG_EX_USB_EPINTE(usbc_base_addr) \ 314 ((usbc_base_addr) + 0x0048) 315 #define USBC_REG_EX_USB_BUSINTF(usbc_base_addr) \ 316 ((usbc_base_addr) + 0x004C) 317 #define USBC_REG_EX_USB_BUSINTE(usbc_base_addr) \ 318 ((usbc_base_addr) + 0x0050) 319 #define USBC_REG_EX_USB_FNUM(usbc_base_addr) \ 320 ((usbc_base_addr) + 0x0054) 321 #define USBC_REG_EX_USB_TESTC(usbc_base_addr) \ 322 ((usbc_base_addr) + 0x007C) 323 324 #define USBC_REG_EX_USB_CSR0(usbc_base_addr) \ 325 ((usbc_base_addr) + 0x0080) 326 #define USBC_REG_EX_USB_TXCSR(usbc_base_addr) \ 327 ((usbc_base_addr) + 0x0080) 328 #define USBC_REG_EX_USB_RXCSR(usbc_base_addr) \ 329 ((usbc_base_addr) + 0x0084) 330 #define USBC_REG_EX_USB_COUNT0(usbc_base_addr) \ 331 ((usbc_base_addr) + 0x0088) 332 #define USBC_REG_EX_USB_RXCOUNT(usbc_base_addr) \ 333 ((usbc_base_addr) + 0x0088) 334 #define USBC_REG_EX_USB_ATTR0(usbc_base_addr) \ 335 ((usbc_base_addr) + 0x008C) 336 #define USBC_REG_EX_USB_EPATTR(usbc_base_addr) \ 337 ((usbc_base_addr) + 0x008C) 338 #define USBC_REG_EX_USB_TXFIFO(usbc_base_addr) \ 339 ((usbc_base_addr) + 0x0090) 340 #define USBC_REG_EX_USB_RXFIFO(usbc_base_addr) \ 341 ((usbc_base_addr) + 0x0094) 342 #define USBC_REG_EX_USB_FADDR(usbc_base_addr) \ 343 ((usbc_base_addr) + 0x0098) 344 #define USBC_REG_EX_USB_TXFADDR(usbc_base_addr) \ 345 ((usbc_base_addr) + 0x0098) 346 #define USBC_REG_EX_USB_RXFADDR(usbc_base_addr) \ 347 ((usbc_base_addr) + 0x009C) 348 349 #define USBC_REG_EX_USB_CONFIGINFO(usbc_base_addr) \ 350 ((usbc_base_addr) + 0x00C0) 351 #define USBC_REG_EX_USB_LINKTIM(usbc_base_addr) \ 352 ((usbc_base_addr) + 0x00C4) 353 #define USBC_REG_EX_USB_OTGTIM(usbc_base_addr) \ 354 ((usbc_base_addr) + 0x00C8) 355 356 #define USBC_REG_EX_USB_ISCR(usbc_base_addr) \ 357 ((usbc_base_addr) + 0x0400) 358 #define USBC_REG_EX_USB_PHYCTL(usbc_base_addr) \ 359 ((usbc_base_addr) + 0x0404) 360 #define USBC_REG_EX_USB_PHYBIST(usbc_base_addr) \ 361 ((usbc_base_addr) + 0x0408) 362 363 /* bit position */ 364 365 /* USB Power Control for Host only */ 366 #define USBC_BP_POWER_H_HIGH_SPEED_EN 5 367 #define USBC_BP_POWER_H_HIGH_SPEED_FLAG 4 368 #define USBC_BP_POWER_H_RESET 3 369 #define USBC_BP_POWER_H_RESUME 2 370 #define USBC_BP_POWER_H_SUSPEND 1 371 #define USBC_BP_POWER_H_SUEPEND_EN 0 372 373 /* USB Power Control for device only */ 374 #define USBC_BP_POWER_D_ISO_UPDATE_EN 7 375 #define USBC_BP_POWER_D_SOFT_CONNECT 6 376 #define USBC_BP_POWER_D_HIGH_SPEED_EN 5 377 #define USBC_BP_POWER_D_HIGH_SPEED_FLAG 4 378 #define USBC_BP_POWER_D_RESET_FLAG 3 379 #define USBC_BP_POWER_D_RESUME 2 380 #define USBC_BP_POWER_D_SUSPEND 1 381 #define USBC_BP_POWER_D_ENABLE_SUSPENDM 0 382 383 /* interrupt flags for ep0 and the Tx ep1~4 */ 384 #define USBC_BP_INTTx_FLAG_EP5 5 385 #define USBC_BP_INTTx_FLAG_EP4 4 386 #define USBC_BP_INTTx_FLAG_EP3 3 387 #define USBC_BP_INTTx_FLAG_EP2 2 388 #define USBC_BP_INTTx_FLAG_EP1 1 389 #define USBC_BP_INTTx_FLAG_EP0 0 390 391 /* interrupt flags for Rx ep1~4 */ 392 #define USBC_BP_INTRx_FLAG_EP5 5 393 #define USBC_BP_INTRx_FLAG_EP4 4 394 #define USBC_BP_INTRx_FLAG_EP3 3 395 #define USBC_BP_INTRx_FLAG_EP2 2 396 #define USBC_BP_INTRx_FLAG_EP1 1 397 398 /* interrupt enable for Tx ep0~4 */ 399 #define USBC_BP_INTTxE_EN_EP5 5 400 #define USBC_BP_INTTxE_EN_EP4 4 401 #define USBC_BP_INTTxE_EN_EP3 3 402 #define USBC_BP_INTTxE_EN_EP2 2 403 #define USBC_BP_INTTxE_EN_EP1 1 404 #define USBC_BP_INTTxE_EN_EP0 0 405 406 /* interrupt enable for Rx ep1~4 */ 407 #define USBC_BP_INTRxE_EN_EP5 5 408 #define USBC_BP_INTRxE_EN_EP4 4 409 #define USBC_BP_INTRxE_EN_EP3 3 410 #define USBC_BP_INTRxE_EN_EP2 2 411 #define USBC_BP_INTRxE_EN_EP1 1 412 413 /* USB interrupt */ 414 #define USBC_BP_INTUSB_VBUS_ERROR 7 415 #define USBC_BP_INTUSB_SESSION_REQ 6 416 #define USBC_BP_INTUSB_DISCONNECT 5 417 #define USBC_BP_INTUSB_CONNECT 4 418 #define USBC_BP_INTUSB_SOF 3 419 #define USBC_BP_INTUSB_RESET 2 420 #define USBC_BP_INTUSB_RESUME 1 421 #define USBC_BP_INTUSB_SUSPEND 0 422 423 /* USB interrupt enable */ 424 #define USBC_BP_INTUSBE_EN_VBUS_ERROR 7 425 #define USBC_BP_INTUSBE_EN_SESSION_REQ 6 426 #define USBC_BP_INTUSBE_EN_DISCONNECT 5 427 #define USBC_BP_INTUSBE_EN_CONNECT 4 428 #define USBC_BP_INTUSBE_EN_SOF 3 429 #define USBC_BP_INTUSBE_EN_RESET 2 430 #define USBC_BP_INTUSBE_EN_RESUME 1 431 #define USBC_BP_INTUSBE_EN_SUSPEND 0 432 433 /* Test Mode Control */ 434 #define USBC_BP_TMCTL_FORCE_HOST 7 435 #define USBC_BP_TMCTL_FIFO_ACCESS 6 436 #define USBC_BP_TMCTL_FORCE_FS 5 437 #define USBC_BP_TMCTL_FORCE_HS 4 438 #define USBC_BP_TMCTL_TEST_PACKET 3 439 #define USBC_BP_TMCTL_TEST_K 2 440 #define USBC_BP_TMCTL_TEST_J 1 441 #define USBC_BP_TMCTL_TEST_SE0_NAK 0 442 443 /* Tx Max packet */ 444 #define USBC_BP_TXMAXP_PACKET_COUNT 11 445 #define USBC_BP_TXMAXP_MAXIMUM_PAYLOAD 0 446 447 /* Control and Status Register for ep0 for Host only */ 448 #define USBC_BP_CSR0_H_DisPing 11 449 #define USBC_BP_CSR0_H_FlushFIFO 8 450 #define USBC_BP_CSR0_H_NAK_Timeout 7 451 #define USBC_BP_CSR0_H_StatusPkt 6 452 #define USBC_BP_CSR0_H_ReqPkt 5 453 #define USBC_BP_CSR0_H_Error 4 454 #define USBC_BP_CSR0_H_SetupPkt 3 455 #define USBC_BP_CSR0_H_RxStall 2 456 #define USBC_BP_CSR0_H_TxPkRdy 1 457 #define USBC_BP_CSR0_H_RxPkRdy 0 458 459 /* Control and Status Register for ep0 for device only */ 460 #define USBC_BP_CSR0_D_FLUSH_FIFO 8 461 #define USBC_BP_CSR0_D_SERVICED_SETUP_END 7 462 #define USBC_BP_CSR0_D_SERVICED_RX_PKT_READY 6 463 #define USBC_BP_CSR0_D_SEND_STALL 5 464 #define USBC_BP_CSR0_D_SETUP_END 4 465 #define USBC_BP_CSR0_D_DATA_END 3 466 #define USBC_BP_CSR0_D_SENT_STALL 2 467 #define USBC_BP_CSR0_D_TX_PKT_READY 1 468 #define USBC_BP_CSR0_D_RX_PKT_READY 0 469 470 /* Tx ep Control and Status Register for Host only */ 471 #define USBC_BP_TXCSR_H_AUTOSET 15 472 #define USBC_BP_TXCSR_H_RESERVED 14 473 #define USBC_BP_TXCSR_H_MODE 13 474 #define USBC_BP_TXCSR_H_DMA_REQ_EN 12 475 #define USBC_BP_TXCSR_H_FORCE_DATA_TOGGLE 11 476 #define USBC_BP_TXCSR_H_DMA_REQ_MODE 10 477 #define USBC_BP_TXCSR_H_DATA_TOGGLE_WR_EN 9 478 #define USBC_BP_TXCSR_H_DATA_TOGGLE 8 479 #define USBC_BP_TXCSR_H_NAK_TIMEOUT 7 480 #define USBC_BP_TXCSR_H_CLEAR_DATA_TOGGLE 6 481 #define USBC_BP_TXCSR_H_TX_STALL 5 482 #define USBC_BP_TXCSR_H_FLUSH_FIFO 3 483 #define USBC_BP_TXCSR_H_ERROR 2 484 #define USBC_BP_TXCSR_H_FIFO_NOT_EMPTY 1 485 #define USBC_BP_TXCSR_H_TX_READY 0 486 487 #define USBC_TXCSR_H_WZC_BITS ((1 << USBC_BP_TXCSR_H_NAK_TIMEOUT) \ 488 | (1 << USBC_BP_TXCSR_H_TX_STALL) \ 489 | (1 << USBC_BP_TXCSR_H_ERROR) \ 490 | (1 << USBC_BP_TXCSR_H_FIFO_NOT_EMPTY)) 491 492 /* Tx ep Control and Status Register for Device only */ 493 #define USBC_BP_TXCSR_D_AUTOSET 15 494 #define USBC_BP_TXCSR_D_ISO 14 495 #define USBC_BP_TXCSR_D_MODE 13 496 #define USBC_BP_TXCSR_D_DMA_REQ_EN 12 497 #define USBC_BP_TXCSR_D_FORCE_DATA_TOGGLE 11 498 #define USBC_BP_TXCSR_D_DMA_REQ_MODE 10 499 #define USBC_BP_TXCSR_D_INCOMPLETE 7 500 #define USBC_BP_TXCSR_D_CLEAR_DATA_TOGGLE 6 501 #define USBC_BP_TXCSR_D_SENT_STALL 5 502 #define USBC_BP_TXCSR_D_SEND_STALL 4 503 #define USBC_BP_TXCSR_D_FLUSH_FIFO 3 504 #define USBC_BP_TXCSR_D_UNDER_RUN 2 505 #define USBC_BP_TXCSR_D_FIFO_NOT_EMPTY 1 506 #define USBC_BP_TXCSR_D_TX_READY 0 507 508 /* Rx Max Packet */ 509 #define USBC_BP_RXMAXP_PACKET_COUNT 11 510 #define USBC_BP_RXMAXP_MAXIMUM_PAYLOAD 0 511 512 /* Rx ep Control and Status Register for Host only */ 513 #define USBC_BP_RXCSR_H_AUTO_CLEAR 15 514 #define USBC_BP_RXCSR_H_AUTO_REQ 14 515 #define USBC_BP_RXCSR_H_DMA_REQ_EN 13 516 #define USBC_BP_RXCSR_H_DISNYET 12 /* dis nyet */ 517 #define USBC_BP_RXCSR_H_PID_ERROR 12 /* pid error */ 518 #define USBC_BP_RXCSR_H_DMA_REQ_MODE 11 519 #define USBC_BP_RXCSR_H_DATA_TOGGLE_WR_EN 10 520 #define USBC_BP_RXCSR_H_DATA_TOGGLE 9 521 #define USBC_BP_RXCSR_H_INCOMPLETE 8 522 #define USBC_BP_RXCSR_H_CLEAR_DATA_TOGGLE 7 523 #define USBC_BP_RXCSR_H_RX_STALL 6 524 #define USBC_BP_RXCSR_H_REQ_PACKET 5 525 #define USBC_BP_RXCSR_H_FLUSH_FIFO 4 526 #define USBC_BP_RXCSR_H_DATA_ERR 3 /* iso */ 527 #define USBC_BP_RXCSR_H_NAK_TIMEOUT 3 /* bulk */ 528 #define USBC_BP_RXCSR_H_ERROR 2 529 #define USBC_BP_RXCSR_H_FIFO_FULL 1 530 #define USBC_BP_RXCSR_H_RX_PKT_READY 0 531 532 #define USBC_RXCSR_H_WZC_BITS ((1 << USBC_BP_RXCSR_H_RX_STALL) \ 533 | (1 << USBC_BP_RXCSR_H_ERROR) \ 534 | (1 << USBC_BP_RXCSR_H_DATA_ERR) \ 535 | (1 << USBC_BP_RXCSR_H_RX_PKT_READY)) 536 537 /* Rx ep Control and Status Register for Device only */ 538 #define USBC_BP_RXCSR_D_AUTO_CLEAR 15 539 #define USBC_BP_RXCSR_D_ISO 14 540 #define USBC_BP_RXCSR_D_DMA_REQ_EN 13 541 #define USBC_BP_RXCSR_D_DISABLE_NYET 12 542 #define USBC_BP_RXCSR_D_DMA_REQ_MODE 11 543 544 #define USBC_BP_RXCSR_D_INCOMPLETE 8 545 #define USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE 7 546 #define USBC_BP_RXCSR_D_SENT_STALL 6 547 #define USBC_BP_RXCSR_D_SEND_STALL 5 548 #define USBC_BP_RXCSR_D_FLUSH_FIFO 4 549 #define USBC_BP_RXCSR_D_DATA_ERROR 3 550 #define USBC_BP_RXCSR_D_OVERRUN 2 551 #define USBC_BP_RXCSR_D_FIFO_FULL 1 552 #define USBC_BP_RXCSR_D_RX_PKT_READY 0 553 554 /* Tx Type Register for host only */ 555 #define USBC_BP_TXTYPE_SPEED 6 /* new */ 556 #define USBC_BP_TXTYPE_PROROCOL 4 557 #define USBC_BP_TXTYPE_TARGET_EP_NUM 0 558 559 /* Rx Type Register for host only */ 560 #define USBC_BP_RXTYPE_SPEED 6 /* new */ 561 #define USBC_BP_RXTYPE_PROROCOL 4 562 #define USBC_BP_RXTYPE_TARGET_EP_NUM 0 563 564 /* Core Configueation */ 565 #define USBC_BP_CONFIGDATA_MPRXE 7 566 #define USBC_BP_CONFIGDATA_MPTXE 6 567 #define USBC_BP_CONFIGDATA_BIGENDIAN 5 568 #define USBC_BP_CONFIGDATA_HBRXE 4 569 #define USBC_BP_CONFIGDATA_HBTXE 3 570 #define USBC_BP_CONFIGDATA_DYNFIFO_SIZING 2 571 #define USBC_BP_CONFIGDATA_SOFTCONE 1 572 #define USBC_BP_CONFIGDATA_UTMI_DATAWIDTH 0 573 574 /* OTG Device Control */ 575 #define USBC_BP_DEVCTL_B_DEVICE 7 576 #define USBC_BP_DEVCTL_FS_DEV 6 577 #define USBC_BP_DEVCTL_LS_DEV 5 578 579 #define USBC_BP_DEVCTL_VBUS 3 580 #define USBC_BP_DEVCTL_HOST_MODE 2 581 #define USBC_BP_DEVCTL_HOST_REQ 1 582 #define USBC_BP_DEVCTL_SESSION 0 583 584 /* Tx EP FIFO size control */ 585 #define USBC_BP_TXFIFOSZ_DPB 4 586 #define USBC_BP_TXFIFOSZ_SZ 0 587 588 /* Rx EP FIFO size control */ 589 #define USBC_BP_RXFIFOSZ_DPB 4 590 #define USBC_BP_RXFIFOSZ_SZ 0 591 592 /* vendor0 */ 593 #define USBC_BP_VEND0_DRQ_SEL 1 594 #define USBC_BP_VEND0_BUS_SEL 0 595 596 /* hub address */ 597 #define USBC_BP_HADDR_MULTI_TT 7 598 599 /* Interface Status and Control */ 600 #define USBC_BP_ISCR_VBUS_VALID_FROM_DATA 30 601 #define USBC_BP_ISCR_VBUS_VALID_FROM_VBUS 29 602 #define USBC_BP_ISCR_EXT_ID_STATUS 28 603 #define USBC_BP_ISCR_EXT_DM_STATUS 27 604 #define USBC_BP_ISCR_EXT_DP_STATUS 26 605 #define USBC_BP_ISCR_MERGED_VBUS_STATUS 25 606 #define USBC_BP_ISCR_MERGED_ID_STATUS 24 607 608 #define USBC_BP_ISCR_ID_PULLUP_EN 17 609 #define USBC_BP_ISCR_DPDM_PULLUP_EN 16 610 #define USBC_BP_ISCR_FORCE_ID 14 611 #define USBC_BP_ISCR_FORCE_VBUS_VALID 12 612 #define USBC_BP_ISCR_VBUS_VALID_SRC 10 613 614 #define USBC_BP_ISCR_HOSC_EN 7 615 #define USBC_BP_ISCR_VBUS_CHANGE_DETECT 6 616 #define USBC_BP_ISCR_ID_CHANGE_DETECT 5 617 #define USBC_BP_ISCR_DPDM_CHANGE_DETECT 4 618 #define USBC_BP_ISCR_IRQ_ENABLE 3 619 #define USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN 2 620 #define USBC_BP_ISCR_ID_CHANGE_DETECT_EN 1 621 #define USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN 0 622 623 /* usb resource description */ 624 #define USBC_MAX_CTL_NUM 1 625 /* max EP support, ep0~5 */ 626 #define USBC_MAX_EP_NUM 6 627 #define USBC0_MAX_FIFO_SIZE (8 * 1024) 628 /* This is non-configurable */ 629 #define USBC_EP0_FIFOSIZE 64 630 631 /* usb OTG mode */ 632 #define USBC_OTG_HOST 0 633 #define USBC_OTG_DEVICE 1 634 635 /* usb device type */ 636 #define USBC_DEVICE_HSDEV 0 637 #define USBC_DEVICE_FSDEV 1 638 #define USBC_DEVICE_LSDEV 2 639 640 /* usb transfer type */ 641 #define USBC_TS_TYPE_IDLE 0 642 #define USBC_TS_TYPE_CTRL 1 643 #define USBC_TS_TYPE_ISO 2 644 #define USBC_TS_TYPE_INT 3 645 #define USBC_TS_TYPE_BULK 4 646 647 /* usb transfer mode */ 648 #define USBC_TS_MODE_UNKNOWN 0 649 #define USBC_TS_MODE_LS 1 650 #define USBC_TS_MODE_FS 2 651 #define USBC_TS_MODE_HS 3 652 653 /* usb Vbus status */ 654 #define USBC_VBUS_STATUS_BELOW_SESSIONEND 0 655 #define USBC_VBUS_STATUS_ABOVE_SESSIONEND_BELOW_AVALID 1 656 #define USBC_VBUS_STATUS_ABOVE_AVALID_BELOW_VBUSVALID 2 657 #define USBC_VBUS_STATUS_ABOVE_VBUSVALID 3 658 659 /* usb io type */ 660 #define USBC_IO_TYPE_PIO 0 661 #define USBC_IO_TYPE_DMA 1 662 663 /* usb ep type */ 664 #define USBC_EP_TYPE_IDLE 0 665 #define USBC_EP_TYPE_EP0 1 666 #define USBC_EP_TYPE_TX 2 667 #define USBC_EP_TYPE_RX 3 668 669 /* usb id type */ 670 #define USBC_ID_TYPE_DISABLE 0 671 #define USBC_ID_TYPE_HOST 1 672 #define USBC_ID_TYPE_DEVICE 2 673 674 /* usb vbus valid type */ 675 #define USBC_VBUS_TYPE_DISABLE 0 676 #define USBC_VBUS_TYPE_LOW 1 677 #define USBC_VBUS_TYPE_HIGH 2 678 679 /* usb a valid source */ 680 #define USBC_A_VALID_SOURCE_UTMI_AVALID 0 681 #define USBC_A_VALID_SOURCE_UTMI_VBUS 1 682 683 /* usb device switch */ 684 #define USBC_DEVICE_SWITCH_OFF 0 685 #define USBC_DEVICE_SWITCH_ON 1 686 687 /* usb fifo config mode */ 688 #define USBC_FIFO_MODE_4K (4 * 1024) 689 #define USBC_FIFO_MODE_8K (8 * 1024) 690 691 /* usb interrupt mask */ 692 693 /* interrupt flags for ep0 and the Tx ep1~4 */ 694 #define USBC_INTTx_FLAG_EP5 (1 << USBC_BP_INTTx_FLAG_EP5) 695 #define USBC_INTTx_FLAG_EP4 (1 << USBC_BP_INTTx_FLAG_EP4) 696 #define USBC_INTTx_FLAG_EP3 (1 << USBC_BP_INTTx_FLAG_EP3) 697 #define USBC_INTTx_FLAG_EP2 (1 << USBC_BP_INTTx_FLAG_EP2) 698 #define USBC_INTTx_FLAG_EP1 (1 << USBC_BP_INTTx_FLAG_EP1) 699 #define USBC_INTTx_FLAG_EP0 (1 << USBC_BP_INTTx_FLAG_EP0) 700 701 /* interrupt flags for Rx ep1~4 */ 702 #define USBC_INTRx_FLAG_EP5 (1 << USBC_BP_INTRx_FLAG_EP5) 703 #define USBC_INTRx_FLAG_EP4 (1 << USBC_BP_INTRx_FLAG_EP4) 704 #define USBC_INTRx_FLAG_EP3 (1 << USBC_BP_INTRx_FLAG_EP3) 705 #define USBC_INTRx_FLAG_EP2 (1 << USBC_BP_INTRx_FLAG_EP2) 706 #define USBC_INTRx_FLAG_EP1 (1 << USBC_BP_INTRx_FLAG_EP1) 707 708 /* USB interrupt */ 709 #define USBC_INTUSB_VBUS_ERROR (1 << USBC_BP_INTUSB_VBUS_ERROR) 710 #define USBC_INTUSB_SESSION_REQ (1 << USBC_BP_INTUSB_SESSION_REQ) 711 #define USBC_INTUSB_DISCONNECT (1 << USBC_BP_INTUSB_DISCONNECT) 712 #define USBC_INTUSB_CONNECT (1 << USBC_BP_INTUSB_CONNECT) 713 #define USBC_INTUSB_SOF (1 << USBC_BP_INTUSB_SOF) 714 #define USBC_INTUSB_RESET (1 << USBC_BP_INTUSB_RESET) 715 #define USBC_INTUSB_RESUME (1 << USBC_BP_INTUSB_RESUME) 716 #define USBC_INTUSB_SUSPEND (1 << USBC_BP_INTUSB_SUSPEND) 717 718 #define USBC_PHY_CTL_LOOPBACKENB 7 719 #define USBC_PHY_CTL_VBUSVLDEXT 5 720 #define USBC_PHY_CTL_SIDDQ 3 721 722 /* USB host operations */ 723 void USBC_Host_SetFunctionAddress_Default(__hdle hUSB, 724 __u32 ep_type, 725 __u32 ep_index); 726 void USBC_Host_SetFunctionAddress(__hdle hUSB, 727 __u32 EpType, 728 __u32 EpIndex, 729 __u32 FunctionAdress, 730 __u32 MultiTT, 731 __u32 HubAddress, 732 __u32 HubPortNumber); 733 void USBC_Host_SetHubAddress_Default(__hdle hUSB, 734 __u32 ep_type, 735 __u32 ep_index); 736 void USBC_Host_SetHubAddress(__hdle hUSB, 737 __u32 ep_type, 738 __u32 ep_index, 739 __u32 is_multi_tt, 740 __u8 address); 741 void USBC_Host_SetHPortAddress_Default(__hdle hUSB, 742 __u32 ep_type, 743 __u32 ep_index); 744 void USBC_Host_SetHPortAddress(__hdle hUSB, 745 __u32 ep_type, 746 __u32 ep_index, 747 __u8 address); 748 749 __u32 USBC_Host_QueryTransferMode(__hdle hUSB); 750 void USBC_Host_ConfigTransferMode(__hdle hUSB, __u32 speed_mode); 751 752 void USBC_Host_ResetPort(__hdle hUSB); 753 void USBC_Host_ClearResetPortFlag(__hdle hUSB); 754 void USBC_Host_RusumePort(__hdle hUSB); 755 void USBC_Host_ClearRusumePortFlag(__hdle hUSB); 756 void USBC_Host_SuspendPort(__hdle hUSB); 757 __u32 USBC_Host_QueryPowerStatus(__hdle hUSB); 758 759 void USBC_Host_EnablePing(__hdle hUSB); 760 void USBC_Host_DisablePing(__hdle hUSB); 761 __u32 USBC_Host_IsReqPktSet(__hdle hUSB, __u32 ep_type); 762 void USBC_Host_StartInToken(__hdle hUSB, __u32 ep_type); 763 void USBC_Host_StopInToken(__hdle hUSB, __u32 ep_type); 764 void USBC_Host_SendCtrlStatus(__hdle hUSB, __u32 is_after_in); 765 void USBC_Host_SendSetupPkt(__hdle hUSB); 766 767 void USBC_Host_StartSession(__hdle hUSB); 768 void USBC_Host_EndSession(__hdle hUSB); 769 void USBC_Host_ConfigRqPktCount(__hdle hUSB, __u32 ep_index, __u32 RqPktCount); 770 void USBC_Host_ClearRqPktCount(__hdle hUSB, __u32 ep_index); 771 772 __u32 USBC_Host_PeripheralType(__hdle hUSB); 773 774 void USBC_Host_FlushFifo(__hdle hUSB, __u32 ep_type); 775 void USBC_Host_ConfigEp_Default(__hdle hUSB, __u32 ep_type); 776 void USBC_Host_ConfigEp(__hdle hUSB, 777 __u32 ep_type, 778 __u32 ep_index, 779 __u32 ts_mode, 780 __u32 ts_type, 781 __u32 is_double_fifo, 782 __u32 ep_MaxPkt, 783 __u32 interval); 784 void USBC_Host_ConfigEpDma(__hdle hUSB, __u32 ep_type); 785 void USBC_Host_ClearEpDma(__hdle hUSB, __u32 ep_type); 786 787 __u32 USBC_Host_IsEpStall(__hdle hUSB, __u32 ep_type); 788 void USBC_Host_ClearEpStall(__hdle hUSB, __u32 ep_type); 789 __u32 USBC_Host_IsEpNakTimeOut(__hdle hUSB, __u32 ep_type); 790 void USBC_Host_ClearEpNakTimeOut(__hdle hUSB, __u32 ep_type); 791 __u32 USBC_Host_IsEpError(__hdle hUSB, __u32 ep_type); 792 void USBC_Host_ClearEpError(__hdle hUSB, __u32 ep_type); 793 void USBC_Host_ClearEpCSR(__hdle hUSB, __u32 ep_type); 794 795 __u32 USBC_Host_IsReadDataReady(__hdle hUSB, __u32 ep_type); 796 __u32 USBC_Host_IsWriteDataReady(__hdle hUSB, __u32 ep_type); 797 __s32 USBC_Host_ReadDataStatus(__hdle hUSB, __u32 ep_type, __u32 complete); 798 __s32 USBC_Host_WriteDataStatus(__hdle hUSB, __u32 ep_type, __u32 complete); 799 800 /* USB device operations */ 801 void USBC_Dev_SetAddress_default(__hdle hUSB); 802 void USBC_Dev_SetAddress(__hdle hUSB, __u8 address); 803 804 __u32 USBC_Dev_QueryTransferMode(__hdle hUSB); 805 void USBC_Dev_ConfigTransferMode(__hdle hUSB, __u8 ts_type, __u8 speed_mode); 806 void USBC_Dev_ConectSwitch(__hdle hUSB, __u32 is_on); 807 __u32 USBC_Dev_QueryPowerStatus(__hdle hUSB); 808 809 __s32 USBC_Dev_ConfigEp(__hdle hUSB, 810 __u32 ts_type, 811 __u32 ep_type, 812 __u32 is_double_fifo, 813 __u32 ep_MaxPkt); 814 __s32 USBC_Dev_ConfigEp_Default(__hdle hUSB, __u32 ep_type); 815 __s32 USBC_Dev_ConfigEpDma(__hdle hUSB, __u32 ep_type); 816 __s32 USBC_Dev_ClearEpDma(__hdle hUSB, __u32 ep_type); 817 818 __s32 USBC_Dev_IsEpStall(__hdle hUSB, __u32 ep_type); 819 __s32 USBC_Dev_EpSendStall(__hdle hUSB, __u32 ep_type); 820 __s32 USBC_Dev_EpClearStall(__hdle hUSB, __u32 ep_type); 821 822 __u32 USBC_Dev_Ctrl_IsSetupEnd(__hdle hUSB); 823 void USBC_Dev_Ctrl_ClearSetupEnd(__hdle hUSB); 824 825 __u32 USBC_Dev_IsReadDataReady(__hdle hUSB, __u32 ep_type); 826 __u32 USBC_Dev_IsWriteDataReady(__hdle hUSB, __u32 ep_type); 827 __u32 USBC_Dev_IsWriteDataReady_FifoEmpty(__hdle hUSB, __u32 ep_type); 828 __s32 USBC_Dev_WriteDataStatus(__hdle hUSB, __u32 ep_type, __u32 complete); 829 __s32 USBC_Dev_ReadDataStatus(__hdle hUSB, __u32 ep_type, __u32 complete); 830 __s32 USBC_Dev_IsoUpdateEnable(__hdle hUSB); 831 void USBC_Dev_FlushFifo(__hdle hUSB, __u32 ep_type); 832 void USBC_Phyx_Write(__hdle hUSB, __u32 data); 833 __u32 USBC_Phyx_Read(__hdle hUSB); 834 835 836 /* usb common ops */ 837 838 /* USB transfer type select, read/write.. */ 839 void USBC_OTG_SelectMode(__hdle hUSB, __u32 mode); 840 841 __u32 USBC_ReadLenFromFifo(__hdle hUSB, __u32 ep_type); 842 __u32 USBC_WritePacket(__hdle hUSB, void __iomem *fifo, __u32 cnt, void *buff); 843 __u32 USBC_ReadPacket(__hdle hUSB, void __iomem *fifo, __u32 cnt, void *buff); 844 845 void USBC_ConfigFIFO_Base(__hdle hUSB, __u32 fifo_mode); 846 void __iomem *USBC_GetPortFifoStartAddr(__hdle hUSB); 847 __u32 USBC_GetPortFifoSize(__hdle hUSB); 848 void __iomem *USBC_SelectFIFO(__hdle hUSB, __u32 ep_index); 849 void USBC_ConfigFifo_Default(__hdle hUSB, __u32 ep_type); 850 void USBC_ConfigFifo(__hdle hUSB, 851 __u32 ep_type, 852 __u32 is_double_fifo, 853 __u32 fifo_size, 854 __u32 fifo_addr); 855 856 void USBC_SelectBus(__hdle hUSB, __u32 io_type, __u32 ep_type, __u32 ep_index); 857 void USBC_SelectPhyToDevice(void __iomem *usbc_base_addr); 858 859 __u32 USBC_GetActiveEp(__hdle hUSB); 860 void USBC_SelectActiveEp(__hdle hUSB, __u8 ep_index); 861 862 void USBC_EnhanceSignal(__hdle hUSB); 863 864 __u32 USBC_GetLastFrameNumber(__hdle hUSB); 865 866 /* usb interrupt ops */ 867 __u32 USBC_INT_EpPending(__hdle hUSB, __u32 ep_type); 868 __u32 USBC_INT_MiscPending(__hdle hUSB); 869 void USBC_INT_ClearEpPending(__hdle hUSB, __u32 ep_type, __u8 ep_index); 870 void USBC_INT_ClearMiscPending(__hdle hUSB, __u32 mask); 871 void USBC_INT_ClearEpPendingAll(__hdle hUSB, __u32 ep_type); 872 void USBC_INT_ClearMiscPendingAll(__hdle hUSB); 873 874 void USBC_INT_EnableEp(__hdle hUSB, __u32 ep_type, __u8 ep_index); 875 void USBC_INT_EnableUsbMiscUint(__hdle hUSB, __u32 mask); 876 877 void USBC_INT_DisableEp(__hdle hUSB, __u32 ep_type, __u8 ep_index); 878 void USBC_INT_DisableUsbMiscUint(__hdle hUSB, __u32 mask); 879 880 void USBC_INT_DisableEpAll(__hdle hUSB, __u32 ep_type); 881 void USBC_INT_DisableUsbMiscAll(__hdle hUSB); 882 883 /* usb control ops */ 884 __u32 USBC_GetVbusStatus(__hdle hUSB); 885 __u32 USBC_GetStatus_Dp(__hdle hUSB); 886 __u32 USBC_GetStatus_Dm(__hdle hUSB); 887 __u32 USBC_GetStatus_DpDm(__hdle hUSB); 888 889 __u32 USBC_GetOtgMode_Form_ID(__hdle hUSB); 890 __u32 USBC_GetOtgMode_Form_BDevice(__hdle hUSB); 891 892 void USBC_SetWakeUp_Default(__hdle hUSB); 893 894 void USBC_EnableIdPullUp(__hdle hUSB); 895 void USBC_DisableIdPullUp(__hdle hUSB); 896 void USBC_EnableDpDmPullUp(__hdle hUSB); 897 void USBC_DisableDpDmPullUp(__hdle hUSB); 898 899 void USBC_ForceId(__hdle hUSB, __u32 id_type); 900 void USBC_ForceVbusValid(__hdle hUSB, __u32 vbus_type); 901 902 void USBC_A_valid_InputSelect(__hdle hUSB, __u32 source); 903 904 void USBC_EnableUsbLineStateBypass(__hdle hUSB); 905 void USBC_DisableUsbLineStateBypass(__hdle hUSB); 906 void USBC_EnableHosc(__hdle hUSB); 907 void USBC_DisableHosc(__hdle hUSB); 908 909 __u32 USBC_IsVbusChange(__hdle hUSB); 910 __u32 USBC_IsIdChange(__hdle hUSB); 911 __u32 USBC_IsDpDmChange(__hdle hUSB); 912 913 void USBC_DisableWakeIrq(__hdle hUSB); 914 void USBC_DisableVbusChange(__hdle hUSB); 915 void USBC_DisableIdChange(__hdle hUSB); 916 void USBC_DisableDpDmChange(__hdle hUSB); 917 918 void USBC_EnableWakeIrq(__hdle hUSB); 919 void USBC_EnableVbusChange(__hdle hUSB); 920 void USBC_EnableIdChange(__hdle hUSB); 921 void USBC_EnableDpDmChange(__hdle hUSB); 922 923 /* usb phy control*/ 924 void USBC_PHY_SetCommonConfig(void); 925 void USBC_PHY_SetPrivateConfig(__hdle hUSB); 926 __u32 USBC_PHY_GetCommonConfig(void); 927 void USBC_phy_Standby(__hdle hUSB, __u32 phy_index); 928 void USBC_Phy_Standby_Recover(__hdle hUSB, __u32 phy_index); 929 void UsbPhyCtl(void __iomem *regs); 930 void USBC_PHY_Set_Ctl(void __iomem *regs, __u32 mask); 931 void USBC_PHY_Clear_Ctl(void __iomem *regs, __u32 mask); 932 void UsbPhyInit(__u32 usbc_no); 933 void UsbPhyEndReset(__u32 usbc_no); 934 void usb_otg_phy_txtune(void __iomem *regs); 935 void usbc_new_phy_res_cal(void __iomem *regs); 936 void usbc_new_phy_init(void __iomem *regs); 937 938 /* usb test mode */ 939 void USBC_EnterMode_TestPacket(__hdle hUSB); 940 void USBC_EnterMode_Test_K(__hdle hUSB); 941 void USBC_EnterMode_Test_J(__hdle hUSB); 942 void USBC_EnterMode_Test_SE0_NAK(__hdle hUSB); 943 void USBC_EnterMode_Idle(__hdle hUSB); 944 945 __u32 USBC_TestMode_ReadReg(__hdle hUSB, __u32 offset, __u32 reg_width); 946 947 /* controller info */ 948 typedef struct tag_usbc_info { 949 __u32 num; /* controller index */ 950 void __iomem *base; /* controller address */ 951 } usbc_info_t; 952 953 typedef struct tag_bsp_usbc { 954 usbc_info_t usbc_info; 955 void __iomem *sram_base; 956 } bsp_usbc_t; 957 958 /* open device */ 959 __hdle USBC_open_otg(__u32 otg_no); 960 __s32 USBC_close_otg(__hdle hUSB); 961 962 /* initialization */ 963 __s32 USBC_init(bsp_usbc_t *usbc); 964 __s32 USBC_exit(bsp_usbc_t *usbc); 965 966 #endif /* __SUNXI_USB_BSP_H__ */ 967