1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_VAD_H 10 #define HPM_VAD_H 11 12 typedef struct { 13 __RW uint32_t CTRL; /* 0x0: Control Register */ 14 __RW uint32_t FILTCTRL; /* 0x4: Filter Control Register */ 15 __RW uint32_t DEC_CTRL0; /* 0x8: Decision Control Register 0 */ 16 __RW uint32_t DEC_CTRL1; /* 0xC: Decision Control Register 1 */ 17 __RW uint32_t DEC_CTRL2; /* 0x10: Decision Control Register 2 */ 18 __R uint8_t RESERVED0[4]; /* 0x14 - 0x17: Reserved */ 19 __RW uint32_t ST; /* 0x18: Status */ 20 __RW uint32_t OFIFO; /* 0x1C: Out FIFO */ 21 __RW uint32_t RUN; /* 0x20: Run Command Register */ 22 __RW uint32_t OFIFO_CTRL; /* 0x24: Out FIFO Control Register */ 23 __RW uint32_t CIC_CFG; /* 0x28: CIC Configuration Register */ 24 __R uint8_t RESERVED1[116]; /* 0x2C - 0x9F: Reserved */ 25 __R uint32_t COEF[1]; /* 0xA0: Short Time Energy Register */ 26 } VAD_Type; 27 28 29 /* Bitfield definition for register: CTRL */ 30 /* 31 * CAPT_DLY (RW) 32 * 33 * Capture cycle delay>=0, should be less than PDM_CLK_HFDIV 34 */ 35 #define VAD_CTRL_CAPT_DLY_MASK (0xF000000UL) 36 #define VAD_CTRL_CAPT_DLY_SHIFT (24U) 37 #define VAD_CTRL_CAPT_DLY_SET(x) (((uint32_t)(x) << VAD_CTRL_CAPT_DLY_SHIFT) & VAD_CTRL_CAPT_DLY_MASK) 38 #define VAD_CTRL_CAPT_DLY_GET(x) (((uint32_t)(x) & VAD_CTRL_CAPT_DLY_MASK) >> VAD_CTRL_CAPT_DLY_SHIFT) 39 40 /* 41 * PDM_CLK_HFDIV (RW) 42 * 43 * The clock divider will work at least 4. 44 * 0: div-by-2, 45 * 1: div-by-4 46 * . . . 47 * n: div-by-2*(n+1) 48 */ 49 #define VAD_CTRL_PDM_CLK_HFDIV_MASK (0xF00000UL) 50 #define VAD_CTRL_PDM_CLK_HFDIV_SHIFT (20U) 51 #define VAD_CTRL_PDM_CLK_HFDIV_SET(x) (((uint32_t)(x) << VAD_CTRL_PDM_CLK_HFDIV_SHIFT) & VAD_CTRL_PDM_CLK_HFDIV_MASK) 52 #define VAD_CTRL_PDM_CLK_HFDIV_GET(x) (((uint32_t)(x) & VAD_CTRL_PDM_CLK_HFDIV_MASK) >> VAD_CTRL_PDM_CLK_HFDIV_SHIFT) 53 54 /* 55 * VAD_IE (RW) 56 * 57 * VAD event interrupt enable 58 */ 59 #define VAD_CTRL_VAD_IE_MASK (0x40000UL) 60 #define VAD_CTRL_VAD_IE_SHIFT (18U) 61 #define VAD_CTRL_VAD_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_VAD_IE_SHIFT) & VAD_CTRL_VAD_IE_MASK) 62 #define VAD_CTRL_VAD_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_VAD_IE_MASK) >> VAD_CTRL_VAD_IE_SHIFT) 63 64 /* 65 * OFIFO_AV_IE (RW) 66 * 67 * OFIFO data available interrupt enable 68 */ 69 #define VAD_CTRL_OFIFO_AV_IE_MASK (0x20000UL) 70 #define VAD_CTRL_OFIFO_AV_IE_SHIFT (17U) 71 #define VAD_CTRL_OFIFO_AV_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_OFIFO_AV_IE_SHIFT) & VAD_CTRL_OFIFO_AV_IE_MASK) 72 #define VAD_CTRL_OFIFO_AV_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_OFIFO_AV_IE_MASK) >> VAD_CTRL_OFIFO_AV_IE_SHIFT) 73 74 /* 75 * MEMBUF_EMPTY_IE (RW) 76 * 77 * Buf empty interrupt enable 78 */ 79 #define VAD_CTRL_MEMBUF_EMPTY_IE_MASK (0x10000UL) 80 #define VAD_CTRL_MEMBUF_EMPTY_IE_SHIFT (16U) 81 #define VAD_CTRL_MEMBUF_EMPTY_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_MEMBUF_EMPTY_IE_SHIFT) & VAD_CTRL_MEMBUF_EMPTY_IE_MASK) 82 #define VAD_CTRL_MEMBUF_EMPTY_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_MEMBUF_EMPTY_IE_MASK) >> VAD_CTRL_MEMBUF_EMPTY_IE_SHIFT) 83 84 /* 85 * OFIFO_OVFL_ERR_IE (RW) 86 * 87 * OFIFO overflow error interrupt enable 88 */ 89 #define VAD_CTRL_OFIFO_OVFL_ERR_IE_MASK (0x8000U) 90 #define VAD_CTRL_OFIFO_OVFL_ERR_IE_SHIFT (15U) 91 #define VAD_CTRL_OFIFO_OVFL_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) & VAD_CTRL_OFIFO_OVFL_ERR_IE_MASK) 92 #define VAD_CTRL_OFIFO_OVFL_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_OFIFO_OVFL_ERR_IE_MASK) >> VAD_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) 93 94 /* 95 * IIR_OVLD_ERR_IE (RW) 96 * 97 * IIR overload error interrupt enable 98 */ 99 #define VAD_CTRL_IIR_OVLD_ERR_IE_MASK (0x4000U) 100 #define VAD_CTRL_IIR_OVLD_ERR_IE_SHIFT (14U) 101 #define VAD_CTRL_IIR_OVLD_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_IIR_OVLD_ERR_IE_SHIFT) & VAD_CTRL_IIR_OVLD_ERR_IE_MASK) 102 #define VAD_CTRL_IIR_OVLD_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_IIR_OVLD_ERR_IE_MASK) >> VAD_CTRL_IIR_OVLD_ERR_IE_SHIFT) 103 104 /* 105 * IIR_OVFL_ERR_IE (RW) 106 * 107 * IIR overflow error interrupt enable 108 */ 109 #define VAD_CTRL_IIR_OVFL_ERR_IE_MASK (0x2000U) 110 #define VAD_CTRL_IIR_OVFL_ERR_IE_SHIFT (13U) 111 #define VAD_CTRL_IIR_OVFL_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_IIR_OVFL_ERR_IE_SHIFT) & VAD_CTRL_IIR_OVFL_ERR_IE_MASK) 112 #define VAD_CTRL_IIR_OVFL_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_IIR_OVFL_ERR_IE_MASK) >> VAD_CTRL_IIR_OVFL_ERR_IE_SHIFT) 113 114 /* 115 * CIC_OVLD_ERR_IE (RW) 116 * 117 * CIC overload Interrupt Enable 118 */ 119 #define VAD_CTRL_CIC_OVLD_ERR_IE_MASK (0x1000U) 120 #define VAD_CTRL_CIC_OVLD_ERR_IE_SHIFT (12U) 121 #define VAD_CTRL_CIC_OVLD_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_CIC_OVLD_ERR_IE_SHIFT) & VAD_CTRL_CIC_OVLD_ERR_IE_MASK) 122 #define VAD_CTRL_CIC_OVLD_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_CIC_OVLD_ERR_IE_MASK) >> VAD_CTRL_CIC_OVLD_ERR_IE_SHIFT) 123 124 /* 125 * CIC_SAT_ERR_IE (RW) 126 * 127 * CIC saturation Interrupt Enable 128 */ 129 #define VAD_CTRL_CIC_SAT_ERR_IE_MASK (0x800U) 130 #define VAD_CTRL_CIC_SAT_ERR_IE_SHIFT (11U) 131 #define VAD_CTRL_CIC_SAT_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_CIC_SAT_ERR_IE_SHIFT) & VAD_CTRL_CIC_SAT_ERR_IE_MASK) 132 #define VAD_CTRL_CIC_SAT_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_CIC_SAT_ERR_IE_MASK) >> VAD_CTRL_CIC_SAT_ERR_IE_SHIFT) 133 134 /* 135 * MEMBUF_DISABLE (RW) 136 * 137 * asserted to disable membuf 138 */ 139 #define VAD_CTRL_MEMBUF_DISABLE_MASK (0x200U) 140 #define VAD_CTRL_MEMBUF_DISABLE_SHIFT (9U) 141 #define VAD_CTRL_MEMBUF_DISABLE_SET(x) (((uint32_t)(x) << VAD_CTRL_MEMBUF_DISABLE_SHIFT) & VAD_CTRL_MEMBUF_DISABLE_MASK) 142 #define VAD_CTRL_MEMBUF_DISABLE_GET(x) (((uint32_t)(x) & VAD_CTRL_MEMBUF_DISABLE_MASK) >> VAD_CTRL_MEMBUF_DISABLE_SHIFT) 143 144 /* 145 * FIFO_THRSH (RW) 146 * 147 * OFIFO threshold to generate ofifo_av (when fillings >= threshold) (fifo size: max 16 items, 16*32bits) 148 */ 149 #define VAD_CTRL_FIFO_THRSH_MASK (0x1E0U) 150 #define VAD_CTRL_FIFO_THRSH_SHIFT (5U) 151 #define VAD_CTRL_FIFO_THRSH_SET(x) (((uint32_t)(x) << VAD_CTRL_FIFO_THRSH_SHIFT) & VAD_CTRL_FIFO_THRSH_MASK) 152 #define VAD_CTRL_FIFO_THRSH_GET(x) (((uint32_t)(x) & VAD_CTRL_FIFO_THRSH_MASK) >> VAD_CTRL_FIFO_THRSH_SHIFT) 153 154 /* 155 * PDM_CLK_DIV_BYPASS (RW) 156 * 157 * asserted to bypass the pdm clock divider 158 */ 159 #define VAD_CTRL_PDM_CLK_DIV_BYPASS_MASK (0x10U) 160 #define VAD_CTRL_PDM_CLK_DIV_BYPASS_SHIFT (4U) 161 #define VAD_CTRL_PDM_CLK_DIV_BYPASS_SET(x) (((uint32_t)(x) << VAD_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) & VAD_CTRL_PDM_CLK_DIV_BYPASS_MASK) 162 #define VAD_CTRL_PDM_CLK_DIV_BYPASS_GET(x) (((uint32_t)(x) & VAD_CTRL_PDM_CLK_DIV_BYPASS_MASK) >> VAD_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) 163 164 /* 165 * PDM_CLK_OE (RW) 166 * 167 * pdm_clk_output_en 168 */ 169 #define VAD_CTRL_PDM_CLK_OE_MASK (0x8U) 170 #define VAD_CTRL_PDM_CLK_OE_SHIFT (3U) 171 #define VAD_CTRL_PDM_CLK_OE_SET(x) (((uint32_t)(x) << VAD_CTRL_PDM_CLK_OE_SHIFT) & VAD_CTRL_PDM_CLK_OE_MASK) 172 #define VAD_CTRL_PDM_CLK_OE_GET(x) (((uint32_t)(x) & VAD_CTRL_PDM_CLK_OE_MASK) >> VAD_CTRL_PDM_CLK_OE_SHIFT) 173 174 /* 175 * CH_POL (RW) 176 * 177 * Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. 178 */ 179 #define VAD_CTRL_CH_POL_MASK (0x6U) 180 #define VAD_CTRL_CH_POL_SHIFT (1U) 181 #define VAD_CTRL_CH_POL_SET(x) (((uint32_t)(x) << VAD_CTRL_CH_POL_SHIFT) & VAD_CTRL_CH_POL_MASK) 182 #define VAD_CTRL_CH_POL_GET(x) (((uint32_t)(x) & VAD_CTRL_CH_POL_MASK) >> VAD_CTRL_CH_POL_SHIFT) 183 184 /* 185 * CHNUM (RW) 186 * 187 * the number of channels to be stored in buffer. Asserted to enable 2 channels. 188 */ 189 #define VAD_CTRL_CHNUM_MASK (0x1U) 190 #define VAD_CTRL_CHNUM_SHIFT (0U) 191 #define VAD_CTRL_CHNUM_SET(x) (((uint32_t)(x) << VAD_CTRL_CHNUM_SHIFT) & VAD_CTRL_CHNUM_MASK) 192 #define VAD_CTRL_CHNUM_GET(x) (((uint32_t)(x) & VAD_CTRL_CHNUM_MASK) >> VAD_CTRL_CHNUM_SHIFT) 193 194 /* Bitfield definition for register: FILTCTRL */ 195 /* 196 * DECRATIO (RW) 197 * 198 * the decimation ratio of iir after CIC -1 199 * 2: means dec-by-3 200 */ 201 #define VAD_FILTCTRL_DECRATIO_MASK (0x700U) 202 #define VAD_FILTCTRL_DECRATIO_SHIFT (8U) 203 #define VAD_FILTCTRL_DECRATIO_SET(x) (((uint32_t)(x) << VAD_FILTCTRL_DECRATIO_SHIFT) & VAD_FILTCTRL_DECRATIO_MASK) 204 #define VAD_FILTCTRL_DECRATIO_GET(x) (((uint32_t)(x) & VAD_FILTCTRL_DECRATIO_MASK) >> VAD_FILTCTRL_DECRATIO_SHIFT) 205 206 /* 207 * IIR_SLOT_EN (RW) 208 * 209 * IIR slot enable 210 */ 211 #define VAD_FILTCTRL_IIR_SLOT_EN_MASK (0xFFU) 212 #define VAD_FILTCTRL_IIR_SLOT_EN_SHIFT (0U) 213 #define VAD_FILTCTRL_IIR_SLOT_EN_SET(x) (((uint32_t)(x) << VAD_FILTCTRL_IIR_SLOT_EN_SHIFT) & VAD_FILTCTRL_IIR_SLOT_EN_MASK) 214 #define VAD_FILTCTRL_IIR_SLOT_EN_GET(x) (((uint32_t)(x) & VAD_FILTCTRL_IIR_SLOT_EN_MASK) >> VAD_FILTCTRL_IIR_SLOT_EN_SHIFT) 215 216 /* Bitfield definition for register: DEC_CTRL0 */ 217 /* 218 * NOISE_TOL (RW) 219 * 220 * the value of amplitude for noise determination when calculationg ZCR 221 */ 222 #define VAD_DEC_CTRL0_NOISE_TOL_MASK (0xFFFF0000UL) 223 #define VAD_DEC_CTRL0_NOISE_TOL_SHIFT (16U) 224 #define VAD_DEC_CTRL0_NOISE_TOL_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL0_NOISE_TOL_SHIFT) & VAD_DEC_CTRL0_NOISE_TOL_MASK) 225 #define VAD_DEC_CTRL0_NOISE_TOL_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL0_NOISE_TOL_MASK) >> VAD_DEC_CTRL0_NOISE_TOL_SHIFT) 226 227 /* 228 * BLK_CFG (RW) 229 * 230 * asserted to have 3 sub-blocks, otherwise to have 2 sub-blocks 231 */ 232 #define VAD_DEC_CTRL0_BLK_CFG_MASK (0x200U) 233 #define VAD_DEC_CTRL0_BLK_CFG_SHIFT (9U) 234 #define VAD_DEC_CTRL0_BLK_CFG_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL0_BLK_CFG_SHIFT) & VAD_DEC_CTRL0_BLK_CFG_MASK) 235 #define VAD_DEC_CTRL0_BLK_CFG_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL0_BLK_CFG_MASK) >> VAD_DEC_CTRL0_BLK_CFG_SHIFT) 236 237 /* 238 * SUBBLK_LEN (RW) 239 * 240 * length of sub-block 241 */ 242 #define VAD_DEC_CTRL0_SUBBLK_LEN_MASK (0x1FFU) 243 #define VAD_DEC_CTRL0_SUBBLK_LEN_SHIFT (0U) 244 #define VAD_DEC_CTRL0_SUBBLK_LEN_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL0_SUBBLK_LEN_SHIFT) & VAD_DEC_CTRL0_SUBBLK_LEN_MASK) 245 #define VAD_DEC_CTRL0_SUBBLK_LEN_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL0_SUBBLK_LEN_MASK) >> VAD_DEC_CTRL0_SUBBLK_LEN_SHIFT) 246 247 /* Bitfield definition for register: DEC_CTRL1 */ 248 /* 249 * ZCR_HIGH (RW) 250 * 251 * ZCR high limit 252 */ 253 #define VAD_DEC_CTRL1_ZCR_HIGH_MASK (0x3FF800UL) 254 #define VAD_DEC_CTRL1_ZCR_HIGH_SHIFT (11U) 255 #define VAD_DEC_CTRL1_ZCR_HIGH_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL1_ZCR_HIGH_SHIFT) & VAD_DEC_CTRL1_ZCR_HIGH_MASK) 256 #define VAD_DEC_CTRL1_ZCR_HIGH_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL1_ZCR_HIGH_MASK) >> VAD_DEC_CTRL1_ZCR_HIGH_SHIFT) 257 258 /* 259 * ZCR_LOW (RW) 260 * 261 * ZCR low limit 262 */ 263 #define VAD_DEC_CTRL1_ZCR_LOW_MASK (0x7FFU) 264 #define VAD_DEC_CTRL1_ZCR_LOW_SHIFT (0U) 265 #define VAD_DEC_CTRL1_ZCR_LOW_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL1_ZCR_LOW_SHIFT) & VAD_DEC_CTRL1_ZCR_LOW_MASK) 266 #define VAD_DEC_CTRL1_ZCR_LOW_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL1_ZCR_LOW_MASK) >> VAD_DEC_CTRL1_ZCR_LOW_SHIFT) 267 268 /* Bitfield definition for register: DEC_CTRL2 */ 269 /* 270 * AMP_HIGH (RW) 271 * 272 * amplitude high limit 273 */ 274 #define VAD_DEC_CTRL2_AMP_HIGH_MASK (0xFFFF0000UL) 275 #define VAD_DEC_CTRL2_AMP_HIGH_SHIFT (16U) 276 #define VAD_DEC_CTRL2_AMP_HIGH_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL2_AMP_HIGH_SHIFT) & VAD_DEC_CTRL2_AMP_HIGH_MASK) 277 #define VAD_DEC_CTRL2_AMP_HIGH_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL2_AMP_HIGH_MASK) >> VAD_DEC_CTRL2_AMP_HIGH_SHIFT) 278 279 /* 280 * AMP_LOW (RW) 281 * 282 * amplitude low limit 283 */ 284 #define VAD_DEC_CTRL2_AMP_LOW_MASK (0xFFFFU) 285 #define VAD_DEC_CTRL2_AMP_LOW_SHIFT (0U) 286 #define VAD_DEC_CTRL2_AMP_LOW_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL2_AMP_LOW_SHIFT) & VAD_DEC_CTRL2_AMP_LOW_MASK) 287 #define VAD_DEC_CTRL2_AMP_LOW_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL2_AMP_LOW_MASK) >> VAD_DEC_CTRL2_AMP_LOW_SHIFT) 288 289 /* Bitfield definition for register: ST */ 290 /* 291 * VAD (W1C) 292 * 293 * VAD event found 294 */ 295 #define VAD_ST_VAD_MASK (0x80U) 296 #define VAD_ST_VAD_SHIFT (7U) 297 #define VAD_ST_VAD_SET(x) (((uint32_t)(x) << VAD_ST_VAD_SHIFT) & VAD_ST_VAD_MASK) 298 #define VAD_ST_VAD_GET(x) (((uint32_t)(x) & VAD_ST_VAD_MASK) >> VAD_ST_VAD_SHIFT) 299 300 /* 301 * OFIFO_AV (RO) 302 * 303 * OFIFO data available 304 */ 305 #define VAD_ST_OFIFO_AV_MASK (0x40U) 306 #define VAD_ST_OFIFO_AV_SHIFT (6U) 307 #define VAD_ST_OFIFO_AV_GET(x) (((uint32_t)(x) & VAD_ST_OFIFO_AV_MASK) >> VAD_ST_OFIFO_AV_SHIFT) 308 309 /* 310 * MEMBUF_EMPTY (W1C) 311 * 312 * Buf empty 313 */ 314 #define VAD_ST_MEMBUF_EMPTY_MASK (0x20U) 315 #define VAD_ST_MEMBUF_EMPTY_SHIFT (5U) 316 #define VAD_ST_MEMBUF_EMPTY_SET(x) (((uint32_t)(x) << VAD_ST_MEMBUF_EMPTY_SHIFT) & VAD_ST_MEMBUF_EMPTY_MASK) 317 #define VAD_ST_MEMBUF_EMPTY_GET(x) (((uint32_t)(x) & VAD_ST_MEMBUF_EMPTY_MASK) >> VAD_ST_MEMBUF_EMPTY_SHIFT) 318 319 /* 320 * OFIFO_OVFL (W1C) 321 * 322 * OFIFO overflow 323 */ 324 #define VAD_ST_OFIFO_OVFL_MASK (0x10U) 325 #define VAD_ST_OFIFO_OVFL_SHIFT (4U) 326 #define VAD_ST_OFIFO_OVFL_SET(x) (((uint32_t)(x) << VAD_ST_OFIFO_OVFL_SHIFT) & VAD_ST_OFIFO_OVFL_MASK) 327 #define VAD_ST_OFIFO_OVFL_GET(x) (((uint32_t)(x) & VAD_ST_OFIFO_OVFL_MASK) >> VAD_ST_OFIFO_OVFL_SHIFT) 328 329 /* 330 * IIR_OVLD (W1C) 331 * 332 * IIR overloading 333 */ 334 #define VAD_ST_IIR_OVLD_MASK (0x8U) 335 #define VAD_ST_IIR_OVLD_SHIFT (3U) 336 #define VAD_ST_IIR_OVLD_SET(x) (((uint32_t)(x) << VAD_ST_IIR_OVLD_SHIFT) & VAD_ST_IIR_OVLD_MASK) 337 #define VAD_ST_IIR_OVLD_GET(x) (((uint32_t)(x) & VAD_ST_IIR_OVLD_MASK) >> VAD_ST_IIR_OVLD_SHIFT) 338 339 /* 340 * IIR_OVFL (W1C) 341 * 342 * IIR oberflow 343 */ 344 #define VAD_ST_IIR_OVFL_MASK (0x4U) 345 #define VAD_ST_IIR_OVFL_SHIFT (2U) 346 #define VAD_ST_IIR_OVFL_SET(x) (((uint32_t)(x) << VAD_ST_IIR_OVFL_SHIFT) & VAD_ST_IIR_OVFL_MASK) 347 #define VAD_ST_IIR_OVFL_GET(x) (((uint32_t)(x) & VAD_ST_IIR_OVFL_MASK) >> VAD_ST_IIR_OVFL_SHIFT) 348 349 /* 350 * CIC_OVLD_ERR (W1C) 351 * 352 * CIC overload 353 */ 354 #define VAD_ST_CIC_OVLD_ERR_MASK (0x2U) 355 #define VAD_ST_CIC_OVLD_ERR_SHIFT (1U) 356 #define VAD_ST_CIC_OVLD_ERR_SET(x) (((uint32_t)(x) << VAD_ST_CIC_OVLD_ERR_SHIFT) & VAD_ST_CIC_OVLD_ERR_MASK) 357 #define VAD_ST_CIC_OVLD_ERR_GET(x) (((uint32_t)(x) & VAD_ST_CIC_OVLD_ERR_MASK) >> VAD_ST_CIC_OVLD_ERR_SHIFT) 358 359 /* 360 * CIC_SAT_ERR (W1C) 361 * 362 * CIC saturation 363 */ 364 #define VAD_ST_CIC_SAT_ERR_MASK (0x1U) 365 #define VAD_ST_CIC_SAT_ERR_SHIFT (0U) 366 #define VAD_ST_CIC_SAT_ERR_SET(x) (((uint32_t)(x) << VAD_ST_CIC_SAT_ERR_SHIFT) & VAD_ST_CIC_SAT_ERR_MASK) 367 #define VAD_ST_CIC_SAT_ERR_GET(x) (((uint32_t)(x) & VAD_ST_CIC_SAT_ERR_MASK) >> VAD_ST_CIC_SAT_ERR_SHIFT) 368 369 /* Bitfield definition for register: OFIFO */ 370 /* 371 * D (RW) 372 * 373 * The PCM data. 374 * When there is only one channel, the samples are from Ch0, and the 2 samples in the 32-bits are: bit [31:16]: the samples earlier in time ([T-1]). Bit [15:0]: the samples later in time ([T]). 375 * When there is two channels, the samples in the 32-bits are: bit [31:16]: the samples belong to Ch 1 (when ch_pol[1:0]==2, the data is captured at the positive part of the pdm clk). bit [15:0]: the samples belong to Ch 0 (when ch_pol[1:0]==2, the data is captured at the negtive part of the pdm clk). 376 */ 377 #define VAD_OFIFO_D_MASK (0xFFFFFFFFUL) 378 #define VAD_OFIFO_D_SHIFT (0U) 379 #define VAD_OFIFO_D_SET(x) (((uint32_t)(x) << VAD_OFIFO_D_SHIFT) & VAD_OFIFO_D_MASK) 380 #define VAD_OFIFO_D_GET(x) (((uint32_t)(x) & VAD_OFIFO_D_MASK) >> VAD_OFIFO_D_SHIFT) 381 382 /* Bitfield definition for register: RUN */ 383 /* 384 * SFTRST (RW) 385 * 386 * software reset. Self-clear 387 */ 388 #define VAD_RUN_SFTRST_MASK (0x2U) 389 #define VAD_RUN_SFTRST_SHIFT (1U) 390 #define VAD_RUN_SFTRST_SET(x) (((uint32_t)(x) << VAD_RUN_SFTRST_SHIFT) & VAD_RUN_SFTRST_MASK) 391 #define VAD_RUN_SFTRST_GET(x) (((uint32_t)(x) & VAD_RUN_SFTRST_MASK) >> VAD_RUN_SFTRST_SHIFT) 392 393 /* 394 * VAD_EN (RW) 395 * 396 * module enable 397 */ 398 #define VAD_RUN_VAD_EN_MASK (0x1U) 399 #define VAD_RUN_VAD_EN_SHIFT (0U) 400 #define VAD_RUN_VAD_EN_SET(x) (((uint32_t)(x) << VAD_RUN_VAD_EN_SHIFT) & VAD_RUN_VAD_EN_MASK) 401 #define VAD_RUN_VAD_EN_GET(x) (((uint32_t)(x) & VAD_RUN_VAD_EN_MASK) >> VAD_RUN_VAD_EN_SHIFT) 402 403 /* Bitfield definition for register: OFIFO_CTRL */ 404 /* 405 * EN (RW) 406 * 407 * Asserted to enable OFIFO 408 */ 409 #define VAD_OFIFO_CTRL_EN_MASK (0x1U) 410 #define VAD_OFIFO_CTRL_EN_SHIFT (0U) 411 #define VAD_OFIFO_CTRL_EN_SET(x) (((uint32_t)(x) << VAD_OFIFO_CTRL_EN_SHIFT) & VAD_OFIFO_CTRL_EN_MASK) 412 #define VAD_OFIFO_CTRL_EN_GET(x) (((uint32_t)(x) & VAD_OFIFO_CTRL_EN_MASK) >> VAD_OFIFO_CTRL_EN_SHIFT) 413 414 /* Bitfield definition for register: CIC_CFG */ 415 /* 416 * POST_SCALE (RW) 417 * 418 * the shift value after CIC results. 419 */ 420 #define VAD_CIC_CFG_POST_SCALE_MASK (0xFC00U) 421 #define VAD_CIC_CFG_POST_SCALE_SHIFT (10U) 422 #define VAD_CIC_CFG_POST_SCALE_SET(x) (((uint32_t)(x) << VAD_CIC_CFG_POST_SCALE_SHIFT) & VAD_CIC_CFG_POST_SCALE_MASK) 423 #define VAD_CIC_CFG_POST_SCALE_GET(x) (((uint32_t)(x) & VAD_CIC_CFG_POST_SCALE_MASK) >> VAD_CIC_CFG_POST_SCALE_SHIFT) 424 425 /* Bitfield definition for register array: COEF */ 426 /* 427 * VAL (RO) 428 * 429 * The current detected short time energy 430 */ 431 #define VAD_COEF_VAL_MASK (0xFFFFFFFFUL) 432 #define VAD_COEF_VAL_SHIFT (0U) 433 #define VAD_COEF_VAL_GET(x) (((uint32_t)(x) & VAD_COEF_VAL_MASK) >> VAD_COEF_VAL_SHIFT) 434 435 436 437 /* COEF register group index macro definition */ 438 #define VAD_COEF_STE_ACT (0UL) 439 440 441 #endif /* HPM_VAD_H */ 442