1 /* 2 * include/linux/amlogic/media/registers/regs/vdec2_regs.h 3 * 4 * Copyright (C) 2017 Amlogic, Inc. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 */ 17 18 #ifndef VDEC2_REGS_HEADER_ 19 #define VDEC2_REGS_HEADER_ 20 21 #define VDEC2_ASSIST_MMC_CTRL0 0x2001 22 #define VDEC2_ASSIST_MMC_CTRL1 0x2002 23 #define VDEC2_ASSIST_AMR1_INT0 0x2025 24 #define VDEC2_ASSIST_AMR1_INT1 0x2026 25 #define VDEC2_ASSIST_AMR1_INT2 0x2027 26 #define VDEC2_ASSIST_AMR1_INT3 0x2028 27 #define VDEC2_ASSIST_AMR1_INT4 0x2029 28 #define VDEC2_ASSIST_AMR1_INT5 0x202a 29 #define VDEC2_ASSIST_AMR1_INT6 0x202b 30 #define VDEC2_ASSIST_AMR1_INT7 0x202c 31 #define VDEC2_ASSIST_AMR1_INT8 0x202d 32 #define VDEC2_ASSIST_AMR1_INT9 0x202e 33 #define VDEC2_ASSIST_AMR1_INTA 0x202f 34 #define VDEC2_ASSIST_AMR1_INTB 0x2030 35 #define VDEC2_ASSIST_AMR1_INTC 0x2031 36 #define VDEC2_ASSIST_AMR1_INTD 0x2032 37 #define VDEC2_ASSIST_AMR1_INTE 0x2033 38 #define VDEC2_ASSIST_AMR1_INTF 0x2034 39 #define VDEC2_ASSIST_AMR2_INT0 0x2035 40 #define VDEC2_ASSIST_AMR2_INT1 0x2036 41 #define VDEC2_ASSIST_AMR2_INT2 0x2037 42 #define VDEC2_ASSIST_AMR2_INT3 0x2038 43 #define VDEC2_ASSIST_AMR2_INT4 0x2039 44 #define VDEC2_ASSIST_AMR2_INT5 0x203a 45 #define VDEC2_ASSIST_AMR2_INT6 0x203b 46 #define VDEC2_ASSIST_AMR2_INT7 0x203c 47 #define VDEC2_ASSIST_AMR2_INT8 0x203d 48 #define VDEC2_ASSIST_AMR2_INT9 0x203e 49 #define VDEC2_ASSIST_AMR2_INTA 0x203f 50 #define VDEC2_ASSIST_AMR2_INTB 0x2040 51 #define VDEC2_ASSIST_AMR2_INTC 0x2041 52 #define VDEC2_ASSIST_AMR2_INTD 0x2042 53 #define VDEC2_ASSIST_AMR2_INTE 0x2043 54 #define VDEC2_ASSIST_AMR2_INTF 0x2044 55 #define VDEC2_ASSIST_MBX_SSEL 0x2045 56 #define VDEC2_ASSIST_TIMER0_LO 0x2060 57 #define VDEC2_ASSIST_TIMER0_HI 0x2061 58 #define VDEC2_ASSIST_TIMER1_LO 0x2062 59 #define VDEC2_ASSIST_TIMER1_HI 0x2063 60 #define VDEC2_ASSIST_DMA_INT 0x2064 61 #define VDEC2_ASSIST_DMA_INT_MSK 0x2065 62 #define VDEC2_ASSIST_DMA_INT2 0x2066 63 #define VDEC2_ASSIST_DMA_INT_MSK2 0x2067 64 #define VDEC2_ASSIST_MBOX0_IRQ_REG 0x2070 65 #define VDEC2_ASSIST_MBOX0_CLR_REG 0x2071 66 #define VDEC2_ASSIST_MBOX0_MASK 0x2072 67 #define VDEC2_ASSIST_MBOX0_FIQ_SEL 0x2073 68 #define VDEC2_ASSIST_MBOX1_IRQ_REG 0x2074 69 #define VDEC2_ASSIST_MBOX1_CLR_REG 0x2075 70 #define VDEC2_ASSIST_MBOX1_MASK 0x2076 71 #define VDEC2_ASSIST_MBOX1_FIQ_SEL 0x2077 72 #define VDEC2_ASSIST_MBOX2_IRQ_REG 0x2078 73 #define VDEC2_ASSIST_MBOX2_CLR_REG 0x2079 74 #define VDEC2_ASSIST_MBOX2_MASK 0x207a 75 #define VDEC2_ASSIST_MBOX2_FIQ_SEL 0x207b 76 77 78 #define VDEC2_MSP 0x2300 79 #define VDEC2_MPSR 0x2301 80 #define VDEC2_MINT_VEC_BASE 0x2302 81 #define VDEC2_MCPU_INTR_GRP 0x2303 82 #define VDEC2_MCPU_INTR_MSK 0x2304 83 #define VDEC2_MCPU_INTR_REQ 0x2305 84 #define VDEC2_MPC_P 0x2306 85 #define VDEC2_MPC_D 0x2307 86 #define VDEC2_MPC_E 0x2308 87 #define VDEC2_MPC_W 0x2309 88 #define VDEC2_MINDEX0_REG 0x230a 89 #define VDEC2_MINDEX1_REG 0x230b 90 #define VDEC2_MINDEX2_REG 0x230c 91 #define VDEC2_MINDEX3_REG 0x230d 92 #define VDEC2_MINDEX4_REG 0x230e 93 #define VDEC2_MINDEX5_REG 0x230f 94 #define VDEC2_MINDEX6_REG 0x2310 95 #define VDEC2_MINDEX7_REG 0x2311 96 #define VDEC2_MMIN_REG 0x2312 97 #define VDEC2_MMAX_REG 0x2313 98 #define VDEC2_MBREAK0_REG 0x2314 99 #define VDEC2_MBREAK1_REG 0x2315 100 #define VDEC2_MBREAK2_REG 0x2316 101 #define VDEC2_MBREAK3_REG 0x2317 102 #define VDEC2_MBREAK_TYPE 0x2318 103 #define VDEC2_MBREAK_CTRL 0x2319 104 #define VDEC2_MBREAK_STAUTS 0x231a 105 #define VDEC2_MDB_ADDR_REG 0x231b 106 #define VDEC2_MDB_DATA_REG 0x231c 107 #define VDEC2_MDB_CTRL 0x231d 108 #define VDEC2_MSFTINT0 0x231e 109 #define VDEC2_MSFTINT1 0x231f 110 #define VDEC2_CSP 0x2320 111 #define VDEC2_CPSR 0x2321 112 #define VDEC2_CINT_VEC_BASE 0x2322 113 #define VDEC2_CCPU_INTR_GRP 0x2323 114 #define VDEC2_CCPU_INTR_MSK 0x2324 115 #define VDEC2_CCPU_INTR_REQ 0x2325 116 #define VDEC2_CPC_P 0x2326 117 #define VDEC2_CPC_D 0x2327 118 #define VDEC2_CPC_E 0x2328 119 #define VDEC2_CPC_W 0x2329 120 #define VDEC2_CINDEX0_REG 0x232a 121 #define VDEC2_CINDEX1_REG 0x232b 122 #define VDEC2_CINDEX2_REG 0x232c 123 #define VDEC2_CINDEX3_REG 0x232d 124 #define VDEC2_CINDEX4_REG 0x232e 125 #define VDEC2_CINDEX5_REG 0x232f 126 #define VDEC2_CINDEX6_REG 0x2330 127 #define VDEC2_CINDEX7_REG 0x2331 128 #define VDEC2_CMIN_REG 0x2332 129 #define VDEC2_CMAX_REG 0x2333 130 #define VDEC2_CBREAK0_REG 0x2334 131 #define VDEC2_CBREAK1_REG 0x2335 132 #define VDEC2_CBREAK2_REG 0x2336 133 #define VDEC2_CBREAK3_REG 0x2337 134 #define VDEC2_CBREAK_TYPE 0x2338 135 #define VDEC2_CBREAK_CTRL 0x2339 136 #define VDEC2_CBREAK_STAUTS 0x233a 137 #define VDEC2_CDB_ADDR_REG 0x233b 138 #define VDEC2_CDB_DATA_REG 0x233c 139 #define VDEC2_CDB_CTRL 0x233d 140 #define VDEC2_CSFTINT0 0x233e 141 #define VDEC2_CSFTINT1 0x233f 142 #define VDEC2_IMEM_DMA_CTRL 0x2340 143 #define VDEC2_IMEM_DMA_ADR 0x2341 144 #define VDEC2_IMEM_DMA_COUNT 0x2342 145 #define VDEC2_WRRSP_IMEM 0x2343 146 #define VDEC2_LMEM_DMA_CTRL 0x2350 147 #define VDEC2_LMEM_DMA_ADR 0x2351 148 #define VDEC2_LMEM_DMA_COUNT 0x2352 149 #define VDEC2_WRRSP_LMEM 0x2353 150 #define VDEC2_MAC_CTRL1 0x2360 151 #define VDEC2_ACC0REG1 0x2361 152 #define VDEC2_ACC1REG1 0x2362 153 #define VDEC2_MAC_CTRL2 0x2370 154 #define VDEC2_ACC0REG2 0x2371 155 #define VDEC2_ACC1REG2 0x2372 156 #define VDEC2_CPU_TRACE 0x2380 157 158 159 160 #define VDEC2_MC_CTRL_REG 0x2900 161 #define VDEC2_MC_MB_INFO 0x2901 162 #define VDEC2_MC_PIC_INFO 0x2902 163 #define VDEC2_MC_HALF_PEL_ONE 0x2903 164 #define VDEC2_MC_HALF_PEL_TWO 0x2904 165 #define VDEC2_POWER_CTL_MC 0x2905 166 #define VDEC2_MC_CMD 0x2906 167 #define VDEC2_MC_CTRL0 0x2907 168 #define VDEC2_MC_PIC_W_H 0x2908 169 #define VDEC2_MC_STATUS0 0x2909 170 #define VDEC2_MC_STATUS1 0x290a 171 #define VDEC2_MC_CTRL1 0x290b 172 #define VDEC2_MC_MIX_RATIO0 0x290c 173 #define VDEC2_MC_MIX_RATIO1 0x290d 174 #define VDEC2_MC_DP_MB_XY 0x290e 175 #define VDEC2_MC_OM_MB_XY 0x290f 176 #define VDEC2_PSCALE_RST 0x2910 177 #define VDEC2_PSCALE_CTRL 0x2911 178 #define VDEC2_PSCALE_PICI_W 0x2912 179 #define VDEC2_PSCALE_PICI_H 0x2913 180 #define VDEC2_PSCALE_PICO_W 0x2914 181 #define VDEC2_PSCALE_PICO_H 0x2915 182 #define VDEC2_PSCALE_PICO_START_X 0x2916 183 #define VDEC2_PSCALE_PICO_START_Y 0x2917 184 #define VDEC2_PSCALE_DUMMY 0x2918 185 #define VDEC2_PSCALE_FILT0_COEF0 0x2919 186 #define VDEC2_PSCALE_FILT0_COEF1 0x291a 187 #define VDEC2_PSCALE_CMD_CTRL 0x291b 188 #define VDEC2_PSCALE_CMD_BLK_X 0x291c 189 #define VDEC2_PSCALE_CMD_BLK_Y 0x291d 190 #define VDEC2_PSCALE_STATUS 0x291e 191 #define VDEC2_PSCALE_BMEM_ADDR 0x291f 192 #define VDEC2_PSCALE_BMEM_DAT 0x2920 193 #define VDEC2_PSCALE_DRAM_BUF_CTRL 0x2921 194 #define VDEC2_PSCALE_MCMD_CTRL 0x2922 195 #define VDEC2_PSCALE_MCMD_XSIZE 0x2923 196 #define VDEC2_PSCALE_MCMD_YSIZE 0x2924 197 #define VDEC2_PSCALE_RBUF_START_BLKX 0x2925 198 #define VDEC2_PSCALE_RBUF_START_BLKY 0x2926 199 #define VDEC2_PSCALE_PICO_SHIFT_XY 0x2928 200 #define VDEC2_PSCALE_CTRL1 0x2929 201 #define VDEC2_PSCALE_SRCKEY_CTRL0 0x292a 202 #define VDEC2_PSCALE_SRCKEY_CTRL1 0x292b 203 #define VDEC2_PSCALE_CANVAS_RD_ADDR 0x292c 204 #define VDEC2_PSCALE_CANVAS_WR_ADDR 0x292d 205 #define VDEC2_PSCALE_CTRL2 0x292e 206 /*add from M8M2*/ 207 #define VDEC2_HDEC_MC_OMEM_AUTO 0x2930 208 #define VDEC2_HDEC_MC_MBRIGHT_IDX 0x2931 209 #define VDEC2_HDEC_MC_MBRIGHT_RD 0x2932 210 /**/ 211 #define VDEC2_MC_MPORT_CTRL 0x2940 212 #define VDEC2_MC_MPORT_DAT 0x2941 213 #define VDEC2_MC_WT_PRED_CTRL 0x2942 214 #define VDEC2_MC_MBBOT_ST_EVEN_ADDR 0x2944 215 #define VDEC2_MC_MBBOT_ST_ODD_ADDR 0x2945 216 #define VDEC2_MC_DPDN_MB_XY 0x2946 217 #define VDEC2_MC_OMDN_MB_XY 0x2947 218 #define VDEC2_MC_HCMDBUF_H 0x2948 219 #define VDEC2_MC_HCMDBUF_L 0x2949 220 #define VDEC2_MC_HCMD_H 0x294a 221 #define VDEC2_MC_HCMD_L 0x294b 222 #define VDEC2_MC_IDCT_DAT 0x294c 223 #define VDEC2_MC_CTRL_GCLK_CTRL 0x294d 224 #define VDEC2_MC_OTHER_GCLK_CTRL 0x294e 225 #define VDEC2_MC_CTRL2 0x294f 226 #define VDEC2_MDEC_PIC_DC_CTRL 0x298e 227 #define VDEC2_MDEC_PIC_DC_STATUS 0x298f 228 #define VDEC2_ANC0_CANVAS_ADDR 0x2990 229 #define VDEC2_ANC1_CANVAS_ADDR 0x2991 230 #define VDEC2_ANC2_CANVAS_ADDR 0x2992 231 #define VDEC2_ANC3_CANVAS_ADDR 0x2993 232 #define VDEC2_ANC4_CANVAS_ADDR 0x2994 233 #define VDEC2_ANC5_CANVAS_ADDR 0x2995 234 #define VDEC2_ANC6_CANVAS_ADDR 0x2996 235 #define VDEC2_ANC7_CANVAS_ADDR 0x2997 236 #define VDEC2_ANC8_CANVAS_ADDR 0x2998 237 #define VDEC2_ANC9_CANVAS_ADDR 0x2999 238 #define VDEC2_ANC10_CANVAS_ADDR 0x299a 239 #define VDEC2_ANC11_CANVAS_ADDR 0x299b 240 #define VDEC2_ANC12_CANVAS_ADDR 0x299c 241 #define VDEC2_ANC13_CANVAS_ADDR 0x299d 242 #define VDEC2_ANC14_CANVAS_ADDR 0x299e 243 #define VDEC2_ANC15_CANVAS_ADDR 0x299f 244 #define VDEC2_ANC16_CANVAS_ADDR 0x29a0 245 #define VDEC2_ANC17_CANVAS_ADDR 0x29a1 246 #define VDEC2_ANC18_CANVAS_ADDR 0x29a2 247 #define VDEC2_ANC19_CANVAS_ADDR 0x29a3 248 #define VDEC2_ANC20_CANVAS_ADDR 0x29a4 249 #define VDEC2_ANC21_CANVAS_ADDR 0x29a5 250 #define VDEC2_ANC22_CANVAS_ADDR 0x29a6 251 #define VDEC2_ANC23_CANVAS_ADDR 0x29a7 252 #define VDEC2_ANC24_CANVAS_ADDR 0x29a8 253 #define VDEC2_ANC25_CANVAS_ADDR 0x29a9 254 #define VDEC2_ANC26_CANVAS_ADDR 0x29aa 255 #define VDEC2_ANC27_CANVAS_ADDR 0x29ab 256 #define VDEC2_ANC28_CANVAS_ADDR 0x29ac 257 #define VDEC2_ANC29_CANVAS_ADDR 0x29ad 258 #define VDEC2_ANC30_CANVAS_ADDR 0x29ae 259 #define VDEC2_ANC31_CANVAS_ADDR 0x29af 260 #define VDEC2_DBKR_CANVAS_ADDR 0x29b0 261 #define VDEC2_DBKW_CANVAS_ADDR 0x29b1 262 #define VDEC2_REC_CANVAS_ADDR 0x29b2 263 #define VDEC2_CURR_CANVAS_CTRL 0x29b3 264 #define VDEC2_MDEC_PIC_DC_THRESH 0x29b8 265 #define VDEC2_MDEC_PICR_BUF_STATUS 0x29b9 266 #define VDEC2_MDEC_PICW_BUF_STATUS 0x29ba 267 #define VDEC2_MCW_DBLK_WRRSP_CNT 0x29bb 268 #define VDEC2_MC_MBBOT_WRRSP_CNT 0x29bc 269 #define VDEC2_MDEC_PICW_BUF2_STATUS 0x29bd 270 #define VDEC2_WRRSP_FIFO_PICW_DBK 0x29be 271 #define VDEC2_WRRSP_FIFO_PICW_MC 0x29bf 272 #define VDEC2_AV_SCRATCH_0 0x29c0 273 #define VDEC2_AV_SCRATCH_1 0x29c1 274 #define VDEC2_AV_SCRATCH_2 0x29c2 275 #define VDEC2_AV_SCRATCH_3 0x29c3 276 #define VDEC2_AV_SCRATCH_4 0x29c4 277 #define VDEC2_AV_SCRATCH_5 0x29c5 278 #define VDEC2_AV_SCRATCH_6 0x29c6 279 #define VDEC2_AV_SCRATCH_7 0x29c7 280 #define VDEC2_AV_SCRATCH_8 0x29c8 281 #define VDEC2_AV_SCRATCH_9 0x29c9 282 #define VDEC2_AV_SCRATCH_A 0x29ca 283 #define VDEC2_AV_SCRATCH_B 0x29cb 284 #define VDEC2_AV_SCRATCH_C 0x29cc 285 #define VDEC2_AV_SCRATCH_D 0x29cd 286 #define VDEC2_AV_SCRATCH_E 0x29ce 287 #define VDEC2_AV_SCRATCH_F 0x29cf 288 #define VDEC2_AV_SCRATCH_G 0x29d0 289 #define VDEC2_AV_SCRATCH_H 0x29d1 290 #define VDEC2_AV_SCRATCH_I 0x29d2 291 #define VDEC2_AV_SCRATCH_J 0x29d3 292 #define VDEC2_AV_SCRATCH_K 0x29d4 293 #define VDEC2_AV_SCRATCH_L 0x29d5 294 #define VDEC2_AV_SCRATCH_M 0x29d6 295 #define VDEC2_AV_SCRATCH_N 0x29d7 296 #define VDEC2_WRRSP_CO_MB 0x29d8 297 #define VDEC2_WRRSP_DCAC 0x29d9 298 /*add from M8M2*/ 299 #define VDEC2_WRRSP_VLD 0x29da 300 #define VDEC2_MDEC_DOUBLEW_CFG0 0x29db 301 #define VDEC2_MDEC_DOUBLEW_CFG1 0x29dc 302 #define VDEC2_MDEC_DOUBLEW_CFG2 0x29dd 303 #define VDEC2_MDEC_DOUBLEW_CFG3 0x29de 304 #define VDEC2_MDEC_DOUBLEW_CFG4 0x29df 305 #define VDEC2_MDEC_DOUBLEW_CFG5 0x29e0 306 #define VDEC2_MDEC_DOUBLEW_CFG6 0x29e1 307 #define VDEC2_MDEC_DOUBLEW_CFG7 0x29e2 308 #define VDEC2_MDEC_DOUBLEW_STATUS 0x29e3 309 /**/ 310 #define VDEC2_DBLK_RST 0x2950 311 #define VDEC2_DBLK_CTRL 0x2951 312 #define VDEC2_DBLK_MB_WID_HEIGHT 0x2952 313 #define VDEC2_DBLK_STATUS 0x2953 314 #define VDEC2_DBLK_CMD_CTRL 0x2954 315 #define VDEC2_DBLK_MB_XY 0x2955 316 #define VDEC2_DBLK_QP 0x2956 317 #define VDEC2_DBLK_Y_BHFILT 0x2957 318 #define VDEC2_DBLK_Y_BHFILT_HIGH 0x2958 319 #define VDEC2_DBLK_Y_BVFILT 0x2959 320 #define VDEC2_DBLK_CB_BFILT 0x295a 321 #define VDEC2_DBLK_CR_BFILT 0x295b 322 #define VDEC2_DBLK_Y_HFILT 0x295c 323 #define VDEC2_DBLK_Y_HFILT_HIGH 0x295d 324 #define VDEC2_DBLK_Y_VFILT 0x295e 325 #define VDEC2_DBLK_CB_FILT 0x295f 326 #define VDEC2_DBLK_CR_FILT 0x2960 327 #define VDEC2_DBLK_BETAX_QP_SEL 0x2961 328 #define VDEC2_DBLK_CLIP_CTRL0 0x2962 329 #define VDEC2_DBLK_CLIP_CTRL1 0x2963 330 #define VDEC2_DBLK_CLIP_CTRL2 0x2964 331 #define VDEC2_DBLK_CLIP_CTRL3 0x2965 332 #define VDEC2_DBLK_CLIP_CTRL4 0x2966 333 #define VDEC2_DBLK_CLIP_CTRL5 0x2967 334 #define VDEC2_DBLK_CLIP_CTRL6 0x2968 335 #define VDEC2_DBLK_CLIP_CTRL7 0x2969 336 #define VDEC2_DBLK_CLIP_CTRL8 0x296a 337 #define VDEC2_DBLK_STATUS1 0x296b 338 #define VDEC2_DBLK_GCLK_FREE 0x296c 339 #define VDEC2_DBLK_GCLK_OFF 0x296d 340 #define VDEC2_DBLK_AVSFLAGS 0x296e 341 #define VDEC2_DBLK_CBPY 0x2970 342 #define VDEC2_DBLK_CBPY_ADJ 0x2971 343 #define VDEC2_DBLK_CBPC 0x2972 344 #define VDEC2_DBLK_CBPC_ADJ 0x2973 345 #define VDEC2_DBLK_VHMVD 0x2974 346 #define VDEC2_DBLK_STRONG 0x2975 347 #define VDEC2_DBLK_RV8_QUANT 0x2976 348 #define VDEC2_DBLK_CBUS_HCMD2 0x2977 349 #define VDEC2_DBLK_CBUS_HCMD1 0x2978 350 #define VDEC2_DBLK_CBUS_HCMD0 0x2979 351 #define VDEC2_DBLK_VLD_HCMD2 0x297a 352 #define VDEC2_DBLK_VLD_HCMD1 0x297b 353 #define VDEC2_DBLK_VLD_HCMD0 0x297c 354 #define VDEC2_DBLK_OST_YBASE 0x297d 355 #define VDEC2_DBLK_OST_CBCRDIFF 0x297e 356 #define VDEC2_DBLK_CTRL1 0x297f 357 #define VDEC2_MCRCC_CTL1 0x2980 358 #define VDEC2_MCRCC_CTL2 0x2981 359 #define VDEC2_MCRCC_CTL3 0x2982 360 #define VDEC2_GCLK_EN 0x2983 361 #define VDEC2_MDEC_SW_RESET 0x2984 362 363 #define VDEC2_VLD_STATUS_CTRL 0x2c00 364 #define VDEC2_MPEG1_2_REG 0x2c01 365 #define VDEC2_F_CODE_REG 0x2c02 366 #define VDEC2_PIC_HEAD_INFO 0x2c03 367 #define VDEC2_SLICE_VER_POS_PIC_TYPE 0x2c04 368 #define VDEC2_QP_VALUE_REG 0x2c05 369 #define VDEC2_MBA_INC 0x2c06 370 #define VDEC2_MB_MOTION_MODE 0x2c07 371 #define VDEC2_POWER_CTL_VLD 0x2c08 372 #define VDEC2_MB_WIDTH 0x2c09 373 #define VDEC2_SLICE_QP 0x2c0a 374 #define VDEC2_PRE_START_CODE 0x2c0b 375 #define VDEC2_SLICE_START_BYTE_01 0x2c0c 376 #define VDEC2_SLICE_START_BYTE_23 0x2c0d 377 #define VDEC2_RESYNC_MARKER_LENGTH 0x2c0e 378 #define VDEC2_DECODER_BUFFER_INFO 0x2c0f 379 #define VDEC2_FST_FOR_MV_X 0x2c10 380 #define VDEC2_FST_FOR_MV_Y 0x2c11 381 #define VDEC2_SCD_FOR_MV_X 0x2c12 382 #define VDEC2_SCD_FOR_MV_Y 0x2c13 383 #define VDEC2_FST_BAK_MV_X 0x2c14 384 #define VDEC2_FST_BAK_MV_Y 0x2c15 385 #define VDEC2_SCD_BAK_MV_X 0x2c16 386 #define VDEC2_SCD_BAK_MV_Y 0x2c17 387 #define VDEC2_VLD_DECODE_CONTROL 0x2c18 388 #define VDEC2_VLD_REVERVED_19 0x2c19 389 #define VDEC2_VIFF_BIT_CNT 0x2c1a 390 #define VDEC2_BYTE_ALIGN_PEAK_HI 0x2c1b 391 #define VDEC2_BYTE_ALIGN_PEAK_LO 0x2c1c 392 #define VDEC2_NEXT_ALIGN_PEAK 0x2c1d 393 #define VDEC2_VC1_CONTROL_REG 0x2c1e 394 #define VDEC2_PMV1_X 0x2c20 395 #define VDEC2_PMV1_Y 0x2c21 396 #define VDEC2_PMV2_X 0x2c22 397 #define VDEC2_PMV2_Y 0x2c23 398 #define VDEC2_PMV3_X 0x2c24 399 #define VDEC2_PMV3_Y 0x2c25 400 #define VDEC2_PMV4_X 0x2c26 401 #define VDEC2_PMV4_Y 0x2c27 402 #define VDEC2_M4_TABLE_SELECT 0x2c28 403 #define VDEC2_M4_CONTROL_REG 0x2c29 404 #define VDEC2_BLOCK_NUM 0x2c2a 405 #define VDEC2_PATTERN_CODE 0x2c2b 406 #define VDEC2_MB_INFO 0x2c2c 407 #define VDEC2_VLD_DC_PRED 0x2c2d 408 #define VDEC2_VLD_ERROR_MASK 0x2c2e 409 #define VDEC2_VLD_DC_PRED_C 0x2c2f 410 #define VDEC2_LAST_SLICE_MV_ADDR 0x2c30 411 #define VDEC2_LAST_MVX 0x2c31 412 #define VDEC2_LAST_MVY 0x2c32 413 #define VDEC2_VLD_C38 0x2c38 414 #define VDEC2_VLD_C39 0x2c39 415 #define VDEC2_VLD_STATUS 0x2c3a 416 #define VDEC2_VLD_SHIFT_STATUS 0x2c3b 417 #define VDEC2_VOFF_STATUS 0x2c3c 418 #define VDEC2_VLD_C3D 0x2c3d 419 #define VDEC2_VLD_DBG_INDEX 0x2c3e 420 #define VDEC2_VLD_DBG_DATA 0x2c3f 421 #define VDEC2_VLD_MEM_VIFIFO_START_PTR 0x2c40 422 #define VDEC2_VLD_MEM_VIFIFO_CURR_PTR 0x2c41 423 #define VDEC2_VLD_MEM_VIFIFO_END_PTR 0x2c42 424 #define VDEC2_VLD_MEM_VIFIFO_BYTES_AVAIL 0x2c43 425 #define VDEC2_VLD_MEM_VIFIFO_CONTROL 0x2c44 426 #define VDEC2_VLD_MEM_VIFIFO_WP 0x2c45 427 #define VDEC2_VLD_MEM_VIFIFO_RP 0x2c46 428 #define VDEC2_VLD_MEM_VIFIFO_LEVEL 0x2c47 429 #define VDEC2_VLD_MEM_VIFIFO_BUF_CNTL 0x2c48 430 #define VDEC2_VLD_TIME_STAMP_CNTL 0x2c49 431 #define VDEC2_VLD_TIME_STAMP_SYNC_0 0x2c4a 432 #define VDEC2_VLD_TIME_STAMP_SYNC_1 0x2c4b 433 #define VDEC2_VLD_TIME_STAMP_0 0x2c4c 434 #define VDEC2_VLD_TIME_STAMP_1 0x2c4d 435 #define VDEC2_VLD_TIME_STAMP_2 0x2c4e 436 #define VDEC2_VLD_TIME_STAMP_3 0x2c4f 437 #define VDEC2_VLD_TIME_STAMP_LENGTH 0x2c50 438 #define VDEC2_VLD_MEM_VIFIFO_WRAP_COUNT 0x2c51 439 #define VDEC2_VLD_MEM_VIFIFO_MEM_CTL 0x2c52 440 #define VDEC2_VLD_MEM_VBUF_RD_PTR 0x2c53 441 #define VDEC2_VLD_MEM_VBUF2_RD_PTR 0x2c54 442 #define VDEC2_VLD_MEM_SWAP_ADDR 0x2c55 443 #define VDEC2_VLD_MEM_SWAP_CTL 0x2c56 444 445 #define VDEC2_VCOP_CTRL_REG 0x2e00 446 #define VDEC2_QP_CTRL_REG 0x2e01 447 #define VDEC2_INTRA_QUANT_MATRIX 0x2e02 448 #define VDEC2_NON_I_QUANT_MATRIX 0x2e03 449 #define VDEC2_DC_SCALER 0x2e04 450 #define VDEC2_DC_AC_CTRL 0x2e05 451 #define VDEC2_DC_AC_SCALE_MUL 0x2e06 452 #define VDEC2_DC_AC_SCALE_DIV 0x2e07 453 #define VDEC2_POWER_CTL_IQIDCT 0x2e08 454 #define VDEC2_RV_AI_Y_X 0x2e09 455 #define VDEC2_RV_AI_U_X 0x2e0a 456 #define VDEC2_RV_AI_V_X 0x2e0b 457 #define VDEC2_RV_AI_MB_COUNT 0x2e0c 458 #define VDEC2_NEXT_INTRA_DMA_ADDRESS 0x2e0d 459 #define VDEC2_IQIDCT_CONTROL 0x2e0e 460 #define VDEC2_IQIDCT_DEBUG_INFO_0 0x2e0f 461 #define VDEC2_DEBLK_CMD 0x2e10 462 #define VDEC2_IQIDCT_DEBUG_IDCT 0x2e11 463 #define VDEC2_DCAC_DMA_CTRL 0x2e12 464 #define VDEC2_DCAC_DMA_ADDRESS 0x2e13 465 #define VDEC2_DCAC_CPU_ADDRESS 0x2e14 466 #define VDEC2_DCAC_CPU_DATA 0x2e15 467 #define VDEC2_DCAC_MB_COUNT 0x2e16 468 #define VDEC2_IQ_QUANT 0x2e17 469 #define VDEC2_VC1_BITPLANE_CTL 0x2e18 470 471 472 473 #endif 474