1 /*
2 *
3 * SPDX-License-Identifier: GPL-2.0
4 *
5 * Copyright (C) 2011-2018 ARM or its affiliates
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 *
18 */
19
20 #ifndef __ACAMERA_ISP_CONFIG_H__
21 #define __ACAMERA_ISP_CONFIG_H__
22
23
24 #include "acamera_isp1_config.h"
25 #include "system_sw_io.h"
26
27 #include "system_hw_io.h"
28
29 // ------------------------------------------------------------------------------ //
30 // Instance 'isp' of module 'common_config'
31 // ------------------------------------------------------------------------------ //
32
33 #define ACAMERA_ISP_BASE_ADDR (0x0L)
34 #define ACAMERA_ISP_SIZE (0x100)
35
36 #define ACAMERA_ISP_MAX_ADDR (4 * 0x3ffff)
37
38 // ------------------------------------------------------------------------------ //
39 // Group: id
40 // ------------------------------------------------------------------------------ //
41
42 // ------------------------------------------------------------------------------ //
43 // Register: API
44 // ------------------------------------------------------------------------------ //
45
46 #define ACAMERA_ISP_ID_API_DEFAULT (0x0)
47 #define ACAMERA_ISP_ID_API_DATASIZE (32)
48 #define ACAMERA_ISP_ID_API_OFFSET (0x0)
49 #define ACAMERA_ISP_ID_API_MASK (0xffffffff)
50
51 // args: data (32-bit)
acamera_isp_id_api_read(uintptr_t base)52 static __inline uint32_t acamera_isp_id_api_read(uintptr_t base) {
53 return system_hw_read_32(0x0L);
54 }
55 // ------------------------------------------------------------------------------ //
56 // Register: Product
57 // ------------------------------------------------------------------------------ //
58
59 #define ACAMERA_ISP_ID_PRODUCT_DEFAULT (2658)
60 #define ACAMERA_ISP_ID_PRODUCT_DATASIZE (32)
61 #define ACAMERA_ISP_ID_PRODUCT_OFFSET (0x4)
62 #define ACAMERA_ISP_ID_PRODUCT_MASK (0xffffffff)
63
64 // args: data (32-bit)
acamera_isp_id_product_read(uintptr_t base)65 static __inline uint32_t acamera_isp_id_product_read(uintptr_t base) {
66 return system_hw_read_32(0x4L);
67 }
68 // ------------------------------------------------------------------------------ //
69 // Register: Version
70 // ------------------------------------------------------------------------------ //
71
72 #define ACAMERA_ISP_ID_VERSION_DEFAULT (0x0)
73 #define ACAMERA_ISP_ID_VERSION_DATASIZE (32)
74 #define ACAMERA_ISP_ID_VERSION_OFFSET (0x8)
75 #define ACAMERA_ISP_ID_VERSION_MASK (0xffffffff)
76
77 // args: data (32-bit)
acamera_isp_id_version_read(uintptr_t base)78 static __inline uint32_t acamera_isp_id_version_read(uintptr_t base) {
79 return system_hw_read_32(0x8L);
80 }
81 // ------------------------------------------------------------------------------ //
82 // Register: Revision
83 // ------------------------------------------------------------------------------ //
84
85 #define ACAMERA_ISP_ID_REVISION_DEFAULT (0x0)
86 #define ACAMERA_ISP_ID_REVISION_DATASIZE (32)
87 #define ACAMERA_ISP_ID_REVISION_OFFSET (0xc)
88 #define ACAMERA_ISP_ID_REVISION_MASK (0xffffffff)
89
90 // args: data (32-bit)
acamera_isp_id_revision_read(uintptr_t base)91 static __inline uint32_t acamera_isp_id_revision_read(uintptr_t base) {
92 return system_hw_read_32(0xcL);
93 }
94 // ------------------------------------------------------------------------------ //
95 // Group: isp global
96 // ------------------------------------------------------------------------------ //
97
98 // ------------------------------------------------------------------------------ //
99 // Miscellaneous top-level ISP controls
100 // ------------------------------------------------------------------------------ //
101
102 // ------------------------------------------------------------------------------ //
103 // Register: Global FSM reset
104 // ------------------------------------------------------------------------------ //
105
106 // ------------------------------------------------------------------------------ //
107 //
108 // 1 = synchronous reset of FSMs in design (faster recovery after broken frame)
109 // when the MCU detects a broken frame or any other abnormal condition, the global_fsm_rest is
110 // expected to be used.
111 // MCU needs to follow a certain sequence for the same
112 // 1. Read the status register to know the exact source of the error interrupt.
113 // 2. Read the details of the error status register.
114 // 3. Mask all the interrupts.
115 // 4. Configure the input port register ISP_COMMON:input port: mode request to safe_stop mode.
116 // 5. Read back the ISP_COMMON:input port: mode status register to see the status of mode request.
117 // And wait until it shows the correct status.
118 // 6. Wait for the ISP_COMMON:isp global monitor: fr pipeline busy signal to become low.
119 // 7. Assert the global fsm reset.
120 // 8. Clear the global fsm reset.
121 // 9. Reconfigure the ISP configuration space.
122 // 10. Unmask the necessary interrupt sources.
123 //11. Configure the input port in safe_start mode.
124 //
125 // ------------------------------------------------------------------------------ //
126
127 #define ACAMERA_ISP_ISP_GLOBAL_GLOBAL_FSM_RESET_DEFAULT (0x0)
128 #define ACAMERA_ISP_ISP_GLOBAL_GLOBAL_FSM_RESET_DATASIZE (1)
129 #define ACAMERA_ISP_ISP_GLOBAL_GLOBAL_FSM_RESET_OFFSET (0x10)
130 #define ACAMERA_ISP_ISP_GLOBAL_GLOBAL_FSM_RESET_MASK (0x1)
131
132 // args: data (1-bit)
acamera_isp_isp_global_global_fsm_reset_write(uintptr_t base,uint8_t data)133 static __inline void acamera_isp_isp_global_global_fsm_reset_write(uintptr_t base, uint8_t data) {
134 uint32_t curr = system_hw_read_32(0x10L);
135 system_hw_write_32(0x10L, (((uint32_t) (data & 0x1)) << 0) | (curr & 0xfffffffe));
136 }
acamera_isp_isp_global_global_fsm_reset_read(uintptr_t base)137 static __inline uint8_t acamera_isp_isp_global_global_fsm_reset_read(uintptr_t base) {
138 return (uint8_t)((system_hw_read_32(0x10L) & 0x1) >> 0);
139 }
140 // ------------------------------------------------------------------------------ //
141 // Register: scaler fsm reset
142 // ------------------------------------------------------------------------------ //
143
144 // ------------------------------------------------------------------------------ //
145 // 1 = synchronous reset of FSMs in scaler design
146 // ------------------------------------------------------------------------------ //
147
148 #define ACAMERA_ISP_ISP_GLOBAL_SCALER_FSM_RESET_DEFAULT (0x0)
149 #define ACAMERA_ISP_ISP_GLOBAL_SCALER_FSM_RESET_DATASIZE (1)
150 #define ACAMERA_ISP_ISP_GLOBAL_SCALER_FSM_RESET_OFFSET (0x10)
151 #define ACAMERA_ISP_ISP_GLOBAL_SCALER_FSM_RESET_MASK (0x2)
152
153 // args: data (1-bit)
acamera_isp_isp_global_scaler_fsm_reset_write(uintptr_t base,uint8_t data)154 static __inline void acamera_isp_isp_global_scaler_fsm_reset_write(uintptr_t base, uint8_t data) {
155 uint32_t curr = system_hw_read_32(0x10L);
156 system_hw_write_32(0x10L, (((uint32_t) (data & 0x1)) << 1) | (curr & 0xfffffffd));
157 }
acamera_isp_isp_global_scaler_fsm_reset_read(uintptr_t base)158 static __inline uint8_t acamera_isp_isp_global_scaler_fsm_reset_read(uintptr_t base) {
159 return (uint8_t)((system_hw_read_32(0x10L) & 0x2) >> 1);
160 }
161 // ------------------------------------------------------------------------------ //
162 // Register: dma global config
163 // ------------------------------------------------------------------------------ //
164
165 // ------------------------------------------------------------------------------ //
166 //
167 // [0] : check bid
168 // [1] : check rid
169 //
170 // The following signals are diagnostic signals which helps identifying some of the AXI interface
171 // error cases. This must be used only as debug signals. You should follow these sequence
172 // - Mask the dma error interrupt
173 // - clear DMA interrupt if there is an active interrupt
174 // - Write appropriate values to these registers
175 // - Clear DMA alarms to clear the existing alarm
176 // - unmask the DMA error interrpt
177 //
178 //
179 // [2] : frame_write_cancel/frame_read_cancel
180 // [10:3] : awmaxwait_limit/armaxwait_limit
181 // [18:11]: wmaxwait_limit
182 // [26:19]: waxct_ostand_limit/rxnfr_ostand_limit
183 //
184 // ------------------------------------------------------------------------------ //
185
186 #define ACAMERA_ISP_ISP_GLOBAL_DMA_GLOBAL_CONFIG_DEFAULT (0x0)
187 #define ACAMERA_ISP_ISP_GLOBAL_DMA_GLOBAL_CONFIG_DATASIZE (27)
188 #define ACAMERA_ISP_ISP_GLOBAL_DMA_GLOBAL_CONFIG_OFFSET (0x10)
189 #define ACAMERA_ISP_ISP_GLOBAL_DMA_GLOBAL_CONFIG_MASK (0x7ffffff0)
190
191 // args: data (27-bit)
acamera_isp_isp_global_dma_global_config_write(uintptr_t base,uint32_t data)192 static __inline void acamera_isp_isp_global_dma_global_config_write(uintptr_t base, uint32_t data) {
193 uint32_t curr = system_hw_read_32(0x10L);
194 system_hw_write_32(0x10L, (((uint32_t) (data & 0x7ffffff)) << 4) | (curr & 0x8000000f));
195 }
acamera_isp_isp_global_dma_global_config_read(uintptr_t base)196 static __inline uint32_t acamera_isp_isp_global_dma_global_config_read(uintptr_t base) {
197 return (uint32_t)((system_hw_read_32(0x10L) & 0x7ffffff0) >> 4);
198 }
199 // ------------------------------------------------------------------------------ //
200 // Register: Flush hblank
201 // ------------------------------------------------------------------------------ //
202
203 // ------------------------------------------------------------------------------ //
204 // Horizontal blanking interval during regeneration (0=measured input interval)
205 // ------------------------------------------------------------------------------ //
206
207 #define ACAMERA_ISP_ISP_GLOBAL_FLUSH_HBLANK_DEFAULT (0x20)
208 #define ACAMERA_ISP_ISP_GLOBAL_FLUSH_HBLANK_DATASIZE (16)
209 #define ACAMERA_ISP_ISP_GLOBAL_FLUSH_HBLANK_OFFSET (0x14)
210 #define ACAMERA_ISP_ISP_GLOBAL_FLUSH_HBLANK_MASK (0xffff)
211
212 // args: data (16-bit)
acamera_isp_isp_global_flush_hblank_write(uintptr_t base,uint16_t data)213 static __inline void acamera_isp_isp_global_flush_hblank_write(uintptr_t base, uint16_t data) {
214 uint32_t curr = system_hw_read_32(0x14L);
215 system_hw_write_32(0x14L, (((uint32_t) (data & 0xffff)) << 0) | (curr & 0xffff0000));
216 }
acamera_isp_isp_global_flush_hblank_read(uintptr_t base)217 static __inline uint16_t acamera_isp_isp_global_flush_hblank_read(uintptr_t base) {
218 return (uint16_t)((system_hw_read_32(0x14L) & 0xffff) >> 0);
219 }
220 // ------------------------------------------------------------------------------ //
221 // Register: ISP monitor select
222 // ------------------------------------------------------------------------------ //
223
224 // ------------------------------------------------------------------------------ //
225 //
226 //
227 // ------------------------------------------------------------------------------ //
228
229 #define ACAMERA_ISP_ISP_GLOBAL_ISP_MONITOR_SELECT_DEFAULT (4)
230 #define ACAMERA_ISP_ISP_GLOBAL_ISP_MONITOR_SELECT_DATASIZE (3)
231 #define ACAMERA_ISP_ISP_GLOBAL_ISP_MONITOR_SELECT_OFFSET (0x14)
232 #define ACAMERA_ISP_ISP_GLOBAL_ISP_MONITOR_SELECT_MASK (0x70000)
233 #define ACAMERA_ISP_ISP_GLOBAL_ISP_MONITOR_SELECT_LINEARISED_DATA_AFTER_LINEARISED_CLUSTER_MSB_ALIGNED_DATA190_16D0 (0)
234 #define ACAMERA_ISP_ISP_GLOBAL_ISP_MONITOR_SELECT_STATIC_DPC_OUTPUT_MSB_ALIGNED_DATA150_20D0 (1)
235 #define ACAMERA_ISP_ISP_GLOBAL_ISP_MONITOR_SELECT_OUTPUT_OF_CA_CORRECTION_MSB_ALIGNED_DATA150_20D0 (2)
236 #define ACAMERA_ISP_ISP_GLOBAL_ISP_MONITOR_SELECT_CNR_OUTPUT_B110_G110_R110 (3)
237 #define ACAMERA_ISP_ISP_GLOBAL_ISP_MONITOR_SELECT_OUTPUT_FORCES_TO_0 (4)
238
239 // args: data (3-bit)
acamera_isp_isp_global_isp_monitor_select_write(uintptr_t base,uint8_t data)240 static __inline void acamera_isp_isp_global_isp_monitor_select_write(uintptr_t base, uint8_t data) {
241 uint32_t curr = system_hw_read_32(0x14L);
242 system_hw_write_32(0x14L, (((uint32_t) (data & 0x7)) << 16) | (curr & 0xfff8ffff));
243 }
acamera_isp_isp_global_isp_monitor_select_read(uintptr_t base)244 static __inline uint8_t acamera_isp_isp_global_isp_monitor_select_read(uintptr_t base) {
245 return (uint8_t)((system_hw_read_32(0x14L) & 0x70000) >> 16);
246 }
247 // ------------------------------------------------------------------------------ //
248 // Register: interline_blanks_min
249 // ------------------------------------------------------------------------------ //
250
251 // ------------------------------------------------------------------------------ //
252 // Minimun H-blank. The frame monitor will checke the frame geometry against this value
253 // ------------------------------------------------------------------------------ //
254
255 #define ACAMERA_ISP_ISP_GLOBAL_INTERLINE_BLANKS_MIN_DEFAULT (0x20)
256 #define ACAMERA_ISP_ISP_GLOBAL_INTERLINE_BLANKS_MIN_DATASIZE (16)
257 #define ACAMERA_ISP_ISP_GLOBAL_INTERLINE_BLANKS_MIN_OFFSET (0x18)
258 #define ACAMERA_ISP_ISP_GLOBAL_INTERLINE_BLANKS_MIN_MASK (0xffff)
259
260 // args: data (16-bit)
acamera_isp_isp_global_interline_blanks_min_write(uintptr_t base,uint16_t data)261 static __inline void acamera_isp_isp_global_interline_blanks_min_write(uintptr_t base, uint16_t data) {
262 uint32_t curr = system_hw_read_32(0x18L);
263 system_hw_write_32(0x18L, (((uint32_t) (data & 0xffff)) << 0) | (curr & 0xffff0000));
264 }
acamera_isp_isp_global_interline_blanks_min_read(uintptr_t base)265 static __inline uint16_t acamera_isp_isp_global_interline_blanks_min_read(uintptr_t base) {
266 return (uint16_t)((system_hw_read_32(0x18L) & 0xffff) >> 0);
267 }
268 // ------------------------------------------------------------------------------ //
269 // Register: interframe_blanks_min
270 // ------------------------------------------------------------------------------ //
271
272 // ------------------------------------------------------------------------------ //
273 // Minimun V-blank. The frame monitor will checke the frame geometry against this value
274 // ------------------------------------------------------------------------------ //
275
276 #define ACAMERA_ISP_ISP_GLOBAL_INTERFRAME_BLANKS_MIN_DEFAULT (0x28)
277 #define ACAMERA_ISP_ISP_GLOBAL_INTERFRAME_BLANKS_MIN_DATASIZE (16)
278 #define ACAMERA_ISP_ISP_GLOBAL_INTERFRAME_BLANKS_MIN_OFFSET (0x18)
279 #define ACAMERA_ISP_ISP_GLOBAL_INTERFRAME_BLANKS_MIN_MASK (0xffff0000)
280
281 // args: data (16-bit)
acamera_isp_isp_global_interframe_blanks_min_write(uintptr_t base,uint16_t data)282 static __inline void acamera_isp_isp_global_interframe_blanks_min_write(uintptr_t base, uint16_t data) {
283 uint32_t curr = system_hw_read_32(0x18L);
284 system_hw_write_32(0x18L, (((uint32_t) (data & 0xffff)) << 16) | (curr & 0xffff));
285 }
acamera_isp_isp_global_interframe_blanks_min_read(uintptr_t base)286 static __inline uint16_t acamera_isp_isp_global_interframe_blanks_min_read(uintptr_t base) {
287 return (uint16_t)((system_hw_read_32(0x18L) & 0xffff0000) >> 16);
288 }
289 // ------------------------------------------------------------------------------ //
290 // Register: watchdog timer max count
291 // ------------------------------------------------------------------------------ //
292
293 // ------------------------------------------------------------------------------ //
294 //
295 // Max count after which watchdog timer should give an interrupt. this count is between frame start and frame end
296 //
297 // ------------------------------------------------------------------------------ //
298
299 #define ACAMERA_ISP_ISP_GLOBAL_WATCHDOG_TIMER_MAX_COUNT_DEFAULT (0xFFFFFFFF)
300 #define ACAMERA_ISP_ISP_GLOBAL_WATCHDOG_TIMER_MAX_COUNT_DATASIZE (32)
301 #define ACAMERA_ISP_ISP_GLOBAL_WATCHDOG_TIMER_MAX_COUNT_OFFSET (0x1c)
302 #define ACAMERA_ISP_ISP_GLOBAL_WATCHDOG_TIMER_MAX_COUNT_MASK (0xffffffff)
303
304 // args: data (32-bit)
acamera_isp_isp_global_watchdog_timer_max_count_write(uintptr_t base,uint32_t data)305 static __inline void acamera_isp_isp_global_watchdog_timer_max_count_write(uintptr_t base, uint32_t data) {
306 system_hw_write_32(0x1cL, data);
307 }
acamera_isp_isp_global_watchdog_timer_max_count_read(uintptr_t base)308 static __inline uint32_t acamera_isp_isp_global_watchdog_timer_max_count_read(uintptr_t base) {
309 return system_hw_read_32(0x1cL);
310 }
311 // ------------------------------------------------------------------------------ //
312 // Register: Mcu override config select
313 // ------------------------------------------------------------------------------ //
314
315 // ------------------------------------------------------------------------------ //
316 //
317 // mcu override config select. When this bit is set, MCU takes control of the ISP ping-pong config swap.
318 // when is signal is set to 1, ISP core works in slave mode and selects configuration space based on MCU instruction.
319 //
320 // ------------------------------------------------------------------------------ //
321
322 #define ACAMERA_ISP_ISP_GLOBAL_MCU_OVERRIDE_CONFIG_SELECT_DEFAULT (0)
323 #define ACAMERA_ISP_ISP_GLOBAL_MCU_OVERRIDE_CONFIG_SELECT_DATASIZE (1)
324 #define ACAMERA_ISP_ISP_GLOBAL_MCU_OVERRIDE_CONFIG_SELECT_OFFSET (0x20)
325 #define ACAMERA_ISP_ISP_GLOBAL_MCU_OVERRIDE_CONFIG_SELECT_MASK (0x1)
326
327 // args: data (1-bit)
acamera_isp_isp_global_mcu_override_config_select_write(uintptr_t base,uint8_t data)328 static __inline void acamera_isp_isp_global_mcu_override_config_select_write(uintptr_t base, uint8_t data) {
329 uint32_t curr = system_hw_read_32(0x20L);
330 system_hw_write_32(0x20L, (((uint32_t) (data & 0x1)) << 0) | (curr & 0xfffffffe));
331 }
acamera_isp_isp_global_mcu_override_config_select_read(uintptr_t base)332 static __inline uint8_t acamera_isp_isp_global_mcu_override_config_select_read(uintptr_t base) {
333 return (uint8_t)((system_hw_read_32(0x20L) & 0x1) >> 0);
334 }
335 // ------------------------------------------------------------------------------ //
336 // Register: Mcu ping pong config select
337 // ------------------------------------------------------------------------------ //
338
339 // ------------------------------------------------------------------------------ //
340 //
341 // This signal is valid when Mcu_override_config_select is set to 1.
342 // when mcu takes control of the config select, this signal indicated whether to use ping and pong config space
343 // If this signal is changed during active active frame, the hardware makes sure that the config space is changed
344 // in the next vertical blanking
345 //
346 // ------------------------------------------------------------------------------ //
347
348 #define ACAMERA_ISP_ISP_GLOBAL_MCU_PING_PONG_CONFIG_SELECT_DEFAULT (0)
349 #define ACAMERA_ISP_ISP_GLOBAL_MCU_PING_PONG_CONFIG_SELECT_DATASIZE (1)
350 #define ACAMERA_ISP_ISP_GLOBAL_MCU_PING_PONG_CONFIG_SELECT_OFFSET (0x20)
351 #define ACAMERA_ISP_ISP_GLOBAL_MCU_PING_PONG_CONFIG_SELECT_MASK (0x2)
352 #define ACAMERA_ISP_ISP_GLOBAL_MCU_PING_PONG_CONFIG_SELECT_USE_PONG_ADDRESS_SPACE (0)
353 #define ACAMERA_ISP_ISP_GLOBAL_MCU_PING_PONG_CONFIG_SELECT_USE_PING_ADDRESS_SPACE (1)
354
355 // args: data (1-bit)
acamera_isp_isp_global_mcu_ping_pong_config_select_write(uintptr_t base,uint8_t data)356 static __inline void acamera_isp_isp_global_mcu_ping_pong_config_select_write(uintptr_t base, uint8_t data) {
357 uint32_t curr = system_hw_read_32(0x20L);
358 system_hw_write_32(0x20L, (((uint32_t) (data & 0x1)) << 1) | (curr & 0xfffffffd));
359 }
acamera_isp_isp_global_mcu_ping_pong_config_select_read(uintptr_t base)360 static __inline uint8_t acamera_isp_isp_global_mcu_ping_pong_config_select_read(uintptr_t base) {
361 return (uint8_t)((system_hw_read_32(0x20L) & 0x2) >> 1);
362 }
363 // ------------------------------------------------------------------------------ //
364 // Register: multi context mode
365 // ------------------------------------------------------------------------------ //
366
367 // ------------------------------------------------------------------------------ //
368 // Multi-context control mode
369 // ------------------------------------------------------------------------------ //
370
371 #define ACAMERA_ISP_ISP_GLOBAL_MULTI_CONTEXT_MODE_DEFAULT (0)
372 #define ACAMERA_ISP_ISP_GLOBAL_MULTI_CONTEXT_MODE_DATASIZE (1)
373 #define ACAMERA_ISP_ISP_GLOBAL_MULTI_CONTEXT_MODE_OFFSET (0x20)
374 #define ACAMERA_ISP_ISP_GLOBAL_MULTI_CONTEXT_MODE_MASK (0x100)
375 #define ACAMERA_ISP_ISP_GLOBAL_MULTI_CONTEXT_MODE_DEFAULT_MODE_THIS_IS_FOR_SINGLE_CONTEXT (0)
376 #define ACAMERA_ISP_ISP_GLOBAL_MULTI_CONTEXT_MODE_MULTICONTEXT_MODE (1)
377
378 // args: data (1-bit)
acamera_isp_isp_global_multi_context_mode_write(uintptr_t base,uint8_t data)379 static __inline void acamera_isp_isp_global_multi_context_mode_write(uintptr_t base, uint8_t data) {
380 uint32_t curr = system_hw_read_32(0x20L);
381 system_hw_write_32(0x20L, (((uint32_t) (data & 0x1)) << 8) | (curr & 0xfffffeff));
382 }
acamera_isp_isp_global_multi_context_mode_read(uintptr_t base)383 static __inline uint8_t acamera_isp_isp_global_multi_context_mode_read(uintptr_t base) {
384 return (uint8_t)((system_hw_read_32(0x20L) & 0x100) >> 8);
385 }
386 // ------------------------------------------------------------------------------ //
387 // Register: ping locked
388 // ------------------------------------------------------------------------------ //
389
390 // ------------------------------------------------------------------------------ //
391 // context swap status. when a address space is locked, all write to that address space will be rejected internally
392 // This signal is set when the 1st pixel comes out of input port and gets cleared when the last pixel comes out of ISp in streaming channels
393 // 1: ping locked
394 // 0: ping free
395 //
396 // ------------------------------------------------------------------------------ //
397
398 #define ACAMERA_ISP_ISP_GLOBAL_PING_LOCKED_DEFAULT (0)
399 #define ACAMERA_ISP_ISP_GLOBAL_PING_LOCKED_DATASIZE (1)
400 #define ACAMERA_ISP_ISP_GLOBAL_PING_LOCKED_OFFSET (0x24)
401 #define ACAMERA_ISP_ISP_GLOBAL_PING_LOCKED_MASK (0x1)
402
403 // args: data (1-bit)
acamera_isp_isp_global_ping_locked_read(uintptr_t base)404 static __inline uint8_t acamera_isp_isp_global_ping_locked_read(uintptr_t base) {
405 return (uint8_t)((system_hw_read_32(0x24L) & 0x1) >> 0);
406 }
407 // ------------------------------------------------------------------------------ //
408 // Register: pong locked
409 // ------------------------------------------------------------------------------ //
410
411 // ------------------------------------------------------------------------------ //
412 // context swap status. when a address space is locked, all write to that address space will be rejected internally.
413 // This signal is set when the 1st pixel comes out of input port and gets cleared when the last pixel comes out of ISp in streaming channels
414 // 1: pong locked
415 // 0: pong free
416 //
417 // ------------------------------------------------------------------------------ //
418
419 #define ACAMERA_ISP_ISP_GLOBAL_PONG_LOCKED_DEFAULT (0)
420 #define ACAMERA_ISP_ISP_GLOBAL_PONG_LOCKED_DATASIZE (1)
421 #define ACAMERA_ISP_ISP_GLOBAL_PONG_LOCKED_OFFSET (0x24)
422 #define ACAMERA_ISP_ISP_GLOBAL_PONG_LOCKED_MASK (0x2)
423
424 // args: data (1-bit)
acamera_isp_isp_global_pong_locked_read(uintptr_t base)425 static __inline uint8_t acamera_isp_isp_global_pong_locked_read(uintptr_t base) {
426 return (uint8_t)((system_hw_read_32(0x24L) & 0x2) >> 1);
427 }
428 // ------------------------------------------------------------------------------ //
429 // Register: ping pong config select
430 // ------------------------------------------------------------------------------ //
431
432 // ------------------------------------------------------------------------------ //
433 //
434 // this signal indicates which of the PING/PONG config is being used by ISP. when MCU takes control of the config management through
435 // Mcu_override_config_select signal, then this signal is just a reflection of what MCU has instructed through Mcu_ping_pong_config_select
436 // signal.
437 //
438 // This signal is a good point to synchronize with hardware. MCU should read this signal in a regular interval to synchronize with its
439 // internal state.
440 //
441 // This signal is changed when the 1st pixel comes in. So this signal must be sampled at the frame_start interrupt.
442 //
443 // 0: pong in use by ISP
444 // 1: ping in use by ISP
445 //
446 // ------------------------------------------------------------------------------ //
447
448 #define ACAMERA_ISP_ISP_GLOBAL_PING_PONG_CONFIG_SELECT_DEFAULT (1)
449 #define ACAMERA_ISP_ISP_GLOBAL_PING_PONG_CONFIG_SELECT_DATASIZE (1)
450 #define ACAMERA_ISP_ISP_GLOBAL_PING_PONG_CONFIG_SELECT_OFFSET (0x24)
451 #define ACAMERA_ISP_ISP_GLOBAL_PING_PONG_CONFIG_SELECT_MASK (0x4)
452
453 // args: data (1-bit)
acamera_isp_isp_global_ping_pong_config_select_read(uintptr_t base)454 static __inline uint8_t acamera_isp_isp_global_ping_pong_config_select_read(uintptr_t base) {
455 return (uint8_t)((system_hw_read_32(0x24L) & 0x4) >> 2);
456 }
457 // ------------------------------------------------------------------------------ //
458 // Group: isp global metering base addr
459 // ------------------------------------------------------------------------------ //
460
461 // ------------------------------------------------------------------------------ //
462 // pragrammable base adressed for metering stats
463 // ------------------------------------------------------------------------------ //
464
465 // ------------------------------------------------------------------------------ //
466 // Register: AWB
467 // ------------------------------------------------------------------------------ //
468
469 // ------------------------------------------------------------------------------ //
470 // base address for AWB stats. Value is set for 33x33 max zones
471 // ------------------------------------------------------------------------------ //
472
473 #define ACAMERA_ISP_ISP_GLOBAL_METERING_BASE_ADDR_AWB_DEFAULT (2192)
474 #define ACAMERA_ISP_ISP_GLOBAL_METERING_BASE_ADDR_AWB_DATASIZE (16)
475 #define ACAMERA_ISP_ISP_GLOBAL_METERING_BASE_ADDR_AWB_OFFSET (0x28)
476 #define ACAMERA_ISP_ISP_GLOBAL_METERING_BASE_ADDR_AWB_MASK (0xffff)
477
478 // args: data (16-bit)
acamera_isp_isp_global_metering_base_addr_awb_write(uintptr_t base,uint16_t data)479 static __inline void acamera_isp_isp_global_metering_base_addr_awb_write(uintptr_t base, uint16_t data) {
480 uint32_t curr = system_hw_read_32(0x28L);
481 system_hw_write_32(0x28L, (((uint32_t) (data & 0xffff)) << 0) | (curr & 0xffff0000));
482 }
acamera_isp_isp_global_metering_base_addr_awb_read(uintptr_t base)483 static __inline uint16_t acamera_isp_isp_global_metering_base_addr_awb_read(uintptr_t base) {
484 return (uint16_t)((system_hw_read_32(0x28L) & 0xffff) >> 0);
485 }
486 // ------------------------------------------------------------------------------ //
487 // Register: AF
488 // ------------------------------------------------------------------------------ //
489
490 // ------------------------------------------------------------------------------ //
491 // base address for AF stats. Value is set for 33x33 max zones
492 // ------------------------------------------------------------------------------ //
493
494 #define ACAMERA_ISP_ISP_GLOBAL_METERING_BASE_ADDR_AF_DEFAULT (4384)
495 #define ACAMERA_ISP_ISP_GLOBAL_METERING_BASE_ADDR_AF_DATASIZE (16)
496 #define ACAMERA_ISP_ISP_GLOBAL_METERING_BASE_ADDR_AF_OFFSET (0x28)
497 #define ACAMERA_ISP_ISP_GLOBAL_METERING_BASE_ADDR_AF_MASK (0xffff0000)
498
499 // args: data (16-bit)
acamera_isp_isp_global_metering_base_addr_af_write(uintptr_t base,uint16_t data)500 static __inline void acamera_isp_isp_global_metering_base_addr_af_write(uintptr_t base, uint16_t data) {
501 uint32_t curr = system_hw_read_32(0x28L);
502 system_hw_write_32(0x28L, (((uint32_t) (data & 0xffff)) << 16) | (curr & 0xffff));
503 }
acamera_isp_isp_global_metering_base_addr_af_read(uintptr_t base)504 static __inline uint16_t acamera_isp_isp_global_metering_base_addr_af_read(uintptr_t base) {
505 return (uint16_t)((system_hw_read_32(0x28L) & 0xffff0000) >> 16);
506 }
507 // ------------------------------------------------------------------------------ //
508 // Register: MAX ADDR
509 // ------------------------------------------------------------------------------ //
510
511 // ------------------------------------------------------------------------------ //
512 // max address for metering stats mem. Value is set for 33x33 max zones
513 // ------------------------------------------------------------------------------ //
514
515 #define ACAMERA_ISP_ISP_GLOBAL_METERING_BASE_ADDR_MAX_ADDR_DEFAULT (6575)
516 #define ACAMERA_ISP_ISP_GLOBAL_METERING_BASE_ADDR_MAX_ADDR_DATASIZE (16)
517 #define ACAMERA_ISP_ISP_GLOBAL_METERING_BASE_ADDR_MAX_ADDR_OFFSET (0x2c)
518 #define ACAMERA_ISP_ISP_GLOBAL_METERING_BASE_ADDR_MAX_ADDR_MASK (0xffff)
519
520 // args: data (16-bit)
acamera_isp_isp_global_metering_base_addr_max_addr_write(uintptr_t base,uint16_t data)521 static __inline void acamera_isp_isp_global_metering_base_addr_max_addr_write(uintptr_t base, uint16_t data) {
522 uint32_t curr = system_hw_read_32(0x2cL);
523 system_hw_write_32(0x2cL, (((uint32_t) (data & 0xffff)) << 0) | (curr & 0xffff0000));
524 }
acamera_isp_isp_global_metering_base_addr_max_addr_read(uintptr_t base)525 static __inline uint16_t acamera_isp_isp_global_metering_base_addr_max_addr_read(uintptr_t base) {
526 return (uint16_t)((system_hw_read_32(0x2cL) & 0xffff) >> 0);
527 }
528 // ------------------------------------------------------------------------------ //
529 // Group: isp global interrupt
530 // ------------------------------------------------------------------------------ //
531
532 // ------------------------------------------------------------------------------ //
533 // interrupt controls
534 // ------------------------------------------------------------------------------ //
535
536 // ------------------------------------------------------------------------------ //
537 // Register: mask_vector
538 // ------------------------------------------------------------------------------ //
539
540 // ------------------------------------------------------------------------------ //
541 // Interrupt mask vector
542 // 0: Interrupt is enabled
543 // 1: interrupt is masked
544 //
545 // ------------------------------------------------------------------------------ //
546
547 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_MASK_VECTOR_DEFAULT (0x0)
548 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_MASK_VECTOR_DATASIZE (32)
549 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_MASK_VECTOR_OFFSET (0x30)
550 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_MASK_VECTOR_MASK (0xffffffff)
551
552 // args: data (32-bit)
acamera_isp_isp_global_interrupt_mask_vector_write(uintptr_t base,uint32_t data)553 static __inline void acamera_isp_isp_global_interrupt_mask_vector_write(uintptr_t base, uint32_t data) {
554 system_hw_write_32(0x30L, data);
555 }
acamera_isp_isp_global_interrupt_mask_vector_read(uintptr_t base)556 static __inline uint32_t acamera_isp_isp_global_interrupt_mask_vector_read(uintptr_t base) {
557 return system_hw_read_32(0x30L);
558 }
559 // ------------------------------------------------------------------------------ //
560 // Register: clear_vector
561 // ------------------------------------------------------------------------------ //
562
563 // ------------------------------------------------------------------------------ //
564 // Interrupt clear vector. its bitwise cleared. When a bit is set to 1. that interrupt
565 // bit in the status register is cleared
566 //
567 // ------------------------------------------------------------------------------ //
568
569 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_CLEAR_VECTOR_DEFAULT (0x0)
570 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_CLEAR_VECTOR_DATASIZE (32)
571 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_CLEAR_VECTOR_OFFSET (0x34)
572 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_CLEAR_VECTOR_MASK (0xffffffff)
573
574 // args: data (32-bit)
acamera_isp_isp_global_interrupt_clear_vector_write(uintptr_t base,uint32_t data)575 static __inline void acamera_isp_isp_global_interrupt_clear_vector_write(uintptr_t base, uint32_t data) {
576 system_hw_write_32(0x34L, data);
577 }
acamera_isp_isp_global_interrupt_clear_vector_read(uintptr_t base)578 static __inline uint32_t acamera_isp_isp_global_interrupt_clear_vector_read(uintptr_t base) {
579 return system_hw_read_32(0x34L);
580 }
581 // ------------------------------------------------------------------------------ //
582 // Register: shadow_disable_vector
583 // ------------------------------------------------------------------------------ //
584
585 // ------------------------------------------------------------------------------ //
586 // Interrupt shadow disable vector.
587 // To disable shadow feature for the specific interrupt event by setting the related bit to 1.
588 //
589 // ------------------------------------------------------------------------------ //
590
591 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_SHADOW_DISABLE_VECTOR_DEFAULT (0x0)
592 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_SHADOW_DISABLE_VECTOR_DATASIZE (32)
593 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_SHADOW_DISABLE_VECTOR_OFFSET (0x38)
594 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_SHADOW_DISABLE_VECTOR_MASK (0xffffffff)
595
596 // args: data (32-bit)
acamera_isp_isp_global_interrupt_shadow_disable_vector_write(uintptr_t base,uint32_t data)597 static __inline void acamera_isp_isp_global_interrupt_shadow_disable_vector_write(uintptr_t base, uint32_t data) {
598 system_hw_write_32(0x38L, data);
599 }
acamera_isp_isp_global_interrupt_shadow_disable_vector_read(uintptr_t base)600 static __inline uint32_t acamera_isp_isp_global_interrupt_shadow_disable_vector_read(uintptr_t base) {
601 return system_hw_read_32(0x38L);
602 }
603 // ------------------------------------------------------------------------------ //
604 // Register: pulse_mode
605 // ------------------------------------------------------------------------------ //
606
607 // ------------------------------------------------------------------------------ //
608 //
609 // When set to 1, the output interrupt will be a pulse. Otherwise it should be level.
610 //
611 // ------------------------------------------------------------------------------ //
612
613 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_PULSE_MODE_DEFAULT (0x0)
614 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_PULSE_MODE_DATASIZE (1)
615 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_PULSE_MODE_OFFSET (0x3c)
616 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_PULSE_MODE_MASK (0x1)
617
618 // args: data (1-bit)
acamera_isp_isp_global_interrupt_pulse_mode_write(uintptr_t base,uint8_t data)619 static __inline void acamera_isp_isp_global_interrupt_pulse_mode_write(uintptr_t base, uint8_t data) {
620 uint32_t curr = system_hw_read_32(0x3cL);
621 system_hw_write_32(0x3cL, (((uint32_t) (data & 0x1)) << 0) | (curr & 0xfffffffe));
622 }
acamera_isp_isp_global_interrupt_pulse_mode_read(uintptr_t base)623 static __inline uint8_t acamera_isp_isp_global_interrupt_pulse_mode_read(uintptr_t base) {
624 return (uint8_t)((system_hw_read_32(0x3cL) & 0x1) >> 0);
625 }
626 // ------------------------------------------------------------------------------ //
627 // Register: clear
628 // ------------------------------------------------------------------------------ //
629
630 // ------------------------------------------------------------------------------ //
631 //
632 // Interrupt clear vector register qualifier. First the vector must be written. Then this bit must be set to 1 and then cleared
633 //
634 // ------------------------------------------------------------------------------ //
635
636 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_CLEAR_DEFAULT (0x0)
637 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_CLEAR_DATASIZE (1)
638 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_CLEAR_OFFSET (0x40)
639 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_CLEAR_MASK (0x1)
640
641 // args: data (1-bit)
acamera_isp_isp_global_interrupt_clear_write(uintptr_t base,uint8_t data)642 static __inline void acamera_isp_isp_global_interrupt_clear_write(uintptr_t base, uint8_t data) {
643 uint32_t curr = system_hw_read_32(0x40L);
644 system_hw_write_32(0x40L, (((uint32_t) (data & 0x1)) << 0) | (curr & 0xfffffffe));
645 }
acamera_isp_isp_global_interrupt_clear_read(uintptr_t base)646 static __inline uint8_t acamera_isp_isp_global_interrupt_clear_read(uintptr_t base) {
647 return (uint8_t)((system_hw_read_32(0x40L) & 0x1) >> 0);
648 }
649 // ------------------------------------------------------------------------------ //
650 // Register: status_vector
651 // ------------------------------------------------------------------------------ //
652
653 // ------------------------------------------------------------------------------ //
654 //
655 // bit[0] : Isp_start
656 // bit[1] : Isp_done
657 // bit[2] : Context management error
658 // bit[3] : Broken frame error
659 // bit[4] : Metering AF done
660 // bit[5] : Metering aexp done
661 // bit[6] : Metering awb done
662 // bit[7] : Metering aexp 1024 bin hist done
663 // bit[8] : Metering antifog hist done
664 // bit[9] : Lut init done
665 // bit[10] : FR y-dma write done
666 // bit[11] : FR uv-dma write done
667 // bit[12] : DS y-dma write done
668 // bit[13] : DS uv-dma write done
669 // bit[14] : Linearization done
670 // bit[15] : Static dpc done
671 // bit[16] : Ca correction done
672 // bit[17] : Iridix done
673 // bit[18] : 3d LIUT done
674 // bit[19] : Watchdog timer timed out
675 // bit[20] : Frame collision error
676 // bit[21] : luma variance done
677 // bit[22] : DMA error interrupt
678 // bit[23] : Input port safely stopped
679 //
680 // ------------------------------------------------------------------------------ //
681
682 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_STATUS_VECTOR_DEFAULT (0x0)
683 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_STATUS_VECTOR_DATASIZE (32)
684 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_STATUS_VECTOR_OFFSET (0x44)
685 #define ACAMERA_ISP_ISP_GLOBAL_INTERRUPT_STATUS_VECTOR_MASK (0xffffffff)
686
687 // args: data (32-bit)
acamera_isp_isp_global_interrupt_status_vector_read(uintptr_t base)688 static __inline uint32_t acamera_isp_isp_global_interrupt_status_vector_read(uintptr_t base) {
689 return system_hw_read_32(0x44L);
690 }
691 // ------------------------------------------------------------------------------ //
692 // Group: isp global lp
693 // ------------------------------------------------------------------------------ //
694
695 // ------------------------------------------------------------------------------ //
696 //
697 // CLK DIS register:
698 // This register shitches off clock of certain blocks.
699 //
700 //
701 // CLK DIS register:
702 // This register controls the clock gate cell which gates clock during V-blank. When this is set to 1, the v-blank clock
703 // gating will be disabled. This register doesnt control the static clock gating which is controlled through CLK DIS register
704 //
705 //
706 // ------------------------------------------------------------------------------ //
707
708 // ------------------------------------------------------------------------------ //
709 // Register: CLK Dis FR Y dma writer
710 // ------------------------------------------------------------------------------ //
711
712 // ------------------------------------------------------------------------------ //
713 //
714 // When set, the output Y/RGB/YUV DMA writer in FR channel will be clock gated. This is applicable
715 // to Y channel of the semi-planner mode and all other non-planner modes. This must be used only when the DMA writer is not used and SOC
716 // environment uses the streaming outputs from ISP
717 //
718 // ------------------------------------------------------------------------------ //
719
720 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_FR_Y_DMA_WRITER_DEFAULT (0)
721 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_FR_Y_DMA_WRITER_DATASIZE (1)
722 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_FR_Y_DMA_WRITER_OFFSET (0x48)
723 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_FR_Y_DMA_WRITER_MASK (0x1)
724
725 // args: data (1-bit)
acamera_isp_isp_global_lp_clk_dis_fr_y_dma_writer_write(uintptr_t base,uint8_t data)726 static __inline void acamera_isp_isp_global_lp_clk_dis_fr_y_dma_writer_write(uintptr_t base, uint8_t data) {
727 uint32_t curr = system_hw_read_32(0x48L);
728 system_hw_write_32(0x48L, (((uint32_t) (data & 0x1)) << 0) | (curr & 0xfffffffe));
729 }
acamera_isp_isp_global_lp_clk_dis_fr_y_dma_writer_read(uintptr_t base)730 static __inline uint8_t acamera_isp_isp_global_lp_clk_dis_fr_y_dma_writer_read(uintptr_t base) {
731 return (uint8_t)((system_hw_read_32(0x48L) & 0x1) >> 0);
732 }
733 // ------------------------------------------------------------------------------ //
734 // Register: CLK Dis FR UV dma writer
735 // ------------------------------------------------------------------------------ //
736
737 // ------------------------------------------------------------------------------ //
738 //
739 // When set, the output UV DMA writer in FR channel will be clock gated. This is applicable
740 // to UV channel of the semi-planner mode . This must be used only when the DMA writer is not used and SOC
741 // environment uses the streaming outputs from ISP, or format is NOT semi-planner
742 //
743 // ------------------------------------------------------------------------------ //
744
745 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_FR_UV_DMA_WRITER_DEFAULT (0)
746 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_FR_UV_DMA_WRITER_DATASIZE (1)
747 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_FR_UV_DMA_WRITER_OFFSET (0x48)
748 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_FR_UV_DMA_WRITER_MASK (0x2)
749
750 // args: data (1-bit)
acamera_isp_isp_global_lp_clk_dis_fr_uv_dma_writer_write(uintptr_t base,uint8_t data)751 static __inline void acamera_isp_isp_global_lp_clk_dis_fr_uv_dma_writer_write(uintptr_t base, uint8_t data) {
752 uint32_t curr = system_hw_read_32(0x48L);
753 system_hw_write_32(0x48L, (((uint32_t) (data & 0x1)) << 1) | (curr & 0xfffffffd));
754 }
acamera_isp_isp_global_lp_clk_dis_fr_uv_dma_writer_read(uintptr_t base)755 static __inline uint8_t acamera_isp_isp_global_lp_clk_dis_fr_uv_dma_writer_read(uintptr_t base) {
756 return (uint8_t)((system_hw_read_32(0x48L) & 0x2) >> 1);
757 }
758 // ------------------------------------------------------------------------------ //
759 // Register: CLK Dis DS Y dma writer
760 // ------------------------------------------------------------------------------ //
761
762 // ------------------------------------------------------------------------------ //
763 //
764 // When set, the output Y/RGB/YUV DMA writer in DS channel will be clock gated. This is applicable
765 // to Y channel of the semi-planner mode and all other non-planner modes. This must be used only when the DMA writer is not used and SOC
766 // environment uses the streaming outputs from ISP
767 //
768 // ------------------------------------------------------------------------------ //
769
770 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_DS1_Y_DMA_WRITER_DEFAULT (0)
771 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_DS1_Y_DMA_WRITER_DATASIZE (1)
772 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_DS1_Y_DMA_WRITER_OFFSET (0x48)
773 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_DS1_Y_DMA_WRITER_MASK (0x4)
774
775 // args: data (1-bit)
acamera_isp_isp_global_lp_clk_dis_ds1_y_dma_writer_write(uintptr_t base,uint8_t data)776 static __inline void acamera_isp_isp_global_lp_clk_dis_ds1_y_dma_writer_write(uintptr_t base, uint8_t data) {
777 uint32_t curr = system_hw_read_32(0x48L);
778 system_hw_write_32(0x48L, (((uint32_t) (data & 0x1)) << 2) | (curr & 0xfffffffb));
779 }
acamera_isp_isp_global_lp_clk_dis_ds1_y_dma_writer_read(uintptr_t base)780 static __inline uint8_t acamera_isp_isp_global_lp_clk_dis_ds1_y_dma_writer_read(uintptr_t base) {
781 return (uint8_t)((system_hw_read_32(0x48L) & 0x4) >> 2);
782 }
783 // ------------------------------------------------------------------------------ //
784 // Register: CLK Dis DS UV dma writer
785 // ------------------------------------------------------------------------------ //
786
787 // ------------------------------------------------------------------------------ //
788 //
789 // When set, the output UV DMA writer in DS channel will be clock gated. This is applicable
790 // to UV channel of the semi-planner mode . This must be used only when the DMA writer is not used and SOC
791 // environment uses the streaming outputs from ISP, or format is NOT semi-planner
792 //
793 // ------------------------------------------------------------------------------ //
794
795 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_DS1_UV_DMA_WRITER_DEFAULT (0)
796 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_DS1_UV_DMA_WRITER_DATASIZE (1)
797 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_DS1_UV_DMA_WRITER_OFFSET (0x48)
798 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_DS1_UV_DMA_WRITER_MASK (0x8)
799
800 // args: data (1-bit)
acamera_isp_isp_global_lp_clk_dis_ds1_uv_dma_writer_write(uintptr_t base,uint8_t data)801 static __inline void acamera_isp_isp_global_lp_clk_dis_ds1_uv_dma_writer_write(uintptr_t base, uint8_t data) {
802 uint32_t curr = system_hw_read_32(0x48L);
803 system_hw_write_32(0x48L, (((uint32_t) (data & 0x1)) << 3) | (curr & 0xfffffff7));
804 }
acamera_isp_isp_global_lp_clk_dis_ds1_uv_dma_writer_read(uintptr_t base)805 static __inline uint8_t acamera_isp_isp_global_lp_clk_dis_ds1_uv_dma_writer_read(uintptr_t base) {
806 return (uint8_t)((system_hw_read_32(0x48L) & 0x8) >> 3);
807 }
808 // ------------------------------------------------------------------------------ //
809 // Register: CLK Dis temper dma
810 // ------------------------------------------------------------------------------ //
811
812 // ------------------------------------------------------------------------------ //
813 //
814 // This signal gates the clock for all temper write and read dma. This should be used only when Temper is not used.
815 //
816 // ------------------------------------------------------------------------------ //
817
818 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_TEMPER_DMA_DEFAULT (0)
819 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_TEMPER_DMA_DATASIZE (1)
820 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_TEMPER_DMA_OFFSET (0x48)
821 #define ACAMERA_ISP_ISP_GLOBAL_LP_CLK_DIS_TEMPER_DMA_MASK (0x10)
822
823 // args: data (1-bit)
acamera_isp_isp_global_lp_clk_dis_temper_dma_write(uintptr_t base,uint8_t data)824 static __inline void acamera_isp_isp_global_lp_clk_dis_temper_dma_write(uintptr_t base, uint8_t data) {
825 uint32_t curr = system_hw_read_32(0x48L);
826 system_hw_write_32(0x48L, (((uint32_t) (data & 0x1)) << 4) | (curr & 0xffffffef));
827 }
acamera_isp_isp_global_lp_clk_dis_temper_dma_read(uintptr_t base)828 static __inline uint8_t acamera_isp_isp_global_lp_clk_dis_temper_dma_read(uintptr_t base) {
829 return (uint8_t)((system_hw_read_32(0x48L) & 0x10) >> 4);
830 }
831 // ------------------------------------------------------------------------------ //
832 // Register: CG Dis frame_stitch
833 // ------------------------------------------------------------------------------ //
834
835 // ------------------------------------------------------------------------------ //
836 // when set, this will disable V-blank Clock gating for WDR path channels.
837 // ------------------------------------------------------------------------------ //
838
839 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_FRAME_STITCH_DEFAULT (0)
840 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_FRAME_STITCH_DATASIZE (1)
841 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_FRAME_STITCH_OFFSET (0x4c)
842 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_FRAME_STITCH_MASK (0x1)
843
844 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_frame_stitch_write(uintptr_t base,uint8_t data)845 static __inline void acamera_isp_isp_global_lp_cg_dis_frame_stitch_write(uintptr_t base, uint8_t data) {
846 uint32_t curr = system_hw_read_32(0x4cL);
847 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 0) | (curr & 0xfffffffe));
848 }
acamera_isp_isp_global_lp_cg_dis_frame_stitch_read(uintptr_t base)849 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_frame_stitch_read(uintptr_t base) {
850 return (uint8_t)((system_hw_read_32(0x4cL) & 0x1) >> 0);
851 }
852 // ------------------------------------------------------------------------------ //
853 // Register: CG Dis raw frontend
854 // ------------------------------------------------------------------------------ //
855
856 // ------------------------------------------------------------------------------ //
857 // when set, this will disable V-blank Clock gating for raw frontend.
858 // ------------------------------------------------------------------------------ //
859
860 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RAW_FRONTEND_DEFAULT (0)
861 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RAW_FRONTEND_DATASIZE (1)
862 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RAW_FRONTEND_OFFSET (0x4c)
863 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RAW_FRONTEND_MASK (0x2)
864
865 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_raw_frontend_write(uintptr_t base,uint8_t data)866 static __inline void acamera_isp_isp_global_lp_cg_dis_raw_frontend_write(uintptr_t base, uint8_t data) {
867 uint32_t curr = system_hw_read_32(0x4cL);
868 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 1) | (curr & 0xfffffffd));
869 }
acamera_isp_isp_global_lp_cg_dis_raw_frontend_read(uintptr_t base)870 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_raw_frontend_read(uintptr_t base) {
871 return (uint8_t)((system_hw_read_32(0x4cL) & 0x2) >> 1);
872 }
873 // ------------------------------------------------------------------------------ //
874 // Register: CG Dis defect pixel
875 // ------------------------------------------------------------------------------ //
876
877 // ------------------------------------------------------------------------------ //
878 // when set, this will disable V-blank Clock gating for defect pixel.
879 // ------------------------------------------------------------------------------ //
880
881 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_DEFECT_PIXEL_DEFAULT (0)
882 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_DEFECT_PIXEL_DATASIZE (1)
883 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_DEFECT_PIXEL_OFFSET (0x4c)
884 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_DEFECT_PIXEL_MASK (0x4)
885
886 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_defect_pixel_write(uintptr_t base,uint8_t data)887 static __inline void acamera_isp_isp_global_lp_cg_dis_defect_pixel_write(uintptr_t base, uint8_t data) {
888 uint32_t curr = system_hw_read_32(0x4cL);
889 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 2) | (curr & 0xfffffffb));
890 }
acamera_isp_isp_global_lp_cg_dis_defect_pixel_read(uintptr_t base)891 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_defect_pixel_read(uintptr_t base) {
892 return (uint8_t)((system_hw_read_32(0x4cL) & 0x4) >> 2);
893 }
894 // ------------------------------------------------------------------------------ //
895 // Register: CG Dis Sinter
896 // ------------------------------------------------------------------------------ //
897
898 // ------------------------------------------------------------------------------ //
899 // when set, this will disable V-blank Clock gating for Sinter.
900 // ------------------------------------------------------------------------------ //
901
902 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_SINTER_DEFAULT (0)
903 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_SINTER_DATASIZE (1)
904 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_SINTER_OFFSET (0x4c)
905 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_SINTER_MASK (0x8)
906
907 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_sinter_write(uintptr_t base,uint8_t data)908 static __inline void acamera_isp_isp_global_lp_cg_dis_sinter_write(uintptr_t base, uint8_t data) {
909 uint32_t curr = system_hw_read_32(0x4cL);
910 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 3) | (curr & 0xfffffff7));
911 }
acamera_isp_isp_global_lp_cg_dis_sinter_read(uintptr_t base)912 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_sinter_read(uintptr_t base) {
913 return (uint8_t)((system_hw_read_32(0x4cL) & 0x8) >> 3);
914 }
915 // ------------------------------------------------------------------------------ //
916 // Register: CG Dis Temper
917 // ------------------------------------------------------------------------------ //
918
919 // ------------------------------------------------------------------------------ //
920 // when set, this will disable V-blank Clock gating for Temper.
921 // ------------------------------------------------------------------------------ //
922
923 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_TEMPER_DEFAULT (0)
924 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_TEMPER_DATASIZE (1)
925 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_TEMPER_OFFSET (0x4c)
926 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_TEMPER_MASK (0x10)
927
928 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_temper_write(uintptr_t base,uint8_t data)929 static __inline void acamera_isp_isp_global_lp_cg_dis_temper_write(uintptr_t base, uint8_t data) {
930 uint32_t curr = system_hw_read_32(0x4cL);
931 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 4) | (curr & 0xffffffef));
932 }
acamera_isp_isp_global_lp_cg_dis_temper_read(uintptr_t base)933 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_temper_read(uintptr_t base) {
934 return (uint8_t)((system_hw_read_32(0x4cL) & 0x10) >> 4);
935 }
936 // ------------------------------------------------------------------------------ //
937 // Register: CG Dis CA Correction
938 // ------------------------------------------------------------------------------ //
939
940 // ------------------------------------------------------------------------------ //
941 // when set, this will disable V-blank Clock gating for CA correction.
942 // ------------------------------------------------------------------------------ //
943
944 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_CA_CORRECTION_DEFAULT (0)
945 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_CA_CORRECTION_DATASIZE (1)
946 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_CA_CORRECTION_OFFSET (0x4c)
947 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_CA_CORRECTION_MASK (0x20)
948
949 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_ca_correction_write(uintptr_t base,uint8_t data)950 static __inline void acamera_isp_isp_global_lp_cg_dis_ca_correction_write(uintptr_t base, uint8_t data) {
951 uint32_t curr = system_hw_read_32(0x4cL);
952 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 5) | (curr & 0xffffffdf));
953 }
acamera_isp_isp_global_lp_cg_dis_ca_correction_read(uintptr_t base)954 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_ca_correction_read(uintptr_t base) {
955 return (uint8_t)((system_hw_read_32(0x4cL) & 0x20) >> 5);
956 }
957 // ------------------------------------------------------------------------------ //
958 // Register: CG Dis radial shading
959 // ------------------------------------------------------------------------------ //
960
961 // ------------------------------------------------------------------------------ //
962 // when set, this will disable V-blank Clock gating for radial shading.
963 // ------------------------------------------------------------------------------ //
964
965 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RADIAL_SHADING_DEFAULT (0)
966 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RADIAL_SHADING_DATASIZE (1)
967 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RADIAL_SHADING_OFFSET (0x4c)
968 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RADIAL_SHADING_MASK (0x40)
969
970 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_radial_shading_write(uintptr_t base,uint8_t data)971 static __inline void acamera_isp_isp_global_lp_cg_dis_radial_shading_write(uintptr_t base, uint8_t data) {
972 uint32_t curr = system_hw_read_32(0x4cL);
973 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 6) | (curr & 0xffffffbf));
974 }
acamera_isp_isp_global_lp_cg_dis_radial_shading_read(uintptr_t base)975 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_radial_shading_read(uintptr_t base) {
976 return (uint8_t)((system_hw_read_32(0x4cL) & 0x40) >> 6);
977 }
978 // ------------------------------------------------------------------------------ //
979 // Register: CG Dis mesh shading
980 // ------------------------------------------------------------------------------ //
981
982 // ------------------------------------------------------------------------------ //
983 // when set, this will disable V-blank Clock gating for mesh shading.
984 // ------------------------------------------------------------------------------ //
985
986 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_MESH_SHADING_DEFAULT (0)
987 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_MESH_SHADING_DATASIZE (1)
988 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_MESH_SHADING_OFFSET (0x4c)
989 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_MESH_SHADING_MASK (0x80)
990
991 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_mesh_shading_write(uintptr_t base,uint8_t data)992 static __inline void acamera_isp_isp_global_lp_cg_dis_mesh_shading_write(uintptr_t base, uint8_t data) {
993 uint32_t curr = system_hw_read_32(0x4cL);
994 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 7) | (curr & 0xffffff7f));
995 }
acamera_isp_isp_global_lp_cg_dis_mesh_shading_read(uintptr_t base)996 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_mesh_shading_read(uintptr_t base) {
997 return (uint8_t)((system_hw_read_32(0x4cL) & 0x80) >> 7);
998 }
999 // ------------------------------------------------------------------------------ //
1000 // Register: CG Dis Iridix
1001 // ------------------------------------------------------------------------------ //
1002
1003 // ------------------------------------------------------------------------------ //
1004 // when set, this will disable V-blank Clock gating for Iridix.
1005 // ------------------------------------------------------------------------------ //
1006
1007 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_IRIDIX_DEFAULT (0)
1008 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_IRIDIX_DATASIZE (1)
1009 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_IRIDIX_OFFSET (0x4c)
1010 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_IRIDIX_MASK (0x100)
1011
1012 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_iridix_write(uintptr_t base,uint8_t data)1013 static __inline void acamera_isp_isp_global_lp_cg_dis_iridix_write(uintptr_t base, uint8_t data) {
1014 uint32_t curr = system_hw_read_32(0x4cL);
1015 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 8) | (curr & 0xfffffeff));
1016 }
acamera_isp_isp_global_lp_cg_dis_iridix_read(uintptr_t base)1017 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_iridix_read(uintptr_t base) {
1018 return (uint8_t)((system_hw_read_32(0x4cL) & 0x100) >> 8);
1019 }
1020 // ------------------------------------------------------------------------------ //
1021 // Register: CG Dis demosaic RGGB
1022 // ------------------------------------------------------------------------------ //
1023
1024 // ------------------------------------------------------------------------------ //
1025 // when set, this will disable V-blank Clock gating for Demosaic RGGB.
1026 // ------------------------------------------------------------------------------ //
1027
1028 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_DEMOSAIC_RGGB_DEFAULT (0)
1029 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_DEMOSAIC_RGGB_DATASIZE (1)
1030 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_DEMOSAIC_RGGB_OFFSET (0x4c)
1031 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_DEMOSAIC_RGGB_MASK (0x200)
1032
1033 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_demosaic_rggb_write(uintptr_t base,uint8_t data)1034 static __inline void acamera_isp_isp_global_lp_cg_dis_demosaic_rggb_write(uintptr_t base, uint8_t data) {
1035 uint32_t curr = system_hw_read_32(0x4cL);
1036 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 9) | (curr & 0xfffffdff));
1037 }
acamera_isp_isp_global_lp_cg_dis_demosaic_rggb_read(uintptr_t base)1038 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_demosaic_rggb_read(uintptr_t base) {
1039 return (uint8_t)((system_hw_read_32(0x4cL) & 0x200) >> 9);
1040 }
1041 // ------------------------------------------------------------------------------ //
1042 // Register: CG Dis demosaic RGBIr
1043 // ------------------------------------------------------------------------------ //
1044
1045 // ------------------------------------------------------------------------------ //
1046 // when set, this will disable V-blank Clock gating for Demosaic RGBIr.
1047 // ------------------------------------------------------------------------------ //
1048
1049 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_DEMOSAIC_RGBIR_DEFAULT (0)
1050 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_DEMOSAIC_RGBIR_DATASIZE (1)
1051 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_DEMOSAIC_RGBIR_OFFSET (0x4c)
1052 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_DEMOSAIC_RGBIR_MASK (0x400)
1053
1054 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_demosaic_rgbir_write(uintptr_t base,uint8_t data)1055 static __inline void acamera_isp_isp_global_lp_cg_dis_demosaic_rgbir_write(uintptr_t base, uint8_t data) {
1056 uint32_t curr = system_hw_read_32(0x4cL);
1057 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 10) | (curr & 0xfffffbff));
1058 }
acamera_isp_isp_global_lp_cg_dis_demosaic_rgbir_read(uintptr_t base)1059 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_demosaic_rgbir_read(uintptr_t base) {
1060 return (uint8_t)((system_hw_read_32(0x4cL) & 0x400) >> 10);
1061 }
1062 // ------------------------------------------------------------------------------ //
1063 // Register: CG Dis PF correction
1064 // ------------------------------------------------------------------------------ //
1065
1066 // ------------------------------------------------------------------------------ //
1067 // when set, this will disable V-blank Clock gating for PF correction.
1068 // ------------------------------------------------------------------------------ //
1069
1070 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_PF_CORRECTION_DEFAULT (0)
1071 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_PF_CORRECTION_DATASIZE (1)
1072 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_PF_CORRECTION_OFFSET (0x4c)
1073 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_PF_CORRECTION_MASK (0x800)
1074
1075 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_pf_correction_write(uintptr_t base,uint8_t data)1076 static __inline void acamera_isp_isp_global_lp_cg_dis_pf_correction_write(uintptr_t base, uint8_t data) {
1077 uint32_t curr = system_hw_read_32(0x4cL);
1078 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 11) | (curr & 0xfffff7ff));
1079 }
acamera_isp_isp_global_lp_cg_dis_pf_correction_read(uintptr_t base)1080 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_pf_correction_read(uintptr_t base) {
1081 return (uint8_t)((system_hw_read_32(0x4cL) & 0x800) >> 11);
1082 }
1083 // ------------------------------------------------------------------------------ //
1084 // Register: CG Dis CNR
1085 // ------------------------------------------------------------------------------ //
1086
1087 // ------------------------------------------------------------------------------ //
1088 // when set, this will disable V-blank Clock gating for CNR and pre-square root and post-square.
1089 // ------------------------------------------------------------------------------ //
1090
1091 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_CNR_DEFAULT (0)
1092 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_CNR_DATASIZE (1)
1093 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_CNR_OFFSET (0x4c)
1094 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_CNR_MASK (0x1000)
1095
1096 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_cnr_write(uintptr_t base,uint8_t data)1097 static __inline void acamera_isp_isp_global_lp_cg_dis_cnr_write(uintptr_t base, uint8_t data) {
1098 uint32_t curr = system_hw_read_32(0x4cL);
1099 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 12) | (curr & 0xffffefff));
1100 }
acamera_isp_isp_global_lp_cg_dis_cnr_read(uintptr_t base)1101 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_cnr_read(uintptr_t base) {
1102 return (uint8_t)((system_hw_read_32(0x4cL) & 0x1000) >> 12);
1103 }
1104 // ------------------------------------------------------------------------------ //
1105 // Register: CG Dis 3D LUT
1106 // ------------------------------------------------------------------------------ //
1107
1108 // ------------------------------------------------------------------------------ //
1109 // when set, this will disable V-blank Clock gating for 3D LUT.
1110 // ------------------------------------------------------------------------------ //
1111
1112 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_3D_LUT_DEFAULT (0)
1113 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_3D_LUT_DATASIZE (1)
1114 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_3D_LUT_OFFSET (0x4c)
1115 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_3D_LUT_MASK (0x2000)
1116
1117 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_3d_lut_write(uintptr_t base,uint8_t data)1118 static __inline void acamera_isp_isp_global_lp_cg_dis_3d_lut_write(uintptr_t base, uint8_t data) {
1119 uint32_t curr = system_hw_read_32(0x4cL);
1120 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 13) | (curr & 0xffffdfff));
1121 }
acamera_isp_isp_global_lp_cg_dis_3d_lut_read(uintptr_t base)1122 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_3d_lut_read(uintptr_t base) {
1123 return (uint8_t)((system_hw_read_32(0x4cL) & 0x2000) >> 13);
1124 }
1125 // ------------------------------------------------------------------------------ //
1126 // Register: CG Dis RGB Scaler
1127 // ------------------------------------------------------------------------------ //
1128
1129 // ------------------------------------------------------------------------------ //
1130 // when set, this will disable V-blank Clock gating for RGB scaler.
1131 // ------------------------------------------------------------------------------ //
1132
1133 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RGB_SCALER_DEFAULT (0)
1134 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RGB_SCALER_DATASIZE (1)
1135 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RGB_SCALER_OFFSET (0x4c)
1136 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RGB_SCALER_MASK (0x4000)
1137
1138 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_rgb_scaler_write(uintptr_t base,uint8_t data)1139 static __inline void acamera_isp_isp_global_lp_cg_dis_rgb_scaler_write(uintptr_t base, uint8_t data) {
1140 uint32_t curr = system_hw_read_32(0x4cL);
1141 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 14) | (curr & 0xffffbfff));
1142 }
acamera_isp_isp_global_lp_cg_dis_rgb_scaler_read(uintptr_t base)1143 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_rgb_scaler_read(uintptr_t base) {
1144 return (uint8_t)((system_hw_read_32(0x4cL) & 0x4000) >> 14);
1145 }
1146 // ------------------------------------------------------------------------------ //
1147 // Register: CG Dis RGB Gamma FR
1148 // ------------------------------------------------------------------------------ //
1149
1150 // ------------------------------------------------------------------------------ //
1151 // when set, this will disable V-blank Clock gating for RGB gamma in FR pipeline.
1152 // ------------------------------------------------------------------------------ //
1153
1154 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RGB_GAMMA_FR_DEFAULT (0)
1155 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RGB_GAMMA_FR_DATASIZE (1)
1156 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RGB_GAMMA_FR_OFFSET (0x4c)
1157 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RGB_GAMMA_FR_MASK (0x8000)
1158
1159 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_rgb_gamma_fr_write(uintptr_t base,uint8_t data)1160 static __inline void acamera_isp_isp_global_lp_cg_dis_rgb_gamma_fr_write(uintptr_t base, uint8_t data) {
1161 uint32_t curr = system_hw_read_32(0x4cL);
1162 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 15) | (curr & 0xffff7fff));
1163 }
acamera_isp_isp_global_lp_cg_dis_rgb_gamma_fr_read(uintptr_t base)1164 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_rgb_gamma_fr_read(uintptr_t base) {
1165 return (uint8_t)((system_hw_read_32(0x4cL) & 0x8000) >> 15);
1166 }
1167 // ------------------------------------------------------------------------------ //
1168 // Register: CG Dis RGB Gamma DS
1169 // ------------------------------------------------------------------------------ //
1170
1171 // ------------------------------------------------------------------------------ //
1172 // when set, this will disable V-blank Clock gating for RGB gamma in DS pipeline.
1173 // ------------------------------------------------------------------------------ //
1174
1175 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RGB_GAMMA_DS_DEFAULT (0)
1176 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RGB_GAMMA_DS_DATASIZE (1)
1177 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RGB_GAMMA_DS_OFFSET (0x4c)
1178 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_RGB_GAMMA_DS_MASK (0x10000)
1179
1180 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_rgb_gamma_ds_write(uintptr_t base,uint8_t data)1181 static __inline void acamera_isp_isp_global_lp_cg_dis_rgb_gamma_ds_write(uintptr_t base, uint8_t data) {
1182 uint32_t curr = system_hw_read_32(0x4cL);
1183 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 16) | (curr & 0xfffeffff));
1184 }
acamera_isp_isp_global_lp_cg_dis_rgb_gamma_ds_read(uintptr_t base)1185 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_rgb_gamma_ds_read(uintptr_t base) {
1186 return (uint8_t)((system_hw_read_32(0x4cL) & 0x10000) >> 16);
1187 }
1188 // ------------------------------------------------------------------------------ //
1189 // Register: CG Dis Sharpen FR
1190 // ------------------------------------------------------------------------------ //
1191
1192 // ------------------------------------------------------------------------------ //
1193 // when set, this will disable V-blank Clock gating for sharpen in FR pipeline.
1194 // ------------------------------------------------------------------------------ //
1195
1196 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_FR_SHARPEN_DEFAULT (0)
1197 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_FR_SHARPEN_DATASIZE (1)
1198 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_FR_SHARPEN_OFFSET (0x4c)
1199 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_FR_SHARPEN_MASK (0x20000)
1200
1201 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_fr_sharpen_write(uintptr_t base,uint8_t data)1202 static __inline void acamera_isp_isp_global_lp_cg_dis_fr_sharpen_write(uintptr_t base, uint8_t data) {
1203 uint32_t curr = system_hw_read_32(0x4cL);
1204 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 17) | (curr & 0xfffdffff));
1205 }
acamera_isp_isp_global_lp_cg_dis_fr_sharpen_read(uintptr_t base)1206 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_fr_sharpen_read(uintptr_t base) {
1207 return (uint8_t)((system_hw_read_32(0x4cL) & 0x20000) >> 17);
1208 }
1209 // ------------------------------------------------------------------------------ //
1210 // Register: CG Dis Sharpen DS
1211 // ------------------------------------------------------------------------------ //
1212
1213 // ------------------------------------------------------------------------------ //
1214 // when set, this will disable V-blank Clock gating for sharpen in DS pipeline.
1215 // ------------------------------------------------------------------------------ //
1216
1217 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_SHARPEN_DS_DEFAULT (0)
1218 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_SHARPEN_DS_DATASIZE (1)
1219 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_SHARPEN_DS_OFFSET (0x4c)
1220 #define ACAMERA_ISP_ISP_GLOBAL_LP_CG_DIS_SHARPEN_DS_MASK (0x40000)
1221
1222 // args: data (1-bit)
acamera_isp_isp_global_lp_cg_dis_sharpen_ds_write(uintptr_t base,uint8_t data)1223 static __inline void acamera_isp_isp_global_lp_cg_dis_sharpen_ds_write(uintptr_t base, uint8_t data) {
1224 uint32_t curr = system_hw_read_32(0x4cL);
1225 system_hw_write_32(0x4cL, (((uint32_t) (data & 0x1)) << 18) | (curr & 0xfffbffff));
1226 }
acamera_isp_isp_global_lp_cg_dis_sharpen_ds_read(uintptr_t base)1227 static __inline uint8_t acamera_isp_isp_global_lp_cg_dis_sharpen_ds_read(uintptr_t base) {
1228 return (uint8_t)((system_hw_read_32(0x4cL) & 0x40000) >> 18);
1229 }
1230 // ------------------------------------------------------------------------------ //
1231 // Group: isp global monitor
1232 // ------------------------------------------------------------------------------ //
1233
1234 // ------------------------------------------------------------------------------ //
1235 // Register: broken_frame status
1236 // ------------------------------------------------------------------------------ //
1237
1238 // ------------------------------------------------------------------------------ //
1239 //
1240 // bit[0] : active width mismatch
1241 // bit[1] : active_height mismatch
1242 // bit[2] : minimum v-blank violated
1243 // bit[3] : minimum h-blank violated
1244 //
1245 // ------------------------------------------------------------------------------ //
1246
1247 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_BROKEN_FRAME_STATUS_DEFAULT (0)
1248 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_BROKEN_FRAME_STATUS_DATASIZE (4)
1249 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_BROKEN_FRAME_STATUS_OFFSET (0x50)
1250 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_BROKEN_FRAME_STATUS_MASK (0xf)
1251
1252 // args: data (4-bit)
acamera_isp_isp_global_monitor_broken_frame_status_read(uintptr_t base)1253 static __inline uint8_t acamera_isp_isp_global_monitor_broken_frame_status_read(uintptr_t base) {
1254 return (uint8_t)((system_hw_read_32(0x50L) & 0xf) >> 0);
1255 }
1256 // ------------------------------------------------------------------------------ //
1257 // Register: fr_pipeline_busy
1258 // ------------------------------------------------------------------------------ //
1259
1260 // ------------------------------------------------------------------------------ //
1261 //
1262 // This signal indicates if ISP pipeline is busy or Not, This signal doesnt include the metereing modules.
1263 // This information is expected to be used when a broken frame is detected and global_fsm_reset needs to be asserted
1264 // global_fsm_reset must be set when this busy signal is low.
1265 // 0: ISP main pipeline (excluding metering) is free
1266 // 1: ISP main pipeline (excluding metering) is busy
1267 //
1268 // ------------------------------------------------------------------------------ //
1269
1270 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_PIPELINE_BUSY_DEFAULT (0x0)
1271 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_PIPELINE_BUSY_DATASIZE (1)
1272 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_PIPELINE_BUSY_OFFSET (0x50)
1273 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_PIPELINE_BUSY_MASK (0x10000)
1274
1275 // args: data (1-bit)
acamera_isp_isp_global_monitor_fr_pipeline_busy_read(uintptr_t base)1276 static __inline uint8_t acamera_isp_isp_global_monitor_fr_pipeline_busy_read(uintptr_t base) {
1277 return (uint8_t)((system_hw_read_32(0x50L) & 0x10000) >> 16);
1278 }
1279 // ------------------------------------------------------------------------------ //
1280 // Register: FR Y DMA WFIFO fail full
1281 // ------------------------------------------------------------------------------ //
1282
1283 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_Y_DMA_WFIFO_FAIL_FULL_DEFAULT (0)
1284 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_Y_DMA_WFIFO_FAIL_FULL_DATASIZE (1)
1285 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_Y_DMA_WFIFO_FAIL_FULL_OFFSET (0x54)
1286 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_Y_DMA_WFIFO_FAIL_FULL_MASK (0x1)
1287
1288 // args: data (1-bit)
acamera_isp_isp_global_monitor_fr_y_dma_wfifo_fail_full_read(uintptr_t base)1289 static __inline uint8_t acamera_isp_isp_global_monitor_fr_y_dma_wfifo_fail_full_read(uintptr_t base) {
1290 return (uint8_t)((system_hw_read_32(0x54L) & 0x1) >> 0);
1291 }
1292 // ------------------------------------------------------------------------------ //
1293 // Register: FR Y DMA WFIFO fail empty
1294 // ------------------------------------------------------------------------------ //
1295
1296 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_Y_DMA_WFIFO_FAIL_EMPTY_DEFAULT (0)
1297 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_Y_DMA_WFIFO_FAIL_EMPTY_DATASIZE (1)
1298 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_Y_DMA_WFIFO_FAIL_EMPTY_OFFSET (0x54)
1299 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_Y_DMA_WFIFO_FAIL_EMPTY_MASK (0x2)
1300
1301 // args: data (1-bit)
acamera_isp_isp_global_monitor_fr_y_dma_wfifo_fail_empty_read(uintptr_t base)1302 static __inline uint8_t acamera_isp_isp_global_monitor_fr_y_dma_wfifo_fail_empty_read(uintptr_t base) {
1303 return (uint8_t)((system_hw_read_32(0x54L) & 0x2) >> 1);
1304 }
1305 // ------------------------------------------------------------------------------ //
1306 // Register: FR UV DMA WFIFO fail full
1307 // ------------------------------------------------------------------------------ //
1308
1309 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_UV_DMA_WFIFO_FAIL_FULL_DEFAULT (0)
1310 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_UV_DMA_WFIFO_FAIL_FULL_DATASIZE (1)
1311 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_UV_DMA_WFIFO_FAIL_FULL_OFFSET (0x54)
1312 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_UV_DMA_WFIFO_FAIL_FULL_MASK (0x4)
1313
1314 // args: data (1-bit)
acamera_isp_isp_global_monitor_fr_uv_dma_wfifo_fail_full_read(uintptr_t base)1315 static __inline uint8_t acamera_isp_isp_global_monitor_fr_uv_dma_wfifo_fail_full_read(uintptr_t base) {
1316 return (uint8_t)((system_hw_read_32(0x54L) & 0x4) >> 2);
1317 }
1318 // ------------------------------------------------------------------------------ //
1319 // Register: FR UV DMA WFIFO fail empty
1320 // ------------------------------------------------------------------------------ //
1321
1322 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_UV_DMA_WFIFO_FAIL_EMPTY_DEFAULT (0)
1323 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_UV_DMA_WFIFO_FAIL_EMPTY_DATASIZE (1)
1324 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_UV_DMA_WFIFO_FAIL_EMPTY_OFFSET (0x54)
1325 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_FR_UV_DMA_WFIFO_FAIL_EMPTY_MASK (0x8)
1326
1327 // args: data (1-bit)
acamera_isp_isp_global_monitor_fr_uv_dma_wfifo_fail_empty_read(uintptr_t base)1328 static __inline uint8_t acamera_isp_isp_global_monitor_fr_uv_dma_wfifo_fail_empty_read(uintptr_t base) {
1329 return (uint8_t)((system_hw_read_32(0x54L) & 0x8) >> 3);
1330 }
1331 // ------------------------------------------------------------------------------ //
1332 // Register: DS Y DMA WFIFO fail full
1333 // ------------------------------------------------------------------------------ //
1334
1335 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DS1_Y_DMA_WFIFO_FAIL_FULL_DEFAULT (0)
1336 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DS1_Y_DMA_WFIFO_FAIL_FULL_DATASIZE (1)
1337 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DS1_Y_DMA_WFIFO_FAIL_FULL_OFFSET (0x54)
1338 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DS1_Y_DMA_WFIFO_FAIL_FULL_MASK (0x10)
1339
1340 // args: data (1-bit)
acamera_isp_isp_global_monitor_ds1_y_dma_wfifo_fail_full_read(uintptr_t base)1341 static __inline uint8_t acamera_isp_isp_global_monitor_ds1_y_dma_wfifo_fail_full_read(uintptr_t base) {
1342 return (uint8_t)((system_hw_read_32(0x54L) & 0x10) >> 4);
1343 }
1344 // ------------------------------------------------------------------------------ //
1345 // Register: DS Y DMA WFIFO fail empty
1346 // ------------------------------------------------------------------------------ //
1347
1348 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DS1_Y_DMA_WFIFO_FAIL_EMPTY_DEFAULT (0)
1349 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DS1_Y_DMA_WFIFO_FAIL_EMPTY_DATASIZE (1)
1350 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DS1_Y_DMA_WFIFO_FAIL_EMPTY_OFFSET (0x54)
1351 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DS1_Y_DMA_WFIFO_FAIL_EMPTY_MASK (0x20)
1352
1353 // args: data (1-bit)
acamera_isp_isp_global_monitor_ds1_y_dma_wfifo_fail_empty_read(uintptr_t base)1354 static __inline uint8_t acamera_isp_isp_global_monitor_ds1_y_dma_wfifo_fail_empty_read(uintptr_t base) {
1355 return (uint8_t)((system_hw_read_32(0x54L) & 0x20) >> 5);
1356 }
1357 // ------------------------------------------------------------------------------ //
1358 // Register: DS UV DMA WFIFO fail full
1359 // ------------------------------------------------------------------------------ //
1360
1361 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DS1_UV_DMA_WFIFO_FAIL_FULL_DEFAULT (0)
1362 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DS1_UV_DMA_WFIFO_FAIL_FULL_DATASIZE (1)
1363 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DS1_UV_DMA_WFIFO_FAIL_FULL_OFFSET (0x54)
1364 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DS1_UV_DMA_WFIFO_FAIL_FULL_MASK (0x40)
1365
1366 // args: data (1-bit)
acamera_isp_isp_global_monitor_ds1_uv_dma_wfifo_fail_full_read(uintptr_t base)1367 static __inline uint8_t acamera_isp_isp_global_monitor_ds1_uv_dma_wfifo_fail_full_read(uintptr_t base) {
1368 return (uint8_t)((system_hw_read_32(0x54L) & 0x40) >> 6);
1369 }
1370 // ------------------------------------------------------------------------------ //
1371 // Register: DS UV DMA WFIFO fail empty
1372 // ------------------------------------------------------------------------------ //
1373
1374 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DS1_UV_DMA_WFIFO_FAIL_EMPTY_DEFAULT (0)
1375 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DS1_UV_DMA_WFIFO_FAIL_EMPTY_DATASIZE (1)
1376 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DS1_UV_DMA_WFIFO_FAIL_EMPTY_OFFSET (0x54)
1377 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DS1_UV_DMA_WFIFO_FAIL_EMPTY_MASK (0x80)
1378
1379 // args: data (1-bit)
acamera_isp_isp_global_monitor_ds1_uv_dma_wfifo_fail_empty_read(uintptr_t base)1380 static __inline uint8_t acamera_isp_isp_global_monitor_ds1_uv_dma_wfifo_fail_empty_read(uintptr_t base) {
1381 return (uint8_t)((system_hw_read_32(0x54L) & 0x80) >> 7);
1382 }
1383 // ------------------------------------------------------------------------------ //
1384 // Register: Temper DMA WFIFO fail empty
1385 // ------------------------------------------------------------------------------ //
1386
1387 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_WFIFO_FAIL_EMPTY_DEFAULT (0)
1388 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_WFIFO_FAIL_EMPTY_DATASIZE (1)
1389 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_WFIFO_FAIL_EMPTY_OFFSET (0x54)
1390 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_WFIFO_FAIL_EMPTY_MASK (0x100)
1391
1392 // args: data (1-bit)
acamera_isp_isp_global_monitor_temper_dma_wfifo_fail_empty_read(uintptr_t base)1393 static __inline uint8_t acamera_isp_isp_global_monitor_temper_dma_wfifo_fail_empty_read(uintptr_t base) {
1394 return (uint8_t)((system_hw_read_32(0x54L) & 0x100) >> 8);
1395 }
1396 // ------------------------------------------------------------------------------ //
1397 // Register: Temper DMA WFIFO fail full
1398 // ------------------------------------------------------------------------------ //
1399
1400 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_WFIFO_FAIL_FULL_DEFAULT (0)
1401 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_WFIFO_FAIL_FULL_DATASIZE (1)
1402 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_WFIFO_FAIL_FULL_OFFSET (0x54)
1403 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_WFIFO_FAIL_FULL_MASK (0x200)
1404
1405 // args: data (1-bit)
acamera_isp_isp_global_monitor_temper_dma_wfifo_fail_full_read(uintptr_t base)1406 static __inline uint8_t acamera_isp_isp_global_monitor_temper_dma_wfifo_fail_full_read(uintptr_t base) {
1407 return (uint8_t)((system_hw_read_32(0x54L) & 0x200) >> 9);
1408 }
1409 // ------------------------------------------------------------------------------ //
1410 // Register: Temper DMA RFIFO fail empty
1411 // ------------------------------------------------------------------------------ //
1412
1413 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_RFIFO_FAIL_EMPTY_DEFAULT (0)
1414 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_RFIFO_FAIL_EMPTY_DATASIZE (1)
1415 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_RFIFO_FAIL_EMPTY_OFFSET (0x54)
1416 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_RFIFO_FAIL_EMPTY_MASK (0x400)
1417
1418 // args: data (1-bit)
acamera_isp_isp_global_monitor_temper_dma_rfifo_fail_empty_read(uintptr_t base)1419 static __inline uint8_t acamera_isp_isp_global_monitor_temper_dma_rfifo_fail_empty_read(uintptr_t base) {
1420 return (uint8_t)((system_hw_read_32(0x54L) & 0x400) >> 10);
1421 }
1422 // ------------------------------------------------------------------------------ //
1423 // Register: Temper DMA RFIFO fail full
1424 // ------------------------------------------------------------------------------ //
1425
1426 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_RFIFO_FAIL_FULL_DEFAULT (0)
1427 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_RFIFO_FAIL_FULL_DATASIZE (1)
1428 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_RFIFO_FAIL_FULL_OFFSET (0x54)
1429 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_RFIFO_FAIL_FULL_MASK (0x800)
1430
1431 // args: data (1-bit)
acamera_isp_isp_global_monitor_temper_dma_rfifo_fail_full_read(uintptr_t base)1432 static __inline uint8_t acamera_isp_isp_global_monitor_temper_dma_rfifo_fail_full_read(uintptr_t base) {
1433 return (uint8_t)((system_hw_read_32(0x54L) & 0x800) >> 11);
1434 }
1435 // ------------------------------------------------------------------------------ //
1436 // Register: DMA alarms
1437 // ------------------------------------------------------------------------------ //
1438
1439 // ------------------------------------------------------------------------------ //
1440 //
1441 // [0] : temper_dma_lsb_wtr_axi_alarm
1442 // [1] : temper_dma_lsb_rdr_axi_alarm
1443 // [2] : temper_dma_msb_wtr_axi_alarm
1444 // [3] : temper_dma_msb_rdr_axi_alarm
1445 // [4] : FR UV dma axi alarm
1446 // [5] : FR dma axi alarm
1447 // [6] : DS UV dma axi alarm
1448 // [7] : DS dma axi alarm
1449 // [8] : Temper LSB dma frame dropped
1450 // [9] : Temper MSB dma frame dropped
1451 // [10]: FR UV-DMA frame dropped
1452 // [11]: FR Y-DMA frame dropped
1453 // [12]: DS UV-DMA frame dropped
1454 // [13]: DS Y-DMA frame dropped
1455 //
1456 // ------------------------------------------------------------------------------ //
1457
1458 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DMA_ALARMS_DEFAULT (0)
1459 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DMA_ALARMS_DATASIZE (14)
1460 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DMA_ALARMS_OFFSET (0x54)
1461 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_DMA_ALARMS_MASK (0x3fff0000)
1462
1463 // args: data (14-bit)
acamera_isp_isp_global_monitor_dma_alarms_read(uintptr_t base)1464 static __inline uint16_t acamera_isp_isp_global_monitor_dma_alarms_read(uintptr_t base) {
1465 return (uint16_t)((system_hw_read_32(0x54L) & 0x3fff0000) >> 16);
1466 }
1467 // ------------------------------------------------------------------------------ //
1468 // Register: broken_frame error clear
1469 // ------------------------------------------------------------------------------ //
1470
1471 // ------------------------------------------------------------------------------ //
1472 //
1473 // This signal must be asserted when the MCu gets broken frame interrupt.
1474 // this signal must be 0->1->0 pulse. The duration of the pulse is not relevant. This rising edge will clear the
1475 // broken frame error status signal
1476 //
1477 // ------------------------------------------------------------------------------ //
1478
1479 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_BROKEN_FRAME_ERROR_CLEAR_DEFAULT (0)
1480 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_BROKEN_FRAME_ERROR_CLEAR_DATASIZE (1)
1481 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_BROKEN_FRAME_ERROR_CLEAR_OFFSET (0x58)
1482 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_BROKEN_FRAME_ERROR_CLEAR_MASK (0x1)
1483
1484 // args: data (1-bit)
acamera_isp_isp_global_monitor_broken_frame_error_clear_write(uintptr_t base,uint8_t data)1485 static __inline void acamera_isp_isp_global_monitor_broken_frame_error_clear_write(uintptr_t base, uint8_t data) {
1486 uint32_t curr = system_hw_read_32(0x58L);
1487 system_hw_write_32(0x58L, (((uint32_t) (data & 0x1)) << 0) | (curr & 0xfffffffe));
1488 }
acamera_isp_isp_global_monitor_broken_frame_error_clear_read(uintptr_t base)1489 static __inline uint8_t acamera_isp_isp_global_monitor_broken_frame_error_clear_read(uintptr_t base) {
1490 return (uint8_t)((system_hw_read_32(0x58L) & 0x1) >> 0);
1491 }
1492 // ------------------------------------------------------------------------------ //
1493 // Register: context error clr
1494 // ------------------------------------------------------------------------------ //
1495
1496 // ------------------------------------------------------------------------------ //
1497 //
1498 // This signal must be asserted when the MCU gets the context error interrupt.
1499 // this signal must be 0->1->0 pulse. The duration of the pulse is not relevant. This rising edge will clear the
1500 // context error status signal
1501 //
1502 // ------------------------------------------------------------------------------ //
1503
1504 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_CONTEXT_ERROR_CLR_DEFAULT (0)
1505 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_CONTEXT_ERROR_CLR_DATASIZE (1)
1506 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_CONTEXT_ERROR_CLR_OFFSET (0x58)
1507 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_CONTEXT_ERROR_CLR_MASK (0x2)
1508
1509 // args: data (1-bit)
acamera_isp_isp_global_monitor_context_error_clr_write(uintptr_t base,uint8_t data)1510 static __inline void acamera_isp_isp_global_monitor_context_error_clr_write(uintptr_t base, uint8_t data) {
1511 uint32_t curr = system_hw_read_32(0x58L);
1512 system_hw_write_32(0x58L, (((uint32_t) (data & 0x1)) << 1) | (curr & 0xfffffffd));
1513 }
acamera_isp_isp_global_monitor_context_error_clr_read(uintptr_t base)1514 static __inline uint8_t acamera_isp_isp_global_monitor_context_error_clr_read(uintptr_t base) {
1515 return (uint8_t)((system_hw_read_32(0x58L) & 0x2) >> 1);
1516 }
1517 // ------------------------------------------------------------------------------ //
1518 // Register: output dma clr alarm
1519 // ------------------------------------------------------------------------------ //
1520
1521 // ------------------------------------------------------------------------------ //
1522 //
1523 // This signal must be asserted when the MCU gets the DMA error interrupt.
1524 // This signal will clear all DMA error status signals for all the output DMA writers (Y/UV DMAs in both of the output channels)
1525 // MCU must follow the following sequance to clear the alarms
1526 // step-1: set this bit to 1
1527 // step-2: Read back the alarm signals
1528 // step-3: If the alarms are cleared, then clear the clr_alarm signal back to 0.
1529 //
1530 // ------------------------------------------------------------------------------ //
1531
1532 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_OUTPUT_DMA_CLR_ALARM_DEFAULT (0)
1533 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_OUTPUT_DMA_CLR_ALARM_DATASIZE (1)
1534 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_OUTPUT_DMA_CLR_ALARM_OFFSET (0x58)
1535 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_OUTPUT_DMA_CLR_ALARM_MASK (0x4)
1536
1537 // args: data (1-bit)
acamera_isp_isp_global_monitor_output_dma_clr_alarm_write(uintptr_t base,uint8_t data)1538 static __inline void acamera_isp_isp_global_monitor_output_dma_clr_alarm_write(uintptr_t base, uint8_t data) {
1539 uint32_t curr = system_hw_read_32(0x58L);
1540 system_hw_write_32(0x58L, (((uint32_t) (data & 0x1)) << 2) | (curr & 0xfffffffb));
1541 }
acamera_isp_isp_global_monitor_output_dma_clr_alarm_read(uintptr_t base)1542 static __inline uint8_t acamera_isp_isp_global_monitor_output_dma_clr_alarm_read(uintptr_t base) {
1543 return (uint8_t)((system_hw_read_32(0x58L) & 0x4) >> 2);
1544 }
1545 // ------------------------------------------------------------------------------ //
1546 // Register: temper dma clr alarm
1547 // ------------------------------------------------------------------------------ //
1548
1549 // ------------------------------------------------------------------------------ //
1550 //
1551 // This signal must be asserted when the MCU gets the DMA error interrupt.
1552 // This signal will clear all DMA error status signals for all the Temper DMA writers/readers
1553 // MCU must follow the following sequance to clear the alarms
1554 // step-1: set this bit to 1
1555 // step-2: Read back the alarm signals
1556 //
1557 // ------------------------------------------------------------------------------ //
1558
1559 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_CLR_ALARM_DEFAULT (0)
1560 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_CLR_ALARM_DATASIZE (1)
1561 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_CLR_ALARM_OFFSET (0x58)
1562 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_TEMPER_DMA_CLR_ALARM_MASK (0x8)
1563
1564 // args: data (1-bit)
acamera_isp_isp_global_monitor_temper_dma_clr_alarm_write(uintptr_t base,uint8_t data)1565 static __inline void acamera_isp_isp_global_monitor_temper_dma_clr_alarm_write(uintptr_t base, uint8_t data) {
1566 uint32_t curr = system_hw_read_32(0x58L);
1567 system_hw_write_32(0x58L, (((uint32_t) (data & 0x1)) << 3) | (curr & 0xfffffff7));
1568 }
acamera_isp_isp_global_monitor_temper_dma_clr_alarm_read(uintptr_t base)1569 static __inline uint8_t acamera_isp_isp_global_monitor_temper_dma_clr_alarm_read(uintptr_t base) {
1570 return (uint8_t)((system_hw_read_32(0x58L) & 0x8) >> 3);
1571 }
1572 // ------------------------------------------------------------------------------ //
1573 // Register: MAX address delay line fr
1574 // ------------------------------------------------------------------------------ //
1575
1576 // ------------------------------------------------------------------------------ //
1577 //
1578 // Delay line max address value for the full resolution ISP set outside ISP
1579 //
1580 // ------------------------------------------------------------------------------ //
1581
1582 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_MAX_ADDRESS_DELAY_LINE_FR_DEFAULT (0x0)
1583 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_MAX_ADDRESS_DELAY_LINE_FR_DATASIZE (16)
1584 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_MAX_ADDRESS_DELAY_LINE_FR_OFFSET (0x60)
1585 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_MAX_ADDRESS_DELAY_LINE_FR_MASK (0xffff)
1586
1587 // args: data (16-bit)
acamera_isp_isp_global_monitor_max_address_delay_line_fr_read(uintptr_t base)1588 static __inline uint16_t acamera_isp_isp_global_monitor_max_address_delay_line_fr_read(uintptr_t base) {
1589 return (uint16_t)((system_hw_read_32(0x60L) & 0xffff) >> 0);
1590 }
1591 // ------------------------------------------------------------------------------ //
1592 // Register: MAX address delay line ds
1593 // ------------------------------------------------------------------------------ //
1594
1595 // ------------------------------------------------------------------------------ //
1596 //
1597 // Delay line max address value for the DS pipeline set outside ISP
1598 //
1599 // ------------------------------------------------------------------------------ //
1600
1601 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_MAX_ADDRESS_DELAY_LINE_DS_DEFAULT (0x0)
1602 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_MAX_ADDRESS_DELAY_LINE_DS_DATASIZE (16)
1603 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_MAX_ADDRESS_DELAY_LINE_DS_OFFSET (0x60)
1604 #define ACAMERA_ISP_ISP_GLOBAL_MONITOR_MAX_ADDRESS_DELAY_LINE_DS_MASK (0xffff0000)
1605
1606 // args: data (16-bit)
acamera_isp_isp_global_monitor_max_address_delay_line_ds_read(uintptr_t base)1607 static __inline uint16_t acamera_isp_isp_global_monitor_max_address_delay_line_ds_read(uintptr_t base) {
1608 return (uint16_t)((system_hw_read_32(0x60L) & 0xffff0000) >> 16);
1609 }
1610 // ------------------------------------------------------------------------------ //
1611 // Group: isp global chicken bit
1612 // ------------------------------------------------------------------------------ //
1613
1614 // ------------------------------------------------------------------------------ //
1615 // Register: frame_end_select
1616 // ------------------------------------------------------------------------------ //
1617
1618 // ------------------------------------------------------------------------------ //
1619 //
1620 // 0: Only ISP main pipeline, ds pipeline and iridix filtering is used to generate the frame_done interrupt
1621 // None of the metering done signals are considered here
1622 // 1: all metering done is taken into account to generate the frame done interrupt
1623 //
1624 // ------------------------------------------------------------------------------ //
1625
1626 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_FRAME_END_SELECT_DEFAULT (0)
1627 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_FRAME_END_SELECT_DATASIZE (1)
1628 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_FRAME_END_SELECT_OFFSET (0x64)
1629 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_FRAME_END_SELECT_MASK (0x1)
1630
1631 // args: data (1-bit)
acamera_isp_isp_global_chicken_bit_frame_end_select_write(uintptr_t base,uint8_t data)1632 static __inline void acamera_isp_isp_global_chicken_bit_frame_end_select_write(uintptr_t base, uint8_t data) {
1633 uint32_t curr = system_hw_read_32(0x64L);
1634 system_hw_write_32(0x64L, (((uint32_t) (data & 0x1)) << 0) | (curr & 0xfffffffe));
1635 }
acamera_isp_isp_global_chicken_bit_frame_end_select_read(uintptr_t base)1636 static __inline uint8_t acamera_isp_isp_global_chicken_bit_frame_end_select_read(uintptr_t base) {
1637 return (uint8_t)((system_hw_read_32(0x64L) & 0x1) >> 0);
1638 }
1639 // ------------------------------------------------------------------------------ //
1640 // Register: rd_start_sel
1641 // ------------------------------------------------------------------------------ //
1642
1643 // ------------------------------------------------------------------------------ //
1644 //
1645 // 0: temper dma reader will start reading based on the frame start
1646 // 1: temper dma reader will start reading based on linetick of the dma reader
1647 //
1648 // ------------------------------------------------------------------------------ //
1649
1650 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_RD_START_SEL_DEFAULT (0)
1651 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_RD_START_SEL_DATASIZE (1)
1652 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_RD_START_SEL_OFFSET (0x64)
1653 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_RD_START_SEL_MASK (0x2)
1654
1655 // args: data (1-bit)
acamera_isp_isp_global_chicken_bit_rd_start_sel_write(uintptr_t base,uint8_t data)1656 static __inline void acamera_isp_isp_global_chicken_bit_rd_start_sel_write(uintptr_t base, uint8_t data) {
1657 uint32_t curr = system_hw_read_32(0x64L);
1658 system_hw_write_32(0x64L, (((uint32_t) (data & 0x1)) << 1) | (curr & 0xfffffffd));
1659 }
acamera_isp_isp_global_chicken_bit_rd_start_sel_read(uintptr_t base)1660 static __inline uint8_t acamera_isp_isp_global_chicken_bit_rd_start_sel_read(uintptr_t base) {
1661 return (uint8_t)((system_hw_read_32(0x64L) & 0x2) >> 1);
1662 }
1663 // ------------------------------------------------------------------------------ //
1664 // Register: input_alignment
1665 // ------------------------------------------------------------------------------ //
1666
1667 // ------------------------------------------------------------------------------ //
1668 //
1669 // 0=LSB aligned
1670 // 1=MSB aligned
1671 //
1672 // ------------------------------------------------------------------------------ //
1673
1674 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_INPUT_ALIGNMENT_DEFAULT (1)
1675 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_INPUT_ALIGNMENT_DATASIZE (1)
1676 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_INPUT_ALIGNMENT_OFFSET (0x64)
1677 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_INPUT_ALIGNMENT_MASK (0x4)
1678
1679 // args: data (1-bit)
acamera_isp_isp_global_chicken_bit_input_alignment_write(uintptr_t base,uint8_t data)1680 static __inline void acamera_isp_isp_global_chicken_bit_input_alignment_write(uintptr_t base, uint8_t data) {
1681 uint32_t curr = system_hw_read_32(0x64L);
1682 system_hw_write_32(0x64L, (((uint32_t) (data & 0x1)) << 2) | (curr & 0xfffffffb));
1683 }
acamera_isp_isp_global_chicken_bit_input_alignment_read(uintptr_t base)1684 static __inline uint8_t acamera_isp_isp_global_chicken_bit_input_alignment_read(uintptr_t base) {
1685 return (uint8_t)((system_hw_read_32(0x64L) & 0x4) >> 2);
1686 }
1687 // ------------------------------------------------------------------------------ //
1688 // Register: watchdog_timer_dis
1689 // ------------------------------------------------------------------------------ //
1690
1691 // ------------------------------------------------------------------------------ //
1692 //
1693 // 0=Watch dog timer enabled
1694 // 1=watch dog timer disabled
1695 //
1696 // ------------------------------------------------------------------------------ //
1697
1698 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_WATCHDOG_TIMER_DIS_DEFAULT (0)
1699 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_WATCHDOG_TIMER_DIS_DATASIZE (1)
1700 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_WATCHDOG_TIMER_DIS_OFFSET (0x64)
1701 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_WATCHDOG_TIMER_DIS_MASK (0x8)
1702
1703 // args: data (1-bit)
acamera_isp_isp_global_chicken_bit_watchdog_timer_dis_write(uintptr_t base,uint8_t data)1704 static __inline void acamera_isp_isp_global_chicken_bit_watchdog_timer_dis_write(uintptr_t base, uint8_t data) {
1705 uint32_t curr = system_hw_read_32(0x64L);
1706 system_hw_write_32(0x64L, (((uint32_t) (data & 0x1)) << 3) | (curr & 0xfffffff7));
1707 }
acamera_isp_isp_global_chicken_bit_watchdog_timer_dis_read(uintptr_t base)1708 static __inline uint8_t acamera_isp_isp_global_chicken_bit_watchdog_timer_dis_read(uintptr_t base) {
1709 return (uint8_t)((system_hw_read_32(0x64L) & 0x8) >> 3);
1710 }
1711 // ------------------------------------------------------------------------------ //
1712 // Register: soft_rst_apply_immediately
1713 // ------------------------------------------------------------------------------ //
1714
1715 // ------------------------------------------------------------------------------ //
1716 //
1717 // 0 = When this chicken bit is et to 0, the soft reset (SW or HW generated) will be stretched by 1024 cycles
1718 // so that it is asserted till the the pipeline delay of internal acl signals.
1719 // 1 = When thiss set to 1, the soft reset will not be stretched internally. The SW must make sure its
1720 // kept high enough.
1721 //
1722 // ------------------------------------------------------------------------------ //
1723
1724 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_SOFT_RST_APPLY_IMMEDIATELY_DEFAULT (0)
1725 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_SOFT_RST_APPLY_IMMEDIATELY_DATASIZE (1)
1726 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_SOFT_RST_APPLY_IMMEDIATELY_OFFSET (0x64)
1727 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_SOFT_RST_APPLY_IMMEDIATELY_MASK (0x10)
1728
1729 // args: data (1-bit)
acamera_isp_isp_global_chicken_bit_soft_rst_apply_immediately_write(uintptr_t base,uint8_t data)1730 static __inline void acamera_isp_isp_global_chicken_bit_soft_rst_apply_immediately_write(uintptr_t base, uint8_t data) {
1731 uint32_t curr = system_hw_read_32(0x64L);
1732 system_hw_write_32(0x64L, (((uint32_t) (data & 0x1)) << 4) | (curr & 0xffffffef));
1733 }
acamera_isp_isp_global_chicken_bit_soft_rst_apply_immediately_read(uintptr_t base)1734 static __inline uint8_t acamera_isp_isp_global_chicken_bit_soft_rst_apply_immediately_read(uintptr_t base) {
1735 return (uint8_t)((system_hw_read_32(0x64L) & 0x10) >> 4);
1736 }
1737 // ------------------------------------------------------------------------------ //
1738 // Register: dma_writer_timeout_disable
1739 // ------------------------------------------------------------------------------ //
1740
1741 // ------------------------------------------------------------------------------ //
1742 //
1743 // 0=timeout enabled. At the end of the frame, if the last data is not drained out from DMA writer within 4000
1744 // AXI clock, cycle, DMA will flush the FIFO and ignore the remainign data.
1745 //
1746 // 1=timeout is disabled. If the last data is not drained out and the next frame starts coming in, DMA will drop the next frame and
1747 // give an interrupt.
1748 // If the timeout is disabled, its S/W responsibility to cancel the frame in all dma engines if frame drop interrupt comes.
1749 //
1750 // ------------------------------------------------------------------------------ //
1751
1752 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_DMA_WRITER_TIMEOUT_DISABLE_DEFAULT (0)
1753 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_DMA_WRITER_TIMEOUT_DISABLE_DATASIZE (1)
1754 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_DMA_WRITER_TIMEOUT_DISABLE_OFFSET (0x64)
1755 #define ACAMERA_ISP_ISP_GLOBAL_CHICKEN_BIT_DMA_WRITER_TIMEOUT_DISABLE_MASK (0x20)
1756
1757 // args: data (1-bit)
acamera_isp_isp_global_chicken_bit_dma_writer_timeout_disable_write(uintptr_t base,uint8_t data)1758 static __inline void acamera_isp_isp_global_chicken_bit_dma_writer_timeout_disable_write(uintptr_t base, uint8_t data) {
1759 uint32_t curr = system_hw_read_32(0x64L);
1760 system_hw_write_32(0x64L, (((uint32_t) (data & 0x1)) << 5) | (curr & 0xffffffdf));
1761 }
acamera_isp_isp_global_chicken_bit_dma_writer_timeout_disable_read(uintptr_t base)1762 static __inline uint8_t acamera_isp_isp_global_chicken_bit_dma_writer_timeout_disable_read(uintptr_t base) {
1763 return (uint8_t)((system_hw_read_32(0x64L) & 0x20) >> 5);
1764 }
1765 // ------------------------------------------------------------------------------ //
1766 // Group: isp global parameter status
1767 // ------------------------------------------------------------------------------ //
1768
1769 // ------------------------------------------------------------------------------ //
1770 //
1771 // ISP provides few CHICKEN_OUT parameters through which certain modules can be removed from ISP.
1772 // This reggister indicates the status of that CHICKEN BIT
1773 //
1774 // ------------------------------------------------------------------------------ //
1775
1776 // ------------------------------------------------------------------------------ //
1777 // Register: dmsc_rgbir
1778 // ------------------------------------------------------------------------------ //
1779
1780 // ------------------------------------------------------------------------------ //
1781 //
1782 // 0: Demosaic RGBIr is present in the design
1783 // 1: Demodaic RGBIr is statically removed from the ISP.
1784 // S/W must not access the ISP_CONFIG_PING:demosaic rgbir and the ISP_CONFIG_PONG:demosaic rgbir registers
1785 //
1786 // ------------------------------------------------------------------------------ //
1787
1788 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_DMSC_RGBIR_DEFAULT (0)
1789 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_DMSC_RGBIR_DATASIZE (1)
1790 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_DMSC_RGBIR_OFFSET (0x68)
1791 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_DMSC_RGBIR_MASK (0x1)
1792
1793 // args: data (1-bit)
acamera_isp_isp_global_parameter_status_dmsc_rgbir_read(uintptr_t base)1794 static __inline uint8_t acamera_isp_isp_global_parameter_status_dmsc_rgbir_read(uintptr_t base) {
1795 return (uint8_t)((system_hw_read_32(0x68L) & 0x1) >> 0);
1796 }
1797 // ------------------------------------------------------------------------------ //
1798 // Register: cac
1799 // ------------------------------------------------------------------------------ //
1800
1801 // ------------------------------------------------------------------------------ //
1802 //
1803 // 0: CA Correction is present in the design
1804 // 1: CA Correction is statically removed from the ISP.
1805 // S/W must not access the ISP_CONFIG_PING:ca correction and the ISP_CONFIG_PONG:ca correction registers
1806 //
1807 // Also SW must not access the following memories
1808 // - CA_CORRECTION_FILTER_PING_MEM
1809 // - CA_CORRECTION_FILTER_PONG_MEM
1810 // - CA_CORRECTION_MESH_PING_MEM
1811 // - CA_CORRECTION_MESH_PONG_MEM
1812 //
1813 // ------------------------------------------------------------------------------ //
1814
1815 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_CAC_DEFAULT (0)
1816 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_CAC_DATASIZE (1)
1817 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_CAC_OFFSET (0x68)
1818 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_CAC_MASK (0x2)
1819
1820 // args: data (1-bit)
acamera_isp_isp_global_parameter_status_cac_read(uintptr_t base)1821 static __inline uint8_t acamera_isp_isp_global_parameter_status_cac_read(uintptr_t base) {
1822 return (uint8_t)((system_hw_read_32(0x68L) & 0x2) >> 1);
1823 }
1824 // ------------------------------------------------------------------------------ //
1825 // Register: ds_pipe
1826 // ------------------------------------------------------------------------------ //
1827
1828 // ------------------------------------------------------------------------------ //
1829 //
1830 // 0: DS pipeline is present in the design
1831 // 1: DS pipeline is statically removed from ISP.
1832 // S/W must not access the following register spaces
1833 // - ISP_CONFIG_PING:ds crop and ISP_CONFIG_PONG:ds crop
1834 // - ISP_CONFIG_PING:ds scaler and ISP_CONFIG_PONG:ds scaler
1835 // - ISP_CONFIG_PING:ds gamma rgb and ISP_CONFIG_PONG:ds gamma rgb
1836 // - ISP_CONFIG_PING:ds sharpen and ISP_CONFIG_PONG:ds sharpen
1837 // - ISP_CONFIG_PING:ds cs conv and ISP_CONFIG_PONG:ds cs conv
1838 // - ISP_CONFIG_PING:ds dma writer and ISP_CONFIG_PONG:ds dma writer
1839 // - ISP_CONFIG_PING:ds uv dma writer and ISP_CONFIG_PONG:ds uv dma writer
1840 //
1841 // Also the S/W must not access the following memories
1842 // - DS_SCALER_HFILT_COEFMEM
1843 // - DS_SCALER_VFILT_COEFMEM
1844 // - DS_GAMMA_RGB_PING_MEM
1845 // - DS_GAMMA_RGB_PONG_MEM
1846 //
1847 // ------------------------------------------------------------------------------ //
1848
1849 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_DS1_PIPE_DEFAULT (0)
1850 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_DS1_PIPE_DATASIZE (1)
1851 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_DS1_PIPE_OFFSET (0x68)
1852 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_DS1_PIPE_MASK (0x4)
1853
1854 // args: data (1-bit)
acamera_isp_isp_global_parameter_status_ds1_pipe_read(uintptr_t base)1855 static __inline uint8_t acamera_isp_isp_global_parameter_status_ds1_pipe_read(uintptr_t base) {
1856 return (uint8_t)((system_hw_read_32(0x68L) & 0x4) >> 2);
1857 }
1858 // ------------------------------------------------------------------------------ //
1859 // Register: LUT 3d
1860 // ------------------------------------------------------------------------------ //
1861
1862 // ------------------------------------------------------------------------------ //
1863 //
1864 // 0: sRGB gamma and 3D LUT is present in the design
1865 // 1: sRGB gamma and 3D LUT is statically removed from ISP.
1866 // The S/W must not accees the following register spaces
1867 // - ISP_CONFIG_PING:nonequ gamma and ISP_CONFIG_PING: nonequ gamma and
1868 //
1869 // Also, the S/W must not access the following memories
1870 // - LUT3D_MEM
1871 //
1872 // ------------------------------------------------------------------------------ //
1873
1874 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_LUT_3D_DEFAULT (0)
1875 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_LUT_3D_DATASIZE (1)
1876 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_LUT_3D_OFFSET (0x68)
1877 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_LUT_3D_MASK (0x8)
1878
1879 // args: data (1-bit)
acamera_isp_isp_global_parameter_status_lut_3d_read(uintptr_t base)1880 static __inline uint8_t acamera_isp_isp_global_parameter_status_lut_3d_read(uintptr_t base) {
1881 return (uint8_t)((system_hw_read_32(0x68L) & 0x8) >> 3);
1882 }
1883 // ------------------------------------------------------------------------------ //
1884 // Register: sinter_version
1885 // ------------------------------------------------------------------------------ //
1886
1887 // ------------------------------------------------------------------------------ //
1888 //
1889 // 0: SINTER2.5 used
1890 // 1: SINTER3 used
1891 //
1892 // ------------------------------------------------------------------------------ //
1893
1894 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_SINTER_VERSION_DEFAULT (1)
1895 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_SINTER_VERSION_DATASIZE (1)
1896 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_SINTER_VERSION_OFFSET (0x68)
1897 #define ACAMERA_ISP_ISP_GLOBAL_PARAMETER_STATUS_SINTER_VERSION_MASK (0x10)
1898
1899 // args: data (1-bit)
acamera_isp_isp_global_parameter_status_sinter_version_read(uintptr_t base)1900 static __inline uint8_t acamera_isp_isp_global_parameter_status_sinter_version_read(uintptr_t base) {
1901 return (uint8_t)((system_hw_read_32(0x68L) & 0x10) >> 4);
1902 }
1903 // ------------------------------------------------------------------------------ //
1904 // Group: isp global dbg
1905 // ------------------------------------------------------------------------------ //
1906
1907 // ------------------------------------------------------------------------------ //
1908 // Register: mode_en
1909 // ------------------------------------------------------------------------------ //
1910
1911 // ------------------------------------------------------------------------------ //
1912 //
1913 // 0: debug signals are disabled
1914 // 1: debug signals are valid
1915 //
1916 // ------------------------------------------------------------------------------ //
1917
1918 #define ACAMERA_ISP_ISP_GLOBAL_DBG_MODE_EN_DEFAULT (0)
1919 #define ACAMERA_ISP_ISP_GLOBAL_DBG_MODE_EN_DATASIZE (1)
1920 #define ACAMERA_ISP_ISP_GLOBAL_DBG_MODE_EN_OFFSET (0x6c)
1921 #define ACAMERA_ISP_ISP_GLOBAL_DBG_MODE_EN_MASK (0x1)
1922
1923 // args: data (1-bit)
acamera_isp_isp_global_dbg_mode_en_write(uintptr_t base,uint8_t data)1924 static __inline void acamera_isp_isp_global_dbg_mode_en_write(uintptr_t base, uint8_t data) {
1925 uint32_t curr = system_hw_read_32(0x6cL);
1926 system_hw_write_32(0x6cL, (((uint32_t) (data & 0x1)) << 0) | (curr & 0xfffffffe));
1927 }
acamera_isp_isp_global_dbg_mode_en_read(uintptr_t base)1928 static __inline uint8_t acamera_isp_isp_global_dbg_mode_en_read(uintptr_t base) {
1929 return (uint8_t)((system_hw_read_32(0x6cL) & 0x1) >> 0);
1930 }
1931 // ------------------------------------------------------------------------------ //
1932 // Register: clear_frame_cnt
1933 // ------------------------------------------------------------------------------ //
1934
1935 // ------------------------------------------------------------------------------ //
1936 //
1937 // must be 0->1->0 to clear the debug counters
1938 //
1939 // ------------------------------------------------------------------------------ //
1940
1941 #define ACAMERA_ISP_ISP_GLOBAL_DBG_CLEAR_FRAME_CNT_DEFAULT (0)
1942 #define ACAMERA_ISP_ISP_GLOBAL_DBG_CLEAR_FRAME_CNT_DATASIZE (1)
1943 #define ACAMERA_ISP_ISP_GLOBAL_DBG_CLEAR_FRAME_CNT_OFFSET (0x6c)
1944 #define ACAMERA_ISP_ISP_GLOBAL_DBG_CLEAR_FRAME_CNT_MASK (0x100)
1945
1946 // args: data (1-bit)
acamera_isp_isp_global_dbg_clear_frame_cnt_write(uintptr_t base,uint8_t data)1947 static __inline void acamera_isp_isp_global_dbg_clear_frame_cnt_write(uintptr_t base, uint8_t data) {
1948 uint32_t curr = system_hw_read_32(0x6cL);
1949 system_hw_write_32(0x6cL, (((uint32_t) (data & 0x1)) << 8) | (curr & 0xfffffeff));
1950 }
acamera_isp_isp_global_dbg_clear_frame_cnt_read(uintptr_t base)1951 static __inline uint8_t acamera_isp_isp_global_dbg_clear_frame_cnt_read(uintptr_t base) {
1952 return (uint8_t)((system_hw_read_32(0x6cL) & 0x100) >> 8);
1953 }
1954 // ------------------------------------------------------------------------------ //
1955 // Register: frame_cnt_ctx0
1956 // ------------------------------------------------------------------------------ //
1957
1958 // ------------------------------------------------------------------------------ //
1959 //
1960 // when debug mode is enabled, this register will show the frame count in context-0
1961 //
1962 // ------------------------------------------------------------------------------ //
1963
1964 #define ACAMERA_ISP_ISP_GLOBAL_DBG_FRAME_CNT_CTX0_DEFAULT (0)
1965 #define ACAMERA_ISP_ISP_GLOBAL_DBG_FRAME_CNT_CTX0_DATASIZE (32)
1966 #define ACAMERA_ISP_ISP_GLOBAL_DBG_FRAME_CNT_CTX0_OFFSET (0x70)
1967 #define ACAMERA_ISP_ISP_GLOBAL_DBG_FRAME_CNT_CTX0_MASK (0xffffffff)
1968
1969 // args: data (32-bit)
acamera_isp_isp_global_dbg_frame_cnt_ctx0_read(uintptr_t base)1970 static __inline uint32_t acamera_isp_isp_global_dbg_frame_cnt_ctx0_read(uintptr_t base) {
1971 return system_hw_read_32(0x70L);
1972 }
1973 // ------------------------------------------------------------------------------ //
1974 // Register: frame_cnt_ctx1
1975 // ------------------------------------------------------------------------------ //
1976
1977 // ------------------------------------------------------------------------------ //
1978 //
1979 // when debug mode is enabled, this register will show the frame count in context-1
1980 //
1981 // ------------------------------------------------------------------------------ //
1982
1983 #define ACAMERA_ISP_ISP_GLOBAL_DBG_FRAME_CNT_CTX1_DEFAULT (0)
1984 #define ACAMERA_ISP_ISP_GLOBAL_DBG_FRAME_CNT_CTX1_DATASIZE (32)
1985 #define ACAMERA_ISP_ISP_GLOBAL_DBG_FRAME_CNT_CTX1_OFFSET (0x74)
1986 #define ACAMERA_ISP_ISP_GLOBAL_DBG_FRAME_CNT_CTX1_MASK (0xffffffff)
1987
1988 // args: data (32-bit)
acamera_isp_isp_global_dbg_frame_cnt_ctx1_read(uintptr_t base)1989 static __inline uint32_t acamera_isp_isp_global_dbg_frame_cnt_ctx1_read(uintptr_t base) {
1990 return system_hw_read_32(0x74L);
1991 }
1992 // ------------------------------------------------------------------------------ //
1993 // Register: frame_cnt_ctx2
1994 // ------------------------------------------------------------------------------ //
1995
1996 // ------------------------------------------------------------------------------ //
1997 //
1998 // when debug mode is enabled, this register will show the frame count in context-2
1999 //
2000 // ------------------------------------------------------------------------------ //
2001
2002 #define ACAMERA_ISP_ISP_GLOBAL_DBG_FRAME_CNT_CTX2_DEFAULT (0)
2003 #define ACAMERA_ISP_ISP_GLOBAL_DBG_FRAME_CNT_CTX2_DATASIZE (32)
2004 #define ACAMERA_ISP_ISP_GLOBAL_DBG_FRAME_CNT_CTX2_OFFSET (0x78)
2005 #define ACAMERA_ISP_ISP_GLOBAL_DBG_FRAME_CNT_CTX2_MASK (0xffffffff)
2006
2007 // args: data (32-bit)
acamera_isp_isp_global_dbg_frame_cnt_ctx2_read(uintptr_t base)2008 static __inline uint32_t acamera_isp_isp_global_dbg_frame_cnt_ctx2_read(uintptr_t base) {
2009 return system_hw_read_32(0x78L);
2010 }
2011 // ------------------------------------------------------------------------------ //
2012 // Register: frame_cnt_ctx3
2013 // ------------------------------------------------------------------------------ //
2014
2015 // ------------------------------------------------------------------------------ //
2016 //
2017 // when debug mode is enabled, this register will show the frame count in context-3
2018 //
2019 // ------------------------------------------------------------------------------ //
2020
2021 #define ACAMERA_ISP_ISP_GLOBAL_DBG_FRAME_CNT_CTX3_DEFAULT (0)
2022 #define ACAMERA_ISP_ISP_GLOBAL_DBG_FRAME_CNT_CTX3_DATASIZE (32)
2023 #define ACAMERA_ISP_ISP_GLOBAL_DBG_FRAME_CNT_CTX3_OFFSET (0x7c)
2024 #define ACAMERA_ISP_ISP_GLOBAL_DBG_FRAME_CNT_CTX3_MASK (0xffffffff)
2025
2026 // args: data (32-bit)
acamera_isp_isp_global_dbg_frame_cnt_ctx3_read(uintptr_t base)2027 static __inline uint32_t acamera_isp_isp_global_dbg_frame_cnt_ctx3_read(uintptr_t base) {
2028 return system_hw_read_32(0x7cL);
2029 }
2030 // ------------------------------------------------------------------------------ //
2031 // Group: input port
2032 // ------------------------------------------------------------------------------ //
2033
2034 // ------------------------------------------------------------------------------ //
2035 // Controls video input port.
2036 // ------------------------------------------------------------------------------ //
2037
2038 // ------------------------------------------------------------------------------ //
2039 // Register: preset
2040 // ------------------------------------------------------------------------------ //
2041
2042 // ------------------------------------------------------------------------------ //
2043 // Allows selection of various input port presets for standard sensor inputs. See ISP Guide for details of available presets.
2044 // 2: preset mode 2, check ISP guide for details
2045 // 6: preset mode 6, check ISP guide for details
2046 // others: reserved
2047 //
2048 // ------------------------------------------------------------------------------ //
2049
2050 #define ACAMERA_ISP_INPUT_PORT_PRESET_DEFAULT (2)
2051 #define ACAMERA_ISP_INPUT_PORT_PRESET_DATASIZE (4)
2052 #define ACAMERA_ISP_INPUT_PORT_PRESET_OFFSET (0x80)
2053 #define ACAMERA_ISP_INPUT_PORT_PRESET_MASK (0xf)
2054
2055 // args: data (4-bit)
acamera_isp_input_port_preset_write(uintptr_t base,uint8_t data)2056 static __inline void acamera_isp_input_port_preset_write(uintptr_t base, uint8_t data) {
2057 uint32_t curr = system_hw_read_32(0x80L);
2058 system_hw_write_32(0x80L, (((uint32_t) (data & 0xf)) << 0) | (curr & 0xfffffff0));
2059 }
acamera_isp_input_port_preset_read(uintptr_t base)2060 static __inline uint8_t acamera_isp_input_port_preset_read(uintptr_t base) {
2061 return (uint8_t)((system_hw_read_32(0x80L) & 0xf) >> 0);
2062 }
2063 // ------------------------------------------------------------------------------ //
2064 // Register: vs_use field
2065 // ------------------------------------------------------------------------------ //
2066
2067 #define ACAMERA_ISP_INPUT_PORT_VS_USE_FIELD_DEFAULT (0)
2068 #define ACAMERA_ISP_INPUT_PORT_VS_USE_FIELD_DATASIZE (1)
2069 #define ACAMERA_ISP_INPUT_PORT_VS_USE_FIELD_OFFSET (0x80)
2070 #define ACAMERA_ISP_INPUT_PORT_VS_USE_FIELD_MASK (0x100)
2071 #define ACAMERA_ISP_INPUT_PORT_VS_USE_FIELD_USE_VSYNC_I_PORT_FOR_VERTICAL_SYNC (0)
2072 #define ACAMERA_ISP_INPUT_PORT_VS_USE_FIELD_USE_FIELD_I_PORT_FOR_VERTICAL_SYNC (1)
2073
2074 // args: data (1-bit)
acamera_isp_input_port_vs_use_field_write(uintptr_t base,uint8_t data)2075 static __inline void acamera_isp_input_port_vs_use_field_write(uintptr_t base, uint8_t data) {
2076 uint32_t curr = system_hw_read_32(0x80L);
2077 system_hw_write_32(0x80L, (((uint32_t) (data & 0x1)) << 8) | (curr & 0xfffffeff));
2078 }
acamera_isp_input_port_vs_use_field_read(uintptr_t base)2079 static __inline uint8_t acamera_isp_input_port_vs_use_field_read(uintptr_t base) {
2080 return (uint8_t)((system_hw_read_32(0x80L) & 0x100) >> 8);
2081 }
2082 // ------------------------------------------------------------------------------ //
2083 // Register: vs toggle
2084 // ------------------------------------------------------------------------------ //
2085
2086 #define ACAMERA_ISP_INPUT_PORT_VS_TOGGLE_DEFAULT (0)
2087 #define ACAMERA_ISP_INPUT_PORT_VS_TOGGLE_DATASIZE (1)
2088 #define ACAMERA_ISP_INPUT_PORT_VS_TOGGLE_OFFSET (0x80)
2089 #define ACAMERA_ISP_INPUT_PORT_VS_TOGGLE_MASK (0x200)
2090 #define ACAMERA_ISP_INPUT_PORT_VS_TOGGLE_VSYNC_IS_PULSETYPE (0)
2091 #define ACAMERA_ISP_INPUT_PORT_VS_TOGGLE_VSYNC_IS_TOGGLETYPE_FIELD_SIGNAL (1)
2092
2093 // args: data (1-bit)
acamera_isp_input_port_vs_toggle_write(uintptr_t base,uint8_t data)2094 static __inline void acamera_isp_input_port_vs_toggle_write(uintptr_t base, uint8_t data) {
2095 uint32_t curr = system_hw_read_32(0x80L);
2096 system_hw_write_32(0x80L, (((uint32_t) (data & 0x1)) << 9) | (curr & 0xfffffdff));
2097 }
acamera_isp_input_port_vs_toggle_read(uintptr_t base)2098 static __inline uint8_t acamera_isp_input_port_vs_toggle_read(uintptr_t base) {
2099 return (uint8_t)((system_hw_read_32(0x80L) & 0x200) >> 9);
2100 }
2101 // ------------------------------------------------------------------------------ //
2102 // Register: vs polarity
2103 // ------------------------------------------------------------------------------ //
2104
2105 #define ACAMERA_ISP_INPUT_PORT_VS_POLARITY_DEFAULT (0)
2106 #define ACAMERA_ISP_INPUT_PORT_VS_POLARITY_DATASIZE (1)
2107 #define ACAMERA_ISP_INPUT_PORT_VS_POLARITY_OFFSET (0x80)
2108 #define ACAMERA_ISP_INPUT_PORT_VS_POLARITY_MASK (0x400)
2109 #define ACAMERA_ISP_INPUT_PORT_VS_POLARITY_HORIZONTAL_COUNTER_RESET_ON_RISING_EDGE (0)
2110 #define ACAMERA_ISP_INPUT_PORT_VS_POLARITY_HORIZONTAL_COUNTER_RESET_ON_FALLING_EDGE (1)
2111
2112 // args: data (1-bit)
acamera_isp_input_port_vs_polarity_write(uintptr_t base,uint8_t data)2113 static __inline void acamera_isp_input_port_vs_polarity_write(uintptr_t base, uint8_t data) {
2114 uint32_t curr = system_hw_read_32(0x80L);
2115 system_hw_write_32(0x80L, (((uint32_t) (data & 0x1)) << 10) | (curr & 0xfffffbff));
2116 }
acamera_isp_input_port_vs_polarity_read(uintptr_t base)2117 static __inline uint8_t acamera_isp_input_port_vs_polarity_read(uintptr_t base) {
2118 return (uint8_t)((system_hw_read_32(0x80L) & 0x400) >> 10);
2119 }
2120 // ------------------------------------------------------------------------------ //
2121 // Register: vs_polarity acl
2122 // ------------------------------------------------------------------------------ //
2123
2124 #define ACAMERA_ISP_INPUT_PORT_VS_POLARITY_ACL_DEFAULT (0)
2125 #define ACAMERA_ISP_INPUT_PORT_VS_POLARITY_ACL_DATASIZE (1)
2126 #define ACAMERA_ISP_INPUT_PORT_VS_POLARITY_ACL_OFFSET (0x80)
2127 #define ACAMERA_ISP_INPUT_PORT_VS_POLARITY_ACL_MASK (0x800)
2128 #define ACAMERA_ISP_INPUT_PORT_VS_POLARITY_ACL_DONT_INVERT_POLARITY_FOR_ACL_GATE (0)
2129 #define ACAMERA_ISP_INPUT_PORT_VS_POLARITY_ACL_INVERT_POLARITY_FOR_ACL_GATE (1)
2130
2131 // args: data (1-bit)
acamera_isp_input_port_vs_polarity_acl_write(uintptr_t base,uint8_t data)2132 static __inline void acamera_isp_input_port_vs_polarity_acl_write(uintptr_t base, uint8_t data) {
2133 uint32_t curr = system_hw_read_32(0x80L);
2134 system_hw_write_32(0x80L, (((uint32_t) (data & 0x1)) << 11) | (curr & 0xfffff7ff));
2135 }
acamera_isp_input_port_vs_polarity_acl_read(uintptr_t base)2136 static __inline uint8_t acamera_isp_input_port_vs_polarity_acl_read(uintptr_t base) {
2137 return (uint8_t)((system_hw_read_32(0x80L) & 0x800) >> 11);
2138 }
2139 // ------------------------------------------------------------------------------ //
2140 // Register: hs_use acl
2141 // ------------------------------------------------------------------------------ //
2142
2143 #define ACAMERA_ISP_INPUT_PORT_HS_USE_ACL_DEFAULT (0)
2144 #define ACAMERA_ISP_INPUT_PORT_HS_USE_ACL_DATASIZE (1)
2145 #define ACAMERA_ISP_INPUT_PORT_HS_USE_ACL_OFFSET (0x80)
2146 #define ACAMERA_ISP_INPUT_PORT_HS_USE_ACL_MASK (0x1000)
2147 #define ACAMERA_ISP_INPUT_PORT_HS_USE_ACL_USE_HSYNC_I_PORT_FOR_ACTIVELINE (0)
2148 #define ACAMERA_ISP_INPUT_PORT_HS_USE_ACL_USE_ACL_I_PORT_FOR_ACTIVELINE (1)
2149
2150 // args: data (1-bit)
acamera_isp_input_port_hs_use_acl_write(uintptr_t base,uint8_t data)2151 static __inline void acamera_isp_input_port_hs_use_acl_write(uintptr_t base, uint8_t data) {
2152 uint32_t curr = system_hw_read_32(0x80L);
2153 system_hw_write_32(0x80L, (((uint32_t) (data & 0x1)) << 12) | (curr & 0xffffefff));
2154 }
acamera_isp_input_port_hs_use_acl_read(uintptr_t base)2155 static __inline uint8_t acamera_isp_input_port_hs_use_acl_read(uintptr_t base) {
2156 return (uint8_t)((system_hw_read_32(0x80L) & 0x1000) >> 12);
2157 }
2158 // ------------------------------------------------------------------------------ //
2159 // Register: vc_c select
2160 // ------------------------------------------------------------------------------ //
2161
2162 #define ACAMERA_ISP_INPUT_PORT_VC_C_SELECT_DEFAULT (0)
2163 #define ACAMERA_ISP_INPUT_PORT_VC_C_SELECT_DATASIZE (1)
2164 #define ACAMERA_ISP_INPUT_PORT_VC_C_SELECT_OFFSET (0x80)
2165 #define ACAMERA_ISP_INPUT_PORT_VC_C_SELECT_MASK (0x4000)
2166 #define ACAMERA_ISP_INPUT_PORT_VC_C_SELECT_VERTICAL_COUNTER_COUNTS_ON_HS (0)
2167 #define ACAMERA_ISP_INPUT_PORT_VC_C_SELECT_VERTICAL_COUNTER_COUNTS_ON_HORIZONTAL_COUNTER_OVERFLOW_OR_RESET (1)
2168
2169 // args: data (1-bit)
acamera_isp_input_port_vc_c_select_write(uintptr_t base,uint8_t data)2170 static __inline void acamera_isp_input_port_vc_c_select_write(uintptr_t base, uint8_t data) {
2171 uint32_t curr = system_hw_read_32(0x80L);
2172 system_hw_write_32(0x80L, (((uint32_t) (data & 0x1)) << 14) | (curr & 0xffffbfff));
2173 }
acamera_isp_input_port_vc_c_select_read(uintptr_t base)2174 static __inline uint8_t acamera_isp_input_port_vc_c_select_read(uintptr_t base) {
2175 return (uint8_t)((system_hw_read_32(0x80L) & 0x4000) >> 14);
2176 }
2177 // ------------------------------------------------------------------------------ //
2178 // Register: vc_r select
2179 // ------------------------------------------------------------------------------ //
2180
2181 #define ACAMERA_ISP_INPUT_PORT_VC_R_SELECT_DEFAULT (0)
2182 #define ACAMERA_ISP_INPUT_PORT_VC_R_SELECT_DATASIZE (1)
2183 #define ACAMERA_ISP_INPUT_PORT_VC_R_SELECT_OFFSET (0x80)
2184 #define ACAMERA_ISP_INPUT_PORT_VC_R_SELECT_MASK (0x8000)
2185 #define ACAMERA_ISP_INPUT_PORT_VC_R_SELECT_VERTICAL_COUNTER_IS_RESET_ON_EDGE_OF_VS (0)
2186 #define ACAMERA_ISP_INPUT_PORT_VC_R_SELECT_VERTICAL_COUNTER_IS_RESET_AFTER_TIMEOUT_ON_HS (1)
2187
2188 // args: data (1-bit)
acamera_isp_input_port_vc_r_select_write(uintptr_t base,uint8_t data)2189 static __inline void acamera_isp_input_port_vc_r_select_write(uintptr_t base, uint8_t data) {
2190 uint32_t curr = system_hw_read_32(0x80L);
2191 system_hw_write_32(0x80L, (((uint32_t) (data & 0x1)) << 15) | (curr & 0xffff7fff));
2192 }
acamera_isp_input_port_vc_r_select_read(uintptr_t base)2193 static __inline uint8_t acamera_isp_input_port_vc_r_select_read(uintptr_t base) {
2194 return (uint8_t)((system_hw_read_32(0x80L) & 0x8000) >> 15);
2195 }
2196 // ------------------------------------------------------------------------------ //
2197 // Register: hs_xor vs
2198 // ------------------------------------------------------------------------------ //
2199
2200 #define ACAMERA_ISP_INPUT_PORT_HS_XOR_VS_DEFAULT (0)
2201 #define ACAMERA_ISP_INPUT_PORT_HS_XOR_VS_DATASIZE (1)
2202 #define ACAMERA_ISP_INPUT_PORT_HS_XOR_VS_OFFSET (0x80)
2203 #define ACAMERA_ISP_INPUT_PORT_HS_XOR_VS_MASK (0x10000)
2204 #define ACAMERA_ISP_INPUT_PORT_HS_XOR_VS_NORMAL_MODE (0)
2205 #define ACAMERA_ISP_INPUT_PORT_HS_XOR_VS_HVALID__HSYNC_XOR_VSYNC (1)
2206
2207 // args: data (1-bit)
acamera_isp_input_port_hs_xor_vs_write(uintptr_t base,uint8_t data)2208 static __inline void acamera_isp_input_port_hs_xor_vs_write(uintptr_t base, uint8_t data) {
2209 uint32_t curr = system_hw_read_32(0x80L);
2210 system_hw_write_32(0x80L, (((uint32_t) (data & 0x1)) << 16) | (curr & 0xfffeffff));
2211 }
acamera_isp_input_port_hs_xor_vs_read(uintptr_t base)2212 static __inline uint8_t acamera_isp_input_port_hs_xor_vs_read(uintptr_t base) {
2213 return (uint8_t)((system_hw_read_32(0x80L) & 0x10000) >> 16);
2214 }
2215 // ------------------------------------------------------------------------------ //
2216 // Register: hs polarity
2217 // ------------------------------------------------------------------------------ //
2218
2219 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_DEFAULT (0)
2220 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_DATASIZE (1)
2221 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_OFFSET (0x80)
2222 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_MASK (0x20000)
2223 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_DONT_INVERT_POLARITY_OF_HS_FOR_ACL_GATE (0)
2224 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_INVERT_POLARITY_OF_HS_FOR_ACL_GATE (1)
2225
2226 // args: data (1-bit)
acamera_isp_input_port_hs_polarity_write(uintptr_t base,uint8_t data)2227 static __inline void acamera_isp_input_port_hs_polarity_write(uintptr_t base, uint8_t data) {
2228 uint32_t curr = system_hw_read_32(0x80L);
2229 system_hw_write_32(0x80L, (((uint32_t) (data & 0x1)) << 17) | (curr & 0xfffdffff));
2230 }
acamera_isp_input_port_hs_polarity_read(uintptr_t base)2231 static __inline uint8_t acamera_isp_input_port_hs_polarity_read(uintptr_t base) {
2232 return (uint8_t)((system_hw_read_32(0x80L) & 0x20000) >> 17);
2233 }
2234 // ------------------------------------------------------------------------------ //
2235 // Register: hs_polarity acl
2236 // ------------------------------------------------------------------------------ //
2237
2238 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_ACL_DEFAULT (0)
2239 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_ACL_DATASIZE (1)
2240 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_ACL_OFFSET (0x80)
2241 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_ACL_MASK (0x40000)
2242 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_ACL_DONT_INVERT_POLARITY_OF_HS_FOR_HS_GATE (0)
2243 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_ACL_INVERT_POLARITY_OF_HS_FOR_HS_GATE (1)
2244
2245 // args: data (1-bit)
acamera_isp_input_port_hs_polarity_acl_write(uintptr_t base,uint8_t data)2246 static __inline void acamera_isp_input_port_hs_polarity_acl_write(uintptr_t base, uint8_t data) {
2247 uint32_t curr = system_hw_read_32(0x80L);
2248 system_hw_write_32(0x80L, (((uint32_t) (data & 0x1)) << 18) | (curr & 0xfffbffff));
2249 }
acamera_isp_input_port_hs_polarity_acl_read(uintptr_t base)2250 static __inline uint8_t acamera_isp_input_port_hs_polarity_acl_read(uintptr_t base) {
2251 return (uint8_t)((system_hw_read_32(0x80L) & 0x40000) >> 18);
2252 }
2253 // ------------------------------------------------------------------------------ //
2254 // Register: hs_polarity hs
2255 // ------------------------------------------------------------------------------ //
2256
2257 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_HS_DEFAULT (0)
2258 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_HS_DATASIZE (1)
2259 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_HS_OFFSET (0x80)
2260 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_HS_MASK (0x80000)
2261 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_HS_HORIZONTAL_COUNTER_IS_RESET_ON_RISING_EDGE_OF_HS (0)
2262 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_HS_HORIZONTAL_COUNTER_IS_RESET_ON_VSYNC_EG_WHEN_HSYNC_IS_NOT_AVAILABLE (1)
2263
2264 // args: data (1-bit)
acamera_isp_input_port_hs_polarity_hs_write(uintptr_t base,uint8_t data)2265 static __inline void acamera_isp_input_port_hs_polarity_hs_write(uintptr_t base, uint8_t data) {
2266 uint32_t curr = system_hw_read_32(0x80L);
2267 system_hw_write_32(0x80L, (((uint32_t) (data & 0x1)) << 19) | (curr & 0xfff7ffff));
2268 }
acamera_isp_input_port_hs_polarity_hs_read(uintptr_t base)2269 static __inline uint8_t acamera_isp_input_port_hs_polarity_hs_read(uintptr_t base) {
2270 return (uint8_t)((system_hw_read_32(0x80L) & 0x80000) >> 19);
2271 }
2272 // ------------------------------------------------------------------------------ //
2273 // Register: hs_polarity vc
2274 // ------------------------------------------------------------------------------ //
2275
2276 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_VC_DEFAULT (1)
2277 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_VC_DATASIZE (1)
2278 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_VC_OFFSET (0x80)
2279 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_VC_MASK (0x100000)
2280 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_VC_VERTICAL_COUNTER_INCREMENTS_ON_RISING_EDGE_OF_HS (0)
2281 #define ACAMERA_ISP_INPUT_PORT_HS_POLARITY_VC_VERTICAL_COUNTER_INCREMENTS_ON_FALLING_EDGE_OF_HS (1)
2282
2283 // args: data (1-bit)
acamera_isp_input_port_hs_polarity_vc_write(uintptr_t base,uint8_t data)2284 static __inline void acamera_isp_input_port_hs_polarity_vc_write(uintptr_t base, uint8_t data) {
2285 uint32_t curr = system_hw_read_32(0x80L);
2286 system_hw_write_32(0x80L, (((uint32_t) (data & 0x1)) << 20) | (curr & 0xffefffff));
2287 }
acamera_isp_input_port_hs_polarity_vc_read(uintptr_t base)2288 static __inline uint8_t acamera_isp_input_port_hs_polarity_vc_read(uintptr_t base) {
2289 return (uint8_t)((system_hw_read_32(0x80L) & 0x100000) >> 20);
2290 }
2291 // ------------------------------------------------------------------------------ //
2292 // Register: hc_r select
2293 // ------------------------------------------------------------------------------ //
2294
2295 #define ACAMERA_ISP_INPUT_PORT_HC_R_SELECT_DEFAULT (0)
2296 #define ACAMERA_ISP_INPUT_PORT_HC_R_SELECT_DATASIZE (1)
2297 #define ACAMERA_ISP_INPUT_PORT_HC_R_SELECT_OFFSET (0x80)
2298 #define ACAMERA_ISP_INPUT_PORT_HC_R_SELECT_MASK (0x800000)
2299 #define ACAMERA_ISP_INPUT_PORT_HC_R_SELECT_VERTICAL_COUNTER_IS_RESET_ON_RISING_EDGE_OF_HS (0)
2300 #define ACAMERA_ISP_INPUT_PORT_HC_R_SELECT_VERTICAL_COUNTER_IS_RESET_ON_RISING_EDGE_OF_VS (1)
2301
2302 // args: data (1-bit)
acamera_isp_input_port_hc_r_select_write(uintptr_t base,uint8_t data)2303 static __inline void acamera_isp_input_port_hc_r_select_write(uintptr_t base, uint8_t data) {
2304 uint32_t curr = system_hw_read_32(0x80L);
2305 system_hw_write_32(0x80L, (((uint32_t) (data & 0x1)) << 23) | (curr & 0xff7fffff));
2306 }
acamera_isp_input_port_hc_r_select_read(uintptr_t base)2307 static __inline uint8_t acamera_isp_input_port_hc_r_select_read(uintptr_t base) {
2308 return (uint8_t)((system_hw_read_32(0x80L) & 0x800000) >> 23);
2309 }
2310 // ------------------------------------------------------------------------------ //
2311 // Register: acl polarity
2312 // ------------------------------------------------------------------------------ //
2313
2314 #define ACAMERA_ISP_INPUT_PORT_ACL_POLARITY_DEFAULT (0)
2315 #define ACAMERA_ISP_INPUT_PORT_ACL_POLARITY_DATASIZE (1)
2316 #define ACAMERA_ISP_INPUT_PORT_ACL_POLARITY_OFFSET (0x80)
2317 #define ACAMERA_ISP_INPUT_PORT_ACL_POLARITY_MASK (0x1000000)
2318 #define ACAMERA_ISP_INPUT_PORT_ACL_POLARITY_DONT_INVERT_ACL_I_FOR_ACL_GATE (0)
2319 #define ACAMERA_ISP_INPUT_PORT_ACL_POLARITY_INVERT_ACL_I_FOR_ACL_GATE (1)
2320
2321 // args: data (1-bit)
acamera_isp_input_port_acl_polarity_write(uintptr_t base,uint8_t data)2322 static __inline void acamera_isp_input_port_acl_polarity_write(uintptr_t base, uint8_t data) {
2323 uint32_t curr = system_hw_read_32(0x80L);
2324 system_hw_write_32(0x80L, (((uint32_t) (data & 0x1)) << 24) | (curr & 0xfeffffff));
2325 }
acamera_isp_input_port_acl_polarity_read(uintptr_t base)2326 static __inline uint8_t acamera_isp_input_port_acl_polarity_read(uintptr_t base) {
2327 return (uint8_t)((system_hw_read_32(0x80L) & 0x1000000) >> 24);
2328 }
2329 // ------------------------------------------------------------------------------ //
2330 // Register: field polarity
2331 // ------------------------------------------------------------------------------ //
2332
2333 #define ACAMERA_ISP_INPUT_PORT_FIELD_POLARITY_DEFAULT (0)
2334 #define ACAMERA_ISP_INPUT_PORT_FIELD_POLARITY_DATASIZE (1)
2335 #define ACAMERA_ISP_INPUT_PORT_FIELD_POLARITY_OFFSET (0x84)
2336 #define ACAMERA_ISP_INPUT_PORT_FIELD_POLARITY_MASK (0x1)
2337 #define ACAMERA_ISP_INPUT_PORT_FIELD_POLARITY_DONT_INVERT_FIELD_I_FOR_FIELD_GATE (0)
2338 #define ACAMERA_ISP_INPUT_PORT_FIELD_POLARITY_INVERT_FIELD_I_FOR_FIELD_GATE (1)
2339
2340 // args: data (1-bit)
acamera_isp_input_port_field_polarity_write(uintptr_t base,uint8_t data)2341 static __inline void acamera_isp_input_port_field_polarity_write(uintptr_t base, uint8_t data) {
2342 uint32_t curr = system_hw_read_32(0x84L);
2343 system_hw_write_32(0x84L, (((uint32_t) (data & 0x1)) << 0) | (curr & 0xfffffffe));
2344 }
acamera_isp_input_port_field_polarity_read(uintptr_t base)2345 static __inline uint8_t acamera_isp_input_port_field_polarity_read(uintptr_t base) {
2346 return (uint8_t)((system_hw_read_32(0x84L) & 0x1) >> 0);
2347 }
2348 // ------------------------------------------------------------------------------ //
2349 // Register: field toggle
2350 // ------------------------------------------------------------------------------ //
2351
2352 #define ACAMERA_ISP_INPUT_PORT_FIELD_TOGGLE_DEFAULT (0)
2353 #define ACAMERA_ISP_INPUT_PORT_FIELD_TOGGLE_DATASIZE (1)
2354 #define ACAMERA_ISP_INPUT_PORT_FIELD_TOGGLE_OFFSET (0x84)
2355 #define ACAMERA_ISP_INPUT_PORT_FIELD_TOGGLE_MASK (0x2)
2356 #define ACAMERA_ISP_INPUT_PORT_FIELD_TOGGLE_FIELD_IS_PULSETYPE (0)
2357 #define ACAMERA_ISP_INPUT_PORT_FIELD_TOGGLE_FIELD_IS_TOGGLETYPE (1)
2358
2359 // args: data (1-bit)
acamera_isp_input_port_field_toggle_write(uintptr_t base,uint8_t data)2360 static __inline void acamera_isp_input_port_field_toggle_write(uintptr_t base, uint8_t data) {
2361 uint32_t curr = system_hw_read_32(0x84L);
2362 system_hw_write_32(0x84L, (((uint32_t) (data & 0x1)) << 1) | (curr & 0xfffffffd));
2363 }
acamera_isp_input_port_field_toggle_read(uintptr_t base)2364 static __inline uint8_t acamera_isp_input_port_field_toggle_read(uintptr_t base) {
2365 return (uint8_t)((system_hw_read_32(0x84L) & 0x2) >> 1);
2366 }
2367 // ------------------------------------------------------------------------------ //
2368 // Register: aclg window0
2369 // ------------------------------------------------------------------------------ //
2370
2371 #define ACAMERA_ISP_INPUT_PORT_ACLG_WINDOW0_DEFAULT (0)
2372 #define ACAMERA_ISP_INPUT_PORT_ACLG_WINDOW0_DATASIZE (1)
2373 #define ACAMERA_ISP_INPUT_PORT_ACLG_WINDOW0_OFFSET (0x84)
2374 #define ACAMERA_ISP_INPUT_PORT_ACLG_WINDOW0_MASK (0x100)
2375 #define ACAMERA_ISP_INPUT_PORT_ACLG_WINDOW0_EXCLUDE_WINDOW0_SIGNAL_IN_ACL_GATE (0)
2376 #define ACAMERA_ISP_INPUT_PORT_ACLG_WINDOW0_INCLUDE_WINDOW0_SIGNAL_IN_ACL_GATE (1)
2377
2378 // args: data (1-bit)
acamera_isp_input_port_aclg_window0_write(uintptr_t base,uint8_t data)2379 static __inline void acamera_isp_input_port_aclg_window0_write(uintptr_t base, uint8_t data) {
2380 uint32_t curr = system_hw_read_32(0x84L);
2381 system_hw_write_32(0x84L, (((uint32_t) (data & 0x1)) << 8) | (curr & 0xfffffeff));
2382 }
acamera_isp_input_port_aclg_window0_read(uintptr_t base)2383 static __inline uint8_t acamera_isp_input_port_aclg_window0_read(uintptr_t base) {
2384 return (uint8_t)((system_hw_read_32(0x84L) & 0x100) >> 8);
2385 }
2386 // ------------------------------------------------------------------------------ //
2387 // Register: aclg hsync
2388 // ------------------------------------------------------------------------------ //
2389
2390 #define ACAMERA_ISP_INPUT_PORT_ACLG_HSYNC_DEFAULT (0)
2391 #define ACAMERA_ISP_INPUT_PORT_ACLG_HSYNC_DATASIZE (1)
2392 #define ACAMERA_ISP_INPUT_PORT_ACLG_HSYNC_OFFSET (0x84)
2393 #define ACAMERA_ISP_INPUT_PORT_ACLG_HSYNC_MASK (0x200)
2394 #define ACAMERA_ISP_INPUT_PORT_ACLG_HSYNC_EXCLUDE_HSYNC_SIGNAL_IN_ACL_GATE (0)
2395 #define ACAMERA_ISP_INPUT_PORT_ACLG_HSYNC_INCLUDE_HSYNC_SIGNAL_IN_ACL_GATE (1)
2396
2397 // args: data (1-bit)
acamera_isp_input_port_aclg_hsync_write(uintptr_t base,uint8_t data)2398 static __inline void acamera_isp_input_port_aclg_hsync_write(uintptr_t base, uint8_t data) {
2399 uint32_t curr = system_hw_read_32(0x84L);
2400 system_hw_write_32(0x84L, (((uint32_t) (data & 0x1)) << 9) | (curr & 0xfffffdff));
2401 }
acamera_isp_input_port_aclg_hsync_read(uintptr_t base)2402 static __inline uint8_t acamera_isp_input_port_aclg_hsync_read(uintptr_t base) {
2403 return (uint8_t)((system_hw_read_32(0x84L) & 0x200) >> 9);
2404 }
2405 // ------------------------------------------------------------------------------ //
2406 // Register: aclg window2
2407 // ------------------------------------------------------------------------------ //
2408
2409 #define ACAMERA_ISP_INPUT_PORT_ACLG_WINDOW2_DEFAULT (0)
2410 #define ACAMERA_ISP_INPUT_PORT_ACLG_WINDOW2_DATASIZE (1)
2411 #define ACAMERA_ISP_INPUT_PORT_ACLG_WINDOW2_OFFSET (0x84)
2412 #define ACAMERA_ISP_INPUT_PORT_ACLG_WINDOW2_MASK (0x400)
2413 #define ACAMERA_ISP_INPUT_PORT_ACLG_WINDOW2_EXCLUDE_WINDOW2_SIGNAL_IN_ACL_GATE (0)
2414 #define ACAMERA_ISP_INPUT_PORT_ACLG_WINDOW2_INCLUDE_WINDOW2_SIGNAL_IN_ACL_GATE (1)
2415
2416 // args: data (1-bit)
acamera_isp_input_port_aclg_window2_write(uintptr_t base,uint8_t data)2417 static __inline void acamera_isp_input_port_aclg_window2_write(uintptr_t base, uint8_t data) {
2418 uint32_t curr = system_hw_read_32(0x84L);
2419 system_hw_write_32(0x84L, (((uint32_t) (data & 0x1)) << 10) | (curr & 0xfffffbff));
2420 }
acamera_isp_input_port_aclg_window2_read(uintptr_t base)2421 static __inline uint8_t acamera_isp_input_port_aclg_window2_read(uintptr_t base) {
2422 return (uint8_t)((system_hw_read_32(0x84L) & 0x400) >> 10);
2423 }
2424 // ------------------------------------------------------------------------------ //
2425 // Register: aclg acl
2426 // ------------------------------------------------------------------------------ //
2427
2428 #define ACAMERA_ISP_INPUT_PORT_ACLG_ACL_DEFAULT (0)
2429 #define ACAMERA_ISP_INPUT_PORT_ACLG_ACL_DATASIZE (1)
2430 #define ACAMERA_ISP_INPUT_PORT_ACLG_ACL_OFFSET (0x84)
2431 #define ACAMERA_ISP_INPUT_PORT_ACLG_ACL_MASK (0x800)
2432 #define ACAMERA_ISP_INPUT_PORT_ACLG_ACL_EXCLUDE_ACL_I_SIGNAL_IN_ACL_GATE (0)
2433 #define ACAMERA_ISP_INPUT_PORT_ACLG_ACL_INCLUDE_ACL_I_SIGNAL_IN_ACL_GATE (1)
2434
2435 // args: data (1-bit)
acamera_isp_input_port_aclg_acl_write(uintptr_t base,uint8_t data)2436 static __inline void acamera_isp_input_port_aclg_acl_write(uintptr_t base, uint8_t data) {
2437 uint32_t curr = system_hw_read_32(0x84L);
2438 system_hw_write_32(0x84L, (((uint32_t) (data & 0x1)) << 11) | (curr & 0xfffff7ff));
2439 }
acamera_isp_input_port_aclg_acl_read(uintptr_t base)2440 static __inline uint8_t acamera_isp_input_port_aclg_acl_read(uintptr_t base) {
2441 return (uint8_t)((system_hw_read_32(0x84L) & 0x800) >> 11);
2442 }
2443 // ------------------------------------------------------------------------------ //
2444 // Register: aclg vsync
2445 // ------------------------------------------------------------------------------ //
2446
2447 #define ACAMERA_ISP_INPUT_PORT_ACLG_VSYNC_DEFAULT (0)
2448 #define ACAMERA_ISP_INPUT_PORT_ACLG_VSYNC_DATASIZE (1)
2449 #define ACAMERA_ISP_INPUT_PORT_ACLG_VSYNC_OFFSET (0x84)
2450 #define ACAMERA_ISP_INPUT_PORT_ACLG_VSYNC_MASK (0x1000)
2451 #define ACAMERA_ISP_INPUT_PORT_ACLG_VSYNC_EXCLUDE_VSYNC_SIGNAL_IN_ACL_GATE (0)
2452 #define ACAMERA_ISP_INPUT_PORT_ACLG_VSYNC_INCLUDE_VSYNC_SIGNAL_IN_ACL_GATE (1)
2453
2454 // args: data (1-bit)
acamera_isp_input_port_aclg_vsync_write(uintptr_t base,uint8_t data)2455 static __inline void acamera_isp_input_port_aclg_vsync_write(uintptr_t base, uint8_t data) {
2456 uint32_t curr = system_hw_read_32(0x84L);
2457 system_hw_write_32(0x84L, (((uint32_t) (data & 0x1)) << 12) | (curr & 0xffffefff));
2458 }
acamera_isp_input_port_aclg_vsync_read(uintptr_t base)2459 static __inline uint8_t acamera_isp_input_port_aclg_vsync_read(uintptr_t base) {
2460 return (uint8_t)((system_hw_read_32(0x84L) & 0x1000) >> 12);
2461 }
2462 // ------------------------------------------------------------------------------ //
2463 // Register: hsg window1
2464 // ------------------------------------------------------------------------------ //
2465
2466 #define ACAMERA_ISP_INPUT_PORT_HSG_WINDOW1_DEFAULT (0)
2467 #define ACAMERA_ISP_INPUT_PORT_HSG_WINDOW1_DATASIZE (1)
2468 #define ACAMERA_ISP_INPUT_PORT_HSG_WINDOW1_OFFSET (0x84)
2469 #define ACAMERA_ISP_INPUT_PORT_HSG_WINDOW1_MASK (0x10000)
2470 #define ACAMERA_ISP_INPUT_PORT_HSG_WINDOW1_EXCLUDE_WINDOW1_SIGNAL_IN_HS_GATE (0)
2471 #define ACAMERA_ISP_INPUT_PORT_HSG_WINDOW1_INCLUDE_WINDOW1_SIGNAL_IN_HS_GATE (1)
2472
2473 // args: data (1-bit)
acamera_isp_input_port_hsg_window1_write(uintptr_t base,uint8_t data)2474 static __inline void acamera_isp_input_port_hsg_window1_write(uintptr_t base, uint8_t data) {
2475 uint32_t curr = system_hw_read_32(0x84L);
2476 system_hw_write_32(0x84L, (((uint32_t) (data & 0x1)) << 16) | (curr & 0xfffeffff));
2477 }
acamera_isp_input_port_hsg_window1_read(uintptr_t base)2478 static __inline uint8_t acamera_isp_input_port_hsg_window1_read(uintptr_t base) {
2479 return (uint8_t)((system_hw_read_32(0x84L) & 0x10000) >> 16);
2480 }
2481 // ------------------------------------------------------------------------------ //
2482 // Register: hsg hsync
2483 // ------------------------------------------------------------------------------ //
2484
2485 #define ACAMERA_ISP_INPUT_PORT_HSG_HSYNC_DEFAULT (0)
2486 #define ACAMERA_ISP_INPUT_PORT_HSG_HSYNC_DATASIZE (1)
2487 #define ACAMERA_ISP_INPUT_PORT_HSG_HSYNC_OFFSET (0x84)
2488 #define ACAMERA_ISP_INPUT_PORT_HSG_HSYNC_MASK (0x20000)
2489 #define ACAMERA_ISP_INPUT_PORT_HSG_HSYNC_EXCLUDE_HSYNC_SIGNAL_IN_HS_GATE (0)
2490 #define ACAMERA_ISP_INPUT_PORT_HSG_HSYNC_INCLUDE_HSYNC_SIGNAL_IN_HS_GATE (1)
2491
2492 // args: data (1-bit)
acamera_isp_input_port_hsg_hsync_write(uintptr_t base,uint8_t data)2493 static __inline void acamera_isp_input_port_hsg_hsync_write(uintptr_t base, uint8_t data) {
2494 uint32_t curr = system_hw_read_32(0x84L);
2495 system_hw_write_32(0x84L, (((uint32_t) (data & 0x1)) << 17) | (curr & 0xfffdffff));
2496 }
acamera_isp_input_port_hsg_hsync_read(uintptr_t base)2497 static __inline uint8_t acamera_isp_input_port_hsg_hsync_read(uintptr_t base) {
2498 return (uint8_t)((system_hw_read_32(0x84L) & 0x20000) >> 17);
2499 }
2500 // ------------------------------------------------------------------------------ //
2501 // Register: hsg vsync
2502 // ------------------------------------------------------------------------------ //
2503
2504 #define ACAMERA_ISP_INPUT_PORT_HSG_VSYNC_DEFAULT (0)
2505 #define ACAMERA_ISP_INPUT_PORT_HSG_VSYNC_DATASIZE (1)
2506 #define ACAMERA_ISP_INPUT_PORT_HSG_VSYNC_OFFSET (0x84)
2507 #define ACAMERA_ISP_INPUT_PORT_HSG_VSYNC_MASK (0x40000)
2508 #define ACAMERA_ISP_INPUT_PORT_HSG_VSYNC_EXCLUDE_VSYNC_SIGNAL_IN_HS_GATE (0)
2509 #define ACAMERA_ISP_INPUT_PORT_HSG_VSYNC_INCLUDE_VSYNC_SIGNAL_IN_HS_GATE (1)
2510
2511 // args: data (1-bit)
acamera_isp_input_port_hsg_vsync_write(uintptr_t base,uint8_t data)2512 static __inline void acamera_isp_input_port_hsg_vsync_write(uintptr_t base, uint8_t data) {
2513 uint32_t curr = system_hw_read_32(0x84L);
2514 system_hw_write_32(0x84L, (((uint32_t) (data & 0x1)) << 18) | (curr & 0xfffbffff));
2515 }
acamera_isp_input_port_hsg_vsync_read(uintptr_t base)2516 static __inline uint8_t acamera_isp_input_port_hsg_vsync_read(uintptr_t base) {
2517 return (uint8_t)((system_hw_read_32(0x84L) & 0x40000) >> 18);
2518 }
2519 // ------------------------------------------------------------------------------ //
2520 // Register: hsg window2
2521 // ------------------------------------------------------------------------------ //
2522
2523 #define ACAMERA_ISP_INPUT_PORT_HSG_WINDOW2_DEFAULT (0)
2524 #define ACAMERA_ISP_INPUT_PORT_HSG_WINDOW2_DATASIZE (1)
2525 #define ACAMERA_ISP_INPUT_PORT_HSG_WINDOW2_OFFSET (0x84)
2526 #define ACAMERA_ISP_INPUT_PORT_HSG_WINDOW2_MASK (0x80000)
2527 #define ACAMERA_ISP_INPUT_PORT_HSG_WINDOW2_EXCLUDE_WINDOW2_SIGNAL_IN_HS_GATE (0)
2528 #define ACAMERA_ISP_INPUT_PORT_HSG_WINDOW2_INCLUDE_WINDOW2_SIGNAL_IN_HS_GATE_MASK_OUT_SPURIOUS_HS_DURING_BLANK (1)
2529
2530 // args: data (1-bit)
acamera_isp_input_port_hsg_window2_write(uintptr_t base,uint8_t data)2531 static __inline void acamera_isp_input_port_hsg_window2_write(uintptr_t base, uint8_t data) {
2532 uint32_t curr = system_hw_read_32(0x84L);
2533 system_hw_write_32(0x84L, (((uint32_t) (data & 0x1)) << 19) | (curr & 0xfff7ffff));
2534 }
acamera_isp_input_port_hsg_window2_read(uintptr_t base)2535 static __inline uint8_t acamera_isp_input_port_hsg_window2_read(uintptr_t base) {
2536 return (uint8_t)((system_hw_read_32(0x84L) & 0x80000) >> 19);
2537 }
2538 // ------------------------------------------------------------------------------ //
2539 // Register: fieldg vsync
2540 // ------------------------------------------------------------------------------ //
2541
2542 #define ACAMERA_ISP_INPUT_PORT_FIELDG_VSYNC_DEFAULT (0)
2543 #define ACAMERA_ISP_INPUT_PORT_FIELDG_VSYNC_DATASIZE (1)
2544 #define ACAMERA_ISP_INPUT_PORT_FIELDG_VSYNC_OFFSET (0x84)
2545 #define ACAMERA_ISP_INPUT_PORT_FIELDG_VSYNC_MASK (0x1000000)
2546 #define ACAMERA_ISP_INPUT_PORT_FIELDG_VSYNC_EXCLUDE_VSYNC_SIGNAL_IN_FIELD_GATE (0)
2547 #define ACAMERA_ISP_INPUT_PORT_FIELDG_VSYNC_INCLUDE_VSYNC_SIGNAL_IN_FIELD_GATE (1)
2548
2549 // args: data (1-bit)
acamera_isp_input_port_fieldg_vsync_write(uintptr_t base,uint8_t data)2550 static __inline void acamera_isp_input_port_fieldg_vsync_write(uintptr_t base, uint8_t data) {
2551 uint32_t curr = system_hw_read_32(0x84L);
2552 system_hw_write_32(0x84L, (((uint32_t) (data & 0x1)) << 24) | (curr & 0xfeffffff));
2553 }
acamera_isp_input_port_fieldg_vsync_read(uintptr_t base)2554 static __inline uint8_t acamera_isp_input_port_fieldg_vsync_read(uintptr_t base) {
2555 return (uint8_t)((system_hw_read_32(0x84L) & 0x1000000) >> 24);
2556 }
2557 // ------------------------------------------------------------------------------ //
2558 // Register: fieldg window2
2559 // ------------------------------------------------------------------------------ //
2560
2561 #define ACAMERA_ISP_INPUT_PORT_FIELDG_WINDOW2_DEFAULT (0)
2562 #define ACAMERA_ISP_INPUT_PORT_FIELDG_WINDOW2_DATASIZE (1)
2563 #define ACAMERA_ISP_INPUT_PORT_FIELDG_WINDOW2_OFFSET (0x84)
2564 #define ACAMERA_ISP_INPUT_PORT_FIELDG_WINDOW2_MASK (0x2000000)
2565 #define ACAMERA_ISP_INPUT_PORT_FIELDG_WINDOW2_EXCLUDE_WINDOW2_SIGNAL_IN_FIELD_GATE (0)
2566 #define ACAMERA_ISP_INPUT_PORT_FIELDG_WINDOW2_INCLUDE_WINDOW2_SIGNAL_IN_FIELD_GATE (1)
2567
2568 // args: data (1-bit)
acamera_isp_input_port_fieldg_window2_write(uintptr_t base,uint8_t data)2569 static __inline void acamera_isp_input_port_fieldg_window2_write(uintptr_t base, uint8_t data) {
2570 uint32_t curr = system_hw_read_32(0x84L);
2571 system_hw_write_32(0x84L, (((uint32_t) (data & 0x1)) << 25) | (curr & 0xfdffffff));
2572 }
acamera_isp_input_port_fieldg_window2_read(uintptr_t base)2573 static __inline uint8_t acamera_isp_input_port_fieldg_window2_read(uintptr_t base) {
2574 return (uint8_t)((system_hw_read_32(0x84L) & 0x2000000) >> 25);
2575 }
2576 // ------------------------------------------------------------------------------ //
2577 // Register: fieldg field
2578 // ------------------------------------------------------------------------------ //
2579
2580 #define ACAMERA_ISP_INPUT_PORT_FIELDG_FIELD_DEFAULT (0)
2581 #define ACAMERA_ISP_INPUT_PORT_FIELDG_FIELD_DATASIZE (1)
2582 #define ACAMERA_ISP_INPUT_PORT_FIELDG_FIELD_OFFSET (0x84)
2583 #define ACAMERA_ISP_INPUT_PORT_FIELDG_FIELD_MASK (0x4000000)
2584 #define ACAMERA_ISP_INPUT_PORT_FIELDG_FIELD_EXCLUDE_FIELD_I_SIGNAL_IN_FIELD_GATE (0)
2585 #define ACAMERA_ISP_INPUT_PORT_FIELDG_FIELD_INCLUDE_FIELD_I_SIGNAL_IN_FIELD_GATE (1)
2586
2587 // args: data (1-bit)
acamera_isp_input_port_fieldg_field_write(uintptr_t base,uint8_t data)2588 static __inline void acamera_isp_input_port_fieldg_field_write(uintptr_t base, uint8_t data) {
2589 uint32_t curr = system_hw_read_32(0x84L);
2590 system_hw_write_32(0x84L, (((uint32_t) (data & 0x1)) << 26) | (curr & 0xfbffffff));
2591 }
acamera_isp_input_port_fieldg_field_read(uintptr_t base)2592 static __inline uint8_t acamera_isp_input_port_fieldg_field_read(uintptr_t base) {
2593 return (uint8_t)((system_hw_read_32(0x84L) & 0x4000000) >> 26);
2594 }
2595 // ------------------------------------------------------------------------------ //
2596 // Register: field mode
2597 // ------------------------------------------------------------------------------ //
2598
2599 #define ACAMERA_ISP_INPUT_PORT_FIELD_MODE_DEFAULT (0)
2600 #define ACAMERA_ISP_INPUT_PORT_FIELD_MODE_DATASIZE (1)
2601 #define ACAMERA_ISP_INPUT_PORT_FIELD_MODE_OFFSET (0x84)
2602 #define ACAMERA_ISP_INPUT_PORT_FIELD_MODE_MASK (0x8000000)
2603 #define ACAMERA_ISP_INPUT_PORT_FIELD_MODE_PULSE_FIELD (0)
2604 #define ACAMERA_ISP_INPUT_PORT_FIELD_MODE_TOGGLE_FIELD (1)
2605
2606 // args: data (1-bit)
acamera_isp_input_port_field_mode_write(uintptr_t base,uint8_t data)2607 static __inline void acamera_isp_input_port_field_mode_write(uintptr_t base, uint8_t data) {
2608 uint32_t curr = system_hw_read_32(0x84L);
2609 system_hw_write_32(0x84L, (((uint32_t) (data & 0x1)) << 27) | (curr & 0xf7ffffff));
2610 }
acamera_isp_input_port_field_mode_read(uintptr_t base)2611 static __inline uint8_t acamera_isp_input_port_field_mode_read(uintptr_t base) {
2612 return (uint8_t)((system_hw_read_32(0x84L) & 0x8000000) >> 27);
2613 }
2614 // ------------------------------------------------------------------------------ //
2615 // Register: hc limit
2616 // ------------------------------------------------------------------------------ //
2617
2618 // ------------------------------------------------------------------------------ //
2619 // horizontal counter limit value (counts: 0,1,...hc_limit-1,hc_limit,0,1,...)
2620 // ------------------------------------------------------------------------------ //
2621
2622 #define ACAMERA_ISP_INPUT_PORT_HC_LIMIT_DEFAULT (0xFFFF)
2623 #define ACAMERA_ISP_INPUT_PORT_HC_LIMIT_DATASIZE (16)
2624 #define ACAMERA_ISP_INPUT_PORT_HC_LIMIT_OFFSET (0x88)
2625 #define ACAMERA_ISP_INPUT_PORT_HC_LIMIT_MASK (0xffff)
2626
2627 // args: data (16-bit)
acamera_isp_input_port_hc_limit_write(uintptr_t base,uint16_t data)2628 static __inline void acamera_isp_input_port_hc_limit_write(uintptr_t base, uint16_t data) {
2629 uint32_t curr = system_hw_read_32(0x88L);
2630 system_hw_write_32(0x88L, (((uint32_t) (data & 0xffff)) << 0) | (curr & 0xffff0000));
2631 }
acamera_isp_input_port_hc_limit_read(uintptr_t base)2632 static __inline uint16_t acamera_isp_input_port_hc_limit_read(uintptr_t base) {
2633 return (uint16_t)((system_hw_read_32(0x88L) & 0xffff) >> 0);
2634 }
2635 // ------------------------------------------------------------------------------ //
2636 // Register: hc start0
2637 // ------------------------------------------------------------------------------ //
2638
2639 // ------------------------------------------------------------------------------ //
2640 // window0 start for ACL gate. See ISP guide for further details.
2641 // ------------------------------------------------------------------------------ //
2642
2643 #define ACAMERA_ISP_INPUT_PORT_HC_START0_DEFAULT (0)
2644 #define ACAMERA_ISP_INPUT_PORT_HC_START0_DATASIZE (16)
2645 #define ACAMERA_ISP_INPUT_PORT_HC_START0_OFFSET (0x88)
2646 #define ACAMERA_ISP_INPUT_PORT_HC_START0_MASK (0xffff0000)
2647
2648 // args: data (16-bit)
acamera_isp_input_port_hc_start0_write(uintptr_t base,uint16_t data)2649 static __inline void acamera_isp_input_port_hc_start0_write(uintptr_t base, uint16_t data) {
2650 uint32_t curr = system_hw_read_32(0x88L);
2651 system_hw_write_32(0x88L, (((uint32_t) (data & 0xffff)) << 16) | (curr & 0xffff));
2652 }
acamera_isp_input_port_hc_start0_read(uintptr_t base)2653 static __inline uint16_t acamera_isp_input_port_hc_start0_read(uintptr_t base) {
2654 return (uint16_t)((system_hw_read_32(0x88L) & 0xffff0000) >> 16);
2655 }
2656 // ------------------------------------------------------------------------------ //
2657 // Register: hc size0
2658 // ------------------------------------------------------------------------------ //
2659
2660 // ------------------------------------------------------------------------------ //
2661 // window0 size for ACL gate. See ISP guide for further details.
2662 // ------------------------------------------------------------------------------ //
2663
2664 #define ACAMERA_ISP_INPUT_PORT_HC_SIZE0_DEFAULT (0)
2665 #define ACAMERA_ISP_INPUT_PORT_HC_SIZE0_DATASIZE (16)
2666 #define ACAMERA_ISP_INPUT_PORT_HC_SIZE0_OFFSET (0x8c)
2667 #define ACAMERA_ISP_INPUT_PORT_HC_SIZE0_MASK (0xffff)
2668
2669 // args: data (16-bit)
acamera_isp_input_port_hc_size0_write(uintptr_t base,uint16_t data)2670 static __inline void acamera_isp_input_port_hc_size0_write(uintptr_t base, uint16_t data) {
2671 uint32_t curr = system_hw_read_32(0x8cL);
2672 system_hw_write_32(0x8cL, (((uint32_t) (data & 0xffff)) << 0) | (curr & 0xffff0000));
2673 }
acamera_isp_input_port_hc_size0_read(uintptr_t base)2674 static __inline uint16_t acamera_isp_input_port_hc_size0_read(uintptr_t base) {
2675 return (uint16_t)((system_hw_read_32(0x8cL) & 0xffff) >> 0);
2676 }
2677 // ------------------------------------------------------------------------------ //
2678 // Register: hc start1
2679 // ------------------------------------------------------------------------------ //
2680
2681 // ------------------------------------------------------------------------------ //
2682 // window1 start for HS gate. See ISP guide for further details.
2683 // ------------------------------------------------------------------------------ //
2684
2685 #define ACAMERA_ISP_INPUT_PORT_HC_START1_DEFAULT (0)
2686 #define ACAMERA_ISP_INPUT_PORT_HC_START1_DATASIZE (16)
2687 #define ACAMERA_ISP_INPUT_PORT_HC_START1_OFFSET (0x8c)
2688 #define ACAMERA_ISP_INPUT_PORT_HC_START1_MASK (0xffff0000)
2689
2690 // args: data (16-bit)
acamera_isp_input_port_hc_start1_write(uintptr_t base,uint16_t data)2691 static __inline void acamera_isp_input_port_hc_start1_write(uintptr_t base, uint16_t data) {
2692 uint32_t curr = system_hw_read_32(0x8cL);
2693 system_hw_write_32(0x8cL, (((uint32_t) (data & 0xffff)) << 16) | (curr & 0xffff));
2694 }
acamera_isp_input_port_hc_start1_read(uintptr_t base)2695 static __inline uint16_t acamera_isp_input_port_hc_start1_read(uintptr_t base) {
2696 return (uint16_t)((system_hw_read_32(0x8cL) & 0xffff0000) >> 16);
2697 }
2698 // ------------------------------------------------------------------------------ //
2699 // Register: hc size1
2700 // ------------------------------------------------------------------------------ //
2701
2702 // ------------------------------------------------------------------------------ //
2703 // window1 size for HS gate. See ISP guide for further details.
2704 // ------------------------------------------------------------------------------ //
2705
2706 #define ACAMERA_ISP_INPUT_PORT_HC_SIZE1_DEFAULT (0)
2707 #define ACAMERA_ISP_INPUT_PORT_HC_SIZE1_DATASIZE (16)
2708 #define ACAMERA_ISP_INPUT_PORT_HC_SIZE1_OFFSET (0x90)
2709 #define ACAMERA_ISP_INPUT_PORT_HC_SIZE1_MASK (0xffff)
2710
2711 // args: data (16-bit)
acamera_isp_input_port_hc_size1_write(uintptr_t base,uint16_t data)2712 static __inline void acamera_isp_input_port_hc_size1_write(uintptr_t base, uint16_t data) {
2713 uint32_t curr = system_hw_read_32(0x90L);
2714 system_hw_write_32(0x90L, (((uint32_t) (data & 0xffff)) << 0) | (curr & 0xffff0000));
2715 }
acamera_isp_input_port_hc_size1_read(uintptr_t base)2716 static __inline uint16_t acamera_isp_input_port_hc_size1_read(uintptr_t base) {
2717 return (uint16_t)((system_hw_read_32(0x90L) & 0xffff) >> 0);
2718 }
2719 // ------------------------------------------------------------------------------ //
2720 // Register: vc limit
2721 // ------------------------------------------------------------------------------ //
2722
2723 // ------------------------------------------------------------------------------ //
2724 // vertical counter limit value (counts: 0,1,...vc_limit-1,vc_limit,0,1,...)
2725 // ------------------------------------------------------------------------------ //
2726
2727 #define ACAMERA_ISP_INPUT_PORT_VC_LIMIT_DEFAULT (0xFFFF)
2728 #define ACAMERA_ISP_INPUT_PORT_VC_LIMIT_DATASIZE (16)
2729 #define ACAMERA_ISP_INPUT_PORT_VC_LIMIT_OFFSET (0x90)
2730 #define ACAMERA_ISP_INPUT_PORT_VC_LIMIT_MASK (0xffff0000)
2731
2732 // args: data (16-bit)
acamera_isp_input_port_vc_limit_write(uintptr_t base,uint16_t data)2733 static __inline void acamera_isp_input_port_vc_limit_write(uintptr_t base, uint16_t data) {
2734 uint32_t curr = system_hw_read_32(0x90L);
2735 system_hw_write_32(0x90L, (((uint32_t) (data & 0xffff)) << 16) | (curr & 0xffff));
2736 }
acamera_isp_input_port_vc_limit_read(uintptr_t base)2737 static __inline uint16_t acamera_isp_input_port_vc_limit_read(uintptr_t base) {
2738 return (uint16_t)((system_hw_read_32(0x90L) & 0xffff0000) >> 16);
2739 }
2740 // ------------------------------------------------------------------------------ //
2741 // Register: vc start
2742 // ------------------------------------------------------------------------------ //
2743
2744 // ------------------------------------------------------------------------------ //
2745 // window2 start for ACL gate. See ISP guide for further details.
2746 // ------------------------------------------------------------------------------ //
2747
2748 #define ACAMERA_ISP_INPUT_PORT_VC_START_DEFAULT (0)
2749 #define ACAMERA_ISP_INPUT_PORT_VC_START_DATASIZE (16)
2750 #define ACAMERA_ISP_INPUT_PORT_VC_START_OFFSET (0x94)
2751 #define ACAMERA_ISP_INPUT_PORT_VC_START_MASK (0xffff)
2752
2753 // args: data (16-bit)
acamera_isp_input_port_vc_start_write(uintptr_t base,uint16_t data)2754 static __inline void acamera_isp_input_port_vc_start_write(uintptr_t base, uint16_t data) {
2755 uint32_t curr = system_hw_read_32(0x94L);
2756 system_hw_write_32(0x94L, (((uint32_t) (data & 0xffff)) << 0) | (curr & 0xffff0000));
2757 }
acamera_isp_input_port_vc_start_read(uintptr_t base)2758 static __inline uint16_t acamera_isp_input_port_vc_start_read(uintptr_t base) {
2759 return (uint16_t)((system_hw_read_32(0x94L) & 0xffff) >> 0);
2760 }
2761 // ------------------------------------------------------------------------------ //
2762 // Register: vc size
2763 // ------------------------------------------------------------------------------ //
2764
2765 // ------------------------------------------------------------------------------ //
2766 // window2 size for ACL gate. See ISP guide for further details.
2767 // ------------------------------------------------------------------------------ //
2768
2769 #define ACAMERA_ISP_INPUT_PORT_VC_SIZE_DEFAULT (0)
2770 #define ACAMERA_ISP_INPUT_PORT_VC_SIZE_DATASIZE (16)
2771 #define ACAMERA_ISP_INPUT_PORT_VC_SIZE_OFFSET (0x94)
2772 #define ACAMERA_ISP_INPUT_PORT_VC_SIZE_MASK (0xffff0000)
2773
2774 // args: data (16-bit)
acamera_isp_input_port_vc_size_write(uintptr_t base,uint16_t data)2775 static __inline void acamera_isp_input_port_vc_size_write(uintptr_t base, uint16_t data) {
2776 uint32_t curr = system_hw_read_32(0x94L);
2777 system_hw_write_32(0x94L, (((uint32_t) (data & 0xffff)) << 16) | (curr & 0xffff));
2778 }
acamera_isp_input_port_vc_size_read(uintptr_t base)2779 static __inline uint16_t acamera_isp_input_port_vc_size_read(uintptr_t base) {
2780 return (uint16_t)((system_hw_read_32(0x94L) & 0xffff0000) >> 16);
2781 }
2782 // ------------------------------------------------------------------------------ //
2783 // Register: frame width
2784 // ------------------------------------------------------------------------------ //
2785
2786 // ------------------------------------------------------------------------------ //
2787 // detected frame width. Read only value.
2788 // ------------------------------------------------------------------------------ //
2789
2790 #define ACAMERA_ISP_INPUT_PORT_FRAME_WIDTH_DEFAULT (0)
2791 #define ACAMERA_ISP_INPUT_PORT_FRAME_WIDTH_DATASIZE (16)
2792 #define ACAMERA_ISP_INPUT_PORT_FRAME_WIDTH_OFFSET (0x98)
2793 #define ACAMERA_ISP_INPUT_PORT_FRAME_WIDTH_MASK (0xffff)
2794
2795 // args: data (16-bit)
acamera_isp_input_port_frame_width_read(uintptr_t base)2796 static __inline uint16_t acamera_isp_input_port_frame_width_read(uintptr_t base) {
2797 return (uint16_t)((system_hw_read_32(0x98L) & 0xffff) >> 0);
2798 }
2799 // ------------------------------------------------------------------------------ //
2800 // Register: frame height
2801 // ------------------------------------------------------------------------------ //
2802
2803 // ------------------------------------------------------------------------------ //
2804 // detected frame height. Read only value.
2805 // ------------------------------------------------------------------------------ //
2806
2807 #define ACAMERA_ISP_INPUT_PORT_FRAME_HEIGHT_DEFAULT (0)
2808 #define ACAMERA_ISP_INPUT_PORT_FRAME_HEIGHT_DATASIZE (16)
2809 #define ACAMERA_ISP_INPUT_PORT_FRAME_HEIGHT_OFFSET (0x98)
2810 #define ACAMERA_ISP_INPUT_PORT_FRAME_HEIGHT_MASK (0xffff0000)
2811
2812 // args: data (16-bit)
acamera_isp_input_port_frame_height_read(uintptr_t base)2813 static __inline uint16_t acamera_isp_input_port_frame_height_read(uintptr_t base) {
2814 return (uint16_t)((system_hw_read_32(0x98L) & 0xffff0000) >> 16);
2815 }
2816 // ------------------------------------------------------------------------------ //
2817 // Register: freeze config
2818 // ------------------------------------------------------------------------------ //
2819
2820 // ------------------------------------------------------------------------------ //
2821 // Used to freeze input port configuration. Used when multiple register writes are required to change input port configuration.
2822 // ------------------------------------------------------------------------------ //
2823
2824 #define ACAMERA_ISP_INPUT_PORT_FREEZE_CONFIG_DEFAULT (0)
2825 #define ACAMERA_ISP_INPUT_PORT_FREEZE_CONFIG_DATASIZE (1)
2826 #define ACAMERA_ISP_INPUT_PORT_FREEZE_CONFIG_OFFSET (0x9c)
2827 #define ACAMERA_ISP_INPUT_PORT_FREEZE_CONFIG_MASK (0x80)
2828 #define ACAMERA_ISP_INPUT_PORT_FREEZE_CONFIG_NORMAL_OPERATION (0)
2829 #define ACAMERA_ISP_INPUT_PORT_FREEZE_CONFIG_HOLD_PREVIOUS_INPUT_PORT_CONFIG_STATE (1)
2830
2831 // args: data (1-bit)
acamera_isp_input_port_freeze_config_write(uintptr_t base,uint8_t data)2832 static __inline void acamera_isp_input_port_freeze_config_write(uintptr_t base, uint8_t data) {
2833 uint32_t curr = system_hw_read_32(0x9cL);
2834 system_hw_write_32(0x9cL, (((uint32_t) (data & 0x1)) << 7) | (curr & 0xffffff7f));
2835 }
acamera_isp_input_port_freeze_config_read(uintptr_t base)2836 static __inline uint8_t acamera_isp_input_port_freeze_config_read(uintptr_t base) {
2837 return (uint8_t)((system_hw_read_32(0x9cL) & 0x80) >> 7);
2838 }
2839 // ------------------------------------------------------------------------------ //
2840 // Register: mode request
2841 // ------------------------------------------------------------------------------ //
2842
2843 // ------------------------------------------------------------------------------ //
2844 // Used to stop and start input port. See ISP guide for further details.
2845 // Only modes-0 and 1 are used. all other values are reserved
2846 //
2847 // ------------------------------------------------------------------------------ //
2848
2849 #define ACAMERA_ISP_INPUT_PORT_MODE_REQUEST_DEFAULT (0)
2850 #define ACAMERA_ISP_INPUT_PORT_MODE_REQUEST_DATASIZE (3)
2851 #define ACAMERA_ISP_INPUT_PORT_MODE_REQUEST_OFFSET (0x9c)
2852 #define ACAMERA_ISP_INPUT_PORT_MODE_REQUEST_MASK (0x7)
2853 #define ACAMERA_ISP_INPUT_PORT_MODE_REQUEST_SAFE_STOP (0)
2854 #define ACAMERA_ISP_INPUT_PORT_MODE_REQUEST_SAFE_START (1)
2855
2856 // args: data (3-bit)
acamera_isp_input_port_mode_request_write(uintptr_t base,uint8_t data)2857 static __inline void acamera_isp_input_port_mode_request_write(uintptr_t base, uint8_t data) {
2858 uint32_t curr = system_hw_read_32(0x9cL);
2859 system_hw_write_32(0x9cL, (((uint32_t) (data & 0x7)) << 0) | (curr & 0xfffffff8));
2860 }
acamera_isp_input_port_mode_request_read(uintptr_t base)2861 static __inline uint8_t acamera_isp_input_port_mode_request_read(uintptr_t base) {
2862 return (uint8_t)((system_hw_read_32(0x9cL) & 0x7) >> 0);
2863 }
2864 // ------------------------------------------------------------------------------ //
2865 // Register: mode status
2866 // ------------------------------------------------------------------------------ //
2867
2868 // ------------------------------------------------------------------------------ //
2869 //
2870 // Used to monitor input port status:
2871 // bit 0: 1=running, 0=stopped, bits 1,2-reserved
2872 //
2873 // ------------------------------------------------------------------------------ //
2874
2875 #define ACAMERA_ISP_INPUT_PORT_MODE_STATUS_DEFAULT (0)
2876 #define ACAMERA_ISP_INPUT_PORT_MODE_STATUS_DATASIZE (3)
2877 #define ACAMERA_ISP_INPUT_PORT_MODE_STATUS_OFFSET (0xa0)
2878 #define ACAMERA_ISP_INPUT_PORT_MODE_STATUS_MASK (0x7)
2879
2880 // args: data (3-bit)
acamera_isp_input_port_mode_status_read(uintptr_t base)2881 static __inline uint8_t acamera_isp_input_port_mode_status_read(uintptr_t base) {
2882 return (uint8_t)((system_hw_read_32(0xa0L) & 0x7) >> 0);
2883 }
2884 // ------------------------------------------------------------------------------ //
2885 // Group: input port frame stats
2886 // ------------------------------------------------------------------------------ //
2887
2888 // ------------------------------------------------------------------------------ //
2889 // Register: stats reset
2890 // ------------------------------------------------------------------------------ //
2891
2892 // ------------------------------------------------------------------------------ //
2893 // Resets the frame statistics registers and starts the sampling period. Note all the frame statistics saturate at 2^31
2894 // ------------------------------------------------------------------------------ //
2895
2896 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_STATS_RESET_DEFAULT (0)
2897 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_STATS_RESET_DATASIZE (1)
2898 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_STATS_RESET_OFFSET (0xa4)
2899 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_STATS_RESET_MASK (0x1)
2900
2901 // args: data (1-bit)
acamera_isp_input_port_frame_stats_stats_reset_write(uintptr_t base,uint8_t data)2902 static __inline void acamera_isp_input_port_frame_stats_stats_reset_write(uintptr_t base, uint8_t data) {
2903 uint32_t curr = system_hw_read_32(0xa4L);
2904 system_hw_write_32(0xa4L, (((uint32_t) (data & 0x1)) << 0) | (curr & 0xfffffffe));
2905 }
acamera_isp_input_port_frame_stats_stats_reset_read(uintptr_t base)2906 static __inline uint8_t acamera_isp_input_port_frame_stats_stats_reset_read(uintptr_t base) {
2907 return (uint8_t)((system_hw_read_32(0xa4L) & 0x1) >> 0);
2908 }
2909 // ------------------------------------------------------------------------------ //
2910 // Register: stats hold
2911 // ------------------------------------------------------------------------------ //
2912
2913 // ------------------------------------------------------------------------------ //
2914 // Synchronously disables the update of the statistics registers. This should be used prior to reading out the register values so as to ensure consistent values
2915 // ------------------------------------------------------------------------------ //
2916
2917 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_STATS_HOLD_DEFAULT (0)
2918 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_STATS_HOLD_DATASIZE (1)
2919 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_STATS_HOLD_OFFSET (0xa8)
2920 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_STATS_HOLD_MASK (0x1)
2921
2922 // args: data (1-bit)
acamera_isp_input_port_frame_stats_stats_hold_write(uintptr_t base,uint8_t data)2923 static __inline void acamera_isp_input_port_frame_stats_stats_hold_write(uintptr_t base, uint8_t data) {
2924 uint32_t curr = system_hw_read_32(0xa8L);
2925 system_hw_write_32(0xa8L, (((uint32_t) (data & 0x1)) << 0) | (curr & 0xfffffffe));
2926 }
acamera_isp_input_port_frame_stats_stats_hold_read(uintptr_t base)2927 static __inline uint8_t acamera_isp_input_port_frame_stats_stats_hold_read(uintptr_t base) {
2928 return (uint8_t)((system_hw_read_32(0xa8L) & 0x1) >> 0);
2929 }
2930 // ------------------------------------------------------------------------------ //
2931 // Register: active width min
2932 // ------------------------------------------------------------------------------ //
2933
2934 // ------------------------------------------------------------------------------ //
2935 // The minimum number of active pixels observed in a line within the sampling period
2936 // ------------------------------------------------------------------------------ //
2937
2938 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_WIDTH_MIN_DEFAULT (0)
2939 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_WIDTH_MIN_DATASIZE (32)
2940 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_WIDTH_MIN_OFFSET (0xb4)
2941 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_WIDTH_MIN_MASK (0xffffffff)
2942
2943 // args: data (32-bit)
acamera_isp_input_port_frame_stats_active_width_min_read(uintptr_t base)2944 static __inline uint32_t acamera_isp_input_port_frame_stats_active_width_min_read(uintptr_t base) {
2945 return system_hw_read_32(0xb4L);
2946 }
2947 // ------------------------------------------------------------------------------ //
2948 // Register: active width max
2949 // ------------------------------------------------------------------------------ //
2950
2951 // ------------------------------------------------------------------------------ //
2952 // The maximum number of active pixels observed in a line within the sampling period
2953 // ------------------------------------------------------------------------------ //
2954
2955 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_WIDTH_MAX_DEFAULT (0)
2956 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_WIDTH_MAX_DATASIZE (32)
2957 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_WIDTH_MAX_OFFSET (0xb8)
2958 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_WIDTH_MAX_MASK (0xffffffff)
2959
2960 // args: data (32-bit)
acamera_isp_input_port_frame_stats_active_width_max_read(uintptr_t base)2961 static __inline uint32_t acamera_isp_input_port_frame_stats_active_width_max_read(uintptr_t base) {
2962 return system_hw_read_32(0xb8L);
2963 }
2964 // ------------------------------------------------------------------------------ //
2965 // Register: active width sum
2966 // ------------------------------------------------------------------------------ //
2967
2968 // ------------------------------------------------------------------------------ //
2969 // The total number of the active pixels values observed in a line within the sampling period
2970 // ------------------------------------------------------------------------------ //
2971
2972 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_WIDTH_SUM_DEFAULT (0)
2973 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_WIDTH_SUM_DATASIZE (32)
2974 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_WIDTH_SUM_OFFSET (0xbc)
2975 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_WIDTH_SUM_MASK (0xffffffff)
2976
2977 // args: data (32-bit)
acamera_isp_input_port_frame_stats_active_width_sum_read(uintptr_t base)2978 static __inline uint32_t acamera_isp_input_port_frame_stats_active_width_sum_read(uintptr_t base) {
2979 return system_hw_read_32(0xbcL);
2980 }
2981 // ------------------------------------------------------------------------------ //
2982 // Register: active width num
2983 // ------------------------------------------------------------------------------ //
2984
2985 // ------------------------------------------------------------------------------ //
2986 // The number of lines observed within the sampling period
2987 // ------------------------------------------------------------------------------ //
2988
2989 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_WIDTH_NUM_DEFAULT (0)
2990 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_WIDTH_NUM_DATASIZE (32)
2991 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_WIDTH_NUM_OFFSET (0xc0)
2992 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_WIDTH_NUM_MASK (0xffffffff)
2993
2994 // args: data (32-bit)
acamera_isp_input_port_frame_stats_active_width_num_read(uintptr_t base)2995 static __inline uint32_t acamera_isp_input_port_frame_stats_active_width_num_read(uintptr_t base) {
2996 return system_hw_read_32(0xc0L);
2997 }
2998 // ------------------------------------------------------------------------------ //
2999 // Register: active height min
3000 // ------------------------------------------------------------------------------ //
3001
3002 // ------------------------------------------------------------------------------ //
3003 // The minimum number of active lines in the frames observed within the sampling period
3004 // ------------------------------------------------------------------------------ //
3005
3006 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_HEIGHT_MIN_DEFAULT (0)
3007 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_HEIGHT_MIN_DATASIZE (32)
3008 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_HEIGHT_MIN_OFFSET (0xc4)
3009 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_HEIGHT_MIN_MASK (0xffffffff)
3010
3011 // args: data (32-bit)
acamera_isp_input_port_frame_stats_active_height_min_read(uintptr_t base)3012 static __inline uint32_t acamera_isp_input_port_frame_stats_active_height_min_read(uintptr_t base) {
3013 return system_hw_read_32(0xc4L);
3014 }
3015 // ------------------------------------------------------------------------------ //
3016 // Register: active height max
3017 // ------------------------------------------------------------------------------ //
3018
3019 // ------------------------------------------------------------------------------ //
3020 // The maximum number of active lines in the frames observed within the sampling period
3021 // ------------------------------------------------------------------------------ //
3022
3023 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_HEIGHT_MAX_DEFAULT (0)
3024 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_HEIGHT_MAX_DATASIZE (32)
3025 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_HEIGHT_MAX_OFFSET (0xc8)
3026 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_HEIGHT_MAX_MASK (0xffffffff)
3027
3028 // args: data (32-bit)
acamera_isp_input_port_frame_stats_active_height_max_read(uintptr_t base)3029 static __inline uint32_t acamera_isp_input_port_frame_stats_active_height_max_read(uintptr_t base) {
3030 return system_hw_read_32(0xc8L);
3031 }
3032 // ------------------------------------------------------------------------------ //
3033 // Register: active height sum
3034 // ------------------------------------------------------------------------------ //
3035
3036 // ------------------------------------------------------------------------------ //
3037 // The total number of active lines in the frames observed within the sampling period
3038 // ------------------------------------------------------------------------------ //
3039
3040 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_HEIGHT_SUM_DEFAULT (0)
3041 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_HEIGHT_SUM_DATASIZE (32)
3042 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_HEIGHT_SUM_OFFSET (0xcc)
3043 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_HEIGHT_SUM_MASK (0xffffffff)
3044
3045 // args: data (32-bit)
acamera_isp_input_port_frame_stats_active_height_sum_read(uintptr_t base)3046 static __inline uint32_t acamera_isp_input_port_frame_stats_active_height_sum_read(uintptr_t base) {
3047 return system_hw_read_32(0xccL);
3048 }
3049 // ------------------------------------------------------------------------------ //
3050 // Register: active height num
3051 // ------------------------------------------------------------------------------ //
3052
3053 // ------------------------------------------------------------------------------ //
3054 // The total number of frames observed within the sampling period
3055 // ------------------------------------------------------------------------------ //
3056
3057 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_HEIGHT_NUM_DEFAULT (0)
3058 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_HEIGHT_NUM_DATASIZE (32)
3059 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_HEIGHT_NUM_OFFSET (0xd0)
3060 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_ACTIVE_HEIGHT_NUM_MASK (0xffffffff)
3061
3062 // args: data (32-bit)
acamera_isp_input_port_frame_stats_active_height_num_read(uintptr_t base)3063 static __inline uint32_t acamera_isp_input_port_frame_stats_active_height_num_read(uintptr_t base) {
3064 return system_hw_read_32(0xd0L);
3065 }
3066 // ------------------------------------------------------------------------------ //
3067 // Register: hblank min
3068 // ------------------------------------------------------------------------------ //
3069
3070 // ------------------------------------------------------------------------------ //
3071 // The minimum number of horizontal blanking samples observed within the sampling period
3072 // ------------------------------------------------------------------------------ //
3073
3074 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_HBLANK_MIN_DEFAULT (0)
3075 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_HBLANK_MIN_DATASIZE (32)
3076 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_HBLANK_MIN_OFFSET (0xd4)
3077 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_HBLANK_MIN_MASK (0xffffffff)
3078
3079 // args: data (32-bit)
acamera_isp_input_port_frame_stats_hblank_min_read(uintptr_t base)3080 static __inline uint32_t acamera_isp_input_port_frame_stats_hblank_min_read(uintptr_t base) {
3081 return system_hw_read_32(0xd4L);
3082 }
3083 // ------------------------------------------------------------------------------ //
3084 // Register: hblank max
3085 // ------------------------------------------------------------------------------ //
3086
3087 // ------------------------------------------------------------------------------ //
3088 // The maximum number of horizontal blanking samples observed within the sampling period
3089 // ------------------------------------------------------------------------------ //
3090
3091 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_HBLANK_MAX_DEFAULT (0)
3092 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_HBLANK_MAX_DATASIZE (32)
3093 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_HBLANK_MAX_OFFSET (0xd8)
3094 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_HBLANK_MAX_MASK (0xffffffff)
3095
3096 // args: data (32-bit)
acamera_isp_input_port_frame_stats_hblank_max_read(uintptr_t base)3097 static __inline uint32_t acamera_isp_input_port_frame_stats_hblank_max_read(uintptr_t base) {
3098 return system_hw_read_32(0xd8L);
3099 }
3100 // ------------------------------------------------------------------------------ //
3101 // Register: hblank sum
3102 // ------------------------------------------------------------------------------ //
3103
3104 // ------------------------------------------------------------------------------ //
3105 // The total number of the horizontal blanking samples observed within the sampling period
3106 // ------------------------------------------------------------------------------ //
3107
3108 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_HBLANK_SUM_DEFAULT (0)
3109 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_HBLANK_SUM_DATASIZE (32)
3110 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_HBLANK_SUM_OFFSET (0xdc)
3111 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_HBLANK_SUM_MASK (0xffffffff)
3112
3113 // args: data (32-bit)
acamera_isp_input_port_frame_stats_hblank_sum_read(uintptr_t base)3114 static __inline uint32_t acamera_isp_input_port_frame_stats_hblank_sum_read(uintptr_t base) {
3115 return system_hw_read_32(0xdcL);
3116 }
3117 // ------------------------------------------------------------------------------ //
3118 // Register: hblank num
3119 // ------------------------------------------------------------------------------ //
3120
3121 // ------------------------------------------------------------------------------ //
3122 // The total number of the lines observed within the sampling period
3123 // ------------------------------------------------------------------------------ //
3124
3125 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_HBLANK_NUM_DEFAULT (0)
3126 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_HBLANK_NUM_DATASIZE (32)
3127 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_HBLANK_NUM_OFFSET (0xe0)
3128 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_HBLANK_NUM_MASK (0xffffffff)
3129
3130 // args: data (32-bit)
acamera_isp_input_port_frame_stats_hblank_num_read(uintptr_t base)3131 static __inline uint32_t acamera_isp_input_port_frame_stats_hblank_num_read(uintptr_t base) {
3132 return system_hw_read_32(0xe0L);
3133 }
3134 // ------------------------------------------------------------------------------ //
3135 // Register: vblank min
3136 // ------------------------------------------------------------------------------ //
3137
3138 // ------------------------------------------------------------------------------ //
3139 // The minimum number of vertical blanking samples observed within the sampling period
3140 // ------------------------------------------------------------------------------ //
3141
3142 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_VBLANK_MIN_DEFAULT (0)
3143 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_VBLANK_MIN_DATASIZE (32)
3144 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_VBLANK_MIN_OFFSET (0xe4)
3145 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_VBLANK_MIN_MASK (0xffffffff)
3146
3147 // args: data (32-bit)
acamera_isp_input_port_frame_stats_vblank_min_read(uintptr_t base)3148 static __inline uint32_t acamera_isp_input_port_frame_stats_vblank_min_read(uintptr_t base) {
3149 return system_hw_read_32(0xe4L);
3150 }
3151 // ------------------------------------------------------------------------------ //
3152 // Register: vblank max
3153 // ------------------------------------------------------------------------------ //
3154
3155 // ------------------------------------------------------------------------------ //
3156 // The maximum number of vertical blanking samples observed within the sampling period
3157 // ------------------------------------------------------------------------------ //
3158
3159 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_VBLANK_MAX_DEFAULT (0)
3160 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_VBLANK_MAX_DATASIZE (32)
3161 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_VBLANK_MAX_OFFSET (0xe8)
3162 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_VBLANK_MAX_MASK (0xffffffff)
3163
3164 // args: data (32-bit)
acamera_isp_input_port_frame_stats_vblank_max_read(uintptr_t base)3165 static __inline uint32_t acamera_isp_input_port_frame_stats_vblank_max_read(uintptr_t base) {
3166 return system_hw_read_32(0xe8L);
3167 }
3168 // ------------------------------------------------------------------------------ //
3169 // Register: vblank sum
3170 // ------------------------------------------------------------------------------ //
3171
3172 // ------------------------------------------------------------------------------ //
3173 // The total number of the vertical blanking samples observed within the sampling period
3174 // ------------------------------------------------------------------------------ //
3175
3176 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_VBLANK_SUM_DEFAULT (0)
3177 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_VBLANK_SUM_DATASIZE (32)
3178 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_VBLANK_SUM_OFFSET (0xec)
3179 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_VBLANK_SUM_MASK (0xffffffff)
3180
3181 // args: data (32-bit)
acamera_isp_input_port_frame_stats_vblank_sum_read(uintptr_t base)3182 static __inline uint32_t acamera_isp_input_port_frame_stats_vblank_sum_read(uintptr_t base) {
3183 return system_hw_read_32(0xecL);
3184 }
3185 // ------------------------------------------------------------------------------ //
3186 // Register: vblank num
3187 // ------------------------------------------------------------------------------ //
3188
3189 // ------------------------------------------------------------------------------ //
3190 // The total number of frames observed within the sampling period
3191 // ------------------------------------------------------------------------------ //
3192
3193 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_VBLANK_NUM_DEFAULT (0)
3194 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_VBLANK_NUM_DATASIZE (32)
3195 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_VBLANK_NUM_OFFSET (0xf0)
3196 #define ACAMERA_ISP_INPUT_PORT_FRAME_STATS_VBLANK_NUM_MASK (0xffffffff)
3197
3198 // args: data (32-bit)
acamera_isp_input_port_frame_stats_vblank_num_read(uintptr_t base)3199 static __inline uint32_t acamera_isp_input_port_frame_stats_vblank_num_read(uintptr_t base) {
3200 return system_hw_read_32(0xf0L);
3201 }
3202 // ------------------------------------------------------------------------------ //
3203 #endif //__ACAMERA_ISP_CONFIG_H__
3204