1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Analogix DP (Display Port) core interface driver.
4 *
5 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
6 * Author: Jingoo Han <jg1.han@samsung.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/component.h>
11 #include <linux/err.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/iopoll.h>
16 #include <linux/irq.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/phy/phy.h>
20 #include <linux/platform_device.h>
21
22 #include <drm/bridge/analogix_dp.h>
23 #include <drm/drm_atomic.h>
24 #include <drm/drm_atomic_helper.h>
25 #include <drm/drm_bridge.h>
26 #include <drm/drm_crtc.h>
27 #include <drm/drm_device.h>
28 #include <drm/drm_panel.h>
29 #include <drm/drm_print.h>
30 #include <drm/drm_probe_helper.h>
31
32 #include "analogix_dp_reg.h"
33 #include "analogix_dp_core.h"
34
35 #define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
36
37 static const bool verify_fast_training;
38
39 struct bridge_init {
40 struct i2c_client *client;
41 struct device_node *node;
42 };
43
analogix_dp_bandwidth_ok(struct analogix_dp_device * dp,const struct drm_display_mode * mode,unsigned int rate,unsigned int lanes)44 static bool analogix_dp_bandwidth_ok(struct analogix_dp_device *dp, const struct drm_display_mode *mode,
45 unsigned int rate, unsigned int lanes)
46 {
47 u32 max_bw, req_bw, bpp = 0x18;
48
49 req_bw = mode->clock * bpp / 0x8;
50 max_bw = lanes * rate;
51 if (req_bw > max_bw) {
52 return false;
53 }
54
55 return true;
56 }
57
analogix_dp_init_dp(struct analogix_dp_device * dp)58 static int analogix_dp_init_dp(struct analogix_dp_device *dp)
59 {
60 int ret;
61
62 analogix_dp_reset(dp);
63
64 analogix_dp_swreset(dp);
65
66 analogix_dp_init_analog_param(dp);
67 analogix_dp_init_interrupt(dp);
68
69 /* SW defined function Normal operation */
70 analogix_dp_enable_sw_function(dp);
71
72 analogix_dp_config_interrupt(dp);
73 ret = analogix_dp_init_analog_func(dp);
74 if (ret) {
75 return ret;
76 }
77
78 analogix_dp_init_hpd(dp);
79 analogix_dp_init_aux(dp);
80 return 0;
81 }
82
analogix_dp_panel_prepare(struct analogix_dp_device * dp)83 static int analogix_dp_panel_prepare(struct analogix_dp_device *dp)
84 {
85 int ret;
86
87 mutex_lock(&dp->panel_lock);
88
89 if (dp->panel_is_prepared) {
90 goto out;
91 }
92
93 ret = drm_panel_prepare(dp->plat_data->panel);
94 if (ret) {
95 goto out;
96 }
97
98 dp->panel_is_prepared = true;
99
100 out:
101 mutex_unlock(&dp->panel_lock);
102 return 0;
103 }
104
analogix_dp_panel_unprepare(struct analogix_dp_device * dp)105 static int analogix_dp_panel_unprepare(struct analogix_dp_device *dp)
106 {
107 int ret;
108
109 mutex_lock(&dp->panel_lock);
110
111 if (!dp->panel_is_prepared) {
112 goto out;
113 }
114
115 ret = drm_panel_unprepare(dp->plat_data->panel);
116 if (ret) {
117 goto out;
118 }
119
120 dp->panel_is_prepared = false;
121
122 out:
123 mutex_unlock(&dp->panel_lock);
124 return 0;
125 }
126
analogix_dp_detect_hpd(struct analogix_dp_device * dp)127 static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
128 {
129 int timeout_loop = 0;
130
131 while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
132 if (analogix_dp_get_plug_in_status(dp) == 0) {
133 return 0;
134 }
135
136 timeout_loop++;
137 usleep_range(0x3e8, 0x44c);
138 }
139
140 /*
141 * Some edp screen do not have hpd signal, so we can't just
142 * return failed when hpd plug in detect failed, DT property
143 * "force-hpd" would indicate whether driver need this.
144 */
145 if (!dp->force_hpd) {
146 return -ETIMEDOUT;
147 }
148
149 /*
150 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
151 * will not work, so we need to give a force hpd action to
152 * set HPD_STATUS manually.
153 */
154 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
155
156 analogix_dp_force_hpd(dp);
157
158 if (analogix_dp_get_plug_in_status(dp) != 0) {
159 dev_err(dp->dev, "failed to get hpd plug in status\n");
160 return -EINVAL;
161 }
162
163 dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
164
165 return 0;
166 }
167
analogix_dp_detect_sink_psr(struct analogix_dp_device * dp)168 static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
169 {
170 unsigned char psr_version;
171 int ret;
172
173 if (!device_property_read_bool(dp->dev, "support-psr")) {
174 return 0;
175 }
176
177 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
178 if (ret != 1) {
179 dev_err(dp->dev, "failed to get PSR version, disable it\n");
180 return false;
181 }
182
183 dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
184 return psr_version & DP_PSR_IS_SUPPORTED;
185 }
186
analogix_dp_enable_sink_psr(struct analogix_dp_device * dp)187 static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
188 {
189 unsigned char psr_en;
190 int ret;
191
192 /* Disable psr function */
193 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
194 if (ret != 1) {
195 dev_err(dp->dev, "failed to get psr config\n");
196 goto end;
197 }
198
199 psr_en &= ~DP_PSR_ENABLE;
200 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
201 if (ret != 1) {
202 dev_err(dp->dev, "failed to disable panel psr\n");
203 goto end;
204 }
205
206 /* Main-Link transmitter remains active during PSR active states */
207 psr_en = DP_PSR_CRC_VERIFICATION;
208 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
209 if (ret != 1) {
210 dev_err(dp->dev, "failed to set panel psr\n");
211 goto end;
212 }
213
214 /* Enable psr function */
215 psr_en = DP_PSR_ENABLE | DP_PSR_CRC_VERIFICATION;
216 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
217 if (ret != 1) {
218 dev_err(dp->dev, "failed to set panel psr\n");
219 goto end;
220 }
221
222 analogix_dp_enable_psr_crc(dp);
223
224 dp->psr_supported = true;
225
226 return 0;
227 end:
228 dev_err(dp->dev, "enable psr fail, force to disable psr\n");
229
230 return ret;
231 }
232
analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device * dp,bool enable)233 static int analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, bool enable)
234 {
235 u8 data;
236 int ret;
237
238 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
239 if (ret != 1) {
240 return ret;
241 }
242
243 if (enable) {
244 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
245 DP_LANE_COUNT_ENHANCED_FRAME_EN | DPCD_LANE_COUNT_SET(data));
246 } else {
247 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, DPCD_LANE_COUNT_SET(data));
248 }
249
250 return ret < 0 ? ret : 0;
251 }
252
analogix_dp_is_enhanced_mode_available(struct analogix_dp_device * dp,u8 * enhanced_mode_support)253 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp, u8 *enhanced_mode_support)
254 {
255 u8 data;
256 int ret;
257
258 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
259 if (ret != 1) {
260 *enhanced_mode_support = 0;
261 return ret;
262 }
263
264 *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data);
265
266 return 0;
267 }
268
analogix_dp_set_enhanced_mode(struct analogix_dp_device * dp)269 static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
270 {
271 u8 data;
272 int ret;
273
274 ret = analogix_dp_is_enhanced_mode_available(dp, &data);
275 if (ret < 0) {
276 return ret;
277 }
278
279 ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data);
280 if (ret < 0) {
281 return ret;
282 }
283
284 if (!data) {
285 /*
286 * A setting of 1 indicates that this is an eDP device that
287 * uses only Enhanced Framing, independently of the setting by
288 * the source of ENHANCED_FRAME_EN
289 */
290 ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_CONFIGURATION_CAP, &data);
291 if (ret < 0) {
292 return ret;
293 }
294
295 data = !!(data & DP_FRAMING_CHANGE_CAP);
296 }
297
298 analogix_dp_enable_enhanced_mode(dp, data);
299
300 dp->link_train.enhanced_framing = data;
301
302 return 0;
303 }
304
analogix_dp_training_pattern_dis(struct analogix_dp_device * dp)305 static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
306 {
307 int ret;
308
309 analogix_dp_set_training_pattern(dp, DP_NONE);
310
311 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
312
313 return ret < 0 ? ret : 0;
314 }
315
analogix_dp_link_start(struct analogix_dp_device * dp)316 static int analogix_dp_link_start(struct analogix_dp_device *dp)
317 {
318 u8 buf[4];
319 int lane, lane_count, retval;
320
321 lane_count = dp->link_train.lane_count;
322
323 dp->link_train.lt_state = CLOCK_RECOVERY;
324 dp->link_train.eq_loop = 0;
325
326 for (lane = 0; lane < lane_count; lane++) {
327 dp->link_train.cr_loop[lane] = 0;
328 }
329
330 /* Set link rate and count as you want to establish */
331 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
332 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
333
334 /* Setup RX configuration */
335 buf[0] = dp->link_train.link_rate;
336 buf[1] = dp->link_train.lane_count;
337 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 0x2);
338 if (retval < 0) {
339 return retval;
340 }
341
342 /* Spread AMP if required, enable 8b/10b coding */
343 buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0;
344 buf[1] = DP_SET_ANSI_8B10B;
345 retval = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 0x2);
346 if (retval < 0) {
347 return retval;
348 }
349
350 /* set enhanced mode if available */
351 retval = analogix_dp_set_enhanced_mode(dp);
352 if (retval < 0) {
353 dev_err(dp->dev, "failed to set enhance mode\n");
354 return retval;
355 }
356
357 /* Set TX voltage-swing and pre-emphasis to minimum */
358 for (lane = 0; lane < lane_count; lane++) {
359 dp->link_train.training_lane[lane] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0;
360 }
361 analogix_dp_set_lane_link_training(dp);
362
363 /* Set training pattern 1 */
364 analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
365
366 /* Set RX training pattern */
367 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
368 if (retval < 0) {
369 return retval;
370 }
371
372 for (lane = 0; lane < lane_count; lane++) {
373 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
374 }
375
376 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lane_count);
377 if (retval < 0) {
378 return retval;
379 }
380
381 return 0;
382 }
383
analogix_dp_get_lane_status(u8 link_status[2],int lane)384 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
385 {
386 int shift = (lane & 1) * 0x4;
387 u8 link_value = link_status[lane >> 1];
388
389 return (link_value >> shift) & 0xf;
390 }
391
analogix_dp_clock_recovery_ok(u8 link_status[2],int lane_count)392 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
393 {
394 int lane;
395 u8 lane_status;
396
397 for (lane = 0; lane < lane_count; lane++) {
398 lane_status = analogix_dp_get_lane_status(link_status, lane);
399 if ((lane_status & DP_LANE_CR_DONE) == 0) {
400 return -EINVAL;
401 }
402 }
403 return 0;
404 }
405
analogix_dp_channel_eq_ok(u8 link_status[2],u8 link_align,int lane_count)406 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, int lane_count)
407 {
408 int lane;
409 u8 lane_status;
410
411 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) {
412 return -EINVAL;
413 }
414
415 for (lane = 0; lane < lane_count; lane++) {
416 lane_status = analogix_dp_get_lane_status(link_status, lane);
417 lane_status &= DP_CHANNEL_EQ_BITS;
418 if (lane_status != DP_CHANNEL_EQ_BITS) {
419 return -EINVAL;
420 }
421 }
422
423 return 0;
424 }
425
analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],int lane)426 static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
427 {
428 int shift = (lane & 1) * 4;
429 u8 link_value = adjust_request[lane >> 1];
430
431 return (link_value >> shift) & 0x3;
432 }
433
analogix_dp_get_adjust_request_pre_emphasis(u8 adjust_request[0x2],int lane)434 static unsigned char analogix_dp_get_adjust_request_pre_emphasis(u8 adjust_request[0x2], int lane)
435 {
436 int shift = (lane & 1) * 0x4;
437 u8 link_value = adjust_request[lane >> 1];
438
439 return ((link_value >> shift) & 0xc) >> 0x2;
440 }
441
analogix_dp_reduce_link_rate(struct analogix_dp_device * dp)442 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
443 {
444 analogix_dp_training_pattern_dis(dp);
445 analogix_dp_set_enhanced_mode(dp);
446
447 dp->link_train.lt_state = FAILED;
448 }
449
analogix_dp_get_adjust_training_lane(struct analogix_dp_device * dp,u8 adjust_request[2])450 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, u8 adjust_request[2])
451 {
452 int lane, lane_count;
453 u8 voltage_swing, pre_emphasis, training_lane;
454
455 lane_count = dp->link_train.lane_count;
456 for (lane = 0; lane < lane_count; lane++) {
457 voltage_swing = analogix_dp_get_adjust_request_voltage(adjust_request, lane);
458 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(adjust_request, lane);
459 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | DPCD_PRE_EMPHASIS_SET(pre_emphasis);
460
461 if (voltage_swing == VOLTAGE_LEVEL_3) {
462 training_lane |= DP_TRAIN_MAX_SWING_REACHED;
463 }
464 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
465 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
466 }
467
468 dp->link_train.training_lane[lane] = training_lane;
469 }
470 }
471
analogix_dp_tps3_supported(struct analogix_dp_device * dp)472 static bool analogix_dp_tps3_supported(struct analogix_dp_device *dp)
473 {
474 bool source_tps3_supported, sink_tps3_supported;
475 u8 dpcd = 0;
476
477 source_tps3_supported = dp->video_info.max_link_rate == DP_LINK_BW_5_4;
478 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &dpcd);
479 sink_tps3_supported = dpcd & DP_TPS3_SUPPORTED;
480
481 return source_tps3_supported && sink_tps3_supported;
482 }
483
analogix_dp_process_clock_recovery(struct analogix_dp_device * dp)484 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
485 {
486 int lane, lane_count, retval;
487 u8 voltage_swing, pre_emphasis, training_lane;
488 u8 link_status[2], adjust_request[2];
489 u8 training_pattern = TRAINING_PTN2;
490
491 usleep_range(0x64, 0x65);
492
493 lane_count = dp->link_train.lane_count;
494
495 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 0x2);
496 if (retval < 0) {
497 return retval;
498 }
499
500 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, adjust_request, 0x2);
501 if (retval < 0) {
502 return retval;
503 }
504
505 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
506 if (analogix_dp_tps3_supported(dp)) {
507 training_pattern = TRAINING_PTN3;
508 }
509
510 /* set training pattern for EQ */
511 analogix_dp_set_training_pattern(dp, training_pattern);
512
513 retval =
514 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
515 DP_LINK_SCRAMBLING_DISABLE |
516 (training_pattern == TRAINING_PTN3 ? DP_TRAINING_PATTERN_3 : DP_TRAINING_PATTERN_2));
517 if (retval < 0) {
518 return retval;
519 }
520
521 dev_dbg(dp->dev, "Link Training Clock Recovery success\n");
522 dp->link_train.lt_state = EQUALIZER_TRAINING;
523 } else {
524 for (lane = 0; lane < lane_count; lane++) {
525 training_lane = analogix_dp_get_lane_link_training(dp, lane);
526 voltage_swing = analogix_dp_get_adjust_request_voltage(adjust_request, lane);
527 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(adjust_request, lane);
528 if (DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing &&
529 DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis) {
530 dp->link_train.cr_loop[lane]++;
531 }
532
533 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || voltage_swing == VOLTAGE_LEVEL_3 ||
534 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
535 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", dp->link_train.cr_loop[lane], voltage_swing,
536 pre_emphasis);
537 analogix_dp_reduce_link_rate(dp);
538 return -EIO;
539 }
540 }
541
542 analogix_dp_get_adjust_training_lane(dp, adjust_request);
543 analogix_dp_set_lane_link_training(dp);
544
545 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->link_train.training_lane, lane_count);
546 if (retval < 0) {
547 return retval;
548 }
549 }
550
551 return 0;
552 }
553
analogix_dp_process_equalizer_training(struct analogix_dp_device * dp)554 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
555 {
556 int lane_count, retval;
557 u32 reg;
558 u8 link_align, link_status[2], adjust_request[2];
559
560 usleep_range(0x190, 0x191);
561
562 lane_count = dp->link_train.lane_count;
563
564 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 0x2);
565 if (retval < 0) {
566 return retval;
567 }
568
569 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
570 analogix_dp_reduce_link_rate(dp);
571 return -EIO;
572 }
573
574 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, adjust_request, 0x2);
575 if (retval < 0) {
576 return retval;
577 }
578
579 retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
580 if (retval < 0) {
581 return retval;
582 }
583
584 analogix_dp_get_adjust_training_lane(dp, adjust_request);
585
586 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
587 /* traing pattern Set to Normal */
588 retval = analogix_dp_training_pattern_dis(dp);
589 if (retval < 0) {
590 return retval;
591 }
592
593 dev_dbg(dp->dev, "Link Training success!\n");
594 analogix_dp_get_link_bandwidth(dp, ®);
595 dp->link_train.link_rate = reg;
596 dev_dbg(dp->dev, "final bandwidth = %.2x\n", dp->link_train.link_rate);
597
598 analogix_dp_get_lane_count(dp, ®);
599 dp->link_train.lane_count = reg;
600 dev_dbg(dp->dev, "final lane count = %.2x\n", dp->link_train.lane_count);
601
602 dp->link_train.lt_state = FINISHED;
603
604 return 0;
605 }
606
607 /* not all locked */
608 dp->link_train.eq_loop++;
609
610 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
611 dev_err(dp->dev, "EQ Max loop\n");
612 analogix_dp_reduce_link_rate(dp);
613 return -EIO;
614 }
615
616 analogix_dp_set_lane_link_training(dp);
617
618 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->link_train.training_lane, lane_count);
619 if (retval < 0) {
620 return retval;
621 }
622
623 return 0;
624 }
625
analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device * dp,u8 * bandwidth)626 static int analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, u8 *bandwidth)
627 {
628 u8 data;
629 int ret;
630
631 /*
632 * For DP rev.1.1, Maximum link rate of Main Link lanes
633 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
634 * For DP rev.1.2, Maximum link rate of Main Link lanes
635 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
636 */
637 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
638 if (ret < 0) {
639 return ret;
640 }
641
642 *bandwidth = data;
643
644 return 0;
645 }
646
analogix_dp_get_max_rx_lane_count(struct analogix_dp_device * dp,u8 * lane_count)647 static int analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, u8 *lane_count)
648 {
649 u8 data;
650 int ret;
651
652 /*
653 * For DP rev.1.1, Maximum number of Main Link lanes
654 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
655 */
656 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
657 if (ret < 0) {
658 return ret;
659 }
660
661 *lane_count = DPCD_MAX_LANE_COUNT(data);
662
663 return 0;
664 }
665
analogix_dp_full_link_train(struct analogix_dp_device * dp,u32 max_lanes,u32 max_rate)666 static int analogix_dp_full_link_train(struct analogix_dp_device *dp, u32 max_lanes, u32 max_rate)
667 {
668 struct video_info *video = &dp->video_info;
669 int retval = 0;
670 bool training_finished = false;
671 u8 dpcd;
672
673 /*
674 * MACRO_RST must be applied after the PLL_LOCK to avoid
675 * the DP inter pair skew issue for at least 10 us
676 */
677 analogix_dp_reset_macro(dp);
678
679 /* Initialize by reading RX's DPCD */
680 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
681 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
682
683 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
684 (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
685 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", dp->link_train.link_rate);
686 dp->link_train.link_rate = DP_LINK_BW_1_62;
687 }
688
689 if (dp->link_train.lane_count == 0) {
690 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n", dp->link_train.lane_count);
691 dp->link_train.lane_count = (u8)LANE_COUNT1;
692 }
693
694 if (!analogix_dp_bandwidth_ok(dp, &video->mode, drm_dp_bw_code_to_link_rate(dp->link_train.link_rate),
695 dp->link_train.lane_count)) {
696 dev_err(dp->dev, "bandwidth overflow\n");
697 return -EINVAL;
698 }
699
700 drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &dpcd);
701 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5);
702
703 /* Setup TX lane count & rate */
704 if (dp->link_train.lane_count > max_lanes) {
705 dp->link_train.lane_count = max_lanes;
706 }
707 if (dp->link_train.link_rate > max_rate) {
708 dp->link_train.link_rate = max_rate;
709 }
710
711 /* All DP analog module power up */
712 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
713
714 dp->link_train.lt_state = START;
715
716 /* Process here */
717 while (!retval && !training_finished) {
718 switch (dp->link_train.lt_state) {
719 case START:
720 retval = analogix_dp_link_start(dp);
721 if (retval) {
722 dev_err(dp->dev, "LT link start failed!\n");
723 }
724 break;
725 case CLOCK_RECOVERY:
726 retval = analogix_dp_process_clock_recovery(dp);
727 if (retval) {
728 dev_err(dp->dev, "LT CR failed!\n");
729 }
730 break;
731 case EQUALIZER_TRAINING:
732 retval = analogix_dp_process_equalizer_training(dp);
733 if (retval) {
734 dev_err(dp->dev, "LT EQ failed!\n");
735 }
736 break;
737 case FINISHED:
738 training_finished = 1;
739 break;
740 case FAILED:
741 return -EREMOTEIO;
742 }
743 }
744 if (retval) {
745 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
746 }
747
748 return retval;
749 }
750
analogix_dp_fast_link_train(struct analogix_dp_device * dp)751 static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
752 {
753 int ret;
754 u8 link_align, link_status[2];
755
756 analogix_dp_reset_macro(dp);
757
758 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
759 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
760 analogix_dp_set_lane_link_training(dp);
761 analogix_dp_enable_enhanced_mode(dp, dp->link_train.enhanced_framing);
762
763 /* source Set training pattern 1 */
764 analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
765 /* From DP spec, pattern must be on-screen for a minimum 500us */
766 usleep_range(0x1f4, 0x258);
767
768 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
769 /* From DP spec, pattern must be on-screen for a minimum 500us */
770 usleep_range(0x1f4, 0x258);
771
772 analogix_dp_set_training_pattern(dp, DP_NONE);
773
774 /*
775 * Useful for debugging issues with fast link training, disable for more
776 * speed
777 */
778 if (verify_fast_training) {
779 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
780 if (ret < 0) {
781 DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n", ret);
782 return ret;
783 }
784
785 ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 0x2);
786 if (ret < 0) {
787 DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n", ret);
788 return ret;
789 }
790
791 if (analogix_dp_clock_recovery_ok(link_status, dp->link_train.lane_count)) {
792 DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
793 analogix_dp_reduce_link_rate(dp);
794 return -EIO;
795 }
796
797 if (analogix_dp_channel_eq_ok(link_status, link_align, dp->link_train.lane_count)) {
798 DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
799 analogix_dp_reduce_link_rate(dp);
800 return -EIO;
801 }
802 }
803
804 return 0;
805 }
806
analogix_dp_train_link(struct analogix_dp_device * dp)807 static int analogix_dp_train_link(struct analogix_dp_device *dp)
808 {
809 if (dp->fast_train_enable) {
810 return analogix_dp_fast_link_train(dp);
811 }
812
813 return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count, dp->video_info.max_link_rate);
814 }
815
analogix_dp_config_video(struct analogix_dp_device * dp)816 static int analogix_dp_config_video(struct analogix_dp_device *dp)
817 {
818 int timeout_loop = 0;
819 int done_count = 0;
820
821 analogix_dp_config_video_slave_mode(dp);
822
823 analogix_dp_set_video_color_format(dp);
824
825 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
826 dev_err(dp->dev, "PLL is not locked yet.\n");
827 return -EINVAL;
828 }
829
830 for (;;) {
831 timeout_loop++;
832 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) {
833 break;
834 }
835 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
836 dev_err(dp->dev, "Timeout of slave video streamclk ok\n");
837 return -ETIMEDOUT;
838 }
839 usleep_range(0x3e8, 0x3e9);
840 }
841
842 /* Set to use the register calculated M/N video */
843 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
844
845 /* For video bist, Video timing must be generated by register */
846 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
847
848 /* Disable video mute */
849 analogix_dp_enable_video_mute(dp, 0);
850
851 /* Configure video slave mode */
852 analogix_dp_enable_video_master(dp, 0);
853
854 /* Enable video */
855 analogix_dp_start_video(dp);
856
857 timeout_loop = 0;
858
859 for (;;) {
860 timeout_loop++;
861 if (analogix_dp_is_video_stream_on(dp) == 0) {
862 done_count++;
863 if (done_count > 0x0a) {
864 break;
865 }
866 } else if (done_count) {
867 done_count = 0;
868 }
869 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
870 dev_warn(dp->dev, "Ignoring timeout of video streamclk ok\n");
871 break;
872 }
873
874 usleep_range(0x3e8, 0x3e9);
875 }
876
877 return 0;
878 }
879
analogix_dp_enable_scramble(struct analogix_dp_device * dp,bool enable)880 static int analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
881 {
882 u8 data;
883 int ret;
884
885 if (enable) {
886 analogix_dp_enable_scrambling(dp);
887
888 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data);
889 if (ret != 1) {
890 return ret;
891 }
892 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
893 } else {
894 analogix_dp_disable_scrambling(dp);
895
896 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data);
897 if (ret != 1) {
898 return ret;
899 }
900 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
901 }
902 return ret < 0 ? ret : 0;
903 }
904
analogix_dp_hpd_irq_handler(int irq,void * arg)905 static irqreturn_t analogix_dp_hpd_irq_handler(int irq, void *arg)
906 {
907 struct analogix_dp_device *dp = arg;
908
909 if (dp->drm_dev) {
910 drm_helper_hpd_irq_event(dp->drm_dev);
911 }
912
913 return IRQ_HANDLED;
914 }
915
analogix_dp_hardirq(int irq,void * arg)916 static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
917 {
918 struct analogix_dp_device *dp = arg;
919 enum dp_irq_type irq_type;
920 int ret;
921
922 ret = pm_runtime_get_sync(dp->dev);
923 if (ret < 0) {
924 return IRQ_NONE;
925 }
926
927 irq_type = analogix_dp_get_irq_type(dp);
928 if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
929 analogix_dp_mute_hpd_interrupt(dp);
930 }
931
932 pm_runtime_put_sync(dp->dev);
933
934 return IRQ_WAKE_THREAD;
935 }
936
analogix_dp_irq_thread(int irq,void * arg)937 static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
938 {
939 struct analogix_dp_device *dp = arg;
940 enum dp_irq_type irq_type;
941 int ret;
942
943 ret = pm_runtime_get_sync(dp->dev);
944 if (ret < 0) {
945 return IRQ_NONE;
946 }
947
948 irq_type = analogix_dp_get_irq_type(dp);
949 if ((irq_type & DP_IRQ_TYPE_HP_CABLE_IN) || (irq_type & DP_IRQ_TYPE_HP_CABLE_OUT)) {
950 dev_dbg(dp->dev, "Detected cable status changed!\n");
951 if (dp->drm_dev) {
952 drm_helper_hpd_irq_event(dp->drm_dev);
953 }
954 }
955
956 if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
957 analogix_dp_clear_hotplug_interrupts(dp);
958 analogix_dp_unmute_hpd_interrupt(dp);
959 }
960
961 pm_runtime_put_sync(dp->dev);
962
963 return IRQ_HANDLED;
964 }
965
analogix_dp_fast_link_train_detection(struct analogix_dp_device * dp)966 static int analogix_dp_fast_link_train_detection(struct analogix_dp_device *dp)
967 {
968 int ret;
969 u8 spread;
970
971 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
972 if (ret != 1) {
973 dev_err(dp->dev, "failed to read downspread %d\n", ret);
974 return ret;
975 }
976 dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
977 dev_dbg(dp->dev, "fast link training %s\n", dp->fast_train_enable ? "supported" : "unsupported");
978 return 0;
979 }
980
analogix_dp_commit(struct analogix_dp_device * dp)981 static int analogix_dp_commit(struct analogix_dp_device *dp)
982 {
983 struct video_info *video = &dp->video_info;
984 int ret;
985
986 if (device_property_read_bool(dp->dev, "panel-self-test")) {
987 return drm_dp_dpcd_writeb(&dp->aux, DP_EDP_CONFIGURATION_SET, DP_PANEL_SELF_TEST_ENABLE);
988 }
989
990 ret = analogix_dp_train_link(dp);
991 if (ret) {
992 dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
993 return ret;
994 }
995
996 ret = analogix_dp_enable_scramble(dp, 1);
997 if (ret < 0) {
998 dev_err(dp->dev, "can not enable scramble\n");
999 return ret;
1000 }
1001
1002 analogix_dp_init_video(dp);
1003 analogix_dp_set_video_format(dp);
1004
1005 if (video->video_bist_enable) {
1006 analogix_dp_video_bist_enable(dp);
1007 }
1008
1009 ret = analogix_dp_config_video(dp);
1010 if (ret) {
1011 dev_err(dp->dev, "unable to config video\n");
1012 return ret;
1013 }
1014
1015 /* Check whether panel supports fast training */
1016 ret = analogix_dp_fast_link_train_detection(dp);
1017 if (ret) {
1018 return ret;
1019 }
1020
1021 if (analogix_dp_detect_sink_psr(dp)) {
1022 ret = analogix_dp_enable_sink_psr(dp);
1023 if (ret) {
1024 return ret;
1025 }
1026 }
1027
1028 return ret;
1029 }
1030
analogix_dp_enable_psr(struct analogix_dp_device * dp)1031 static int analogix_dp_enable_psr(struct analogix_dp_device *dp)
1032 {
1033 struct dp_sdp psr_vsc;
1034 int ret;
1035 u8 sink;
1036
1037 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
1038 if (ret != 1) {
1039 DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
1040 } else if (sink == DP_PSR_SINK_ACTIVE_RFB) {
1041 return 0;
1042 }
1043
1044 /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
1045 memset(&psr_vsc, 0, sizeof(psr_vsc));
1046 psr_vsc.sdp_header.HB0 = 0;
1047 psr_vsc.sdp_header.HB1 = 0x7;
1048 psr_vsc.sdp_header.HB2 = 0x2;
1049 psr_vsc.sdp_header.HB3 = 0x8;
1050 psr_vsc.db[0] = 0;
1051 psr_vsc.db[1] = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
1052
1053 ret = analogix_dp_send_psr_spd(dp, &psr_vsc, true);
1054 if (!ret) {
1055 analogix_dp_set_analog_power_down(dp, POWER_ALL, true);
1056 }
1057
1058 return ret;
1059 }
1060
analogix_dp_disable_psr(struct analogix_dp_device * dp)1061 static int analogix_dp_disable_psr(struct analogix_dp_device *dp)
1062 {
1063 struct dp_sdp psr_vsc;
1064 int ret;
1065 u8 sink;
1066
1067 analogix_dp_set_analog_power_down(dp, POWER_ALL, false);
1068
1069 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
1070 if (ret != 1) {
1071 DRM_DEV_ERROR(dp->dev, "Failed to set DP Power0 %d\n", ret);
1072 return ret;
1073 }
1074
1075 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
1076 if (ret != 1) {
1077 DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
1078 return ret;
1079 } else if (sink == DP_PSR_SINK_INACTIVE) {
1080 DRM_DEV_ERROR(dp->dev, "sink inactive, skip disable psr");
1081 return 0;
1082 }
1083
1084 ret = analogix_dp_train_link(dp);
1085 if (ret) {
1086 DRM_DEV_ERROR(dp->dev, "Failed to train the link %d\n", ret);
1087 return ret;
1088 }
1089
1090 /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
1091 memset(&psr_vsc, 0, sizeof(psr_vsc));
1092 psr_vsc.sdp_header.HB0 = 0;
1093 psr_vsc.sdp_header.HB1 = 0x7;
1094 psr_vsc.sdp_header.HB2 = 0x2;
1095 psr_vsc.sdp_header.HB3 = 0x8;
1096
1097 psr_vsc.db[0] = 0;
1098 psr_vsc.db[1] = 0;
1099
1100 return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
1101 }
1102
analogix_dp_get_modes(struct drm_connector * connector)1103 static int analogix_dp_get_modes(struct drm_connector *connector)
1104 {
1105 struct analogix_dp_device *dp = to_dp(connector);
1106 struct edid *edid;
1107 int num_modes = 0;
1108
1109 if (dp->plat_data->panel) {
1110 num_modes += drm_panel_get_modes(dp->plat_data->panel, connector);
1111 }
1112
1113 if (!num_modes) {
1114 if (dp->plat_data->panel) {
1115 analogix_dp_panel_prepare(dp);
1116 }
1117
1118 pm_runtime_get_sync(dp->dev);
1119 edid = drm_get_edid(connector, &dp->aux.ddc);
1120 pm_runtime_put(dp->dev);
1121 if (edid) {
1122 drm_connector_update_edid_property(&dp->connector, edid);
1123 num_modes += drm_add_edid_modes(&dp->connector, edid);
1124 kfree(edid);
1125 }
1126 }
1127
1128 if (dp->plat_data->get_modes) {
1129 num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
1130 }
1131
1132 if (num_modes > 0 && dp->plat_data->split_mode) {
1133 struct drm_display_mode *mode;
1134
1135 list_for_each_entry(mode, &connector->probed_modes, head) dp->plat_data->convert_to_split_mode(mode);
1136 }
1137
1138 return num_modes;
1139 }
1140
analogix_dp_best_encoder(struct drm_connector * connector)1141 static struct drm_encoder *analogix_dp_best_encoder(struct drm_connector *connector)
1142 {
1143 struct analogix_dp_device *dp = to_dp(connector);
1144
1145 return dp->encoder;
1146 }
1147
analogix_dp_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)1148 static int analogix_dp_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state)
1149 {
1150 struct analogix_dp_device *dp = to_dp(connector);
1151 struct drm_connector_state *conn_state;
1152 struct drm_crtc_state *crtc_state;
1153
1154 conn_state = drm_atomic_get_new_connector_state(state, connector);
1155 if (WARN_ON(!conn_state)) {
1156 return -ENODEV;
1157 }
1158
1159 conn_state->self_refresh_aware = true;
1160
1161 if (!conn_state->crtc) {
1162 return 0;
1163 }
1164
1165 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
1166 if (!crtc_state) {
1167 return 0;
1168 }
1169
1170 if (crtc_state->self_refresh_active && !dp->psr_supported) {
1171 return -EINVAL;
1172 }
1173
1174 return 0;
1175 }
1176
1177 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
1178 .get_modes = analogix_dp_get_modes,
1179 .best_encoder = analogix_dp_best_encoder,
1180 .atomic_check = analogix_dp_atomic_check,
1181 };
1182
analogix_dp_detect(struct analogix_dp_device * dp)1183 static enum drm_connector_status analogix_dp_detect(struct analogix_dp_device *dp)
1184 {
1185 enum drm_connector_status status = connector_status_disconnected;
1186 int ret;
1187
1188 if (dp->plat_data->panel) {
1189 analogix_dp_panel_prepare(dp);
1190 }
1191
1192 pm_runtime_get_sync(dp->dev);
1193
1194 if (!analogix_dp_detect_hpd(dp)) {
1195 ret = analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
1196 if (ret) {
1197 dev_err(dp->dev, "failed to read max link rate\n");
1198 goto out;
1199 }
1200
1201 ret = analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
1202 if (ret) {
1203 dev_err(dp->dev, "failed to read max lane count\n");
1204 goto out;
1205 }
1206
1207 status = connector_status_connected;
1208 }
1209
1210 out:
1211 pm_runtime_put(dp->dev);
1212
1213 return status;
1214 }
1215
analogix_dp_connector_detect(struct drm_connector * connector,bool force)1216 static enum drm_connector_status analogix_dp_connector_detect(struct drm_connector *connector, bool force)
1217 {
1218 struct analogix_dp_device *dp = to_dp(connector);
1219
1220 if (dp->plat_data->right && analogix_dp_detect(dp->plat_data->right) != connector_status_connected) {
1221 return connector_status_disconnected;
1222 }
1223
1224 return analogix_dp_detect(dp);
1225 }
1226
1227 static const struct drm_connector_funcs analogix_dp_connector_funcs = {
1228 .fill_modes = drm_helper_probe_single_connector_modes,
1229 .detect = analogix_dp_connector_detect,
1230 .destroy = drm_connector_cleanup,
1231 .reset = drm_atomic_helper_connector_reset,
1232 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1233 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1234 };
1235
analogix_dp_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)1236 static int analogix_dp_bridge_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags)
1237 {
1238 struct analogix_dp_device *dp = bridge->driver_private;
1239 struct drm_encoder *encoder = dp->encoder;
1240 struct drm_connector *connector = NULL;
1241 int ret = 0;
1242
1243 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
1244 return 0;
1245 }
1246
1247 if (!bridge->encoder) {
1248 DRM_ERROR("Parent encoder object not found");
1249 return -ENODEV;
1250 }
1251
1252 if (!dp->plat_data->skip_connector) {
1253 connector = &dp->connector;
1254 connector->polled = DRM_CONNECTOR_POLL_HPD;
1255
1256 ret = drm_connector_init(dp->drm_dev, connector, &analogix_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
1257 if (ret) {
1258 DRM_ERROR("Failed to initialize connector with drm\n");
1259 return ret;
1260 }
1261
1262 drm_connector_helper_add(connector, &analogix_dp_connector_helper_funcs);
1263 drm_connector_attach_encoder(connector, encoder);
1264 }
1265
1266 /*
1267 * NOTE: the connector registration is implemented in analogix
1268 * platform driver, that to say connector would be exist after
1269 * plat_data->attch return, that's why we record the connector
1270 * point after plat attached.
1271 */
1272 if (dp->plat_data->attach) {
1273 ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1274 if (ret) {
1275 DRM_ERROR("Failed at platform attach func\n");
1276 return ret;
1277 }
1278 }
1279
1280 return 0;
1281 }
1282
analogix_dp_bridge_detach(struct drm_bridge * bridge)1283 static void analogix_dp_bridge_detach(struct drm_bridge *bridge)
1284 {
1285 struct analogix_dp_device *dp = bridge->driver_private;
1286
1287 if (dp->plat_data->detach) {
1288 dp->plat_data->detach(dp->plat_data, bridge);
1289 }
1290 }
analogix_dp_get_old_crtc(struct analogix_dp_device * dp,struct drm_atomic_state * state)1291 static struct drm_crtc *analogix_dp_get_old_crtc(struct analogix_dp_device *dp, struct drm_atomic_state *state)
1292 {
1293 struct drm_encoder *encoder = dp->encoder;
1294 struct drm_connector *connector;
1295 struct drm_connector_state *conn_state;
1296
1297 connector = drm_atomic_get_old_connector_for_encoder(state, encoder);
1298 if (!connector)
1299 return NULL;
1300
1301 conn_state = drm_atomic_get_old_connector_state(state, connector);
1302 if (!conn_state)
1303 return NULL;
1304
1305 return conn_state->crtc;
1306 }
1307
analogix_dp_get_new_crtc(struct analogix_dp_device * dp,struct drm_atomic_state * state)1308 static struct drm_crtc *analogix_dp_get_new_crtc(struct analogix_dp_device *dp, struct drm_atomic_state *state)
1309 {
1310 struct drm_encoder *encoder = dp->encoder;
1311 struct drm_connector *connector;
1312 struct drm_connector_state *conn_state;
1313
1314 connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
1315 if (!connector) {
1316 return NULL;
1317 }
1318
1319 conn_state = drm_atomic_get_new_connector_state(state, connector);
1320 if (!conn_state) {
1321 return NULL;
1322 }
1323
1324 return conn_state->crtc;
1325 }
1326
analogix_dp_bridge_atomic_pre_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1327 static void analogix_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge, struct drm_bridge_state *old_bridge_state)
1328 {
1329 struct drm_atomic_state *old_state = old_bridge_state->base.state;
1330 struct analogix_dp_device *dp = bridge->driver_private;
1331 struct drm_crtc *crtc;
1332 struct drm_crtc_state *old_crtc_state;
1333
1334 if (dp->psr_supported) {
1335 crtc = analogix_dp_get_new_crtc(dp, old_state);
1336 if (!crtc) {
1337 return;
1338 }
1339
1340 old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
1341 /* Don't touch the panel if we're coming back from PSR */
1342 if (old_crtc_state && old_crtc_state->self_refresh_active) {
1343 return;
1344 }
1345 }
1346
1347 if (dp->plat_data->panel) {
1348 analogix_dp_panel_prepare(dp);
1349 }
1350 }
1351
analogix_dp_set_bridge(struct analogix_dp_device * dp)1352 static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
1353 {
1354 int ret;
1355
1356 pm_runtime_get_sync(dp->dev);
1357
1358 if (dp->plat_data->power_on_start) {
1359 dp->plat_data->power_on_start(dp->plat_data);
1360 }
1361
1362 analogix_dp_phy_power_on(dp);
1363
1364 ret = analogix_dp_init_dp(dp);
1365 if (ret) {
1366 goto out_dp_init;
1367 }
1368
1369 /*
1370 * According to DP spec v1.3 chap 3.5.1.2 Link Training,
1371 * We should first make sure the HPD signal is asserted high by device
1372 * when we want to establish a link with it.
1373 */
1374 ret = analogix_dp_detect_hpd(dp);
1375 if (ret) {
1376 DRM_ERROR("failed to get hpd single ret = %d\n", ret);
1377 goto out_dp_init;
1378 }
1379
1380 ret = analogix_dp_commit(dp);
1381 if (ret < 0) {
1382 DRM_ERROR("dp commit error, ret = %d\n", ret);
1383 goto out_dp_init;
1384 }
1385
1386 if (dp->plat_data->panel) {
1387 drm_panel_enable(dp->plat_data->panel);
1388 }
1389
1390 if (dp->plat_data->power_on_end) {
1391 dp->plat_data->power_on_end(dp->plat_data);
1392 }
1393
1394 enable_irq(dp->irq);
1395 return 0;
1396
1397 out_dp_init:
1398 analogix_dp_phy_power_off(dp);
1399 if (dp->plat_data->power_off) {
1400 dp->plat_data->power_off(dp->plat_data);
1401 }
1402 pm_runtime_put_sync(dp->dev);
1403
1404 return ret;
1405 }
1406
analogix_dp_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1407 static void analogix_dp_bridge_atomic_enable(struct drm_bridge *bridge, struct drm_bridge_state *old_bridge_state)
1408 {
1409 struct drm_atomic_state *old_state = old_bridge_state->base.state;
1410 struct analogix_dp_device *dp = bridge->driver_private;
1411 struct drm_crtc *crtc;
1412 struct drm_crtc_state *old_crtc_state;
1413 int timeout_loop = 0;
1414 int ret;
1415
1416 if (dp->psr_supported) {
1417 crtc = analogix_dp_get_new_crtc(dp, old_state);
1418 if (!crtc) {
1419 return;
1420 }
1421
1422 old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
1423 /* Not a full enable, just disable PSR and continue */
1424 if (old_crtc_state && old_crtc_state->self_refresh_active) {
1425 ret = analogix_dp_disable_psr(dp);
1426 if (ret) {
1427 DRM_ERROR("Failed to disable psr %d\n", ret);
1428 }
1429 return;
1430 }
1431 }
1432
1433 if (dp->dpms_mode == DRM_MODE_DPMS_ON) {
1434 return;
1435 }
1436
1437 while (timeout_loop < MAX_PLL_LOCK_LOOP) {
1438 if (analogix_dp_set_bridge(dp) == 0) {
1439 dp->dpms_mode = DRM_MODE_DPMS_ON;
1440 return;
1441 }
1442 dev_err(dp->dev, "failed to set bridge, retry: %d\n", timeout_loop);
1443 timeout_loop++;
1444 usleep_range(0xa, 0xb);
1445 }
1446 dev_err(dp->dev, "too many times retry set bridge, give it up\n");
1447 }
1448
analogix_dp_bridge_disable(struct drm_bridge * bridge)1449 static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1450 {
1451 struct analogix_dp_device *dp_dev = bridge->driver_private;
1452
1453 if (dp_dev->dpms_mode != DRM_MODE_DPMS_ON) {
1454 return;
1455 }
1456
1457 if (dp_dev->plat_data->panel) {
1458 if (drm_panel_disable(dp_dev->plat_data->panel)) {
1459 DRM_ERROR("failed to disable the panel\n");
1460 return;
1461 }
1462 }
1463
1464 disable_irq(dp_dev->irq);
1465
1466 if (dp_dev->plat_data->power_off) {
1467 dp_dev->plat_data->power_off(dp_dev->plat_data);
1468 }
1469
1470 analogix_dp_reset_aux(dp_dev);
1471 analogix_dp_set_analog_power_down(dp_dev, POWER_ALL, 1);
1472 analogix_dp_phy_power_off(dp_dev);
1473
1474 pm_runtime_put_sync(dp_dev->dev);
1475
1476 if (dp_dev->plat_data->panel) {
1477 analogix_dp_panel_unprepare(dp_dev);
1478 }
1479
1480 dp_dev->fast_train_enable = false;
1481 dp_dev->psr_supported = false;
1482 dp_dev->dpms_mode = DRM_MODE_DPMS_OFF;
1483 }
1484
analogix_dp_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1485 static void analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge, struct drm_bridge_state *old_bridge_state)
1486 {
1487 struct drm_atomic_state *old_state = old_bridge_state->base.state;
1488 struct analogix_dp_device *dp_dev = bridge->driver_private;
1489 struct drm_crtc *old_crtc, *new_crtc;
1490 struct drm_crtc_state *old_crtc_state = NULL;
1491 struct drm_crtc_state *new_crtc_state = NULL;
1492 int ret;
1493 new_crtc = analogix_dp_get_new_crtc(dp_dev, old_state);
1494 if (!new_crtc) {
1495 goto out;
1496 }
1497 new_crtc_state = drm_atomic_get_new_crtc_state(old_state, new_crtc);
1498 if (!new_crtc_state) {
1499 goto out;
1500 }
1501 /* Don't do a full disable on PSR transitions */
1502 if (new_crtc_state->self_refresh_active) {
1503 return;
1504 }
1505 out:
1506 old_crtc = analogix_dp_get_old_crtc(dp_dev, old_state);
1507 if (old_crtc) {
1508 old_crtc_state = drm_atomic_get_old_crtc_state(old_state, old_crtc);
1509 /* When moving from PSR to fully disabled, exit PSR first. */
1510 if (old_crtc_state && old_crtc_state->self_refresh_active) {
1511 ret = analogix_dp_disable_psr(dp_dev);
1512 if (ret) {
1513 DRM_ERROR("Failed to disable psr (%d)\n", ret);
1514 }
1515 }
1516 }
1517
1518 analogix_dp_bridge_disable(bridge);
1519 }
1520
analogix_dp_bridge_atomic_post_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1521 static void analogix_dp_bridge_atomic_post_disable(struct drm_bridge *bridge, struct drm_bridge_state *old_bridge_state)
1522 {
1523 struct drm_atomic_state *old_state = old_bridge_state->base.state;
1524 struct analogix_dp_device *dp = bridge->driver_private;
1525 struct drm_crtc *crtc;
1526 struct drm_crtc_state *new_crtc_state;
1527 int ret;
1528
1529 crtc = analogix_dp_get_new_crtc(dp, old_state);
1530 if (!crtc) {
1531 return;
1532 }
1533
1534 new_crtc_state = drm_atomic_get_new_crtc_state(old_state, crtc);
1535 if (!new_crtc_state || !new_crtc_state->self_refresh_active) {
1536 return;
1537 }
1538
1539 ret = analogix_dp_enable_psr(dp);
1540 if (ret) {
1541 DRM_ERROR("Failed to enable psr (%d)\n", ret);
1542 }
1543 }
1544
analogix_dp_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * orig_mode,const struct drm_display_mode * adj_mode)1545 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge, const struct drm_display_mode *orig_mode,
1546 const struct drm_display_mode *adj_mode)
1547 {
1548 struct analogix_dp_device *dp = bridge->driver_private;
1549 struct drm_display_info *display_info = &dp->connector.display_info;
1550 struct video_info *video = &dp->video_info;
1551 struct drm_display_mode *mode = &video->mode;
1552 struct device_node *dp_node = dp->dev->of_node;
1553 int vic;
1554
1555 drm_mode_copy(mode, adj_mode);
1556 if (dp->plat_data->split_mode) {
1557 dp->plat_data->convert_to_origin_mode(mode);
1558 }
1559
1560 /* Input video interlaces & hsync pol & vsync pol */
1561 video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1562 video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1563 video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1564
1565 /* Input video dynamic_range & colorimetry */
1566 vic = drm_match_cea_mode(mode);
1567 if ((vic == 0x6) || (vic == 0x7) || (vic == 0x15) || (vic == 0x16) || (vic == 0x2) || \
1568 (vic == 0x3) || (vic == 0x11) || (vic == 0x12)) {
1569 video->dynamic_range = CEA;
1570 video->ycbcr_coeff = COLOR_YCBCR601;
1571 } else if (vic) {
1572 video->dynamic_range = CEA;
1573 video->ycbcr_coeff = COLOR_YCBCR709;
1574 } else {
1575 video->dynamic_range = VESA;
1576 video->ycbcr_coeff = COLOR_YCBCR709;
1577 }
1578
1579 /* Input vide bpc and color_formats */
1580 switch (display_info->bpc) {
1581 case 0xc:
1582 video->color_depth = COLOR_12;
1583 break;
1584 case 0xa:
1585 video->color_depth = COLOR_10;
1586 break;
1587 case 0x8:
1588 video->color_depth = COLOR_8;
1589 break;
1590 case 0x6:
1591 video->color_depth = COLOR_6;
1592 break;
1593 default:
1594 video->color_depth = COLOR_8;
1595 break;
1596 }
1597 if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444) {
1598 video->color_space = COLOR_YCBCR444;
1599 } else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422) {
1600 video->color_space = COLOR_YCBCR422;
1601 } else {
1602 video->color_space = COLOR_RGB;
1603 }
1604
1605 /*
1606 * NOTE: those property parsing code is used for providing backward
1607 * compatibility for samsung platform.
1608 * Due to we used the "of_property_read_u32" interfaces, when this
1609 * property isn't present, the "video_info" can keep the original
1610 * values and wouldn't be modified.
1611 */
1612 of_property_read_u32(dp_node, "samsung,color-space", &video->color_space);
1613 of_property_read_u32(dp_node, "samsung,dynamic-range", &video->dynamic_range);
1614 of_property_read_u32(dp_node, "samsung,ycbcr-coeff", &video->ycbcr_coeff);
1615 of_property_read_u32(dp_node, "samsung,color-depth", &video->color_depth);
1616 if (of_property_read_bool(dp_node, "hsync-active-high")) {
1617 video->h_sync_polarity = true;
1618 }
1619 if (of_property_read_bool(dp_node, "vsync-active-high")) {
1620 video->v_sync_polarity = true;
1621 }
1622 if (of_property_read_bool(dp_node, "interlaced")) {
1623 video->interlaced = true;
1624 }
1625 }
1626
analogix_dp_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)1627 static enum drm_mode_status analogix_dp_bridge_mode_valid(struct drm_bridge *bridge,
1628 const struct drm_display_info *info,
1629 const struct drm_display_mode *mode)
1630 {
1631 struct analogix_dp_device *dp = bridge->driver_private;
1632 struct drm_display_mode m;
1633
1634 drm_mode_copy(&m, mode);
1635
1636 if (dp->plat_data->split_mode) {
1637 dp->plat_data->convert_to_origin_mode(&m);
1638 }
1639
1640 if (!analogix_dp_bandwidth_ok(dp, &m, drm_dp_bw_code_to_link_rate(dp->link_train.link_rate),
1641 dp->link_train.lane_count)) {
1642 return MODE_BAD;
1643 }
1644
1645 return MODE_OK;
1646 }
1647
1648 static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1649 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1650 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1651 .atomic_reset = drm_atomic_helper_bridge_reset,
1652 .atomic_pre_enable = analogix_dp_bridge_atomic_pre_enable,
1653 .atomic_enable = analogix_dp_bridge_atomic_enable,
1654 .atomic_disable = analogix_dp_bridge_atomic_disable,
1655 .atomic_post_disable = analogix_dp_bridge_atomic_post_disable,
1656 .mode_set = analogix_dp_bridge_mode_set,
1657 .attach = analogix_dp_bridge_attach,
1658 .detach = analogix_dp_bridge_detach,
1659 .mode_valid = analogix_dp_bridge_mode_valid,
1660 };
1661
analogix_dp_bridge_init(struct analogix_dp_device * dp)1662 static int analogix_dp_bridge_init(struct analogix_dp_device *dp)
1663 {
1664 struct drm_bridge *bridge = &dp->bridge;
1665 int ret;
1666
1667 if (!dp->plat_data->left) {
1668 ret = drm_bridge_attach(dp->encoder, bridge, NULL, 0);
1669 if (ret) {
1670 DRM_ERROR("failed to attach drm bridge\n");
1671 return ret;
1672 }
1673 }
1674
1675 if (dp->plat_data->right) {
1676 struct analogix_dp_device *secondary = dp->plat_data->right;
1677
1678 ret = drm_bridge_attach(dp->encoder, &secondary->bridge, bridge, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1679 if (ret) {
1680 return ret;
1681 }
1682 }
1683
1684 return 0;
1685 }
1686
analogix_dp_dt_parse_pdata(struct analogix_dp_device * dp)1687 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
1688 {
1689 struct device_node *dp_node = dp->dev->of_node;
1690 struct video_info *video_info = &dp->video_info;
1691
1692 switch (dp->plat_data->dev_type) {
1693 case RK3288_DP:
1694 case RK3568_EDP:
1695 /*
1696 * Like Rk3288 DisplayPort TRM indicate that "Main link
1697 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
1698 */
1699 video_info->max_link_rate = 0x0A;
1700 video_info->max_lane_count = 0x04;
1701 break;
1702 case RK3399_EDP:
1703 case RK3588_EDP:
1704 video_info->max_link_rate = 0x14;
1705 video_info->max_lane_count = 0x04;
1706 break;
1707 case EXYNOS_DP:
1708 /*
1709 * NOTE: those property parseing code is used for
1710 * providing backward compatibility for samsung platform.
1711 */
1712 of_property_read_u32(dp_node, "samsung,link-rate", &video_info->max_link_rate);
1713 of_property_read_u32(dp_node, "samsung,lane-count", &video_info->max_lane_count);
1714 break;
1715 }
1716
1717 video_info->video_bist_enable = of_property_read_bool(dp_node, "analogix,video-bist-enable");
1718
1719 return 0;
1720 }
1721
analogix_dpaux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)1722 static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1723 {
1724 struct analogix_dp_device *dp = to_dp(aux);
1725 int ret;
1726 pm_runtime_get_sync(dp->dev);
1727 ret = analogix_dp_detect_hpd(dp);
1728 if (ret) {
1729 goto out;
1730 }
1731 ret = analogix_dp_transfer(dp, msg);
1732 out:
1733 pm_runtime_put(dp->dev);
1734 return ret;
1735 }
analogix_dp_audio_hw_params(struct analogix_dp_device * dp,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)1736 int analogix_dp_audio_hw_params(struct analogix_dp_device *dp, struct hdmi_codec_daifmt *daifmt,
1737 struct hdmi_codec_params *params)
1738 {
1739 switch (daifmt->fmt) {
1740 case HDMI_SPDIF:
1741 analogix_dp_audio_config_spdif(dp);
1742 break;
1743 case HDMI_I2S:
1744 analogix_dp_audio_config_i2s(dp);
1745 break;
1746 default:
1747 DRM_DEV_ERROR(dp->dev, "invalid daifmt %d\n", daifmt->fmt);
1748 return -EINVAL;
1749 }
1750
1751 return 0;
1752 }
1753 EXPORT_SYMBOL_GPL(analogix_dp_audio_hw_params);
1754
analogix_dp_audio_shutdown(struct analogix_dp_device * dp)1755 void analogix_dp_audio_shutdown(struct analogix_dp_device *dp)
1756 {
1757 analogix_dp_audio_disable(dp);
1758 }
1759 EXPORT_SYMBOL_GPL(analogix_dp_audio_shutdown);
1760
analogix_dp_audio_startup(struct analogix_dp_device * dp)1761 int analogix_dp_audio_startup(struct analogix_dp_device *dp)
1762 {
1763 analogix_dp_audio_enable(dp);
1764
1765 return 0;
1766 }
1767 EXPORT_SYMBOL_GPL(analogix_dp_audio_startup);
1768
analogix_dp_audio_get_eld(struct analogix_dp_device * dp,u8 * buf,size_t len)1769 int analogix_dp_audio_get_eld(struct analogix_dp_device *dp, u8 *buf, size_t len)
1770 {
1771 memcpy(buf, dp->connector.eld, min(sizeof(dp->connector.eld), len));
1772
1773 return 0;
1774 }
1775 EXPORT_SYMBOL_GPL(analogix_dp_audio_get_eld);
1776
analogix_dp_loader_protect(struct analogix_dp_device * dp)1777 int analogix_dp_loader_protect(struct analogix_dp_device *dp)
1778 {
1779 int ret;
1780
1781 ret = pm_runtime_resume_and_get(dp->dev);
1782 if (ret) {
1783 dev_err(dp->dev, "failed to get runtime PM: %d\n", ret);
1784 return ret;
1785 }
1786
1787 analogix_dp_phy_power_on(dp);
1788
1789 dp->dpms_mode = DRM_MODE_DPMS_ON;
1790
1791 return 0;
1792 }
1793 EXPORT_SYMBOL_GPL(analogix_dp_loader_protect);
1794
analogix_dp_probe(struct device * dev,struct analogix_dp_plat_data * plat_data)1795 struct analogix_dp_device *analogix_dp_probe(struct device *dev, struct analogix_dp_plat_data *plat_data)
1796 {
1797 struct platform_device *pdevice = to_platform_device(dev);
1798 struct analogix_dp_device *dp_dev;
1799 struct resource *res;
1800 int ret;
1801
1802 if (!plat_data) {
1803 dev_err(dev, "Invalided input plat_data\n");
1804 return ERR_PTR(-EINVAL);
1805 }
1806
1807 dp_dev = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
1808 if (!dp_dev) {
1809 return ERR_PTR(-ENOMEM);
1810 }
1811
1812 dp_dev->dev = &pdevice->dev;
1813 dp_dev->dpms_mode = DRM_MODE_DPMS_OFF;
1814
1815 mutex_init(&dp_dev->panel_lock);
1816 dp_dev->panel_is_prepared = false;
1817 dp_dev->plat_data = plat_data;
1818
1819 ret = analogix_dp_dt_parse_pdata(dp_dev);
1820 if (ret) {
1821 return ERR_PTR(ret);
1822 }
1823
1824 dp_dev->phy = devm_phy_get(dp_dev->dev, "dp");
1825 if (IS_ERR(dp_dev->phy)) {
1826 dev_err(dp_dev->dev, "no DP phy configured\n");
1827 ret = PTR_ERR(dp_dev->phy);
1828 if (ret) {
1829 /*
1830 * phy itself is not enabled, so we can move forward
1831 * assigning NULL to phy pointer.
1832 */
1833 if (ret == -ENOSYS || ret == -ENODEV) {
1834 dp_dev->phy = NULL;
1835 } else {
1836 return ERR_PTR(ret);
1837 }
1838 }
1839 }
1840
1841 ret = devm_clk_bulk_get_all(dev, &dp_dev->clks);
1842 if (ret < 0) {
1843 dev_err(dev, "failed to get clocks %d\n", ret);
1844 return ERR_PTR(ret);
1845 }
1846
1847 dp_dev->nr_clks = ret;
1848
1849 res = platform_get_resource(pdevice, IORESOURCE_MEM, 0);
1850
1851 dp_dev->reg_base = devm_ioremap_resource(&pdevice->dev, res);
1852 if (IS_ERR(dp_dev->reg_base)) {
1853 ret = PTR_ERR(dp_dev->reg_base);
1854 goto err_disable_clk;
1855 }
1856
1857 dp_dev->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
1858
1859 /* Try two different names */
1860 dp_dev->hpd_gpiod = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
1861 if (!dp_dev->hpd_gpiod) {
1862 dp_dev->hpd_gpiod = devm_gpiod_get_optional(dev, "samsung,hpd", GPIOD_IN);
1863 }
1864 if (IS_ERR(dp_dev->hpd_gpiod)) {
1865 dev_err(dev, "error getting HDP GPIO: %ld\n", PTR_ERR(dp_dev->hpd_gpiod));
1866 ret = PTR_ERR(dp_dev->hpd_gpiod);
1867 goto err_disable_clk;
1868 }
1869
1870 if (dp_dev->hpd_gpiod) {
1871 ret = devm_request_threaded_irq(dev, gpiod_to_irq(dp_dev->hpd_gpiod), NULL, analogix_dp_hpd_irq_handler,
1872 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, "analogix-hpd", dp_dev);
1873 if (ret) {
1874 dev_err(dev, "failed to request hpd IRQ: %d\n", ret);
1875 return ERR_PTR(ret);
1876 }
1877 }
1878
1879 dp_dev->irq = platform_get_irq(pdevice, 0);
1880 if (dp_dev->irq == -ENXIO) {
1881 dev_err(&pdevice->dev, "failed to get irq\n");
1882 ret = -ENODEV;
1883 goto err_disable_clk;
1884 }
1885
1886 irq_set_status_flags(dp_dev->irq, IRQ_NOAUTOEN);
1887 ret = devm_request_threaded_irq(&pdevice->dev, dp_dev->irq, analogix_dp_hardirq,
1888 analogix_dp_irq_thread, 0, "analogix-dp", dp_dev);
1889 if (ret) {
1890 dev_err(&pdevice->dev, "failed to request irq\n");
1891 goto err_disable_clk;
1892 }
1893
1894 dp_dev->bridge.driver_private = dp_dev;
1895 dp_dev->bridge.funcs = &analogix_dp_bridge_funcs;
1896
1897 return dp_dev;
1898 err_disable_clk:
1899 clk_bulk_disable_unprepare(dp_dev->nr_clks, dp_dev->clks);
1900 return ERR_PTR(ret);
1901 }
1902 EXPORT_SYMBOL_GPL(analogix_dp_probe);
1903
analogix_dp_bind(struct analogix_dp_device * dp,struct drm_device * drm_dev)1904 int analogix_dp_bind(struct analogix_dp_device *dp, struct drm_device *drm_dev)
1905 {
1906 int ret;
1907
1908 dp->drm_dev = drm_dev;
1909 dp->encoder = dp->plat_data->encoder;
1910
1911 dp->aux.name = "DP-AUX";
1912 dp->aux.transfer = analogix_dpaux_transfer;
1913 dp->aux.dev = dp->dev;
1914
1915 ret = drm_dp_aux_register(&dp->aux);
1916 if (ret) {
1917 return ret;
1918 }
1919
1920 pm_runtime_enable(dp->dev);
1921
1922 ret = analogix_dp_bridge_init(dp);
1923 if (ret) {
1924 DRM_ERROR("failed to init bridge (%d)\n", ret);
1925 goto err_disable_pm_runtime;
1926 }
1927
1928 return 0;
1929
1930 err_disable_pm_runtime:
1931 pm_runtime_disable(dp->dev);
1932
1933 return ret;
1934 }
1935 EXPORT_SYMBOL_GPL(analogix_dp_bind);
1936
analogix_dp_unbind(struct analogix_dp_device * dp)1937 void analogix_dp_unbind(struct analogix_dp_device *dp)
1938 {
1939 dp->connector.funcs->destroy(&dp->connector);
1940 drm_dp_aux_unregister(&dp->aux);
1941 pm_runtime_disable(dp->dev);
1942 }
1943 EXPORT_SYMBOL_GPL(analogix_dp_unbind);
1944
analogix_dp_remove(struct analogix_dp_device * dp)1945 void analogix_dp_remove(struct analogix_dp_device *dp)
1946 {
1947 }
1948 EXPORT_SYMBOL_GPL(analogix_dp_remove);
1949
analogix_dp_runtime_suspend(struct analogix_dp_device * dp)1950 int analogix_dp_runtime_suspend(struct analogix_dp_device *dp)
1951 {
1952 clk_bulk_disable_unprepare(dp->nr_clks, dp->clks);
1953
1954 return 0;
1955 }
1956 EXPORT_SYMBOL_GPL(analogix_dp_runtime_suspend);
1957
analogix_dp_runtime_resume(struct analogix_dp_device * dp)1958 int analogix_dp_runtime_resume(struct analogix_dp_device *dp)
1959 {
1960 return clk_bulk_prepare_enable(dp->nr_clks, dp->clks);
1961 }
1962 EXPORT_SYMBOL_GPL(analogix_dp_runtime_resume);
1963
analogix_dp_start_crc(struct drm_connector * connector)1964 int analogix_dp_start_crc(struct drm_connector *connector)
1965 {
1966 struct analogix_dp_device *dp = to_dp(connector);
1967
1968 if (!connector->state->crtc) {
1969 DRM_ERROR("Connector %s doesn't currently have a CRTC.\n", connector->name);
1970 return -EINVAL;
1971 }
1972
1973 return drm_dp_start_crc(&dp->aux, connector->state->crtc);
1974 }
1975 EXPORT_SYMBOL_GPL(analogix_dp_start_crc);
1976
analogix_dp_stop_crc(struct drm_connector * connector)1977 int analogix_dp_stop_crc(struct drm_connector *connector)
1978 {
1979 struct analogix_dp_device *dp = to_dp(connector);
1980
1981 return drm_dp_stop_crc(&dp->aux);
1982 }
1983 EXPORT_SYMBOL_GPL(analogix_dp_stop_crc);
1984
1985 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1986 MODULE_DESCRIPTION("Analogix DP Core Driver");
1987 MODULE_LICENSE("GPL v2");
1988